created Mon Jun 13 18:56:28 2022

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peek Data FSI slave A part 1)
Addr:	00000000000004A0 (FSI)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.PEEK4A0
Constant(s):	PERV_PEEK4A0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPVSB.FSI.W.FSI_SLAVE.MST_PEEK_DATA_A(0:3) [0000]
	4:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.OPB2FSI.Q_ACT_ERROR_CODE.FSILAT.LATCH.LATC.L2(0:3) [0000]
	8	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_PRT_ENABLE.FSILAT.LATCH.LATC.L2(0) [0]
	9	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#0.PRT.COMP.PRTCTL.GEN.Q_FSI_DI_LEVEL.FSILAT.LATCH.LATC.L2(0) [0]
	10:11	TP.TPVSB.FSI.W.FSI_SLAVE.MST_PEEK_DATA_A(10:11) [00]
	12	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_PRT_ENABLE.FSILAT.LATCH.LATC.L2(1) [0]
	13	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#1.PRT.COMP.PRTCTL.GEN.Q_FSI_DI_LEVEL.FSILAT.LATCH.LATC.L2(0) [0]
	14:15	TP.TPVSB.FSI.W.FSI_SLAVE.MST_PEEK_DATA_A(14:15) [00]
	16	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_PRT_ENABLE.FSILAT.LATCH.LATC.L2(2) [0]
	17	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#2.PRT.COMP.PRTCTL.GEN.Q_FSI_DI_LEVEL.FSILAT.LATCH.LATC.L2(0) [0]
	18:19	TP.TPVSB.FSI.W.FSI_SLAVE.MST_PEEK_DATA_A(18:19) [00]
	20	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_PRT_ENABLE.FSILAT.LATCH.LATC.L2(3) [0]
	21	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#3.PRT.COMP.PRTCTL.GEN.Q_FSI_DI_LEVEL.FSILAT.LATCH.LATC.L2(0) [0]
	22:23	TP.TPVSB.FSI.W.FSI_SLAVE.MST_PEEK_DATA_A(22:23) [00]
	24	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_PRT_ENABLE.FSILAT.LATCH.LATC.L2(4) [0]
	25	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#4.PRT.COMP.PRTCTL.GEN.Q_FSI_DI_LEVEL.FSILAT.LATCH.LATC.L2(0) [0]
	26:27	TP.TPVSB.FSI.W.FSI_SLAVE.MST_PEEK_DATA_A(26:27) [00]
	28	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_PRT_ENABLE.FSILAT.LATCH.LATC.L2(5) [0]
	29	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#5.PRT.COMP.PRTCTL.GEN.Q_FSI_DI_LEVEL.FSILAT.LATCH.LATC.L2(0) [0]
	30:31	TP.TPVSB.FSI.W.FSI_SLAVE.MST_PEEK_DATA_A(30:31) [00]
Bit(s)	FSI			Dial: Description
0:3	ROX
4:7	ROX			FSI_A_MST_0_ACTUAL_ERROR: error code of last operation bridge (OPB) Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
8	ROX			FSI_A_MST_0_PORT_0_ENABLE: enable Master port 0 enable
9:11	ROX
12	ROX			FSI_A_MST_0_PORT_1_ENABLE: enable Master port 0 enable
13:15	ROX
16	ROX			FSI_A_MST_0_PORT_2_ENABLE: enable Master port 0 enable
17:19	ROX
20	ROX			FSI_A_MST_0_PORT_3_ENABLE: enable Master port 0 enable
21:23	ROX
24	ROX			FSI_A_MST_0_PORT_4_ENABLE: enable Master port 0 enable
25:27	ROX
28	ROX			FSI_A_MST_0_PORT_5_ENABLE: enable Master port 0 enable
29:31	ROX

peek Data FSI slave A part 2)
Addr:	00000000000004A4 (FSI)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.PEEK4A4
Constant(s):	PERV_PEEK4A4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_PRT_ENABLE.FSILAT.LATCH.LATC.L2(6) [0]
	1	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#6.PRT.COMP.PRTCTL.GEN.Q_FSI_DI_LEVEL.FSILAT.LATCH.LATC.L2(0) [0]
	2:3	TP.TPVSB.FSI.W.FSI_SLAVE.MST_PEEK_DATA_A(34:35) [00]
	4	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_PRT_ENABLE.FSILAT.LATCH.LATC.L2(7) [0]
	5	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#7.PRT.COMP.PRTCTL.GEN.Q_FSI_DI_LEVEL.FSILAT.LATCH.LATC.L2(0) [0]
	6:7	TP.TPVSB.FSI.W.FSI_SLAVE.MST_PEEK_DATA_A(38:39) [00]
	8:11	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.OPB2FSI.Q_ACT_ERROR_CODE.FSILAT.LATCH.LATC.L2(0:3) [0000]
	12	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_PRT_ENABLE.FSILAT.LATCH.LATC.L2(0) [0]
	13	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#0.PRT.COMP.PRTCTL.GEN.Q_FSI_DI_LEVEL.FSILAT.LATCH.LATC.L2(0) [0]
	14:15	TP.TPVSB.FSI.W.FSI_SLAVE.MST_PEEK_DATA_A(46:47) [00]
	16	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_PRT_ENABLE.FSILAT.LATCH.LATC.L2(1) [0]
	17	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#1.PRT.COMP.PRTCTL.GEN.Q_FSI_DI_LEVEL.FSILAT.LATCH.LATC.L2(0) [0]
	18:19	TP.TPVSB.FSI.W.FSI_SLAVE.MST_PEEK_DATA_A(50:51) [00]
	20	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_PRT_ENABLE.FSILAT.LATCH.LATC.L2(2) [0]
	21	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#2.PRT.COMP.PRTCTL.GEN.Q_FSI_DI_LEVEL.FSILAT.LATCH.LATC.L2(0) [0]
	22:23	TP.TPVSB.FSI.W.FSI_SLAVE.MST_PEEK_DATA_A(54:55) [00]
	24	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_PRT_ENABLE.FSILAT.LATCH.LATC.L2(3) [0]
	25	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#3.PRT.COMP.PRTCTL.GEN.Q_FSI_DI_LEVEL.FSILAT.LATCH.LATC.L2(0) [0]
	26:27	TP.TPVSB.FSI.W.FSI_SLAVE.MST_PEEK_DATA_A(58:59) [00]
	28	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_PRT_ENABLE.FSILAT.LATCH.LATC.L2(4) [0]
	29	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#4.PRT.COMP.PRTCTL.GEN.Q_FSI_DI_LEVEL.FSILAT.LATCH.LATC.L2(0) [0]
	30:31	TP.TPVSB.FSI.W.FSI_SLAVE.MST_PEEK_DATA_A(62:63) [00]
Bit(s)	FSI			Dial: Description
0	ROX			FSI_A_MST_0_PORT_6_ENABLE: enable Master port 0 enable
1:3	ROX
4	ROX			FSI_A_MST_0_PORT_7_ENABLE: enable Master port 0 enable
5:7	ROX
8:11	ROX			FSI_A_MST_1_ACTUAL_ERROR: error code of last operation bridge (OPB) Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
12	ROX			FSI_A_MST_1_PORT_0_ENABLE: enable Master port 0 enable
13:15	ROX
16	ROX			FSI_A_MST_1_PORT_1_ENABLE: enable Master port 0 enable
17:19	ROX
20	ROX			FSI_A_MST_1_PORT_2_ENABLE: enable Master port 0 enable
21:23	ROX
24	ROX			FSI_A_MST_1_PORT_3_ENABLE: enable Master port 0 enable
25:27	ROX
28	ROX			FSI_A_MST_1_PORT_4_ENABLE: enable Master port 0 enable
29:31	ROX

peek Data time FSI slave A part 1)
Addr:	00000000000004B0 (FSI)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.PEEK4B0
Constant(s):	PERV_PEEK4B0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.OPB2FSI.TIMER.ELAPSEDL.FSILAT.LATCH.LATC.L2(0:15) [0000000000000000]
	16:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.OPB2FSI.TIMER.LIMITL.FSILAT.LATCH.LATC.L2(0:15) [0000000000000000]
Bit(s)	FSI			Dial: Description
0:31	ROX

peek Data time FSI slave A part 2)
Addr:	00000000000004B4 (FSI)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.PEEK4B4
Constant(s):	PERV_PEEK4B4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.OPB2FSI.TIMER.ELAPSEDL.FSILAT.LATCH.LATC.L2(0:15) [0000000000000000]
	16:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.OPB2FSI.TIMER.LIMITL.FSILAT.LATCH.LATC.L2(0:15) [0000000000000000]
Bit(s)	FSI			Dial: Description
0:31	ROX

FSI SLAVE SMODE FSI-0 view
Addr:	0000000000000800 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SMODE
Constant(s):	PERV_FSI_A_SMODE
Comments:	FSI Slave mode register Bit 0:23 common, Bit 24:31 FSI0 specific
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_MODE_REG_01.FSILAT.LATCH.LATC.L2(0:15) [0000000000000000]
	20:23	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_MODE_REG_2.FSILAT.LATCH.LATC.L2(0:3) [0000]
	28:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_MODE_REG_3.FSILAT.LATCH.LATC.L2(0:3) [0000]
Bit(s)	FSI0			Dial: Description
0	RW_WOR			FSI_A_WARM_START_COMPLETED: the warm start has completed
1	RWX			FSI_A_ENABLE_AUX_PORT_UNUSED: enable auxiliary port -> not used
2	RW			FSI_A_ENABLE_HW_ERROR_RECOVERY: enable hardware recovery
3:5	RW
6:7	RW			FSI_A_OWN_ID_THIS_FSI_SLAVE: traditional own_id. Current usage 0b11 is default for compatibility with limited addressability; 0b00 for working with 21+2 bit addressing enabled Dial enums: DEFAULT=>0b11 WORKING=>0b00 UNDEF_0=>0b01 UNDEF_1=>0b10
8:11	RW			FSI_A_ECHO_DELAY_CYCLES: echo delay in binary cycles
12:15	RW			FSI_A_SEND_DELAY_CYCLES: send delay in binary cycles
16:19	RO			constant=0b0000
20:23	RW			FSI_A_LBUS_CLOCK_DIVIDER: LBUS clock divider
24:27	RO			constant=0b0000
28:31	RW			briefing_data_to_slave_side_1

FSI SLAVE SMODE FSI-1 view
Addr:	0000000000000800 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SMODE
Constant(s):	PERV_FSI_B_SMODE
Comments:	FSI Slave mode register Bit 0:23 common, Bit 24:31 FSI1 specific
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_MODE_REG_01.FSILAT.LATCH.LATC.L2(0:15) [0000000000000000]
	20:23	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_MODE_REG_2.FSILAT.LATCH.LATC.L2(0:3) [0000]
	24:27	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_MODE_REG_3.FSILAT.LATCH.LATC.L2(0:3) [0000]
Bit(s)	FSI1			Dial: Description
0	RW_WOR			FSI_B_WARM_START_COMPLETED: the warm start has completed
1	RWX			FSI_B_ENABLE_AUX_PORT_UNUSED: enable auxiliary port -> not used
2	RW			FSI_B_ENABLE_HW_ERROR_RECOVERY: enable hardware recovery
3:5	RW
6:7	RW			FSI_B_OWN_ID_THIS_FSI_SLAVE: traditional own_id. Current usage 0b11 is default for compatibility with limited addressability; 0b00 for working with 21+2 bit addressing enabled Dial enums: DEFAULT=>0b11 WORKING=>0b00 UNDEF_0=>0b01 UNDEF_1=>0b10
8:11	RW			FSI_B_ECHO_DELAY_CYCLES: echo delay in binary cycles
12:15	RW			FSI_B_SEND_DELAY_CYCLES: send delay in binary cycles
16:19	RO			constant=0b0000
20:23	RW			FSI_B_LBUS_CLOCK_DIVIDER: LBUS clock divider
24:27	RW			briefing_data_to_slave_side_0
28:31	RO			constant=0b0000

FSI SLAVE SDMA
Addr:	0000000000000804 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SDMA
Constant(s):	PERV_FSI_A_SDMA
Comments:	Slave DMA Control / Select DMA request source
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	3:7	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_DMA1_SELECT.FSILAT.LATCH.LATC.L2(0:4) [00000]
	11:15	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_DMA2_SELECT.FSILAT.LATCH.LATC.L2(0:4) [00000]
	16:23	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_CMST_DMA_SELECT.FSILAT.LATCH.LATC.L2(0:7) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_PMST_DMA_SELECT.FSILAT.LATCH.LATC.L2(0:7) [00000000]
Bit(s)	FSI0			Dial: Description
0:2	RO			constant=0b000
3:7	RW			DMA_REQUEST_1_select
8:10	RO			constant=0b000
11:15	RW			DMA_REQUEST_2_select
16:18	RW
19:21	RW			cMFSI_port_ID_select
22:23	RW			cMFSI_slave_ID_select
24:26	RW
27:29	RW			MFSI_port_ID_select
30:31	RW			MFSI_slave_ID_select

FSI SLAVE SDMA
Addr:	0000000000000804 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SDMA
Constant(s):	PERV_FSI_B_SDMA
Comments:	Slave DMA Control / Select DMA request source
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	3:7	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_DMA1_SELECT.FSILAT.LATCH.LATC.L2(0:4) [00000]
	11:15	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_DMA2_SELECT.FSILAT.LATCH.LATC.L2(0:4) [00000]
	16:23	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_CMST_DMA_SELECT.FSILAT.LATCH.LATC.L2(0:7) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_PMST_DMA_SELECT.FSILAT.LATCH.LATC.L2(0:7) [00000000]
Bit(s)	FSI1			Dial: Description
0:2	RO			constant=0b000
3:7	RW			DMA_REQUEST_1_select
8:10	RO			constant=0b000
11:15	RW			DMA_REQUEST_2_select
16:18	RW
19:21	RW			cMFSI_port_ID_select
22:23	RW			cMFSI_slave_ID_select
24:26	RW
27:29	RW			MFSI_port_ID_select
30:31	RW			MFSI_slave_ID_select

Clear Slave Interrupt Condition
Addr:	0000000000000808 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SCISC
Constant(s):	PERV_FSI_A_SCISC
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:1	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.SLV_INTR_CONDITIONS(0:1) [00]
	2	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_PARITY_ERROR.FSILAT.LATCH.LATC.L2(0) [0]
	3	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_LBUS_PROTOCOL_ERROR.FSILAT.LATCH.LATC.L2(0) [0]
	4	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_ACCESS_ERROR.FSILAT.LATCH.LATC.L2(0) [0]
	5	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_LBUS_OWNERSHIP_ERROR.FSILAT.LATCH.LATC.L2(0) [0]
Bit(s)	FSI0			Dial: Description
0:5	WOX_CLEAR

Slave Interrupt Condition
Addr:	0000000000000808 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SISC
Constant(s):	PERV_FSI_A_SISC
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:1	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.SLV_INTR_CONDITIONS(0:1) [00]
	2	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_PARITY_ERROR.FSILAT.LATCH.LATC.L2(0) [0]
	3	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_LBUS_PROTOCOL_ERROR.FSILAT.LATCH.LATC.L2(0) [0]
	4	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_ACCESS_ERROR.FSILAT.LATCH.LATC.L2(0) [0]
	5	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_LBUS_OWNERSHIP_ERROR.FSILAT.LATCH.LATC.L2(0) [0]
	6:9	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.SLV_INTR_CONDITIONS(6:9) [0000]
	10	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_WARM_START_SYNC_FR_LEFT.FSILAT.FSILAT2X.LATC.CSDFFSRPQ1.L2(0) [0]
	11	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_LBUS_REQ_SYNC_FR_LEFT.FSILAT.FSILAT2X.LATC.CSDFFSRPQ1.L2(0) [0]
	12:13	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.SLV_INTR_CONDITIONS(12:13) [00]
	14	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_WARM_START_SYNC_FR_RIGHT.FSILAT.FSILAT2X.LATC.CSDFFSRPQ1.L2(0) [0]
	15	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_LBUS_REQ_SYNC_FR_RIGHT.FSILAT.FSILAT2X.LATC.CSDFFSRPQ1.L2(0) [0]
	16:17	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.SLV_INTR_CONDITIONS(16:17) [00]
	18:23	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.CAP_ERR.L.FSILAT.LATCH.LATC.L2(0:5) [000000]
	24:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.SLV_INTR_CONDITIONS(24:31) [00000000]
Bit(s)	FSI0			Dial: Description
0:31	ROX

Clear Slave Interrupt Condition
Addr:	0000000000000808 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SCISC
Constant(s):	PERV_FSI_B_SCISC
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:1	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.SLV_INTR_CONDITIONS(0:1) [00]
	2	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_PARITY_ERROR.FSILAT.LATCH.LATC.L2(0) [0]
	3	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_LBUS_PROTOCOL_ERROR.FSILAT.LATCH.LATC.L2(0) [0]
	4	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_ACCESS_ERROR.FSILAT.LATCH.LATC.L2(0) [0]
	5	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_LBUS_OWNERSHIP_ERROR.FSILAT.LATCH.LATC.L2(0) [0]
Bit(s)	FSI1			Dial: Description
0:5	WOX_CLEAR

Slave Interrupt Condition
Addr:	0000000000000808 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SISC
Constant(s):	PERV_FSI_B_SISC
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:1	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.SLV_INTR_CONDITIONS(0:1) [00]
	2	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_PARITY_ERROR.FSILAT.LATCH.LATC.L2(0) [0]
	3	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_LBUS_PROTOCOL_ERROR.FSILAT.LATCH.LATC.L2(0) [0]
	4	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_ACCESS_ERROR.FSILAT.LATCH.LATC.L2(0) [0]
	5	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_LBUS_OWNERSHIP_ERROR.FSILAT.LATCH.LATC.L2(0) [0]
	6:9	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.SLV_INTR_CONDITIONS(6:9) [0000]
	10	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_WARM_START_SYNC_FR_LEFT.FSILAT.FSILAT2X.LATC.CSDFFSRPQ1.L2(0) [0]
	11	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_LBUS_REQ_SYNC_FR_LEFT.FSILAT.FSILAT2X.LATC.CSDFFSRPQ1.L2(0) [0]
	12:13	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.SLV_INTR_CONDITIONS(12:13) [00]
	14	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_WARM_START_SYNC_FR_RIGHT.FSILAT.FSILAT2X.LATC.CSDFFSRPQ1.L2(0) [0]
	15	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_LBUS_REQ_SYNC_FR_RIGHT.FSILAT.FSILAT2X.LATC.CSDFFSRPQ1.L2(0) [0]
	16:17	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.SLV_INTR_CONDITIONS(16:17) [00]
	18:23	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.CAP_ERR.L.FSILAT.LATCH.LATC.L2(0:5) [000000]
	24:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.SLV_INTR_CONDITIONS(24:31) [00000000]
Bit(s)	FSI1			Dial: Description
0:31	ROX

FSI Slave Interrupt Mask
Addr:	000000000000080C (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SISM
Constant(s):	PERV_FSI_A_SISM
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_SLV_INTR_MASK_0.FSILAT.LATCH.LATC.L2(0:7) [00000000]
	12:15	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_SLV_INTR_MASK_1.FSILAT.LATCH.LATC.L2(0:3) [0000]
	20:23	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_SLV_INTR_MASK_2.FSILAT.LATCH.LATC.L2(4:7) [0000]
	24:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_SLV_INTR_MASK_3.FSILAT.LATCH.LATC.L2(0:7) [00000000]
Bit(s)	FSI0			Dial: Description
0:7	RW
8:11	RO			constant=0b0000
12:15	RW
16:19	RO			constant=0b0000
20:31	RW

FSI Slave Interrupt Mask
Addr:	000000000000080C (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SISM
Constant(s):	PERV_FSI_B_SISM
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_SLV_INTR_MASK_0.FSILAT.LATCH.LATC.L2(0:7) [00000000]
	8:11	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_SLV_INTR_MASK_1.FSILAT.LATCH.LATC.L2(0:3) [0000]
	20:23	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_SLV_INTR_MASK_2.FSILAT.LATCH.LATC.L2(4:7) [0000]
	24:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_SLV_INTR_MASK_3.FSILAT.LATCH.LATC.L2(0:7) [00000000]
Bit(s)	FSI1			Dial: Description
0:11	RW
12:19	RO			constant=0b00000000
20:31	RW

Slave Interrupt Status
Addr:	0000000000000810 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SISS
Constant(s):	PERV_FSI_A_SISS
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.SLV_INTR_STATUS(0:7) [00000000]
	12:15	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.SLV_INTR_STATUS(12:15) [0000]
	20:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.SLV_INTR_STATUS(20:31) [000000000000]
Bit(s)	FSI0			Dial: Description
0:7	RO
8:11	RO			constant=0b0000
12:15	RO
16:19	RO			constant=0b0000
20:31	RO

Set Slave Interrupt Mask
Addr:	0000000000000810 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SSISM
Constant(s):	PERV_FSI_A_SSISM
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_SLV_INTR_MASK_0.FSILAT.LATCH.LATC.L2(0:7) [00000000]
	12:15	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_SLV_INTR_MASK_1.FSILAT.LATCH.LATC.L2(0:3) [0000]
	20:23	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_SLV_INTR_MASK_2.FSILAT.LATCH.LATC.L2(4:7) [0000]
	24:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_SLV_INTR_MASK_3.FSILAT.LATCH.LATC.L2(0:7) [00000000]
Bit(s)	FSI0			Dial: Description
0:7	WO_OR
8:11	n/a			not implemented
12:15	WO_OR
16:19	n/a			not implemented
20:31	WO_OR

Slave Interrupt Status
Addr:	0000000000000810 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SISS
Constant(s):	PERV_FSI_B_SISS
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:11	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.SLV_INTR_STATUS(0:11) [000000000000]
	20:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.SLV_INTR_STATUS(20:31) [000000000000]
Bit(s)	FSI1			Dial: Description
0:11	RO
12:19	RO			constant=0b00000000
20:31	RO

Set Slave Interrupt Mask
Addr:	0000000000000810 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SSISM
Constant(s):	PERV_FSI_B_SSISM
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_SLV_INTR_MASK_0.FSILAT.LATCH.LATC.L2(0:7) [00000000]
	8:11	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_SLV_INTR_MASK_1.FSILAT.LATCH.LATC.L2(0:3) [0000]
	20:23	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_SLV_INTR_MASK_2.FSILAT.LATCH.LATC.L2(4:7) [0000]
	24:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_SLV_INTR_MASK_3.FSILAT.LATCH.LATC.L2(0:7) [00000000]
Bit(s)	FSI1			Dial: Description
0:11	WO_OR
12:19	n/a			not implemented
20:31	WO_OR

Clear Slave Interrupt Mask
Addr:	0000000000000814 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SCISM
Constant(s):	PERV_FSI_A_SCISM
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_SLV_INTR_MASK_0.FSILAT.LATCH.LATC.L2(0:7) [00000000]
	8:11	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.SLV_INTR_MASK(8:11) [0000]
	12:15	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_SLV_INTR_MASK_1.FSILAT.LATCH.LATC.L2(0:3) [0000]
	16:19	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.SLV_INTR_MASK(16:19) [0000]
	20:23	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_SLV_INTR_MASK_2.FSILAT.LATCH.LATC.L2(4:7) [0000]
	24:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_SLV_INTR_MASK_3.FSILAT.LATCH.LATC.L2(0:7) [00000000]
Bit(s)	FSI0			Dial: Description
0:31	WO_CLEAR

Slave Status
Addr:	0000000000000814 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SSTAT
Constant(s):	PERV_FSI_A_SSTAT
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.STATUS_REG(0) [0]
	1	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_ID_DIRTY.FSILAT.LATCH.LATC.L2(0) [0]
	2	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_WARM_START_SYNC_FR_LEFT.FSILAT.FSILAT2X.LATC.CSDFFSRPQ1.L2(0) [0]
	3	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_WARM_START_SYNC_FR_RIGHT.FSILAT.FSILAT2X.LATC.CSDFFSRPQ1.L2(0) [0]
	4:11	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.STATUS_REG(4:11) [00000000]
	12:15	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_BRIEFING_DATA_SYNC.FSILAT.FSILAT2X.LATC.CSDFFSRPQ1.L2(0:3) [0000]
	16	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_LBUS_REQ_SYNC_FR_LEFT.FSILAT.FSILAT2X.LATC.CSDFFSRPQ1.L2(0) [0]
	17	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_LBUS_REQ_SYNC_FR_RIGHT.FSILAT.FSILAT2X.LATC.CSDFFSRPQ1.L2(0) [0]
	18	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_LBUS_REQ.FSILAT.LATCH.LATC.L2(0) [0]
	19	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_LBUS_LOCK.FSILAT.LATCH.LATC.L2(0) [0]
	20:21	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_LBUS_GNT.FSILAT.LATCH.LATC.L2(0:1) [00]
	22:23	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.STATUS_REG(22:23) [00]
	24	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_OWNERSHIP_FF1.FSILAT.LATCH.LATC.L2(0) [0]
	25	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_OWNERSHIP_FF2.FSILAT.LATCH.LATC.L2(0) [0]
	26:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.STATUS_REG(26:31) [000000]
Bit(s)	FSI0			Dial: Description
0	ROX			any_slv_error
1	ROX			id_dirty
2	ROX			warm_start_sync_fr_left
3	ROX			warm_start_sync_fr_right
4	ROX			mail_delivered_to_left
5	ROX			mail_delivered_to_right
6	ROX			mail_received_fr_left
7	ROX			mail_received_fr_right
8:11	ROX			briefing_data_sync_fr_left
12:15	ROX			briefing_data_sync_fr_right
16	ROX			lbus_req_sync_fr_left
17	ROX			lbus_req_sync_fr_right
18	ROX			this_lbus_req
19	ROX			lbus_lock
20:21	ROX			lbus_gnt
22:23	ROX			this_side
24	ROX			ownership_ff1
25	ROX			ownership_ff2
26	ROX			aux_di_level
27	ROX			aux_di_reference
28:31	ROX			crc_err_ctr

Clear Slave Interrupt Mask
Addr:	0000000000000814 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SCISM
Constant(s):	PERV_FSI_B_SCISM
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_SLV_INTR_MASK_0.FSILAT.LATCH.LATC.L2(0:7) [00000000]
	8:11	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_SLV_INTR_MASK_1.FSILAT.LATCH.LATC.L2(0:3) [0000]
	12:19	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.SLV_INTR_MASK(12:19) [00000000]
	20:23	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_SLV_INTR_MASK_2.FSILAT.LATCH.LATC.L2(4:7) [0000]
	24:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_SLV_INTR_MASK_3.FSILAT.LATCH.LATC.L2(0:7) [00000000]
Bit(s)	FSI1			Dial: Description
0:31	WO_CLEAR

Slave Status
Addr:	0000000000000814 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SSTAT
Constant(s):	PERV_FSI_B_SSTAT
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.STATUS_REG(0) [0]
	1	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_ID_DIRTY.FSILAT.LATCH.LATC.L2(0) [0]
	2	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_WARM_START_SYNC_FR_LEFT.FSILAT.FSILAT2X.LATC.CSDFFSRPQ1.L2(0) [0]
	3	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_WARM_START_SYNC_FR_RIGHT.FSILAT.FSILAT2X.LATC.CSDFFSRPQ1.L2(0) [0]
	4:7	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.STATUS_REG(4:7) [0000]
	8:11	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_BRIEFING_DATA_SYNC.FSILAT.FSILAT2X.LATC.CSDFFSRPQ1.L2(0:3) [0000]
	12:15	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.STATUS_REG(12:15) [0000]
	16	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_LBUS_REQ_SYNC_FR_LEFT.FSILAT.FSILAT2X.LATC.CSDFFSRPQ1.L2(0) [0]
	17	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_LBUS_REQ_SYNC_FR_RIGHT.FSILAT.FSILAT2X.LATC.CSDFFSRPQ1.L2(0) [0]
	18	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_LBUS_REQ.FSILAT.LATCH.LATC.L2(0) [0]
	19	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_LBUS_LOCK.FSILAT.LATCH.LATC.L2(0) [0]
	20:21	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_LBUS_GNT.FSILAT.LATCH.LATC.L2(0:1) [00]
	22:23	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.STATUS_REG(22:23) [00]
	24	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_OWNERSHIP_FF1.FSILAT.LATCH.LATC.L2(0) [0]
	25	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_OWNERSHIP_FF2.FSILAT.LATCH.LATC.L2(0) [0]
	26:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.STATUS_REG(26:31) [000000]
Bit(s)	FSI1			Dial: Description
0	ROX			any_slv_error
1	ROX			id_dirty
2	ROX			warm_start_sync_fr_left
3	ROX			warm_start_sync_fr_right
4	ROX			mail_delivered_to_left
5	ROX			mail_delivered_to_right
6	ROX			mail_received_fr_left
7	ROX			mail_received_fr_right
8:11	ROX			briefing_data_sync_fr_left
12:15	ROX			briefing_data_sync_fr_right
16	ROX			lbus_req_sync_fr_left
17	ROX			lbus_req_sync_fr_right
18	ROX			this_lbus_req
19	ROX			lbus_lock
20:21	ROX			lbus_gnt
22:23	ROX			this_side
24	ROX			ownership_ff1
25	ROX			ownership_ff2
26	ROX			aux_di_level
27	ROX			aux_di_reference
28:31	ROX			crc_err_ctr

Interrupt-1 Mask
Addr:	0000000000000818 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SI1M
Constant(s):	PERV_FSI_A_SI1M
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:6	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_ENG_INTR1_MASK.FSILAT.LATCH.LATC.L2(0:6) [0000000]
Bit(s)	FSI0			Dial: Description
0:6	RW

Interrupt-1 Mask
Addr:	0000000000000818 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SI1M
Constant(s):	PERV_FSI_B_SI1M
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:6	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_ENG_INTR1_MASK.FSILAT.LATCH.LATC.L2(0:6) [0000000]
Bit(s)	FSI1			Dial: Description
0:6	RW

Engine Interrupt-1 Status
Addr:	000000000000081C (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SI1S
Constant(s):	PERV_FSI_A_SI1S
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.ENG_INTR1_STATUS(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:31	RO

Set Slave Interrupt-1 Mask
Addr:	000000000000081C (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SSI1M
Constant(s):	PERV_FSI_A_SSI1M
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:6	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_ENG_INTR1_MASK.FSILAT.LATCH.LATC.L2(0:6) [0000000]
Bit(s)	FSI0			Dial: Description
0:6	WO_OR

Engine Interrupt-1 Status
Addr:	000000000000081C (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SI1S
Constant(s):	PERV_FSI_B_SI1S
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.ENG_INTR1_STATUS(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:31	RO

Set Slave Interrupt-1 Mask
Addr:	000000000000081C (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SSI1M
Constant(s):	PERV_FSI_B_SSI1M
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:6	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_ENG_INTR1_MASK.FSILAT.LATCH.LATC.L2(0:6) [0000000]
Bit(s)	FSI1			Dial: Description
0:6	WO_OR

Clear Slave Interrupt-1 Mask
Addr:	0000000000000820 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SCI1M
Constant(s):	PERV_FSI_A_SCI1M
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:6	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_ENG_INTR1_MASK.FSILAT.LATCH.LATC.L2(0:6) [0000000]
Bit(s)	FSI0			Dial: Description
0:6	WO_CLEAR

Engine Interrupt Condition
Addr:	0000000000000820 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SIC
Constant(s):	PERV_FSI_A_SIC
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.ENG_INTR_CONDITIONS(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:31	RO

Clear Slave Interrupt-1 Mask
Addr:	0000000000000820 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SCI1M
Constant(s):	PERV_FSI_B_SCI1M
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:6	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_ENG_INTR1_MASK.FSILAT.LATCH.LATC.L2(0:6) [0000000]
Bit(s)	FSI1			Dial: Description
0:6	WO_CLEAR

Engine Interrupt Condition
Addr:	0000000000000820 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SIC
Constant(s):	PERV_FSI_B_SIC
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.ENG_INTR_CONDITIONS(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:31	RO

Interrupt-2 MaskInterrupt-2 Mask
Addr:	0000000000000824 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SI2M
Constant(s):	PERV_FSI_A_SI2M
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:6	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_ENG_INTR2_MASK.FSILAT.LATCH.LATC.L2(0:6) [0000000]
Bit(s)	FSI0			Dial: Description
0:6	RW

Interrupt-2 MaskInterrupt-2 Mask
Addr:	0000000000000824 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SI2M
Constant(s):	PERV_FSI_B_SI2M
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:6	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_ENG_INTR2_MASK.FSILAT.LATCH.LATC.L2(0:6) [0000000]
Bit(s)	FSI1			Dial: Description
0:6	RW

Engine Interrupt-2 Status
Addr:	0000000000000828 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SI2S
Constant(s):	PERV_FSI_A_SI2S
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.ENG_INTR2_STATUS(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:31	RO

Set Slave Interrupt-2 Mask
Addr:	0000000000000828 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SSI2M
Constant(s):	PERV_FSI_A_SSI2M
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:6	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_ENG_INTR2_MASK.FSILAT.LATCH.LATC.L2(0:6) [0000000]
Bit(s)	FSI0			Dial: Description
0:6	WO_OR

Engine Interrupt-2 Status
Addr:	0000000000000828 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SI2S
Constant(s):	PERV_FSI_B_SI2S
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.ENG_INTR2_STATUS(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:31	RO

Set Slave Interrupt-2 Mask
Addr:	0000000000000828 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SSI2M
Constant(s):	PERV_FSI_B_SSI2M
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:6	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_ENG_INTR2_MASK.FSILAT.LATCH.LATC.L2(0:6) [0000000]
Bit(s)	FSI1			Dial: Description
0:6	WO_OR

Clear Slave Interrupt-2 Mask
Addr:	000000000000082C (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SCI2CM
Constant(s):	PERV_FSI_A_SCI2CM
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:6	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_ENG_INTR2_MASK.FSILAT.LATCH.LATC.L2(0:6) [0000000]
Bit(s)	FSI0			Dial: Description
0:6	WO_CLEAR

Last Command Trace
Addr:	000000000000082C (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SCMDT
Constant(s):	PERV_FSI_A_SCMDT
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.TRACE_COMMAND(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:31	RO

Clear Slave Interrupt-2 Mask
Addr:	000000000000082C (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SCI2CM
Constant(s):	PERV_FSI_B_SCI2CM
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:6	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_ENG_INTR2_MASK.FSILAT.LATCH.LATC.L2(0:6) [0000000]
Bit(s)	FSI1			Dial: Description
0:6	WO_CLEAR

Last Command Trace
Addr:	000000000000082C (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SCMDT
Constant(s):	PERV_FSI_B_SCMDT
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.TRACE_COMMAND(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:31	RO

Last Data Trace
Addr:	0000000000000830 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SDATA
Constant(s):	PERV_FSI_A_SDATA
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.TRACE_DATA(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:31	RO

LBUS Ownership
Addr:	0000000000000830 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SLBUS
Constant(s):	PERV_FSI_A_SLBUS
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	FSI0			Dial: Description
0	WOX			Force_LBUS_ownership
1	WO			Request_LBUS_ownership
2:3	WO			Release_LBUS_ownership
4	WOX			Reset_LBUS_request
5:7	RO			constant=0b000
8:15	WO			Lock_LBUS_access
16:31	RO			constant=0b0000000000000000

Last Data Trace
Addr:	0000000000000830 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SDATA
Constant(s):	PERV_FSI_B_SDATA
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.TRACE_DATA(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:31	RO

LBUS Ownership
Addr:	0000000000000830 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SLBUS
Constant(s):	PERV_FSI_B_SLBUS
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	FSI1			Dial: Description
0	WOX			Force_LBUS_ownership
1	WO			Request_LBUS_ownership
2:3	WO			Release_LBUS_ownership
4	WOX			Reset_LBUS_request
5:7	RO			constant=0b000
8:15	WO			Lock_LBUS_access
16:31	RO			constant=0b0000000000000000

Last FSI data sent Reset
Addr:	0000000000000834 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SLASTD_SRES
Constant(s):	PERV_FSI_A_SLASTD_SRES
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_LOCAL_DATA.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:31	RW

Last FSI data sent Reset
Addr:	0000000000000834 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SLASTD_SRES
Constant(s):	PERV_FSI_B_SLASTD_SRES
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_LOCAL_DATA.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:31	RW

Mailbox to Left Port (Side)
Addr:	0000000000000838 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SMBL
Constant(s):	PERV_FSI_A_SMBL
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.MAIL_BOX_REG_TO_LEFT(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:31	RW

Mailbox to Left Port (Side)
Addr:	0000000000000838 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SMBL
Constant(s):	PERV_FSI_B_SMBL
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_MAIL_BOX_REG.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:31	RW

Old Mail from Left Port (Side)
Addr:	000000000000083C (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SOML
Constant(s):	PERV_FSI_A_SOML
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.MAIL_IN_FR_LEFT(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:31	RO

Set Mailbox to Left Port (Side)
Addr:	000000000000083C (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SSMBL
Constant(s):	PERV_FSI_A_SSMBL
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.MAIL_BOX_REG_TO_LEFT(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:31	WO_OR

Old Mail from Left Port (Side)
Addr:	000000000000083C (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SOML
Constant(s):	PERV_FSI_B_SOML
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.MAIL_IN_FR_LEFT(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:31	RO

Set Mailbox to Left Port (Side)
Addr:	000000000000083C (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SSMBL
Constant(s):	PERV_FSI_B_SSMBL
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_MAIL_BOX_REG.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:31	WO_OR

Clear Mailbox to Left Port (Side)
Addr:	0000000000000840 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SCMBL
Constant(s):	PERV_FSI_A_SCMBL
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.MAIL_BOX_REG_TO_LEFT(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:31	WO_CLEAR

New Mail from Left Port (Side)
Addr:	0000000000000840 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SNML
Constant(s):	PERV_FSI_A_SNML
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.MAIL_IN_FR_LEFT(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:31	RO

Clear Mailbox to Left Port (Side)
Addr:	0000000000000840 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SCMBL
Constant(s):	PERV_FSI_B_SCMBL
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_MAIL_BOX_REG.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:31	WO_CLEAR

New Mail from Left Port (Side)
Addr:	0000000000000840 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SNML
Constant(s):	PERV_FSI_B_SNML
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.MAIL_IN_FR_LEFT(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:31	RO

Mailbox to Right Port (Side)
Addr:	0000000000000844 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SMBR
Constant(s):	PERV_FSI_A_SMBR
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_MAIL_BOX_REG.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:31	RW

Mailbox to Right Port (Side)
Addr:	0000000000000844 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SMBR
Constant(s):	PERV_FSI_B_SMBR
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.MAIL_BOX_REG_TO_RIGHT(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:31	RW

Old Mail from Right Port (Side)
Addr:	0000000000000848 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SOMR
Constant(s):	PERV_FSI_A_SOMR
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.MAIL_IN_FR_RIGHT(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:31	RO

Set Mailbox to Right Port (Side)
Addr:	0000000000000848 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SSMBR
Constant(s):	PERV_FSI_A_SSMBR
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_MAIL_BOX_REG.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:31	WO_OR

Old Mail from Right Port (Side)
Addr:	0000000000000848 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SOMR
Constant(s):	PERV_FSI_B_SOMR
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.MAIL_IN_FR_RIGHT(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:31	RO

Set Mailbox to Right Port (Side)
Addr:	0000000000000848 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SSMBR
Constant(s):	PERV_FSI_B_SSMBR
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.MAIL_BOX_REG_TO_RIGHT(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:31	WO_OR

Clear Mailbox to Right Port (Side)
Addr:	000000000000084C (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SCMBR
Constant(s):	PERV_FSI_A_SCMBR
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_MAIL_BOX_REG.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:31	WO_CLEAR

New Mail from Right Port (Side)
Addr:	000000000000084C (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SNMR
Constant(s):	PERV_FSI_A_SNMR
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.MAIL_IN_FR_RIGHT(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:31	RO

Clear Mailbox to Right Port (Side)
Addr:	000000000000084C (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SCMBR
Constant(s):	PERV_FSI_B_SCMBR
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.MAIL_BOX_REG_TO_RIGHT(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:31	WO_CLEAR

New Mail from Right Port (Side)
Addr:	000000000000084C (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SNMR
Constant(s):	PERV_FSI_B_SNMR
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.MAIL_IN_FR_RIGHT(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:31	RO

cMFSI Remote Slave Interrupt Condition port 0:3 / Clear cMFSI Remote Slave Interrupt Condition port 0:3
Addr:	0000000000000850 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SCRSIC0
Constant(s):	PERV_FSI_A_SCRSIC0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_CMST_REMOTE_SLV_INTR0.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:31	RW_WCLEAR

cMFSI Remote Slave Interrupt Condition port 0:3 / Clear cMFSI Remote Slave Interrupt Condition port 0:3
Addr:	0000000000000850 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SCRSIC0
Constant(s):	PERV_FSI_B_SCRSIC0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_CMST_REMOTE_SLV_INTR0.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:31	RW_WCLEAR

cMFSI Remote Slave Interrupt Condition port 4:7 / Clear cMFSI Remote Slave Interrupt Condition port 4:7
Addr:	0000000000000854 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SCRSIC4
Constant(s):	PERV_FSI_A_SCRSIC4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_CMST_REMOTE_SLV_INTR4.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:31	RW_WCLEAR

cMFSI Remote Slave Interrupt Condition port 4:7 / Clear cMFSI Remote Slave Interrupt Condition port 4:7
Addr:	0000000000000854 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SCRSIC4
Constant(s):	PERV_FSI_B_SCRSIC4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_CMST_REMOTE_SLV_INTR4.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:31	RW_WCLEAR

cMFSI Remote Slave Interrupt Mask port 0:3
Addr:	0000000000000858 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SCRSIM0
Constant(s):	PERV_FSI_A_SCRSIM0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_CMST_REMOTE_SLV_INTR_MASK0.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:31	RW

cMFSI Remote Slave Interrupt Mask port 0:3
Addr:	0000000000000858 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SCRSIM0
Constant(s):	PERV_FSI_B_SCRSIM0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_CMST_REMOTE_SLV_INTR_MASK0.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:31	RW

cMFSI Remote Slave Interrupt Mask port 4:7
Addr:	000000000000085C (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SCRSIM4
Constant(s):	PERV_FSI_A_SCRSIM4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_CMST_REMOTE_SLV_INTR_MASK4.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:31	RW

cMFSI Remote Slave Interrupt Mask port 4:7
Addr:	000000000000085C (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SCRSIM4
Constant(s):	PERV_FSI_B_SCRSIM4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_CMST_REMOTE_SLV_INTR_MASK4.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:31	RW

cMFSI Remote Slave Interrupt Status port 0:3 1)
Addr:	0000000000000860 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SCRSIS0
Constant(s):	PERV_FSI_A_SCRSIS0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.CMST_REMOTE_SLV_INTR_STATUS0(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:31	RO

cMFSI Remote Slave Interrupt Status port 0:3 1)
Addr:	0000000000000860 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SCRSIS0
Constant(s):	PERV_FSI_B_SCRSIS0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.CMST_REMOTE_SLV_INTR_STATUS0(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:31	RO

cMFSI Remote Slave Interrupt Status port 4:7 1)
Addr:	0000000000000864 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SCRSIS4
Constant(s):	PERV_FSI_A_SCRSIS4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.CMST_REMOTE_SLV_INTR_STATUS4(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:31	RO

cMFSI Remote Slave Interrupt Status port 4:7 1)
Addr:	0000000000000864 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SCRSIS4
Constant(s):	PERV_FSI_B_SCRSIS4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.CMST_REMOTE_SLV_INTR_STATUS4(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:31	RO

MFSI Remote Slave Interrupt Condition port 0:3 / Clear MFSI Remote Slave Interrupt Condition port 0:3
Addr:	0000000000000868 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SRSIC0
Constant(s):	PERV_FSI_A_SRSIC0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_PMST_REMOTE_SLV_INTR0.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:31	RW_WCLEAR

MFSI Remote Slave Interrupt Condition port 0:3 / Clear MFSI Remote Slave Interrupt Condition port 0:3
Addr:	0000000000000868 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SRSIC0
Constant(s):	PERV_FSI_B_SRSIC0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_PMST_REMOTE_SLV_INTR0.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:31	RW_WCLEAR

MFSI Remote Slave Interrupt Condition port 4:7 / Clear MFSI Remote Slave Interrupt Condition port 4:7
Addr:	000000000000086C (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SRSIC4
Constant(s):	PERV_FSI_A_SRSIC4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_PMST_REMOTE_SLV_INTR4.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:31	RW_WCLEAR

MFSI Remote Slave Interrupt Condition port 4:7 / Clear MFSI Remote Slave Interrupt Condition port 4:7
Addr:	000000000000086C (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SRSIC4
Constant(s):	PERV_FSI_B_SRSIC4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_PMST_REMOTE_SLV_INTR4.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:31	RW_WCLEAR

MFSI Remote Slave Interrupt Mask port 0:3
Addr:	0000000000000870 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SRSIM0
Constant(s):	PERV_FSI_A_SRSIM0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_PMST_REMOTE_SLV_INTR_MASK0.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:31	RW

MFSI Remote Slave Interrupt Mask port 0:3
Addr:	0000000000000870 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SRSIM0
Constant(s):	PERV_FSI_B_SRSIM0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_PMST_REMOTE_SLV_INTR_MASK0.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:31	RW

MFSI Remote Slave Interrupt Mask port 4:7
Addr:	0000000000000874 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SRSIM4
Constant(s):	PERV_FSI_A_SRSIM4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.Q_PMST_REMOTE_SLV_INTR_MASK4.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:31	RW

MFSI Remote Slave Interrupt Mask port 4:7
Addr:	0000000000000874 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SRSIM4
Constant(s):	PERV_FSI_B_SRSIM4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.Q_PMST_REMOTE_SLV_INTR_MASK4.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:31	RW

MFSI Remote Slave Interrupt Status port 0:3 1)
Addr:	0000000000000878 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SRSIS0
Constant(s):	PERV_FSI_A_SRSIS0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.PMST_REMOTE_SLV_INTR_STATUS0(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:31	RO

MFSI Remote Slave Interrupt Status port 0:3 1)
Addr:	0000000000000878 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SRSIS0
Constant(s):	PERV_FSI_B_SRSIS0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.PMST_REMOTE_SLV_INTR_STATUS0(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:31	RO

MFSI Remote Slave Interrupt Status port 4:7 1)
Addr:	000000000000087C (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SRSIS4
Constant(s):	PERV_FSI_A_SRSIS4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.KL.PMST_REMOTE_SLV_INTR_STATUS4(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:31	RO

MFSI Remote Slave Interrupt Status port 4:7 1)
Addr:	000000000000087C (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SRSIS4
Constant(s):	PERV_FSI_B_SRSIS4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.KL.PMST_REMOTE_SLV_INTR_STATUS4(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:31	RO

FSI SLAVE LLMOD
Addr:	0000000000000900 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_LLMOD
Constant(s):	PERV_FSI_A_LLMOD
Comments:	link layer mode register
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	24	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.AS.LLMO.DY_LLMO.FSILAT.LATCH.LATC.L2(0) [0]
	29:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.AS.LLMO.EFF_LLMO.FSILAT.LATCH.LATC.L2(0:2) [000]
Bit(s)	FSI0			Dial: Description
0:23	RO			constant=0b000000000000000000000000
24	WO			cmux_reset
25:28	RO			constant=0b0000
29	RW			extend_timo
30	RW			disable_gap
31	RW			FSI_A_ASYNC_MODE: asycronous (BMC mode)

FSI SLAVE LLMOD
Addr:	0000000000000900 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_LLMOD
Constant(s):	PERV_FSI_B_LLMOD
Comments:	link layer mode register
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	24	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.AS.LLMO.DY_LLMO.FSILAT.LATCH.LATC.L2(0) [0]
	29:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.AS.LLMO.EFF_LLMO.FSILAT.LATCH.LATC.L2(0:2) [000]
Bit(s)	FSI1			Dial: Description
0:23	RO			constant=0b000000000000000000000000
24	WO			cmux_reset
25:28	RO			constant=0b0000
29	RW			extend_timo
30	RW			disable_gap
31	RW			FSI_B_ASYNC_MODE: asycronous (BMC mode)

FSI SLAVE LLSTAT
Addr:	0000000000000904 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_LLSTAT
Constant(s):	PERV_FSI_A_LLSTAT
Comments:	link layer status register
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_A.COMP.GEN.AS.LLSTA.L.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI0			Dial: Description
0:6	RO			reserved_0
7	RO			no_clk
8:9	RO			reserved_2
10	RO			bad_handshake_at_start
11	RO			timeout
12	RO			lbus_busy
13	RO			opb_busy
14	RO			reserved_3
15	RO			break_pending
16:17	RO			reserved_4
18:19	RO			handshake_state
20:23	RO			cfam_cycle_time
24:27	RO			refclock_status
28:30	RO			reserved_5
31	RO			async_mode

FSI SLAVE LLSTAT
Addr:	0000000000000904 (FSI1)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_LLSTAT
Constant(s):	PERV_FSI_B_LLSTAT
Comments:	link layer status register
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_SLV_B.COMP.GEN.AS.LLSTA.L.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI1			Dial: Description
0:6	RO			reserved_0
7	RO			no_clk
8:9	RO			reserved_2
10	RO			bad_handshake_at_start
11	RO			timeout
12	RO			lbus_busy
13	RO			opb_busy
14	RO			reserved_3
15	RO			break_pending
16:17	RO			reserved_4
18:19	RO			handshake_state
20:23	RO			cfam_cycle_time
24:27	RO			refclock_status
28:30	RO			reserved_5
31	RO			async_mode

Addr:	0000000000000C00 (SCOMFSI0) 0000000000003000 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MMODE
Constant(s):	PERV_FSI_A_MST_0_MMODE PERV_FSISHIFT_FSI_A_MST_0_MMODE
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_MODE_REG.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	RW	RW		FSI_A_MST_0_ENABLE_IPOLL_AND_DMA: enable ipoll and DMA
1	RW	RW		FSI_A_MST_0_ENABLE_HW_ERROR_RECOVERY: enable hardware error recovery
2	RW	RW		FSI_A_MST_0_ENABLE_RELATIVE_ADDRESS_CMDS: enable relative addressing
3	RW	RW		FSI_A_MST_0_ENABLE_PARITY_CHECK: enable parity checking
4:13	RW	RW		FSI_A_MST_0_CLOCK_RATE_SELECTION_0: clock rate selection 0
14:23	RW	RW		FSI_A_MST_0_CLOCK_RATE_SELECTION_1: clock rate selection 1
24	RW	RW
25	RW	RW		FSI_A_MST_0_CLOCK_DIV_4: clock divided by 4 mode (default off is for legacy/ as fall back)
26:27	RW	RW		FSI_A_MST_0_TIMEOUT_SEL: 0b00: for PIB only 1ms; 0b01: 0.9ms; 0b10: 0.8ms; 0b11 as measured previously (see workbook) Dial enums: TO_1M_PIB_ONLY=>0b00 TO_0_9=>0b01 TO_0_8=>0b10 TO_AS_MEASURED=>0b11
28	RW	RW		Dial enums: TO_1M_PIB_ONLY=>0b00 TO_0_9=>0b01 TO_0_8=>0b10 TO_AS_MEASURED=>0b11
29:31	RW	RW		FSI_A_MST_0_RECEIVER_MODE: receiver mode / several settings in case of problems Dial enums: AUTO=>0b000 AUTO_NO_SW_ON_FAIL=>0b001 AUTO_AT_START_ONLY_NO_SW_ON_FAIL=>0b100 AUTO_AT_START_ONLY_NO_SW_ON_BAD_QUALITY=>0b101 FIX_RISE=>0b010 FIX_FALL=>0b011

contains command to the shift engine
Addr:	0000000000000C01 (FSI) 0000000000000C04 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SHIFT.COMMAND_REGISTER
Constant(s):	PERV_FSISHIFT_COMMAND_REGISTER
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SHIFT.COMP.CMD.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0	RWX	RWX		CMDREG_WRITE_FLAG: write flag: if set then engine performs a scan-in operation
1	RWX	RWX		CMDREG_BROADCAST_FLAG: broadcast flag: notice: if set then header check shall be disabled
2:15	RWX	RWX		CMDREG_SCAN_ADDRESS: scan address
16:27	RWX	RWX		CMDREG_SCAN_REGION: scan region
28:31	RWX	RWX		CMDREG_SCAN_TYPE: encoded scan type

Addr:	0000000000000C01 (SCOMFSI0) 0000000000003004 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MDLYR
Constant(s):	PERV_FSI_A_MST_0_MDLYR PERV_FSISHIFT_FSI_A_MST_0_MDLYR
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_DLY_REG.FSILAT.LATCH.LATC.L2(0:15) [0000000000000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:15	RW	RW
16:31	RO	RO		constant=0b0000000000000000

contains number of bits to be shifted
Addr:	0000000000000C02 (FSI) 0000000000000C08 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SHIFT.FRONT_END_LENGTH_REGISTER
Constant(s):	PERV_FSISHIFT_FRONT_END_LENGTH_REGISTER
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_SHIFT.COMP.CONTROL_LTH.FSILAT.LATCH.LATC.L2(0:7) [00000000]
	8:31	TP.TPVSB.FSI.W.FSI_SHIFT.COMP.REFCNT.CNTREG.FSILAT.LATCH.LATC.L2(0:23) [000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:7	RWX	RWX		control_bits control
8:31	RWX	RWX		front_end_length front end length

Addr:	0000000000000C02 (SCOMFSI0) 0000000000003008 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MCRSP0
Constant(s):	PERV_FSI_A_MST_0_MCRSP0 PERV_FSISHIFT_FSI_A_MST_0_MCRSP0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_CLK_SEL.FSILAT.LATCH.LATC.L2(0:7) [00000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:7	RW	RW
8:31	RO	RO		constant=0b000000000000000000000000

returns the content of the buffer placed between FIFO and scan data
Addr:	0000000000000C03 (FSI) 0000000000000C0C (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SHIFT.READ_BUFFER
Constant(s):	PERV_FSISHIFT_READ_BUFFER
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SHIFT.COMP.R_BUF.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	ROX	ROX		READ_BUFFER_REG: Read receive buffer

Addr:	0000000000000C03 (SCOMFSI0) 000000000000300C (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MCRSP1
Constant(s):	PERV_FSI_A_MST_0_MCRSP1 PERV_FSISHIFT_FSI_A_MST_0_MCRSP1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

Addr:	0000000000000C04 (SCOMFSI0) 0000000000003010 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MENP0
Constant(s):	PERV_FSI_A_MST_0_MENP0 PERV_FSISHIFT_FSI_A_MST_0_MENP0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_PRT_ENABLE.FSILAT.LATCH.LATC.L2(0:7) [00000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	RW	RW		FSI_A_MST_0_PORT_0_ENABLE: enable Master port 0 enable
1	RW	RW		FSI_A_MST_0_PORT_1_ENABLE: enable Master port 0 enable
2	RW	RW		FSI_A_MST_0_PORT_2_ENABLE: enable Master port 0 enable
3	RW	RW		FSI_A_MST_0_PORT_3_ENABLE: enable Master port 0 enable
4	RW	RW		FSI_A_MST_0_PORT_4_ENABLE: enable Master port 0 enable
5	RW	RW		FSI_A_MST_0_PORT_5_ENABLE: enable Master port 0 enable
6	RW	RW		FSI_A_MST_0_PORT_6_ENABLE: enable Master port 0 enable
7	RW	RW		FSI_A_MST_0_PORT_7_ENABLE: enable Master port 0 enable
8:31	RO	RO		constant=0b000000000000000000000000

Addr:	0000000000000C05 (SCOMFSI0) 0000000000003014 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MENP1
Constant(s):	PERV_FSI_A_MST_0_MENP1 PERV_FSISHIFT_FSI_A_MST_0_MENP1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

Reset all regs
Addr:	0000000000000C06 (FSI) 0000000000000C18 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SHIFT.RESET
Constant(s):	PERV_FSISHIFT_RESET
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0	WOX_1P	WOX_1P		reset Reset

Addr:	0000000000000C06 (SCOMFSI0) 0000000000003018 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MLEVP0
Constant(s):	PERV_FSI_A_MST_0_MLEVP0 PERV_FSISHIFT_FSI_A_MST_0_MLEVP0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.COMMON_PRT_STATUS_RD(0:31) [00000000000000000000000000000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	ROX	ROX		port_level_0
1	ROX	ROX		port_level_1
2	ROX	ROX		port_level_2
3	ROX	ROX		port_level_3
4	ROX	ROX		port_level_4
5	ROX	ROX		port_level_5
6	ROX	ROX		port_level_6
7	ROX	ROX		port_level_7
8:31	RO	RO

Addr:	0000000000000C06 (SCOMFSI0) 0000000000003018 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSENP0
Constant(s):	PERV_FSI_A_MST_0_MSENP0 PERV_FSISHIFT_FSI_A_MST_0_MSENP0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_PRT_ENABLE.FSILAT.LATCH.LATC.L2(0:7) [00000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	WO_OR	WO_OR		FSI_A_MST_0_PORT_0_ENABLE: enable Master port 0 enable
1	WO_OR	WO_OR		FSI_A_MST_0_PORT_1_ENABLE: enable Master port 0 enable
2	WO_OR	WO_OR		FSI_A_MST_0_PORT_2_ENABLE: enable Master port 0 enable
3	WO_OR	WO_OR		FSI_A_MST_0_PORT_3_ENABLE: enable Master port 0 enable
4	WO_OR	WO_OR		FSI_A_MST_0_PORT_4_ENABLE: enable Master port 0 enable
5	WO_OR	WO_OR		FSI_A_MST_0_PORT_5_ENABLE: enable Master port 0 enable
6	WO_OR	WO_OR		FSI_A_MST_0_PORT_6_ENABLE: enable Master port 0 enable
7	WO_OR	WO_OR		FSI_A_MST_0_PORT_7_ENABLE: enable Master port 0 enable
8:31	RO	RO		constant=0b000000000000000000000000

Reset errors
Addr:	0000000000000C07 (FSI) 0000000000000C1C (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SHIFT.RESET_ERRORS
Constant(s):	PERV_FSISHIFT_RESET_ERRORS
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0	WOX_1P	WOX_1P		reset_errors Reset errors

status register
Addr:	0000000000000C07 (FSI) 0000000000000C1C (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SHIFT.STATUS
Constant(s):	PERV_FSISHIFT_STATUS
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPVSB.FSI.W.FSI_SHIFT.COMP.STATUS(0) [0]
	1:12	TP.TPVSB.FSI.W.FSI_SHIFT.COMP.SREG.FSILAT.LATCH.LATC.L2(0:11) [000000000000]
	13:14	TP.TPVSB.FSI.W.FSI_SHIFT.COMP.STATUS(13:14) [00]
	15:23	TP.TPVSB.FSI.W.FSI_SHIFT.COMP.SREG.FSILAT.LATCH.LATC.L2(14:22) [000000000]
	24:28	TP.TPVSB.FSI.W.FSI_SHIFT.COMP.STATUS(24:28) [00000]
	29:31	TP.TPVSB.FSI.W.FSI_SHIFT.COMP.FIFOLVL.CNTREG.FSILAT.LATCH.LATC.L2(0:2) [000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	ROX	ROX		status__register Bit0 : Front end count NOT zero (also readable via peek engine) Bit1 : Command address parity (LBUS address) (also readable via peek engine) Bit2 : Back end parity (data read from FIFO has incorrect parity) (also readable via peek engine) Bit3-4 : 3:FIFO overrun, 4: FIFO underrun; any active bit would indicate a hardware error Bit5 : Command overrun (also readable via peek engine) Bit6 : Header check failed: TP scan: receive_buffer(32:39) != 0xA5; PIB scan receive_buffer(0:31) != 0xA5A55A5A Bit7-9 : Reserved Bit10 : internal state machine busy Bit11 : No zeros detected during shift Bit12 : No ones detected during shift Bit13-14 : Reserved Bit15 : Protection check Bit16 : Reserved Bit17-19 : PCB/PIB error condition Bit20 : Parity error on incoming data Bit21 : PIB abort Bit22-23 : Reserved Bit24-31 : FIFO level

Addr:	0000000000000C07 (SCOMFSI0) 000000000000301C (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MLEVP1
Constant(s):	PERV_FSI_A_MST_0_MLEVP1 PERV_FSISHIFT_FSI_A_MST_0_MLEVP1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.COMMON_PRT_STATUS_RD(32:63) [00000000000000000000000000000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	ROX	ROX		port_level_0
1	ROX	ROX		port_level_1
2	ROX	ROX		port_level_2
3	ROX	ROX		port_level_3
4	ROX	ROX		port_level_4
5	ROX	ROX		port_level_5
6	ROX	ROX		port_level_6
7	ROX	ROX		port_level_7
8:31	RO	RO

extra status
Addr:	0000000000000C08 (FSI) 0000000000000C20 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SHIFT.EXTENDED_STATUS
Constant(s):	PERV_FSISHIFT_EXTENDED_STATUS
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	16	TP.TPVSB.FSI.W.FSI_SHIFT.COMP.EXT_STATUS(16) [0]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:15	RO	RO		constant=0b0000000000000100
16	ROX	ROX		residual_fe_cnt_is_zero Residual FE Count equal to zero
17:31	RO	RO		constant=0b000000000000001

Addr:	0000000000000C08 (SCOMFSI0) 0000000000003020 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MCENP0
Constant(s):	PERV_FSI_A_MST_0_MCENP0 PERV_FSISHIFT_FSI_A_MST_0_MCENP0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_PRT_ENABLE.FSILAT.LATCH.LATC.L2(0:7) [00000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	WO_CLEAR	WO_CLEAR		FSI_A_MST_0_PORT_0_ENABLE: enable Master port 0 enable
1	WO_CLEAR	WO_CLEAR		FSI_A_MST_0_PORT_1_ENABLE: enable Master port 0 enable
2	WO_CLEAR	WO_CLEAR		FSI_A_MST_0_PORT_2_ENABLE: enable Master port 0 enable
3	WO_CLEAR	WO_CLEAR		FSI_A_MST_0_PORT_3_ENABLE: enable Master port 0 enable
4	WO_CLEAR	WO_CLEAR		FSI_A_MST_0_PORT_4_ENABLE: enable Master port 0 enable
5	WO_CLEAR	WO_CLEAR		FSI_A_MST_0_PORT_5_ENABLE: enable Master port 0 enable
6	WO_CLEAR	WO_CLEAR		FSI_A_MST_0_PORT_6_ENABLE: enable Master port 0 enable
7	WO_CLEAR	WO_CLEAR		FSI_A_MST_0_PORT_7_ENABLE: enable Master port 0 enable
8:31	RO	RO		constant=0b000000000000000000000000

Addr:	0000000000000C08 (SCOMFSI0) 0000000000003020 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MREFP0
Constant(s):	PERV_FSI_A_MST_0_MREFP0 PERV_FSISHIFT_FSI_A_MST_0_MREFP0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.COMMON_PRT_STATUS_RD(0:31) [00000000000000000000000000000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	ROX	ROX		port_hot_plug_0
1	ROX	ROX		port_hot_plug_1
2	ROX	ROX		port_hot_plug_2
3	ROX	ROX		port_hot_plug_3
4	ROX	ROX		port_hot_plug_4
5	ROX	ROX		port_hot_plug_5
6	ROX	ROX		port_hot_plug_6
7	ROX	ROX		port_hot_plug_7
8:31	RO	RO

CFAM CHIP ID
Addr:	0000000000000C09 (FSI) 0000000000000C24 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SHIFT.CHIP_ID
Constant(s):	PERV_FSISHIFT_CHIP_ID
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:19	TP.TPVSB.FSI.W.FSI_SHIFT.COMP.ID_REG(0:19) [00000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:19	ROX	ROX		cfam_chip_id CHIP ID comes from outside
20:31	RO	RO		constant=0b000001001001

Addr:	0000000000000C09 (SCOMFSI0) 0000000000003024 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MREFP1
Constant(s):	PERV_FSI_A_MST_0_MREFP1 PERV_FSISHIFT_FSI_A_MST_0_MREFP1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.COMMON_PRT_STATUS_RD(32:63) [00000000000000000000000000000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	ROX	ROX		port_hot_plug_0
1	ROX	ROX		port_hot_plug_1
2	ROX	ROX		port_hot_plug_2
3	ROX	ROX		port_hot_plug_3
4	ROX	ROX		port_hot_plug_4
5	ROX	ROX		port_hot_plug_5
6	ROX	ROX		port_hot_plug_6
7	ROX	ROX		port_hot_plug_7
8:31	RO	RO

Complement mask register
Addr:	0000000000000C0C (FSI) 0000000000000C30 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SHIFT.COMPLEMENT_MASK
Constant(s):	PERV_FSISHIFT_COMPLEMENT_MASK
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SHIFT.COMP.CM.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	RWX	RWX		COMPLEMENT_MASK_REG: Complement Mask for controlling generation of interrupts

Addr:	0000000000000C0C (SCOMFSI0) 0000000000003030 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSIEP0
Constant(s):	PERV_FSI_A_MST_0_MSIEP0 PERV_FSISHIFT_FSI_A_MST_0_MSIEP0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_SLV_INTR_ENABLE.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RW	RW

True Mask Register
Addr:	0000000000000C0D (FSI) 0000000000000C34 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SHIFT.TRUE_MASK
Constant(s):	PERV_FSISHIFT_TRUE_MASK
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SHIFT.COMP.TM.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	RWX	RWX		TRUE_MASK_REG: True Mask for controlling generation of interrupts

Addr:	0000000000000C0D (SCOMFSI0) 0000000000003034 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSIEP1
Constant(s):	PERV_FSI_A_MST_0_MSIEP1 PERV_FSISHIFT_FSI_A_MST_0_MSIEP1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

Addr:	0000000000000C0E (SCOMFSI0) 0000000000003038 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSIEP2
Constant(s):	PERV_FSI_A_MST_0_MSIEP2 PERV_FSISHIFT_FSI_A_MST_0_MSIEP2
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

Addr:	0000000000000C0F (SCOMFSI0) 000000000000303C (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSIEP3
Constant(s):	PERV_FSI_A_MST_0_MSIEP3 PERV_FSISHIFT_FSI_A_MST_0_MSIEP3
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

Shift control register
Addr:	0000000000000C10 (FSI) 0000000000000C40 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SHIFT.SHIFT_CONTROL_REGISTER_2
Constant(s):	PERV_FSISHIFT_SHIFT_CONTROL_REGISTER_2
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SHIFT.COMP.CTRL2.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	RWX	RWX		SHIFT_CONTROL_REGISTER: Controls the length of the set pulse

Addr:	0000000000000C10 (SCOMFSI0) 0000000000003040 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSIEP4
Constant(s):	PERV_FSI_A_MST_0_MSIEP4 PERV_FSISHIFT_FSI_A_MST_0_MSIEP4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

Addr:	0000000000000C11 (SCOMFSI0) 0000000000003044 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSIEP5
Constant(s):	PERV_FSI_A_MST_0_MSIEP5 PERV_FSISHIFT_FSI_A_MST_0_MSIEP5
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

Addr:	0000000000000C12 (SCOMFSI0) 0000000000003048 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSIEP6
Constant(s):	PERV_FSI_A_MST_0_MSIEP6 PERV_FSISHIFT_FSI_A_MST_0_MSIEP6
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

Addr:	0000000000000C13 (SCOMFSI0) 000000000000304C (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSIEP7
Constant(s):	PERV_FSI_A_MST_0_MSIEP7 PERV_FSISHIFT_FSI_A_MST_0_MSIEP7
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

Addr:	0000000000000C14 (SCOMFSI0) 0000000000003050 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MAESP0
Constant(s):	PERV_FSI_A_MST_0_MAESP0 PERV_FSISHIFT_FSI_A_MST_0_MAESP0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.ANY_PRT_ERROR_RD(0:31) [00000000000000000000000000000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO

Addr:	0000000000000C14 (SCOMFSI0) 0000000000003050 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSSIEP0
Constant(s):	PERV_FSI_A_MST_0_MSSIEP0 PERV_FSISHIFT_FSI_A_MST_0_MSSIEP0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_SLV_INTR_ENABLE.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	WO_OR	WO_OR

Addr:	0000000000000C15 (SCOMFSI0) 0000000000003054 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MAESP1
Constant(s):	PERV_FSI_A_MST_0_MAESP1 PERV_FSISHIFT_FSI_A_MST_0_MAESP1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

Addr:	0000000000000C16 (SCOMFSI0) 0000000000003058 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MAESP2
Constant(s):	PERV_FSI_A_MST_0_MAESP2 PERV_FSISHIFT_FSI_A_MST_0_MAESP2
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

Addr:	0000000000000C17 (SCOMFSI0) 000000000000305C (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MAESP3
Constant(s):	PERV_FSI_A_MST_0_MAESP3 PERV_FSISHIFT_FSI_A_MST_0_MAESP3
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

Addr:	0000000000000C18 (SCOMFSI0) 0000000000003060 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MAESP4
Constant(s):	PERV_FSI_A_MST_0_MAESP4 PERV_FSISHIFT_FSI_A_MST_0_MAESP4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

DMA mode register
Addr:	0000000000000C19 (FSI) 0000000000000C64 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SHIFT.DMA_MODE_REGISTER
Constant(s):	PERV_FSISHIFT_DMA_MODE_REGISTER
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SHIFT.COMP.DMA_MODE_LTH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0	RW	RW		DMA_MODE_REG_ENABLE: enables DMA mode for DMA-based CFAM init
1	RW	RW		DMA_MODE_REG_FIFO_SIZE_EQ_1: set FIFO size to 1 (for debugging purposes)
2:31	RW	RW		DMA_MODE_REG_UNUSED: Reserved

Addr:	0000000000000C19 (SCOMFSI0) 0000000000003064 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MAESP5
Constant(s):	PERV_FSI_A_MST_0_MAESP5 PERV_FSISHIFT_FSI_A_MST_0_MAESP5
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

DMA status compare mask register
Addr:	0000000000000C1A (FSI) 0000000000000C68 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SHIFT.DMA_STAT_COMP_MASK_REGISTER
Constant(s):	PERV_FSISHIFT_DMA_STAT_COMP_MASK_REGISTER
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SHIFT.COMP.DMA_STAT_COMP_MASK_LTH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	RW	RW		DMA_STAT_COMP_MASK_REG: defines the error bits of the status register (for debugging purposes)

Addr:	0000000000000C1A (SCOMFSI0) 0000000000003068 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MAESP6
Constant(s):	PERV_FSI_A_MST_0_MAESP6 PERV_FSISHIFT_FSI_A_MST_0_MAESP6
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

DMA OP/BLOCKSIZE register
Addr:	0000000000000C1B (FSI) 0000000000000C6C (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SHIFT.DMA_OP_BLOCKSIZE_REGISTER
Constant(s):	PERV_FSISHIFT_DMA_OP_BLOCKSIZE_REGISTER
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SHIFT.COMP.DMA_OP_BLOCKSIZE_LTH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:7	ROX	ROX		DMA_OP_BLOCKSIZE_OPCODE: operation code of block command (for debugging purposes)
8:31	ROX	ROX		DMA_OP_BLOCKSIZE_SIZE: size of block command (for debugging purposes)

Addr:	0000000000000C1B (SCOMFSI0) 000000000000306C (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MAESP7
Constant(s):	PERV_FSI_A_MST_0_MAESP7 PERV_FSISHIFT_FSI_A_MST_0_MAESP7
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

DMA remaining size register
Addr:	0000000000000C1C (FSI) 0000000000000C70 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SHIFT.DMA_REM_SIZE_REGISTER
Constant(s):	PERV_FSISHIFT_DMA_REM_SIZE_REGISTER
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	8:31	TP.TPVSB.FSI.W.FSI_SHIFT.COMP.DMA_REMSIZE_CTR_LTH.CNTREG.FSILAT.LATCH.LATC.L2(0:23) [000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:7	RO	RO		constant=0b00000000
8:31	ROX	ROX		DMA_REM_SIZE_REMAINING_WORDS: number of 32bit words to be executed to complete block command

Addr:	0000000000000C1C (SCOMFSI0) 0000000000003070 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MAEB
Constant(s):	PERV_FSI_A_MST_0_MAEB PERV_FSISHIFT_FSI_A_MST_0_MAEB
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	RO	RO		bridge_error
1:23	RO	RO		constant=0b00000000000000000000000

Addr:	0000000000000C1C (SCOMFSI0) 0000000000003070 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MCSIEP0
Constant(s):	PERV_FSI_A_MST_0_MCSIEP0 PERV_FSISHIFT_FSI_A_MST_0_MCSIEP0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_SLV_INTR_ENABLE.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	WO_CLEAR	WO_CLEAR

DMA PIB send data0 register
Addr:	0000000000000C1D (FSI) 0000000000000C74 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SHIFT.DMA_PIB_SND_BUFFER0_REGISTER
Constant(s):	PERV_FSISHIFT_DMA_PIB_SND_BUFFER0_REGISTER
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SHIFT.COMP.DMA_PIB_SND_BUF0_LTH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	ROX	ROX		DMA_PIB_SND_BUF0_REG_DATA0: holds the data to be sent to PIB (for debugging purposes)

Addr:	0000000000000C1D (SCOMFSI0) 0000000000003074 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MVER
Constant(s):	PERV_FSI_A_MST_0_MVER PERV_FSISHIFT_FSI_A_MST_0_MVER
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b10010010000000010000100000000000

DMA PIB send data1 register
Addr:	0000000000000C1E (FSI) 0000000000000C78 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SHIFT.DMA_PIB_SND_BUFFER1_REGISTER
Constant(s):	PERV_FSISHIFT_DMA_PIB_SND_BUFFER1_REGISTER
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SHIFT.COMP.DMA_PIB_SND_BUF1_LTH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	ROX	ROX		DMA_PIB_SND_BUF1_REG_DATA0: holds the data to be sent to PIB (for debugging purposes)

DMA PIB receive data0 register
Addr:	0000000000000C1F (FSI) 0000000000000C7C (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SHIFT.DMA_PIB_RCV_BUFFER0_REGISTER
Constant(s):	PERV_FSISHIFT_DMA_PIB_RCV_BUFFER0_REGISTER
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SHIFT.COMP.DMA_PIB_RCV_BUF0_LTH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	ROX	ROX		DMA_PIB_RCV_BUF0_REG_DATA0: buffers the read data from PIB (for debugging purposes)

DMA PIB receive data1 register
Addr:	0000000000000C20 (FSI) 0000000000000C80 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SHIFT.DMA_PIB_RCV_BUFFER1_REGISTER
Constant(s):	PERV_FSISHIFT_DMA_PIB_RCV_BUFFER1_REGISTER
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SHIFT.COMP.DMA_PIB_RCV_BUF1_LTH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	ROX	ROX		DMA_PIB_RCV_BUF1_REG_DATA1: buffers the read data from PIB (for debugging purposes)

DMA error pointer register
Addr:	0000000000000C21 (FSI) 0000000000000C84 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SHIFT.DMA_ERROR_PTR_REGISTER
Constant(s):	PERV_FSISHIFT_DMA_ERROR_PTR_REGISTER
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SHIFT.COMP.DMA_ERROR_PTR_LTH.CNTREG.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	ROX	ROX		DMA_ERROR_PTR_REG: points to the last loaded block command word (for debugging purposes)

DMA SCOM command register
Addr:	0000000000000C22 (FSI) 0000000000000C88 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SHIFT.DMA_SCOM_CMD_REGISTER
Constant(s):	PERV_FSISHIFT_DMA_SCOM_CMD_REGISTER
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SHIFT.COMP.DMA_SCOM_CMD_LTH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	ROX	ROX		DMA_SCOM_CMD_REG: holds the SCOM command (for debugging purposes)

Addr:	0000000000000C34 (SCOMFSI0) 00000000000030D0 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MRESP0
Constant(s):	PERV_FSI_A_MST_0_MRESP0 PERV_FSISHIFT_FSI_A_MST_0_MRESP0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.GEN_RESET_TO_PRT_D(0) [0]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	WOX	WOX		port_general_reset
1	WOX	WOX		port_error_reset
2	WOX	WOX		all_bridge_general_reset
3	WOX	WOX		all_port_general_reset
4	WOX	WOX		control_register_reset
5	WOX	WOX		parity_error_reset
6:31	RO	RO		constant=0b00000000000000000000000000

Addr:	0000000000000C34 (SCOMFSI0) 00000000000030D0 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSTAP0
Constant(s):	PERV_FSI_A_MST_0_MSTAP0 PERV_FSISHIFT_FSI_A_MST_0_MSTAP0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#0.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(0:2) [000]
	5:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#0.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(3:5) [000]
	9:11	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#0.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(6:8) [000]
	13:15	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#0.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(9:11) [000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	RO	RO		constant=0b0
1:3	RO	RO		FSI_A_MST_0_PORT0_ERROR_CODE_0: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
4	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
5:7	RO	RO		FSI_A_MST_0_PORT0_ERROR_CODE_1: error code 0 MFSI port 0 (error code: 0 first, 3 last) error code 1 MFSI port 0 (error code: 0 first, 3 last) error code 2 MFSI port 0 (error code: 0 first, 3 last) Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
8	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
9:11	RO	RO		FSI_A_MST_0_PORT0_ERROR_CODE_2: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
12	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
13:15	RO	RO		fourth_error Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
16:19	RO	RO		crc_error_count Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
20	RO	RO		hot_plug_flag Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
21:31	RO	RO		constant=0b00000000000 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110

Addr:	0000000000000C35 (SCOMFSI0) 00000000000030D4 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MRESP1
Constant(s):	PERV_FSI_A_MST_0_MRESP1 PERV_FSISHIFT_FSI_A_MST_0_MRESP1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_GEN_RESET_TO_PRT.FSILAT.LATCH.LATC.L2(1) [0]
	1	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_ERR_RESET_TO_PRT.FSILAT.LATCH.LATC.L2(1) [0]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	WOX	WOX		FSI_A_MST_0_PORT_GENERAL_RESET_1: port 1 general reset
1	WOX	WOX		FSI_A_MST_0_PORT_ERROR_RESET_1: port 1 error reset
2:31	RO	RO		constant=0b000000000000000000000000000000

Addr:	0000000000000C35 (SCOMFSI0) 00000000000030D4 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSTAP1
Constant(s):	PERV_FSI_A_MST_0_MSTAP1 PERV_FSISHIFT_FSI_A_MST_0_MSTAP1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#1.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(0:2) [000]
	5:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#1.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(3:5) [000]
	9:11	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#1.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(6:8) [000]
	13:15	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#1.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(9:11) [000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	RO	RO		constant=0b0
1:3	RO	RO		FSI_A_MST_0_PORT1_ERROR_CODE_0: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
4	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
5:7	RO	RO		FSI_A_MST_0_PORT1_ERROR_CODE_1: error code 0 MFSI port 1 (error code: 0 first, 3 last) error code 1 MFSI port 1 (error code: 0 first, 3 last) error code 2 MFSI port 1 (error code: 0 first, 3 last) Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
8	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
9:11	RO	RO		FSI_A_MST_0_PORT1_ERROR_CODE_2: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
12	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
13:15	RO	RO		fourth_error Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
16:19	RO	RO		crc_error_count Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
20	RO	RO		hot_plug_flag Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
21:31	RO	RO		constant=0b00000000000 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110

Addr:	0000000000000C36 (SCOMFSI0) 00000000000030D8 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MRESP2
Constant(s):	PERV_FSI_A_MST_0_MRESP2 PERV_FSISHIFT_FSI_A_MST_0_MRESP2
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_GEN_RESET_TO_PRT.FSILAT.LATCH.LATC.L2(2) [0]
	1	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_ERR_RESET_TO_PRT.FSILAT.LATCH.LATC.L2(2) [0]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	WOX	WOX		FSI_A_MST_0_PORT_GENERAL_RESET_2: port 2 general reset
1	WOX	WOX		FSI_A_MST_0_PORT_ERROR_RESET_2: port 2 error reset
2:31	RO	RO		constant=0b000000000000000000000000000000

Addr:	0000000000000C36 (SCOMFSI0) 00000000000030D8 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSTAP2
Constant(s):	PERV_FSI_A_MST_0_MSTAP2 PERV_FSISHIFT_FSI_A_MST_0_MSTAP2
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#2.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(0:2) [000]
	5:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#2.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(3:5) [000]
	9:11	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#2.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(6:8) [000]
	13:15	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#2.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(9:11) [000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	RO	RO		constant=0b0
1:3	RO	RO		FSI_A_MST_0_PORT2_ERROR_CODE_0: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
4	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
5:7	RO	RO		FSI_A_MST_0_PORT2_ERROR_CODE_1: error code 0 MFSI port 2 (error code: 0 first, 3 last) error code 1 MFSI port 2 (error code: 0 first, 3 last) error code 2 MFSI port 2 (error code: 0 first, 3 last) Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
8	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
9:11	RO	RO		FSI_A_MST_0_PORT2_ERROR_CODE_2: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
12	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
13:15	RO	RO		fourth_error Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
16:19	RO	RO		crc_error_count Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
20	RO	RO		hot_plug_flag Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
21:31	RO	RO		constant=0b00000000000 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110

Addr:	0000000000000C37 (SCOMFSI0) 00000000000030DC (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MRESP3
Constant(s):	PERV_FSI_A_MST_0_MRESP3 PERV_FSISHIFT_FSI_A_MST_0_MRESP3
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_GEN_RESET_TO_PRT.FSILAT.LATCH.LATC.L2(3) [0]
	1	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_ERR_RESET_TO_PRT.FSILAT.LATCH.LATC.L2(3) [0]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	WOX	WOX		FSI_A_MST_0_PORT_GENERAL_RESET_3: port 3 general reset
1	WOX	WOX		FSI_A_MST_0_PORT_ERROR_RESET_3: port 3 error reset
2:31	RO	RO		constant=0b000000000000000000000000000000

Addr:	0000000000000C37 (SCOMFSI0) 00000000000030DC (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSTAP3
Constant(s):	PERV_FSI_A_MST_0_MSTAP3 PERV_FSISHIFT_FSI_A_MST_0_MSTAP3
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#3.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(0:2) [000]
	5:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#3.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(3:5) [000]
	9:11	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#3.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(6:8) [000]
	13:15	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#3.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(9:11) [000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	RO	RO		constant=0b0
1:3	RO	RO		FSI_A_MST_0_PORT3_ERROR_CODE_0: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
4	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
5:7	RO	RO		FSI_A_MST_0_PORT3_ERROR_CODE_1: error code 0 MFSI port 3 (error code: 0 first, 3 last) error code 1 MFSI port 3 (error code: 0 first, 3 last) error code 2 MFSI port 3 (error code: 0 first, 3 last) Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
8	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
9:11	RO	RO		FSI_A_MST_0_PORT3_ERROR_CODE_2: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
12	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
13:15	RO	RO		fourth_error Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
16:19	RO	RO		crc_error_count Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
20	RO	RO		hot_plug_flag Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
21:31	RO	RO		constant=0b00000000000 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110

Addr:	0000000000000C38 (SCOMFSI0) 00000000000030E0 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MRESP4
Constant(s):	PERV_FSI_A_MST_0_MRESP4 PERV_FSISHIFT_FSI_A_MST_0_MRESP4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_GEN_RESET_TO_PRT.FSILAT.LATCH.LATC.L2(4) [0]
	1	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_ERR_RESET_TO_PRT.FSILAT.LATCH.LATC.L2(4) [0]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	WOX	WOX		FSI_A_MST_0_PORT_GENERAL_RESET_4: port 4 general reset
1	WOX	WOX		FSI_A_MST_0_PORT_ERROR_RESET_4: port 4 error reset
2:31	RO	RO		constant=0b000000000000000000000000000000

Addr:	0000000000000C38 (SCOMFSI0) 00000000000030E0 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSTAP4
Constant(s):	PERV_FSI_A_MST_0_MSTAP4 PERV_FSISHIFT_FSI_A_MST_0_MSTAP4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#4.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(0:2) [000]
	5:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#4.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(3:5) [000]
	9:11	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#4.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(6:8) [000]
	13:15	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#4.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(9:11) [000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	RO	RO		constant=0b0
1:3	RO	RO		FSI_A_MST_0_PORT4_ERROR_CODE_0: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
4	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
5:7	RO	RO		FSI_A_MST_0_PORT4_ERROR_CODE_1: error code 0 MFSI port 4 (error code: 0 first, 3 last) error code 1 MFSI port 4 (error code: 0 first, 3 last) error code 2 MFSI port 4 (error code: 0 first, 3 last) Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
8	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
9:11	RO	RO		FSI_A_MST_0_PORT4_ERROR_CODE_2: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
12	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
13:15	RO	RO		fourth_error Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
16:19	RO	RO		crc_error_count Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
20	RO	RO		hot_plug_flag Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
21:31	RO	RO		constant=0b00000000000 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110

Addr:	0000000000000C39 (SCOMFSI0) 00000000000030E4 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MRESP5
Constant(s):	PERV_FSI_A_MST_0_MRESP5 PERV_FSISHIFT_FSI_A_MST_0_MRESP5
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_GEN_RESET_TO_PRT.FSILAT.LATCH.LATC.L2(5) [0]
	1	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_ERR_RESET_TO_PRT.FSILAT.LATCH.LATC.L2(5) [0]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	WOX	WOX		FSI_A_MST_0_PORT_GENERAL_RESET_5: port 5 general reset
1	WOX	WOX		FSI_A_MST_0_PORT_ERROR_RESET_5: port 5 error reset
2:31	RO	RO		constant=0b000000000000000000000000000000

Addr:	0000000000000C39 (SCOMFSI0) 00000000000030E4 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSTAP5
Constant(s):	PERV_FSI_A_MST_0_MSTAP5 PERV_FSISHIFT_FSI_A_MST_0_MSTAP5
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#5.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(0:2) [000]
	5:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#5.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(3:5) [000]
	9:11	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#5.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(6:8) [000]
	13:15	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#5.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(9:11) [000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	RO	RO		constant=0b0
1:3	RO	RO		FSI_A_MST_0_PORT5_ERROR_CODE_0: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
4	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
5:7	RO	RO		FSI_A_MST_0_PORT5_ERROR_CODE_1: error code 0 MFSI port 5 (error code: 0 first, 3 last) error code 1 MFSI port 5 (error code: 0 first, 3 last) error code 2 MFSI port 5 (error code: 0 first, 3 last) Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
8	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
9:11	RO	RO		FSI_A_MST_0_PORT5_ERROR_CODE_2: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
12	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
13:15	RO	RO		fourth_error Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
16:19	RO	RO		crc_error_count Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
20	RO	RO		hot_plug_flag Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
21:31	RO	RO		constant=0b00000000000 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110

Addr:	0000000000000C3A (SCOMFSI0) 00000000000030E8 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MRESP6
Constant(s):	PERV_FSI_A_MST_0_MRESP6 PERV_FSISHIFT_FSI_A_MST_0_MRESP6
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_GEN_RESET_TO_PRT.FSILAT.LATCH.LATC.L2(6) [0]
	1	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_ERR_RESET_TO_PRT.FSILAT.LATCH.LATC.L2(6) [0]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	WOX	WOX		FSI_A_MST_0_PORT_GENERAL_RESET_6: port 6 general reset
1	WOX	WOX		FSI_A_MST_0_PORT_ERROR_RESET_6: port 6 error reset
2:31	RO	RO		constant=0b000000000000000000000000000000

Addr:	0000000000000C3A (SCOMFSI0) 00000000000030E8 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSTAP6
Constant(s):	PERV_FSI_A_MST_0_MSTAP6 PERV_FSISHIFT_FSI_A_MST_0_MSTAP6
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#6.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(0:2) [000]
	5:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#6.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(3:5) [000]
	9:11	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#6.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(6:8) [000]
	13:15	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#6.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(9:11) [000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	RO	RO		constant=0b0
1:3	RO	RO		FSI_A_MST_0_PORT6_ERROR_CODE_0: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
4	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
5:7	RO	RO		FSI_A_MST_0_PORT6_ERROR_CODE_1: error code 0 MFSI port 6 (error code: 0 first, 3 last) error code 1 MFSI port 6 (error code: 0 first, 3 last) error code 2 MFSI port 6 (error code: 0 first, 3 last) Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
8	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
9:11	RO	RO		FSI_A_MST_0_PORT6_ERROR_CODE_2: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
12	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
13:15	RO	RO		fourth_error Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
16:19	RO	RO		crc_error_count Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
20	RO	RO		hot_plug_flag Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
21:31	RO	RO		constant=0b00000000000 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110

Addr:	0000000000000C3B (SCOMFSI0) 00000000000030EC (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MRESP7
Constant(s):	PERV_FSI_A_MST_0_MRESP7 PERV_FSISHIFT_FSI_A_MST_0_MRESP7
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_GEN_RESET_TO_PRT.FSILAT.LATCH.LATC.L2(7) [0]
	1	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_ERR_RESET_TO_PRT.FSILAT.LATCH.LATC.L2(7) [0]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	WOX	WOX		FSI_A_MST_0_PORT_GENERAL_RESET_7: port 7 general reset
1	WOX	WOX		FSI_A_MST_0_PORT_ERROR_RESET_7: port 7 error reset
2:31	RO	RO		constant=0b000000000000000000000000000000

Addr:	0000000000000C3B (SCOMFSI0) 00000000000030EC (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSTAP7
Constant(s):	PERV_FSI_A_MST_0_MSTAP7 PERV_FSISHIFT_FSI_A_MST_0_MSTAP7
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#7.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(0:2) [000]
	5:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#7.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(3:5) [000]
	9:11	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#7.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(6:8) [000]
	13:15	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.GEN#7.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(9:11) [000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	RO	RO		constant=0b0
1:3	RO	RO		FSI_A_MST_0_PORT7_ERROR_CODE_0: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
4	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
5:7	RO	RO		FSI_A_MST_0_PORT7_ERROR_CODE_1: error code 0 MFSI port 7 (error code: 0 first, 3 last) error code 1 MFSI port 7 (error code: 0 first, 3 last) error code 2 MFSI port 7 (error code: 0 first, 3 last) Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
8	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
9:11	RO	RO		FSI_A_MST_0_PORT7_ERROR_CODE_2: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
12	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
13:15	RO	RO		fourth_error Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
16:19	RO	RO		crc_error_count Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
20	RO	RO		hot_plug_flag Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
21:31	RO	RO		constant=0b00000000000 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110

Addr:	0000000000000C74 (SCOMFSI0) 00000000000031D0 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MESRB0
Constant(s):	PERV_FSI_A_MST_0_MESRB0 PERV_FSISHIFT_FSI_A_MST_0_MESRB0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.OPB2FSI.Q_FRST_ERROR_CODE.FSILAT.LATCH.LATC.L2(0:3) [0000]
	4:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.OPB2FSI.Q_CRC_ERR_CTR.FSILAT.LATCH.LATC.L2(0:3) [0000]
	8:15	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_PARITY_ERROR.FSILAT.LATCH.LATC.L2(0:7) [00000000]
	16	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_REG_ACCESS_ERROR.FSILAT.LATCH.LATC.L2(0) [0]
	17:19	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.OPB2FSI.Q_FAIL_MST.FSILAT.LATCH.LATC.L2(0:2) [000]
	20:23	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.OPB2FSI.Q_ACT_ERROR_CODE.FSILAT.LATCH.LATC.L2(0:3) [0000]
	24:27	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.OPB2FSI.SEL_ERROR_CODE(0:3) [0000]
	29:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.OPB2FSI.Q_FAIL_MSTF.FSILAT.LATCH.LATC.L2(0:2) [000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:3	ROX	ROX		FSI_A_MST_0_FIRST_ERROR: first error 'error code' bridge (OPB) Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
4:7	ROX	ROX		crc_error_count Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
8	ROX	ROX		MMODE_parity_check Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
9	ROX	ROX		MDLYR_parity_check Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
10	ROX	ROX		MCRSP0_parity_check Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
11	ROX	ROX		MENP0_parity_check Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
12	ROX	ROX		MSIEP0_parity_check Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
13	ROX	ROX		MSSIEP0_parity_check Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
14	ROX	ROX		register_access_FSM_check Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
15	ROX	ROX		OPB_bus_access_FSM_check Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
16	ROX	ROX		register_access_error Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
17:19	ROX	ROX		FSI_A_MST_0_FAILING_OPB_MASTER_FRST: actual OPB master, frozen when first error 'error code' unequal 0x0 Dial enums: FSI_SLAVE=>0b100 PIB_TO_OPB_PORT0=>0b101 PIB_TO_OPB_PORT1=>0b110 NO_OPB_MASTER_SELECTED=>0b000 CONFLICT_MULTI_OPB_SELECT=>0b001
20:23	ROX	ROX		FSI_A_MST_0_ACTUAL_ERROR: error code of last operation bridge (OPB) Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
24:27	ROX	ROX		selected_error Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
28	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
29:31	ROX	ROX		FSI_A_MST_0_FAILING_OPB_MASTER_ACT: OPB master of last operation Dial enums: FSI_SLAVE=>0b100 PIB_TO_OPB_PORT0=>0b101 PIB_TO_OPB_PORT1=>0b110 NO_OPB_MASTER_SELECTED=>0b000 CONFLICT_MULTI_OPB_SELECT=>0b001

Addr:	0000000000000C74 (SCOMFSI0) 00000000000031D0 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MRESB0
Constant(s):	PERV_FSI_A_MST_0_MRESB0 PERV_FSISHIFT_FSI_A_MST_0_MRESB0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.GEN_RESET_TO_BDG_D(0) [0]
	1	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.ERR_RESET_TO_BDG_D(0) [0]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	WOX	WOX		bridge_general_reset
1	WOX	WOX		bridge_error_reset
2:4	RO	RO		constant=0b000
5	WOX	WOX		set_dma_irq_suspend_mode
6	WOX	WOX		clear_dma_irq_suspend_mode
7	WOX	WOX		set_dly_measurement
8:31	RO	RO		constant=0b000000000000000000000000

Addr:	0000000000000C75 (SCOMFSI0) 00000000000031D4 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSCSB0
Constant(s):	PERV_FSI_A_MST_0_MSCSB0 PERV_FSISHIFT_FSI_A_MST_0_MSCSB0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.OPB2FSI.Q_MST_CMD_FIRST.FSILAT.LATCH.LATC.L2(0:2) [000]
	3:5	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.OPB2FSI.Q_SLV_CMD_FIRST.FSILAT.LATCH.LATC.L2(0:2) [000]
	6:8	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.OPB2FSI.Q_MST_CMD_STACK.FSILAT.LATCH.LATC.L2(0:2) [000]
	9:11	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.OPB2FSI.Q_SLV_CMD_STACK.FSILAT.LATCH.LATC.L2(0:2) [000]
	12:14	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.OPB2FSI.Q_MST_CMD_STACK.FSILAT.LATCH.LATC.L2(3:5) [000]
	15:17	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.OPB2FSI.Q_SLV_CMD_STACK.FSILAT.LATCH.LATC.L2(3:5) [000]
	18:20	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.OPB2FSI.Q_MST_CMD_STACK.FSILAT.LATCH.LATC.L2(6:8) [000]
	21:23	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.OPB2FSI.Q_SLV_CMD_STACK.FSILAT.LATCH.LATC.L2(6:8) [000]
	24:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.OPB2FSI.Q_CMD_LOOP_CTR.FSILAT.LATCH.LATC.L2(0:7) [00000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO

Addr:	0000000000000C76 (SCOMFSI0) 00000000000031D8 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MATRB0
Constant(s):	PERV_FSI_A_MST_0_MATRB0 PERV_FSISHIFT_FSI_A_MST_0_MATRB0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.OPB2FSI.Q_TRACE_ADDR.FSILAT.LATCH.LATC.L2(0:7) [00000000]
	9:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.OPB2FSI.Q_TRACE_ADDR.FSILAT.LATCH.LATC.L2(8:30) [00000000000000000000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:7	RO	RO
8	RO	RO		constant=0b0
9:31	RO	RO

Addr:	0000000000000C77 (SCOMFSI0) 00000000000031DC (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MDTRB0
Constant(s):	PERV_FSI_A_MST_0_MDTRB0 PERV_FSISHIFT_FSI_A_MST_0_MDTRB0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.OPB2FSI.Q_TRACE_DATA.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO

Addr:	0000000000000CB8 (SCOMFSI0) 00000000000032E0 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MECTRL
Constant(s):	PERV_FSI_A_MST_0_MECTRL PERV_FSISHIFT_FSI_A_MST_0_MECTRL
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	8:22	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#0.MST.CTRL.COMP.FSIREG.GEN.Q_CHK_CTL_REG.FSILAT.LATCH.LATC.L2(0:14) [000000000000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:7	RO	RO		constant=0b00000000
8:22	RW	RW
23:31	RO	RO		constant=0b000000000

Addr:	0000000000000D00 (SCOMFSI0) 0000000000003400 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MMODE
Constant(s):	PERV_FSI_A_MST_1_MMODE
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_MODE_REG.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	RW	RW		FSI_A_MST_1_ENABLE_IPOLL_AND_DMA: enable ipoll and DMA
1	RW	RW		FSI_A_MST_1_ENABLE_HW_ERROR_RECOVERY: enable hardware error recovery
2	RW	RW		FSI_A_MST_1_ENABLE_RELATIVE_ADDRESS_CMDS: enable relative addressing
3	RW	RW		FSI_A_MST_1_ENABLE_PARITY_CHECK: enable parity checking
4:13	RW	RW		FSI_A_MST_1_CLOCK_RATE_SELECTION_0: clock rate selection 0
14:23	RW	RW		FSI_A_MST_1_CLOCK_RATE_SELECTION_1: clock rate selection 1
24	RW	RW
25	RW	RW		FSI_A_MST_1_CLOCK_DIV_4: clock divided by 4 mode (default off is for legacy/ as fall back)
26:27	RW	RW		FSI_A_MST_1_TIMEOUT_SEL: 0b00: for PIB only 1ms; 0b01: 0.9ms; 0b10: 0.8ms; 0b11 as measured previously (see workbook) Dial enums: TO_1M_PIB_ONLY=>0b00 TO_0_9=>0b01 TO_0_8=>0b10 TO_AS_MEASURED=>0b11
28	RW	RW		Dial enums: TO_1M_PIB_ONLY=>0b00 TO_0_9=>0b01 TO_0_8=>0b10 TO_AS_MEASURED=>0b11
29:31	RW	RW		FSI_A_MST_1_RECEIVER_MODE: receiver mode / several settings in case of problems Dial enums: AUTO=>0b000 AUTO_NO_SW_ON_FAIL=>0b001 AUTO_AT_START_ONLY_NO_SW_ON_FAIL=>0b100 AUTO_AT_START_ONLY_NO_SW_ON_BAD_QUALITY=>0b101 FIX_RISE=>0b010 FIX_FALL=>0b011

Addr:	0000000000000D01 (SCOMFSI0) 0000000000003404 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MDLYR
Constant(s):	PERV_FSI_A_MST_1_MDLYR
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_DLY_REG.FSILAT.LATCH.LATC.L2(0:15) [0000000000000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:15	RW	RW
16:31	RO	RO		constant=0b0000000000000000

Addr:	0000000000000D02 (SCOMFSI0) 0000000000003408 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MCRSP0
Constant(s):	PERV_FSI_A_MST_1_MCRSP0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_CLK_SEL.FSILAT.LATCH.LATC.L2(0:7) [00000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:7	RW	RW
8:31	RO	RO		constant=0b000000000000000000000000

Addr:	0000000000000D03 (SCOMFSI0) 000000000000340C (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MCRSP1
Constant(s):	PERV_FSI_A_MST_1_MCRSP1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

Addr:	0000000000000D04 (SCOMFSI0) 0000000000003410 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MENP0
Constant(s):	PERV_FSI_A_MST_1_MENP0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_PRT_ENABLE.FSILAT.LATCH.LATC.L2(0:7) [00000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	RW	RW		FSI_A_MST_1_PORT_0_ENABLE: enable Master port 0 enable
1	RW	RW		FSI_A_MST_1_PORT_1_ENABLE: enable Master port 0 enable
2	RW	RW		FSI_A_MST_1_PORT_2_ENABLE: enable Master port 0 enable
3	RW	RW		FSI_A_MST_1_PORT_3_ENABLE: enable Master port 0 enable
4	RW	RW		FSI_A_MST_1_PORT_4_ENABLE: enable Master port 0 enable
5	RW	RW		FSI_A_MST_1_PORT_5_ENABLE: enable Master port 0 enable
6	RW	RW		FSI_A_MST_1_PORT_6_ENABLE: enable Master port 0 enable
7	RW	RW		FSI_A_MST_1_PORT_7_ENABLE: enable Master port 0 enable
8:31	RO	RO		constant=0b000000000000000000000000

Addr:	0000000000000D05 (SCOMFSI0) 0000000000003414 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MENP1
Constant(s):	PERV_FSI_A_MST_1_MENP1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

Addr:	0000000000000D06 (SCOMFSI0) 0000000000003418 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MLEVP0
Constant(s):	PERV_FSI_A_MST_1_MLEVP0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.COMMON_PRT_STATUS_RD(0:31) [00000000000000000000000000000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	ROX	ROX		port_level_0
1	ROX	ROX		port_level_1
2	ROX	ROX		port_level_2
3	ROX	ROX		port_level_3
4	ROX	ROX		port_level_4
5	ROX	ROX		port_level_5
6	ROX	ROX		port_level_6
7	ROX	ROX		port_level_7
8:31	RO	RO

Addr:	0000000000000D06 (SCOMFSI0) 0000000000003418 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSENP0
Constant(s):	PERV_FSI_A_MST_1_MSENP0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_PRT_ENABLE.FSILAT.LATCH.LATC.L2(0:7) [00000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	WO_OR	WO_OR		FSI_A_MST_1_PORT_0_ENABLE: enable Master port 0 enable
1	WO_OR	WO_OR		FSI_A_MST_1_PORT_1_ENABLE: enable Master port 0 enable
2	WO_OR	WO_OR		FSI_A_MST_1_PORT_2_ENABLE: enable Master port 0 enable
3	WO_OR	WO_OR		FSI_A_MST_1_PORT_3_ENABLE: enable Master port 0 enable
4	WO_OR	WO_OR		FSI_A_MST_1_PORT_4_ENABLE: enable Master port 0 enable
5	WO_OR	WO_OR		FSI_A_MST_1_PORT_5_ENABLE: enable Master port 0 enable
6	WO_OR	WO_OR		FSI_A_MST_1_PORT_6_ENABLE: enable Master port 0 enable
7	WO_OR	WO_OR		FSI_A_MST_1_PORT_7_ENABLE: enable Master port 0 enable
8:31	RO	RO		constant=0b000000000000000000000000

Addr:	0000000000000D07 (SCOMFSI0) 000000000000341C (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MLEVP1
Constant(s):	PERV_FSI_A_MST_1_MLEVP1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.COMMON_PRT_STATUS_RD(32:63) [00000000000000000000000000000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	ROX	ROX		port_level_0
1	ROX	ROX		port_level_1
2	ROX	ROX		port_level_2
3	ROX	ROX		port_level_3
4	ROX	ROX		port_level_4
5	ROX	ROX		port_level_5
6	ROX	ROX		port_level_6
7	ROX	ROX		port_level_7
8:31	RO	RO

Addr:	0000000000000D08 (SCOMFSI0) 0000000000003420 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MCENP0
Constant(s):	PERV_FSI_A_MST_1_MCENP0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_PRT_ENABLE.FSILAT.LATCH.LATC.L2(0:7) [00000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	WO_CLEAR	WO_CLEAR		FSI_A_MST_1_PORT_0_ENABLE: enable Master port 0 enable
1	WO_CLEAR	WO_CLEAR		FSI_A_MST_1_PORT_1_ENABLE: enable Master port 0 enable
2	WO_CLEAR	WO_CLEAR		FSI_A_MST_1_PORT_2_ENABLE: enable Master port 0 enable
3	WO_CLEAR	WO_CLEAR		FSI_A_MST_1_PORT_3_ENABLE: enable Master port 0 enable
4	WO_CLEAR	WO_CLEAR		FSI_A_MST_1_PORT_4_ENABLE: enable Master port 0 enable
5	WO_CLEAR	WO_CLEAR		FSI_A_MST_1_PORT_5_ENABLE: enable Master port 0 enable
6	WO_CLEAR	WO_CLEAR		FSI_A_MST_1_PORT_6_ENABLE: enable Master port 0 enable
7	WO_CLEAR	WO_CLEAR		FSI_A_MST_1_PORT_7_ENABLE: enable Master port 0 enable
8:31	RO	RO		constant=0b000000000000000000000000

Addr:	0000000000000D08 (SCOMFSI0) 0000000000003420 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MREFP0
Constant(s):	PERV_FSI_A_MST_1_MREFP0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.COMMON_PRT_STATUS_RD(0:31) [00000000000000000000000000000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	ROX	ROX		port_hot_plug_0
1	ROX	ROX		port_hot_plug_1
2	ROX	ROX		port_hot_plug_2
3	ROX	ROX		port_hot_plug_3
4	ROX	ROX		port_hot_plug_4
5	ROX	ROX		port_hot_plug_5
6	ROX	ROX		port_hot_plug_6
7	ROX	ROX		port_hot_plug_7
8:31	RO	RO

Addr:	0000000000000D09 (SCOMFSI0) 0000000000003424 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MREFP1
Constant(s):	PERV_FSI_A_MST_1_MREFP1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.COMMON_PRT_STATUS_RD(32:63) [00000000000000000000000000000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	ROX	ROX		port_hot_plug_0
1	ROX	ROX		port_hot_plug_1
2	ROX	ROX		port_hot_plug_2
3	ROX	ROX		port_hot_plug_3
4	ROX	ROX		port_hot_plug_4
5	ROX	ROX		port_hot_plug_5
6	ROX	ROX		port_hot_plug_6
7	ROX	ROX		port_hot_plug_7
8:31	RO	RO

Addr:	0000000000000D0C (SCOMFSI0) 0000000000003430 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSIEP0
Constant(s):	PERV_FSI_A_MST_1_MSIEP0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_SLV_INTR_ENABLE.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RW	RW

Addr:	0000000000000D0D (SCOMFSI0) 0000000000003434 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSIEP1
Constant(s):	PERV_FSI_A_MST_1_MSIEP1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

Addr:	0000000000000D0E (SCOMFSI0) 0000000000003438 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSIEP2
Constant(s):	PERV_FSI_A_MST_1_MSIEP2
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

Addr:	0000000000000D0F (SCOMFSI0) 000000000000343C (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSIEP3
Constant(s):	PERV_FSI_A_MST_1_MSIEP3
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

Addr:	0000000000000D10 (SCOMFSI0) 0000000000003440 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSIEP4
Constant(s):	PERV_FSI_A_MST_1_MSIEP4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

Addr:	0000000000000D11 (SCOMFSI0) 0000000000003444 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSIEP5
Constant(s):	PERV_FSI_A_MST_1_MSIEP5
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

Addr:	0000000000000D12 (SCOMFSI0) 0000000000003448 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSIEP6
Constant(s):	PERV_FSI_A_MST_1_MSIEP6
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

Addr:	0000000000000D13 (SCOMFSI0) 000000000000344C (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSIEP7
Constant(s):	PERV_FSI_A_MST_1_MSIEP7
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

Addr:	0000000000000D14 (SCOMFSI0) 0000000000003450 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MAESP0
Constant(s):	PERV_FSI_A_MST_1_MAESP0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.ANY_PRT_ERROR_RD(0:31) [00000000000000000000000000000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO

Addr:	0000000000000D14 (SCOMFSI0) 0000000000003450 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSSIEP0
Constant(s):	PERV_FSI_A_MST_1_MSSIEP0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_SLV_INTR_ENABLE.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	WO_OR	WO_OR

Addr:	0000000000000D15 (SCOMFSI0) 0000000000003454 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MAESP1
Constant(s):	PERV_FSI_A_MST_1_MAESP1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

Addr:	0000000000000D16 (SCOMFSI0) 0000000000003458 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MAESP2
Constant(s):	PERV_FSI_A_MST_1_MAESP2
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

Addr:	0000000000000D17 (SCOMFSI0) 000000000000345C (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MAESP3
Constant(s):	PERV_FSI_A_MST_1_MAESP3
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

Addr:	0000000000000D18 (SCOMFSI0) 0000000000003460 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MAESP4
Constant(s):	PERV_FSI_A_MST_1_MAESP4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

Addr:	0000000000000D19 (SCOMFSI0) 0000000000003464 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MAESP5
Constant(s):	PERV_FSI_A_MST_1_MAESP5
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

Addr:	0000000000000D1A (SCOMFSI0) 0000000000003468 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MAESP6
Constant(s):	PERV_FSI_A_MST_1_MAESP6
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

Addr:	0000000000000D1B (SCOMFSI0) 000000000000346C (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MAESP7
Constant(s):	PERV_FSI_A_MST_1_MAESP7
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b00000000000000000000000000000000

Addr:	0000000000000D1C (SCOMFSI0) 0000000000003470 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MAEB
Constant(s):	PERV_FSI_A_MST_1_MAEB
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	RO	RO		bridge_error
1:23	RO	RO		constant=0b00000000000000000000000

Addr:	0000000000000D1C (SCOMFSI0) 0000000000003470 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MCSIEP0
Constant(s):	PERV_FSI_A_MST_1_MCSIEP0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_SLV_INTR_ENABLE.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	WO_CLEAR	WO_CLEAR

Addr:	0000000000000D1D (SCOMFSI0) 0000000000003474 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MVER
Constant(s):	PERV_FSI_A_MST_1_MVER
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO		constant=0b10010010000000010000100000000000

Addr:	0000000000000D34 (SCOMFSI0) 00000000000034D0 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MRESP0
Constant(s):	PERV_FSI_A_MST_1_MRESP0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.GEN_RESET_TO_PRT_D(0) [0]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	WOX	WOX		port_general_reset
1	WOX	WOX		port_error_reset
2	WOX	WOX		all_bridge_general_reset
3	WOX	WOX		all_port_general_reset
4	WOX	WOX		control_register_reset
5	WOX	WOX		parity_error_reset
6:31	RO	RO		constant=0b00000000000000000000000000

Addr:	0000000000000D34 (SCOMFSI0) 00000000000034D0 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSTAP0
Constant(s):	PERV_FSI_A_MST_1_MSTAP0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#0.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(0:2) [000]
	5:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#0.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(3:5) [000]
	9:11	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#0.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(6:8) [000]
	13:15	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#0.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(9:11) [000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	RO	RO		constant=0b0
1:3	RO	RO		FSI_A_MST_1_PORT0_ERROR_CODE_0: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
4	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
5:7	RO	RO		FSI_A_MST_1_PORT0_ERROR_CODE_1: error code 0 MFSI port 0 (error code: 0 first, 3 last) error code 1 MFSI port 0 (error code: 0 first, 3 last) error code 2 MFSI port 0 (error code: 0 first, 3 last) Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
8	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
9:11	RO	RO		FSI_A_MST_1_PORT0_ERROR_CODE_2: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
12	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
13:15	RO	RO		fourth_error Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
16:19	RO	RO		crc_error_count Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
20	RO	RO		hot_plug_flag Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
21:31	RO	RO		constant=0b00000000000 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110

Addr:	0000000000000D35 (SCOMFSI0) 00000000000034D4 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MRESP1
Constant(s):	PERV_FSI_A_MST_1_MRESP1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_GEN_RESET_TO_PRT.FSILAT.LATCH.LATC.L2(1) [0]
	1	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_ERR_RESET_TO_PRT.FSILAT.LATCH.LATC.L2(1) [0]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	WOX	WOX		FSI_A_MST_1_PORT_GENERAL_RESET_1: port 1 general reset
1	WOX	WOX		FSI_A_MST_1_PORT_ERROR_RESET_1: port 1 error reset
2:31	RO	RO		constant=0b000000000000000000000000000000

Addr:	0000000000000D35 (SCOMFSI0) 00000000000034D4 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSTAP1
Constant(s):	PERV_FSI_A_MST_1_MSTAP1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#1.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(0:2) [000]
	5:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#1.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(3:5) [000]
	9:11	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#1.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(6:8) [000]
	13:15	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#1.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(9:11) [000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	RO	RO		constant=0b0
1:3	RO	RO		FSI_A_MST_1_PORT1_ERROR_CODE_0: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
4	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
5:7	RO	RO		FSI_A_MST_1_PORT1_ERROR_CODE_1: error code 0 MFSI port 1 (error code: 0 first, 3 last) error code 1 MFSI port 1 (error code: 0 first, 3 last) error code 2 MFSI port 1 (error code: 0 first, 3 last) Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
8	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
9:11	RO	RO		FSI_A_MST_1_PORT1_ERROR_CODE_2: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
12	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
13:15	RO	RO		fourth_error Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
16:19	RO	RO		crc_error_count Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
20	RO	RO		hot_plug_flag Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
21:31	RO	RO		constant=0b00000000000 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110

Addr:	0000000000000D36 (SCOMFSI0) 00000000000034D8 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MRESP2
Constant(s):	PERV_FSI_A_MST_1_MRESP2
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_GEN_RESET_TO_PRT.FSILAT.LATCH.LATC.L2(2) [0]
	1	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_ERR_RESET_TO_PRT.FSILAT.LATCH.LATC.L2(2) [0]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	WOX	WOX		FSI_A_MST_1_PORT_GENERAL_RESET_2: port 2 general reset
1	WOX	WOX		FSI_A_MST_1_PORT_ERROR_RESET_2: port 2 error reset
2:31	RO	RO		constant=0b000000000000000000000000000000

Addr:	0000000000000D36 (SCOMFSI0) 00000000000034D8 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSTAP2
Constant(s):	PERV_FSI_A_MST_1_MSTAP2
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#2.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(0:2) [000]
	5:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#2.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(3:5) [000]
	9:11	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#2.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(6:8) [000]
	13:15	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#2.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(9:11) [000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	RO	RO		constant=0b0
1:3	RO	RO		FSI_A_MST_1_PORT2_ERROR_CODE_0: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
4	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
5:7	RO	RO		FSI_A_MST_1_PORT2_ERROR_CODE_1: error code 0 MFSI port 2 (error code: 0 first, 3 last) error code 1 MFSI port 2 (error code: 0 first, 3 last) error code 2 MFSI port 2 (error code: 0 first, 3 last) Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
8	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
9:11	RO	RO		FSI_A_MST_1_PORT2_ERROR_CODE_2: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
12	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
13:15	RO	RO		fourth_error Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
16:19	RO	RO		crc_error_count Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
20	RO	RO		hot_plug_flag Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
21:31	RO	RO		constant=0b00000000000 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110

Addr:	0000000000000D37 (SCOMFSI0) 00000000000034DC (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MRESP3
Constant(s):	PERV_FSI_A_MST_1_MRESP3
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_GEN_RESET_TO_PRT.FSILAT.LATCH.LATC.L2(3) [0]
	1	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_ERR_RESET_TO_PRT.FSILAT.LATCH.LATC.L2(3) [0]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	WOX	WOX		FSI_A_MST_1_PORT_GENERAL_RESET_3: port 3 general reset
1	WOX	WOX		FSI_A_MST_1_PORT_ERROR_RESET_3: port 3 error reset
2:31	RO	RO		constant=0b000000000000000000000000000000

Addr:	0000000000000D37 (SCOMFSI0) 00000000000034DC (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSTAP3
Constant(s):	PERV_FSI_A_MST_1_MSTAP3
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#3.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(0:2) [000]
	5:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#3.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(3:5) [000]
	9:11	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#3.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(6:8) [000]
	13:15	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#3.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(9:11) [000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	RO	RO		constant=0b0
1:3	RO	RO		FSI_A_MST_1_PORT3_ERROR_CODE_0: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
4	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
5:7	RO	RO		FSI_A_MST_1_PORT3_ERROR_CODE_1: error code 0 MFSI port 3 (error code: 0 first, 3 last) error code 1 MFSI port 3 (error code: 0 first, 3 last) error code 2 MFSI port 3 (error code: 0 first, 3 last) Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
8	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
9:11	RO	RO		FSI_A_MST_1_PORT3_ERROR_CODE_2: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
12	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
13:15	RO	RO		fourth_error Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
16:19	RO	RO		crc_error_count Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
20	RO	RO		hot_plug_flag Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
21:31	RO	RO		constant=0b00000000000 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110

Addr:	0000000000000D38 (SCOMFSI0) 00000000000034E0 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MRESP4
Constant(s):	PERV_FSI_A_MST_1_MRESP4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_GEN_RESET_TO_PRT.FSILAT.LATCH.LATC.L2(4) [0]
	1	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_ERR_RESET_TO_PRT.FSILAT.LATCH.LATC.L2(4) [0]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	WOX	WOX		FSI_A_MST_1_PORT_GENERAL_RESET_4: port 4 general reset
1	WOX	WOX		FSI_A_MST_1_PORT_ERROR_RESET_4: port 4 error reset
2:31	RO	RO		constant=0b000000000000000000000000000000

Addr:	0000000000000D38 (SCOMFSI0) 00000000000034E0 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSTAP4
Constant(s):	PERV_FSI_A_MST_1_MSTAP4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#4.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(0:2) [000]
	5:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#4.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(3:5) [000]
	9:11	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#4.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(6:8) [000]
	13:15	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#4.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(9:11) [000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	RO	RO		constant=0b0
1:3	RO	RO		FSI_A_MST_1_PORT4_ERROR_CODE_0: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
4	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
5:7	RO	RO		FSI_A_MST_1_PORT4_ERROR_CODE_1: error code 0 MFSI port 4 (error code: 0 first, 3 last) error code 1 MFSI port 4 (error code: 0 first, 3 last) error code 2 MFSI port 4 (error code: 0 first, 3 last) Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
8	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
9:11	RO	RO		FSI_A_MST_1_PORT4_ERROR_CODE_2: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
12	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
13:15	RO	RO		fourth_error Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
16:19	RO	RO		crc_error_count Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
20	RO	RO		hot_plug_flag Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
21:31	RO	RO		constant=0b00000000000 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110

Addr:	0000000000000D39 (SCOMFSI0) 00000000000034E4 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MRESP5
Constant(s):	PERV_FSI_A_MST_1_MRESP5
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_GEN_RESET_TO_PRT.FSILAT.LATCH.LATC.L2(5) [0]
	1	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_ERR_RESET_TO_PRT.FSILAT.LATCH.LATC.L2(5) [0]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	WOX	WOX		FSI_A_MST_1_PORT_GENERAL_RESET_5: port 5 general reset
1	WOX	WOX		FSI_A_MST_1_PORT_ERROR_RESET_5: port 5 error reset
2:31	RO	RO		constant=0b000000000000000000000000000000

Addr:	0000000000000D39 (SCOMFSI0) 00000000000034E4 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSTAP5
Constant(s):	PERV_FSI_A_MST_1_MSTAP5
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#5.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(0:2) [000]
	5:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#5.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(3:5) [000]
	9:11	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#5.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(6:8) [000]
	13:15	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#5.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(9:11) [000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	RO	RO		constant=0b0
1:3	RO	RO		FSI_A_MST_1_PORT5_ERROR_CODE_0: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
4	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
5:7	RO	RO		FSI_A_MST_1_PORT5_ERROR_CODE_1: error code 0 MFSI port 5 (error code: 0 first, 3 last) error code 1 MFSI port 5 (error code: 0 first, 3 last) error code 2 MFSI port 5 (error code: 0 first, 3 last) Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
8	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
9:11	RO	RO		FSI_A_MST_1_PORT5_ERROR_CODE_2: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
12	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
13:15	RO	RO		fourth_error Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
16:19	RO	RO		crc_error_count Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
20	RO	RO		hot_plug_flag Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
21:31	RO	RO		constant=0b00000000000 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110

Addr:	0000000000000D3A (SCOMFSI0) 00000000000034E8 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MRESP6
Constant(s):	PERV_FSI_A_MST_1_MRESP6
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_GEN_RESET_TO_PRT.FSILAT.LATCH.LATC.L2(6) [0]
	1	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_ERR_RESET_TO_PRT.FSILAT.LATCH.LATC.L2(6) [0]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	WOX	WOX		FSI_A_MST_1_PORT_GENERAL_RESET_6: port 6 general reset
1	WOX	WOX		FSI_A_MST_1_PORT_ERROR_RESET_6: port 6 error reset
2:31	RO	RO		constant=0b000000000000000000000000000000

Addr:	0000000000000D3A (SCOMFSI0) 00000000000034E8 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSTAP6
Constant(s):	PERV_FSI_A_MST_1_MSTAP6
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#6.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(0:2) [000]
	5:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#6.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(3:5) [000]
	9:11	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#6.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(6:8) [000]
	13:15	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#6.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(9:11) [000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	RO	RO		constant=0b0
1:3	RO	RO		FSI_A_MST_1_PORT6_ERROR_CODE_0: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
4	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
5:7	RO	RO		FSI_A_MST_1_PORT6_ERROR_CODE_1: error code 0 MFSI port 6 (error code: 0 first, 3 last) error code 1 MFSI port 6 (error code: 0 first, 3 last) error code 2 MFSI port 6 (error code: 0 first, 3 last) Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
8	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
9:11	RO	RO		FSI_A_MST_1_PORT6_ERROR_CODE_2: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
12	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
13:15	RO	RO		fourth_error Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
16:19	RO	RO		crc_error_count Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
20	RO	RO		hot_plug_flag Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
21:31	RO	RO		constant=0b00000000000 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110

Addr:	0000000000000D3B (SCOMFSI0) 00000000000034EC (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MRESP7
Constant(s):	PERV_FSI_A_MST_1_MRESP7
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_GEN_RESET_TO_PRT.FSILAT.LATCH.LATC.L2(7) [0]
	1	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_ERR_RESET_TO_PRT.FSILAT.LATCH.LATC.L2(7) [0]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	WOX	WOX		FSI_A_MST_1_PORT_GENERAL_RESET_7: port 7 general reset
1	WOX	WOX		FSI_A_MST_1_PORT_ERROR_RESET_7: port 7 error reset
2:31	RO	RO		constant=0b000000000000000000000000000000

Addr:	0000000000000D3B (SCOMFSI0) 00000000000034EC (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSTAP7
Constant(s):	PERV_FSI_A_MST_1_MSTAP7
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#7.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(0:2) [000]
	5:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#7.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(3:5) [000]
	9:11	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#7.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(6:8) [000]
	13:15	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.GEN#7.PRT.COMP.PRTCTL.GEN.P_PRT_ERROR_CODE.FSILAT.LATCH.LATC.L2(9:11) [000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	RO	RO		constant=0b0
1:3	RO	RO		FSI_A_MST_1_PORT7_ERROR_CODE_0: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
4	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
5:7	RO	RO		FSI_A_MST_1_PORT7_ERROR_CODE_1: error code 0 MFSI port 7 (error code: 0 first, 3 last) error code 1 MFSI port 7 (error code: 0 first, 3 last) error code 2 MFSI port 7 (error code: 0 first, 3 last) Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
8	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
9:11	RO	RO		FSI_A_MST_1_PORT7_ERROR_CODE_2: Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
12	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
13:15	RO	RO		fourth_error Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
16:19	RO	RO		crc_error_count Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
20	RO	RO		hot_plug_flag Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110
21:31	RO	RO		constant=0b00000000000 Dial enums: NO_ERROR=>0b000 ANY_SLAVE_ERROR=>0b001 ANY_SLAVE_CRC_ERROR=>0b010 ANY_IP_CRC_ERROR=>0b011 SET_ID_ERROR=>0b100 TIEMOUT_ERROR=>0b101 SET_IP_STATE_ERROR=>0b110

Addr:	0000000000000D74 (SCOMFSI0) 00000000000035D0 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MESRB0
Constant(s):	PERV_FSI_A_MST_1_MESRB0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.OPB2FSI.Q_FRST_ERROR_CODE.FSILAT.LATCH.LATC.L2(0:3) [0000]
	4:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.OPB2FSI.Q_CRC_ERR_CTR.FSILAT.LATCH.LATC.L2(0:3) [0000]
	8:15	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_PARITY_ERROR.FSILAT.LATCH.LATC.L2(0:7) [00000000]
	16	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_REG_ACCESS_ERROR.FSILAT.LATCH.LATC.L2(0) [0]
	17:19	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.OPB2FSI.Q_FAIL_MST.FSILAT.LATCH.LATC.L2(0:2) [000]
	20:23	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.OPB2FSI.Q_ACT_ERROR_CODE.FSILAT.LATCH.LATC.L2(0:3) [0000]
	24:27	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.OPB2FSI.SEL_ERROR_CODE(0:3) [0000]
	29:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.OPB2FSI.Q_FAIL_MSTF.FSILAT.LATCH.LATC.L2(0:2) [000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:3	ROX	ROX		FSI_A_MST_1_FIRST_ERROR: first error 'error code' bridge (OPB) Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
4:7	ROX	ROX		crc_error_count Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
8	ROX	ROX		MMODE_parity_check Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
9	ROX	ROX		MDLYR_parity_check Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
10	ROX	ROX		MCRSP0_parity_check Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
11	ROX	ROX		MENP0_parity_check Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
12	ROX	ROX		MSIEP0_parity_check Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
13	ROX	ROX		MSSIEP0_parity_check Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
14	ROX	ROX		register_access_FSM_check Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
15	ROX	ROX		OPB_bus_access_FSM_check Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
16	ROX	ROX		register_access_error Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
17:19	ROX	ROX		FSI_A_MST_1_FAILING_OPB_MASTER_FRST: actual OPB master, frozen when first error 'error code' unequal 0x0 Dial enums: FSI_SLAVE=>0b100 PIB_TO_OPB_PORT0=>0b101 PIB_TO_OPB_PORT1=>0b110 NO_OPB_MASTER_SELECTED=>0b000 CONFLICT_MULTI_OPB_SELECT=>0b001
20:23	ROX	ROX		FSI_A_MST_1_ACTUAL_ERROR: error code of last operation bridge (OPB) Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
24:27	ROX	ROX		selected_error Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
28	RO	RO		constant=0b0 Dial enums: NO_ERROR=>0b0000 OPB_ERROR=>0b0001 OPB_FSM_CHECK=>0b0010 PORT_ACCESS_ERROR=>0b0011 ID_MISMATCH=>0b0100 DMA_SELECTION_ERROR=>0b0101 PORT_TIMEOUT=>0b0110 MASTER_TIMEOUT=>0b0111 MASTER_CRC_ERROR=>0b1000 SLAVE_ANY_ERROR=>0b1001 SLAVE_CRC_ERROR=>0b1010 PROTOCOL_ERROR=>0b1011 BRIDGE_PARITY_ERROR=>0b1100
29:31	ROX	ROX		FSI_A_MST_1_FAILING_OPB_MASTER_ACT: OPB master of last operation Dial enums: FSI_SLAVE=>0b100 PIB_TO_OPB_PORT0=>0b101 PIB_TO_OPB_PORT1=>0b110 NO_OPB_MASTER_SELECTED=>0b000 CONFLICT_MULTI_OPB_SELECT=>0b001

Addr:	0000000000000D74 (SCOMFSI0) 00000000000035D0 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MRESB0
Constant(s):	PERV_FSI_A_MST_1_MRESB0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.GEN_RESET_TO_BDG_D(0) [0]
	1	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.ERR_RESET_TO_BDG_D(0) [0]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0	WOX	WOX		bridge_general_reset
1	WOX	WOX		bridge_error_reset
2:4	RO	RO		constant=0b000
5	WOX	WOX		set_dma_irq_suspend_mode
6	WOX	WOX		clear_dma_irq_suspend_mode
7	WOX	WOX		set_dly_measurement
8:31	RO	RO		constant=0b000000000000000000000000

Addr:	0000000000000D75 (SCOMFSI0) 00000000000035D4 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSCSB0
Constant(s):	PERV_FSI_A_MST_1_MSCSB0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.OPB2FSI.Q_MST_CMD_FIRST.FSILAT.LATCH.LATC.L2(0:2) [000]
	3:5	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.OPB2FSI.Q_SLV_CMD_FIRST.FSILAT.LATCH.LATC.L2(0:2) [000]
	6:8	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.OPB2FSI.Q_MST_CMD_STACK.FSILAT.LATCH.LATC.L2(0:2) [000]
	9:11	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.OPB2FSI.Q_SLV_CMD_STACK.FSILAT.LATCH.LATC.L2(0:2) [000]
	12:14	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.OPB2FSI.Q_MST_CMD_STACK.FSILAT.LATCH.LATC.L2(3:5) [000]
	15:17	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.OPB2FSI.Q_SLV_CMD_STACK.FSILAT.LATCH.LATC.L2(3:5) [000]
	18:20	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.OPB2FSI.Q_MST_CMD_STACK.FSILAT.LATCH.LATC.L2(6:8) [000]
	21:23	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.OPB2FSI.Q_SLV_CMD_STACK.FSILAT.LATCH.LATC.L2(6:8) [000]
	24:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.OPB2FSI.Q_CMD_LOOP_CTR.FSILAT.LATCH.LATC.L2(0:7) [00000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO

Addr:	0000000000000D76 (SCOMFSI0) 00000000000035D8 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MATRB0
Constant(s):	PERV_FSI_A_MST_1_MATRB0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.OPB2FSI.Q_TRACE_ADDR.FSILAT.LATCH.LATC.L2(0:7) [00000000]
	9:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.OPB2FSI.Q_TRACE_ADDR.FSILAT.LATCH.LATC.L2(8:30) [00000000000000000000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:7	RO	RO
8	RO	RO		constant=0b0
9:31	RO	RO

Addr:	0000000000000D77 (SCOMFSI0) 00000000000035DC (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MDTRB0
Constant(s):	PERV_FSI_A_MST_1_MDTRB0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.OPB2FSI.Q_TRACE_DATA.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:31	RO	RO

Addr:	0000000000000DB8 (SCOMFSI0) 00000000000036E0 (FSI0)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MECTRL
Constant(s):	PERV_FSI_A_MST_1_MECTRL
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	8:22	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.M#1.MST.CTRL.COMP.FSIREG.GEN.Q_CHK_CTL_REG.FSILAT.LATCH.LATC.L2(0:14) [000000000000000]
Bit(s)	SCOMFSI0	FSI0		Dial: Description
0:7	RO	RO		constant=0b00000000
8:22	RW	RW
23:31	RO	RO		constant=0b000000000

FSI data register 0
Addr:	0000000000001000 (FSI)
Name:	TP.TPVSB.FSI.W.FSI2PIB.DATA_REGISTER_0
Constant(s):	PERV_FSI2PIB_DATA_REGISTER_0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI2PIB.COMP.CORE.D0_LTH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI			Dial: Description
0:31	RWX			DATA_REG_0: First 32 bits for PIB access

FSI data register 1
Addr:	0000000000001001 (FSI) 0000000000001004 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI2PIB.DATA_REGISTER_1
Constant(s):	PERV_FSI2PIB_DATA_REGISTER_1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI2PIB.COMP.CORE.D1_LTH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	RWX	RWX		DATA_REG_1: Second 32 bits for PIB access

contains command to the FSI2PIB engine
Addr:	0000000000001002 (FSI) 0000000000001008 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI2PIB.COMMAND_REGISTER
Constant(s):	PERV_FSI2PIB_COMMAND_REGISTER
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI2PIB.COMP.CORE.A_LTH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	RWX	RWX		CMD_REG: command register

resets data,command,status registers
Addr:	0000000000001006 (FSI) 0000000000001018 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI2PIB.RESET
Constant(s):	PERV_FSI2PIB_RESET
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0	WOX_1P	WOX_1P		reset resets command,mode,watermark,interrupt mask,status,complement mask,true mask registers

Reset PIB master IF
Addr:	0000000000001007 (FSI) 000000000000101C (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI2PIB.SET_PIB_RESET
Constant(s):	PERV_FSI2PIB_SET_PIB_RESET
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0	WOX_1P	WOX_1P		set_pib_reset Reset PIB master IF

status register
Addr:	0000000000001007 (FSI) 000000000000101C (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI2PIB.STATUS
Constant(s):	PERV_FSI2PIB_STATUS
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI2PIB.COMP.CORE.STATUS_LTH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0	ROX	ROX		ANY_ERROR: One of the following STATUS register bits are active: bit1 or bit2 or bit3 or bit5
1	ROX	ROX		SYSTEM_CHECKSTOP: System checkstop P10 ERRATUM: Not reliable while VDN is not powered
2	ROX	ROX		SPECIAL_ATTENTION: Special attention P10 ERRATUM: Not reliable while VDN is not powered
3	ROX	ROX		RECOVERABLE_ERROR: Recoverable error P10 ERRATUM: Not reliable while VDN is not powered
4	ROX	ROX		CHIPLET_INTERRUPT_FROM_HOST: Chiplet interrupt from host P10 ERRATUM: Not reliable while VDN is not powered
5	ROX	ROX		PARITY_CHECK: FSI2PIB engine has detected parity error
6	ROX	ROX		POWER_MANAGEMENT_INTERRUPT: Power management interrupt P10 ERRATUM: Not reliable while VDN is not powered
7	ROX	ROX		PROTECTION_CHECK: FSI2PIB engine blocked operation due to security
8	ROX	ROX		RESERVED_8: Reserved
9	ROX	ROX		RESERVED_9: Reserved
10	ROX	ROX		IDLE_INDICATION: IDLE indication of pib_master interface component. 0b0 = unit is requesting a PIB operation to pib master or pib master is still in busy state. When being in gsd2pib mode then it indicates a busy CBS state machine.
11	ROX	ROX		PIB_ABORT: PIB reset occured during requested/granted PIB operation
12:15	ROX	ROX		TP_TPFSI_RCS_ERROR_STATUS_DC: RCS Error Status: bit12: RCS: CLK_ERROR_A: missing edge was detected on the A path 100 MHz bit13: RCS: CLK_ERROR_B: missing edge was detected on the B path 100 MHz bit14: RCS: UNLOCKDET_A: indicates when non-used side phase alignment loop is unlocked bit15: RCS: UNLOCKDET_A: indicates when non-used side phase alignment loop is unlocked
16	ROX	ROX		VDD_NEST_OBSERVE: VDN power is on
17:19	ROX	ROX		PIB_ERROR_CODE: PIB response code: 0b000 = no error 0b001 = XSCOM command blocked (resource in use). Retry later 0b010 = chiplet offline 0b011 = partial good 0b100 = invalid address, address error, access error (bad access type) 0b101 = clock error 0b110 = address parity error, data parity error, unexpected packet, wrong packet number, protocol two phase handshaking error 0b111 = timeout
20	ROX	ROX		TP_TPFSI_PLL_LOCK_0_DC: PLL locked RCS1 P10 ERRATUM: Not reliable while VDN is not powered
21	ROX	ROX		TP_TPFSI_PLL_LOCK_1_DC: PLL locked RCS2 P10 ERRATUM: Not reliable while VDN is not powered
22	ROX	ROX		TP_TPFSI_PLL_LOCK_2_DC: PLL locked TOD FILTER P10 ERRATUM: Not reliable while VDN is not powered
23	ROX	ROX		TP_TPFSI_PLL_LOCK_3_DC: PLL locked Nest FILTER P10 ERRATUM: Not reliable while VDN is not powered
24	ROX	ROX		TP_TPFSI_PLL_LOCK_4_DC: PLL locked IO FILTER P10 ERRATUM: Not reliable while VDN is not powered
25	ROX	ROX		TP_TPFSI_PLL_LOCK_5_DC: PLL locked IO Spread FILTER P10 ERRATUM: Not reliable while VDN is not powered
26	ROX	ROX		TP_TPFSI_PLL_LOCK_6_DC: PLL locked PAU DPLL P10 ERRATUM: Not reliable while VDN is not powered
27	ROX	ROX		TP_TPFSI_PLL_LOCK_7_DC: PLL locked NEST DPLL P10 ERRATUM: Not reliable while VDN is not powered
28	ROX	ROX		INTERRUPT_CONDITION_PENDING: Pending FSI2PIB interrupt condition
29	ROX	ROX		INTERRUPT_ENABLED: FSI2PIB interrupt enabled
30	ROX	ROX		SELFBOOT_ENGINE_ATTENTION: SBE requires attention
31	ROX	ROX		RESERVED_31: Reserved

CFAM chip ID
Addr:	000000000000100A (FSI) 0000000000001028 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI2PIB.CHIPID
Constant(s):	PERV_FSI2PIB_CHIPID
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:19	TP.TPVSB.FSI.W.FSI2PIB.COMP.CORE.CHIPID(0:19) [00000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:19	ROX	ROX		chip_id Chip ID
20:31	RO	RO		constant=0b000001001001

INTERRUPT STATUS register
Addr:	000000000000100B (FSI) 000000000000102C (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI2PIB.INTERRUPT
Constant(s):	PERV_FSI2PIB_INTERRUPT
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI2PIB.COMP.CORE.INT_STATUS_REG.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	ROX	ROX		INTERRUPT_STATUS_REG: Contains status information, but gets frozen when interrupt occurs

Complement mask register
Addr:	000000000000100C (FSI) 0000000000001030 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI2PIB.COMPLEMENT_MASK
Constant(s):	PERV_FSI2PIB_COMPLEMENT_MASK
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI2PIB.COMP.CORE.CM_LTH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	RWX	RWX		COMPLEMENT_MASK_REG: Complement Mask for controlling generation of interrupts

True Mask Register
Addr:	000000000000100D (FSI) 0000000000001034 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI2PIB.TRUE_MASK
Constant(s):	PERV_FSI2PIB_TRUE_MASK
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI2PIB.COMP.CORE.TM_LTH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	RWX	RWX		TRUE_MASK_REG: True Mask for controlling generation of interrupts

Scratch pad size
Addr:	0000000000001400 (FSI)
Name:	TP.TPVSB.FSI.W.FSI2PIB.SCPSIZE
Constant(s):	PERV_SCPSIZE
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI2PIB.COMP.SCR0_RD_DATA(0:31) [00000000000000000000000000000000]
Bit(s)	FSI			Dial: Description
0:31	RO			scr0_rd_data Scratch pad size

FSI scratch pad 1
Addr:	0000000000001401 (FSI) 0000000000001404 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI2PIB.FSISCRPD1
Constant(s):	PERV_FSISCRPD1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI2PIB.COMP.SCRATCHPAD1_LTH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	RW	RW		FSI_SCRATCH_PAD1: FSI scratch pad 1 register

FSI scratch pad 2
Addr:	0000000000001402 (FSI) 0000000000001408 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI2PIB.FSISCRPD2
Constant(s):	PERV_FSISCRPD2
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI2PIB.COMP.SCRATCHPAD2_LTH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	RW	RW		FSI_SCRATCH_PAD2: FSI scratch pad 2 register

FSI scratch pad 3
Addr:	0000000000001403 (FSI) 000000000000140C (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI2PIB.FSISCRPD3
Constant(s):	PERV_FSISCRPD3
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI2PIB.COMP.SCRATCHPAD3_LTH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	RW	RW		FSI_SCRATCH_PAD3: FSI scratch pad 3 register

FIFO1_REGISTER_READ_A
Addr:	0000000000001800 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_I2C.FIFO1_REGISTER_READ_A
Constant(s):	PERV_FSII2C_FIFO1_REGISTER_READ_A
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_I2C.I2CM.FIFO_BITS_OUT_INST.FSILAT.LATCH.LATC.L2(0:7) [00000000]
Bit(s)	SCOM			Dial: Description
0:7	ROX			FIFO_BITS_READ0_000: As FIFO is not a normal register, cannot be completely verified in regchk . So this is a dummy register to maintain address in HTML fifo data byte 0 .Should be able to read/write 1 bytes
8:31	RO			constant=0b000000000000000000000000

COMMAND_REGISTER_A
Addr:	0000000000001801 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_I2C.COMMAND_REGISTER_A
Constant(s):	PERV_FSII2C_COMMAND_REGISTER_A
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_I2C.I2CM.CMD_REG_INST.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RWX			WITH_START_000: Decides start command to be issued or not during the beginiing of the operation Decides start command to be issued or not during the beginiing of the operation
1	RWX			WITH_ADDRESS_000: Decides Device address to be send or not during the beginning of the operation Decides Device address to be send or not during the beginning of the operation
2	RWX			READ_CONTINUE_000: Decides Next read operation is continuation of present operation or not Decides Next read operation is continuation of present operation or not
3	RWX			WITH_STOP_000: Decides stop command to be issued or not during the end of the operation Decides stop command to be issued or not during the end of the operation
4:7	RWX			NOT_USED_000: not used not used
8:14	RWX			DEVICE_ADDRESS_000: Device address of Slave on the I2C Bus Device address of Slave on the I2C Bus
15	RWX			READ_NOT_WRITE_000: I2C read or write I2C read or write
16:31	RWX			LENGTH_IN_BYTES_000: Length of Bytes to be accessed through the I2C Bus Length of Bytes to be accessed through the I2C Bus

MODE_REGISTER_A
Addr:	0000000000001802 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_I2C.MODE_REGISTER_A
Constant(s):	PERV_FSII2C_MODE_REGISTER_A
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPVSB.FSI.W.FSI_I2C.I2CM.BIT_RATE_DIVISOR_INST.FSILAT.LATCH.LATC.L2(0:15) [0000000000000000]
	16:21	TP.TPVSB.FSI.W.FSI_I2C.I2CM.MODE_REG_INST.FSILAT.LATCH.LATC.L2(0:5) [000000]
	28:31	TP.TPVSB.FSI.W.FSI_I2C.I2CM.MODE_REG_INST.FSILAT.LATCH.LATC.L2(6:9) [0000]
Bit(s)	SCOM			Dial: Description
0:15	RWX			BIT_RATE_DIVISOR_000: Decides the speed on the I2C bus
16:21	RWX			PORT_NUMBER_000: port number
22:27	RO			constant=0b000000
28	RWX			FGAT_MODE_000: fgat mode
29	RWX			DIAG_MODE_000: diag mode
30	RWX			PACING_ALLOW_MODE_000: pacing allow mode
31	RWX			WRAP_MODE_000: wrap_mode

WATER_MARK_REGISTER_A
Addr:	0000000000001803 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_I2C.WATER_MARK_REGISTER_A
Constant(s):	PERV_FSII2C_WATER_MARK_REGISTER_A
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	16:31	TP.TPVSB.FSI.W.FSI_I2C.I2CM.WATERMARK_REG_16_INST.FSILAT.LATCH.LATC.L2(16:31) [0000000000000000]
Bit(s)	SCOM			Dial: Description
0:15	RO			constant=0b0000000000000000
16:31	RWX			WATERMARK_REG_000: water mark register water mark register

INTERRUPT_MASK_REGISTER_A
Addr:	0000000000001804 (SCOM) 0000000000001805 (SCOM1) 0000000000001806 (SCOM2)
Name:	TP.TPVSB.FSI.W.FSI_I2C.INTERRUPT_MASK_REGISTER_A
Constant(s):	PERV_FSII2C_INTERRUPT_MASK_REGISTER_A
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	16:31	TP.TPVSB.FSI.W.FSI_I2C.I2CM.INT_MASK_16_INST.FSILAT.LATCH.LATC.L2(16:31) [0000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0:15	RO	RO	RO	constant=0b0000000000000000
16:31	WOX	WOX_OR	WOX_AND	INT_MASK_000: interrupt mask register interrupt mask register

INTERRUPT_MASK_REGISTER_read_A
Addr:	0000000000001804 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_I2C.INTERRUPT_MASK_REGISTER_READ_A
Constant(s):	PERV_FSII2C_INTERRUPT_MASK_REGISTER_READ_A
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	16:31	TP.TPVSB.FSI.W.FSI_I2C.I2CM.INT_MASK_16_INST.FSILAT.LATCH.LATC.L2(16:31) [0000000000000000]
Bit(s)	SCOM			Dial: Description
0:15	RO			constant=0b0000000000000000
16:31	ROX			INT_MASK_000: interrupt mask register interrupt mask register

INTERRUPT_CONDITION_A
Addr:	0000000000001805 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_I2C.INTERRUPT_COND_A
Constant(s):	PERV_FSII2C_INTERRUPT_COND_A
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	16:21	TP.TPVSB.FSI.W.FSI_I2C.I2CM.FREE_RUNNING_LATCHES_INST.FSILAT.LATCH.LATC.L2(17:22) [000000]
	22	TP.TPVSB.FSI.W.FSI_I2C.I2CM.FREE_RUNNING_LATCHES_INST.FSILAT.LATCH.LATC.L2(11) [0]
	23	TP.TPVSB.FSI.W.FSI_I2C.I2CM.INT_CONDS(23) [0]
	24	TP.TPVSB.FSI.W.FSI_I2C.I2CM.FREE_RUNNING_LATCHES_INST.FSILAT.LATCH.LATC.L2(23) [0]
	25:26	TP.TPVSB.FSI.W.FSI_I2C.I2CM.INT_CONDS(25:26) [00]
	28:31	TP.TPVSB.FSI.W.FSI_I2C.I2CM.INT_CONDS(28:31) [0000]
Bit(s)	SCOM			Dial: Description
0:15	RO			constant=0b0000000000000000 intterupt conditions
16	ROX			INVALID_CMD_000: invalid command : new command given when old command is not yet completed intterupt conditions
17	ROX			LBUS_PARITY_ERROR_000: local bus parity error intterupt conditions
18	ROX			BE_OV_ERROR_000: back end overrun error : Writing/reading into full/empty fifo resply intterupt conditions
19	ROX			BE_ACC_ERROR_000: back end access error : Writing/Reading more data than requested intterupt conditions
20	ROX			ARBITRATION_LOST_ERROR_000: arbitration lost error: I2C bus is held by someother master when trying to access intterupt conditions
21	ROX			NACK_RECEIVED_ERROR_000: nack receieved error: Slave is not responding back with the ACK. intterupt conditions
22	ROX			DATA_REQUEST_000: data request: FIFO needs to be accesssed some more times to full fill the expectation intterupt conditions
23	ROX			int_conds_cmd_complete_000 intterupt conditions
24	ROX			STOP_ERROR_000: stop error: Didnot able to send the stop condition on the BUS intterupt conditions
25	ROX			int_conds_i2c_busy_000 intterupt conditions
26	ROX			int_conds_not_i2c_busy_000 intterupt conditions
27	RO			constant=0b0 intterupt conditions
28	ROX			int_conds_scl_eq_1_000 intterupt conditions
29	ROX			int_conds_scl_eq_0_000 intterupt conditions
30	ROX			int_conds_sda_eq_1_000 intterupt conditions
31	ROX			int_conds_sda_eq_0_000 intterupt conditions

INTERRUPTS_REGISTER_A
Addr:	0000000000001806 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_I2C.INTERRUPTS_A
Constant(s):	PERV_FSII2C_INTERRUPTS_A
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_I2C.I2CM.INTS(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	ROX			ints_000 interrupts

IMM_RESET_I2C_A
Addr:	0000000000001807 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_I2C.IMM_RESET_I2C_A
Constant(s):	PERV_FSII2C_IMM_RESET_I2C_A
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_reset_i2c_000 resets command,mode,watermark,interrupt mask,status registers

STATUS_REGISTER_ENGINE_A
Addr:	0000000000001807 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_I2C.STATUS_REGISTER_ENGINE_A
Constant(s):	PERV_FSII2C_STATUS_REGISTER_ENGINE_A
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:5	TP.TPVSB.FSI.W.FSI_I2C.I2CM.FREE_RUNNING_LATCHES_INST.FSILAT.LATCH.LATC.L2(17:22) [000000]
	8	TP.TPVSB.FSI.W.FSI_I2C.I2CM.FREE_RUNNING_LATCHES_INST.FSILAT.LATCH.LATC.L2(23) [0]
	20	TP.TPVSB.FSI.W.FSI_I2C.I2CM.SCL_SYN(0) [0]
	23	TP.TPVSB.FSI.W.FSI_I2C.I2CM.FREE_RUNNING_LATCHES_INST.FSILAT.LATCH.LATC.L2(37) [0]
	28:31	TP.TPVSB.FSI.W.FSI_I2C.I2CM.FIFO_LVL.DOUT_INST.FSILAT.LATCH.LATC.L2(0:3) [0000]
Bit(s)	SCOM			Dial: Description
0	ROX			INVALID_CMD_000: invalid command : new command given when old command is not yet completed invalid command : new command given when old command is not yet completed
1	ROX			LBUS_PARITY_ERROR_000: local bus parity error local bus parity error
2	ROX			BE_OV_ERROR_000: back end overrun error : Writing/reading into full/empty fifo resply back end overrun error
3	ROX			BE_ACC_ERROR_000: back end access error : Writing/Reading more data than requested back end access error
4	ROX			ARBITRATION_LOST_ERROR_000: arbitration lost error: I2C bus is held by someother master when trying to access arbitration lost error
5	ROX			NACK_RECEIVED_ERROR_000: nack receieved error: Slave is not responding back with the ACK. nack receieved error
6	ROX			DATA_REQUEST_000: data request: FIFO needs to be accesssed some more times to full fill the expectation data request
7	ROX			cmd_complete_000 command complete : Indicates the completion of command
8	ROX			STOP_ERROR_000: stop error: Didnot able to send the stop condition on the BUS stop error
9:15	ROX			max_num_of_ports_000 maximum number of ports defined for this Engine
16	ROX			any_i2c_int_000 any_i2c_int
17:18	RO			constant=0b00
19	ROX			i2c_port_history_busy_000 i2c_port_history_busy_000
20	ROX			scl_syn_000 scl_syn
21	ROX			sda_syn_000 sda_syn
22	ROX			i2c_busy_000 i2c busy: I2C bus is occupied
23	ROX			SELF_BUSY_000: self busy: I2C bus is occupied by itself self busy: I2C bus is occupied by itself
24:27	RO			constant=0b0000
28:31	ROX			FIFO_ENTRY_COUNT_000: fifo_entry count : Number of bytes present in the FIFO fifo_entry count : Number of bytes present in the FIFO

EXTENDED_STATUS_A
Addr:	0000000000001808 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_I2C.EXTENDED_STATUS_A
Constant(s):	PERV_FSII2C_EXTENDED_STATUS_A
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_I2C.I2CM.FIFO_SIZE(0:7) [00000000]
	11:15	TP.TPVSB.FSI.W.FSI_I2C.I2CM.FREE_RUNNING_LATCHES_INST.FSILAT.LATCH.LATC.L2(39:43) [00000]
	16	TP.TPVSB.FSI.W.FSI_I2C.I2CM.SCL_SYN(0) [0]
	17	TP.TPVSB.FSI.W.FSI_I2C.I2CM.SDA_SYN(0) [0]
	18:19	TP.TPVSB.FSI.W.FSI_I2C.I2CM.FREE_RUNNING_LATCHES_INST.FSILAT.LATCH.LATC.L2(46:47) [00]
	20	TP.TPVSB.FSI.W.FSI_I2C.I2CM.FREE_RUNNING_LATCHES_INST.FSILAT.LATCH.LATC.L2(38) [0]
	25	TP.TPVSB.FSI.W.FSI_I2C.I2CM.FREE_RUNNING_LATCHES_INST.FSILAT.LATCH.LATC.L2(37) [0]
Bit(s)	SCOM			Dial: Description
0:7	ROX			fifo_size_000 total fifo size
8:10	RO			constant=0b000
11:15	ROX			MSM_CURR_STATE_000: current state current state
16	ROX			scl_syn_ext_000 scl_syn
17	ROX			sda_syn_ext_000 sda_syn
18	ROX			s_scl_000 s_scl : clock input for wrap mode
19	ROX			s_sda_000 s_sda : Data input for wrap mode
20	ROX			m_scl_000 m_scl : clock output for wrap mode
21	ROX			m_sda_000 m_sda : data output for wrap mode
22	ROX			high_water_000 high water mark : FIFO reached higest water level
23	ROX			low_water_000 low water mark : FIFO reached lowest water level
24	ROX			i2c_busy_ext_000 i2c busy : I2C bus is busy
25	ROX			SELF_BUSY_000: self busy: I2C bus is occupied by itself self busy : I2C bus is held busy by itself
26:31	RO			constant=0b011000

IMM_RESET_ERR_A
Addr:	0000000000001808 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_I2C.IMM_RESET_ERR_A
Constant(s):	PERV_FSII2C_IMM_RESET_ERR_A
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_reset_errors_000 resets fifo ,some status bits and state machine

IMM_SET_S_SCL_A
Addr:	0000000000001809 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_I2C.IMM_SET_S_SCL_A
Constant(s):	PERV_FSII2C_IMM_SET_S_SCL_A
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_set_s_scl_000 sets output s_scl

RESIDUAL_FRONT_END_BACK_END_LENGTH_A
Addr:	0000000000001809 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_I2C.RESIDUAL_FRONT_END_BACK_END_LENGTH_A
Constant(s):	PERV_FSII2C_RESIDUAL_FRONT_END_BACK_END_LENGTH_A
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPVSB.FSI.W.FSI_I2C.I2CM.RESID_FE_LEN_INST.FSILAT.LATCH.LATC.L2(0:15) [0000000000000000]
	16:31	TP.TPVSB.FSI.W.FSI_I2C.I2CM.RESID_BE_LEN(0:15) [0000000000000000]
Bit(s)	SCOM			Dial: Description
0:15	ROX			RESID_FE_LEN_000: residual front end length register residual front end length register
16:31	ROX			resid_be_len_000 residual back end length register

I2C_BUSY_REGISTER_A
Addr:	000000000000180A (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_I2C.I2C_BUSY_REGISTER_A
Constant(s):	PERV_FSII2C_I2C_BUSY_REGISTER_A
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:17	TP.TPVSB.FSI.W.FSI_I2C.I2CM.I2C_BUSY_ALL_0_INST.FSILAT.LATCH.LATC.L2(0:17) [000000000000000000]
	18:31	TP.TPVSB.FSI.W.FSI_I2C.I2CM.I2C_BUSY_REG(18:31) [00000000000000]
Bit(s)	SCOM			Dial: Description
0:31	RWX			port_busy_000 corresponding port is busy if it is '1' no one should access . If '0' can be accessed

IMM_RESET_S_SCL_A
Addr:	000000000000180B (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_I2C.IMM_RESET_S_SCL_A
Constant(s):	PERV_FSII2C_IMM_RESET_S_SCL_A
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_reset_s_scl_000 resets output s_scl

IMM_SET_S_SDA_A
Addr:	000000000000180C (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_I2C.IMM_SET_S_SDA_A
Constant(s):	PERV_FSII2C_IMM_SET_S_SDA_A
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_set_s_sda_000 sets output s_sda

IMM_RESET_S_SDA_A
Addr:	000000000000180D (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_I2C.IMM_RESET_S_SDA_A
Constant(s):	PERV_FSII2C_IMM_RESET_S_SDA_A
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_reset_s_sda_000 resets output s_sda

FSI data register 0
Addr:	0000000000001C00 (FSI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.DATA_REGISTER_0
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.D0_LTH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI			Dial: Description
0:31	RWX			DATA_REG_0: First 32 bits for PIB access

FSI data register 1
Addr:	0000000000001C01 (FSI) 0000000000001C04 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.DATA_REGISTER_1
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.D1_LTH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	RWX	RWX		DATA_REG_1: Second 32 bits for PIB access

contains command to the FSI2PIB engine
Addr:	0000000000001C02 (FSI) 0000000000001C08 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.COMMAND_REGISTER
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.A_LTH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	RWX	RWX		CMD_REG: command register

resets data,command,status registers
Addr:	0000000000001C06 (FSI) 0000000000001C18 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.RESET
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0	WOX_1P	WOX_1P		reset resets command,mode,watermark,interrupt mask,status,complement mask,true mask registers

Reset PIB master IF
Addr:	0000000000001C07 (FSI) 0000000000001C1C (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.SET_PIB_RESET
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0	WOX_1P	WOX_1P		set_pib_reset Reset PIB master IF

status register
Addr:	0000000000001C07 (FSI) 0000000000001C1C (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.STATUS
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.STATUS_LTH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0	ROX	ROX		ANY_ERROR: One of the following STATUS register bits are active: bit1 or bit2 or bit3 or bit5
1	ROX	ROX		RESERVED_1: Reserved
2	ROX	ROX		RESERVED_2: Reserved
3	ROX	ROX		RESERVED_3: Reserved
4	ROX	ROX		RESERVED_4: Reserved
5	ROX	ROX		PARITY_CHECK: FSI2PIB engine has detected parity error
6	ROX	ROX		RESERVED_6: Reserved
7	ROX	ROX		PROTECTION_CHECK: FSI2PIB engine blocked operation due to security
8	ROX	ROX		RESERVED_8: Reserved
9	ROX	ROX		RESERVED_9: Reserved
10	ROX	ROX		IDLE_INDICATION: IDLE indication of pib_master interface component. 0b0 = unit is requesting a PIB operation to pib master or pib master is still in busy state. When being in gsd2pib mode then it indicates a busy CBS state machine.
11	ROX	ROX		PIB_ABORT: PIB reset occured during requested/granted PIB operation
12:15	ROX	ROX		RESERVED_12_15: Reserved
16	ROX	ROX		RESERVED_16: Reserved
17:19	ROX	ROX		PIB_ERROR_CODE: PIB response code: 0b000 = no error 0b001 = XSCOM command blocked (resource in use). Retry later 0b010 = chiplet offline 0b011 = partial good 0b100 = invalid address, address error, access error (bad access type) 0b101 = clock error 0b110 = address parity error, data parity error, unexpected packet, wrong packet number, protocol two phase handshaking error 0b111 = timeout
20:27	ROX	ROX		RESERVED_20_27: Reserved
28	ROX	ROX		INTERRUPT_CONDITION_PENDING: Pending FSI2PIB interrupt condition
29	ROX	ROX		INTERRUPT_ENABLED: FSI2PIB interrupt enabled
30:31	ROX	ROX		RESERVED_30_31: Reserved

INTERRUPT STATUS register
Addr:	0000000000001C0B (FSI) 0000000000001C2C (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.INTERRUPT
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.INT_STATUS_REG.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	ROX	ROX		INTERRUPT_STATUS_REG: Contains status information, but gets frozen when interrupt occurs

Complement mask register
Addr:	0000000000001C0C (FSI) 0000000000001C30 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.COMPLEMENT_MASK
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.CM_LTH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	RWX	RWX		COMPLEMENT_MASK_REG: Complement Mask for controlling generation of interrupts

True Mask Register
Addr:	0000000000001C0D (FSI) 0000000000001C34 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.TRUE_MASK
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.TM_LTH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	RWX	RWX		TRUE_MASK_REG: True Mask for controlling generation of interrupts

Enqueuing location of upstream FIFO
Addr:	0000000000002400 (FSI)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_UPFIFO_DATA_IN
Constant(s):	PERV_FSB_FSB_UPFIFO_DATA_IN
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.SBE_FIFO_INST1.UPFIFO_DATA_IN(0:31) [00000000000000000000000000000000]
Bit(s)	FSI			Dial: Description
0:31	WOX			upfifo_data_in_port

Status register of upstream FIFO
Addr:	0000000000002401 (FSI) 0000000000002404 (FSI_BYTE) 00000000000B0001 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_UPFIFO_STATUS
Constant(s):	PERV_FSB_FSB_UPFIFO_STATUS PU_FSB_UPFIFO_STATUS
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	2	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.SBE_FIFO_INST1.Q_UPFIFO_STATUS_LATCH.LATC.L2(2) [0]
	6:8	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.SBE_FIFO_INST1.Q_UPFIFO_STATUS_LATCH.LATC.L2(6:8) [000]
	10:31	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.SBE_FIFO_INST1.Q_UPFIFO_STATUS_LATCH.LATC.L2(10:31) [0000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:1	RO	RO	RO	constant=0b00
2	ROX	ROX	ROX	UPFIFO_STATUS_DATA_OUT_PARITY: Dequeuing operation has detected a parity error
3:5	RO	RO	RO	constant=0b000
6	ROX	ROX	ROX	UPFIFO_STATUS_REQ_RESET_FR_SP: External Service Processor (SP) is requesting a FIFO reset
7	ROX	ROX	ROX	UPFIFO_STATUS_REQ_RESET_FR_SBE: SBE is requesting a FIFO reset through downstream path
8	ROX	ROX	ROX	UPFIFO_STATUS_DEQUEUED_EOT_FLAG: A fifo entry has been dequeued with set EOT flag
9	RO	RO	RO	constant=0b0
10	ROX	ROX	ROX	UPFIFO_STATUS_FIFO_FULL: Upstream FIFO is full
11	ROX	ROX	ROX	UPFIFO_STATUS_FIFO_EMPTY: Upstream FIFO is empty
12:15	ROX	ROX	ROX	UPFIFO_STATUS_FIFO_ENTRY_COUNT: Number of currently hold entries
16:23	ROX	ROX	ROX	UPFIFO_STATUS_FIFO_VALID_FLAGS: Valid flags of ALL currently hold entries
24:31	ROX	ROX	ROX	UPFIFO_STATUS_FIFO_EOT_FLAGS: EOT flags of ALL currently hold entries

Signaling location for EndOfTransfer (EOT)
Addr:	0000000000002402 (FSI) 0000000000002408 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_UPFIFO_SIG_EOT
Constant(s):	PERV_FSB_FSB_UPFIFO_SIG_EOT
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.SBE_FIFO_INST1.UPFIFO_DATA_IN(33) [0]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0	WOX	WOX		upfifo_signal_EOT

Signaling location for requesting FIFO reset
Addr:	0000000000002403 (FSI) 000000000000240C (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_UPFIFO_REQ_RESET
Constant(s):	PERV_FSB_FSB_UPFIFO_REQ_RESET
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0	WOX	WOX		upfifo_req_reset

Dequeuing location of downstream FIFO
Addr:	0000000000002410 (FSI) 0000000000002440 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_DNFIFO_DATA_OUT
Constant(s):	PERV_FSB_FSB_DNFIFO_DATA_OUT
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.SBE_FIFO_INST1.DNFIFO_DATA_OUT(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	ROX	ROX		dnfifo_data_out_port

Status register of downstream FIFO
Addr:	0000000000002411 (FSI) 0000000000002444 (FSI_BYTE) 00000000000B0011 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_DOWNFIFO_STATUS
Constant(s):	PERV_FSB_FSB_DOWNFIFO_STATUS PU_FSB_DOWNFIFO_STATUS
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	2	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.SBE_FIFO_INST1.Q_DNFIFO_STATUS_LATCH.LATC.L2(2) [0]
	6:31	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.SBE_FIFO_INST1.Q_DNFIFO_STATUS_LATCH.LATC.L2(6:31) [00000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:1	RO	RO	RO	constant=0b00
2	ROX	ROX	ROX	DNFIFO_STATUS_DATA_OUT_PARITY: Dequeuing operation has detected a parity error
3:5	RO	RO	RO	constant=0b000
6	ROX	ROX	ROX	DNFIFO_STATUS_REQ_RESET_FR_SBE: SBE is requesting a FIFO reset
7	ROX	ROX	ROX	DNFIFO_STATUS_REQ_RESET_FR_SP: External Service Processor (SP) is requesting a FIFO reset through upstream path
8	ROX	ROX	ROX	DNFIFO_STATUS_DEQUEUED_EOT_FLAG: A fifo entry has been dequeued with set EOT flag
9	RW	RW	RW
10	ROX	ROX	ROX	DNFIFO_STATUS_FIFO_FULL: Downstream FIFO is full
11	ROX	ROX	ROX	DNFIFO_STATUS_FIFO_EMPTY: Downstream FIFO is empty
12:15	ROX	ROX	ROX	DNFIFO_STATUS_FIFO_ENTRY_COUNT: Number of currently hold entries
16:23	ROX	ROX	ROX	DNFIFO_STATUS_FIFO_VALID_FLAGS: Valid flags of ALL currently hold entries
24:31	ROX	ROX	ROX	DNFIFO_STATUS_FIFO_EOT_FLAGS: EOT flags of ALL currently hold entries

Applying reset function to upstream and downstream FIFO
Addr:	0000000000002414 (FSI) 0000000000002450 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_DOWNFIFO_RESET
Constant(s):	PERV_FSB_FSB_DOWNFIFO_RESET
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0	WOX	WOX		dnfifo_reset

Acknowledging EndOfTransfer (EOT)
Addr:	0000000000002415 (FSI) 0000000000002454 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_DOWNFIFO_ACK_EOT
Constant(s):	PERV_FSB_FSB_DOWNFIFO_ACK_EOT
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0	WOX	WOX		dnfifo_ack_EOT

Limits the 32bit data word transfer through the downstream FIFO
Addr:	0000000000002416 (FSI) 0000000000002458 (FSI_BYTE) 00000000000B0016 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_DOWNFIFO_MTC
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.SBE_FIFO_INST1.Q_DNFIFO_MTC_LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	RWX	DNFIFO_MCT: Max Transfer Counter

Enqueuing location of Host upstream FIFO
Addr:	0000000000002420 (FSI) 0000000000002480 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HUPFIFO_DATA_IN
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.SBE_FIFO_INST2.UPFIFO_DATA_IN(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	WOX	WOX		hupfifo_data_in_port

Status register of Host upstream FIFO
Addr:	0000000000002421 (FSI) 0000000000002484 (FSI_BYTE) 00000000000B0021 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HUPFIFO_STATUS
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	2	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.SBE_FIFO_INST2.Q_UPFIFO_STATUS_LATCH.LATC.L2(2) [0]
	6:8	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.SBE_FIFO_INST2.Q_UPFIFO_STATUS_LATCH.LATC.L2(6:8) [000]
	10:31	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.SBE_FIFO_INST2.Q_UPFIFO_STATUS_LATCH.LATC.L2(10:31) [0000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:1	RO	RO	RO	constant=0b00
2	ROX	ROX	ROX	HUPFIFO_STATUS_DATA_OUT_PARITY: Dequeuing operation has detected a parity error
3:5	RO	RO	RO	constant=0b000
6	ROX	ROX	ROX	HUPFIFO_STATUS_REQ_RESET_FR_SP: Host is requesting a FIFO reset
7	ROX	ROX	ROX	HUPFIFO_STATUS_REQ_RESET_FR_SBE: SBE is requesting a FIFO reset through downstream path
8	ROX	ROX	ROX	HUPFIFO_STATUS_DEQUEUED_EOT_FLAG: A fifo entry has been dequeued with set EOT flag
9	RO	RO	RO	constant=0b0
10	ROX	ROX	ROX	HUPFIFO_STATUS_FIFO_FULL: Host Upstream FIFO is full
11	ROX	ROX	ROX	HUPFIFO_STATUS_FIFO_EMPTY: Host Upstream FIFO is empty
12:15	ROX	ROX	ROX	HUPFIFO_STATUS_FIFO_ENTRY_COUNT: Number of currently hold entries
16:23	ROX	ROX	ROX	HUPFIFO_STATUS_FIFO_VALID_FLAGS: Valid flags of ALL currently hold entries
24:31	ROX	ROX	ROX	HUPFIFO_STATUS_FIFO_EOT_FLAGS: EOT flags of ALL currently hold entries

Signaling location for EndOfTransfer (EOT)
Addr:	0000000000002422 (FSI) 0000000000002488 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HUPFIFO_SIG_EOT
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.SBE_FIFO_INST2.UPFIFO_DATA_IN(33) [0]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0	WOX	WOX		hupfifo_signal_EOT

Signaling location for requesting FIFO reset
Addr:	0000000000002423 (FSI) 000000000000248C (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HUPFIFO_REQ_RESET
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0	WOX	WOX		hupfifo_req_reset

Dequeuing location of Host downstream FIFO
Addr:	0000000000002430 (FSI) 00000000000024C0 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HDNFIFO_DATA_OUT
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.SBE_FIFO_INST2.DNFIFO_DATA_OUT(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	ROX	ROX		hdnfifo_data_out_port

Status register of Host downstream FIFO
Addr:	0000000000002431 (FSI) 00000000000024C4 (FSI_BYTE) 00000000000B0031 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HDOWNFIFO_STATUS
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	2	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.SBE_FIFO_INST2.Q_DNFIFO_STATUS_LATCH.LATC.L2(2) [0]
	6:31	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.SBE_FIFO_INST2.Q_DNFIFO_STATUS_LATCH.LATC.L2(6:31) [00000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:1	RO	RO	RO	constant=0b00
2	ROX	ROX	ROX	HDNFIFO_STATUS_DATA_OUT_PARITY: Dequeuing operation has detected a parity error
3:5	RO	RO	RO	constant=0b000
6	ROX	ROX	ROX	HDNFIFO_STATUS_REQ_RESET_FR_SBE: SBE is requesting a FIFO reset
7	ROX	ROX	ROX	HDNFIFO_STATUS_REQ_RESET_FR_SP: Host is requesting a FIFO reset through upstream path
8	ROX	ROX	ROX	HDNFIFO_STATUS_DEQUEUED_EOT_FLAG: A fifo entry has been dequeued with set EOT flag
9	RW	RW	RW
10	ROX	ROX	ROX	HDNFIFO_STATUS_FIFO_FULL: Host Downstream FIFO is full
11	ROX	ROX	ROX	HDNFIFO_STATUS_FIFO_EMPTY: Host Downstream FIFO is empty
12:15	ROX	ROX	ROX	HDNFIFO_STATUS_FIFO_ENTRY_COUNT: Number of currently hold entries
16:23	ROX	ROX	ROX	HDNFIFO_STATUS_FIFO_VALID_FLAGS: Valid flags of ALL currently hold entries
24:31	ROX	ROX	ROX	HDNFIFO_STATUS_FIFO_EOT_FLAGS: EOT flags of ALL currently hold entries

Applying reset function to Host upstream and downstream FIFO
Addr:	0000000000002434 (FSI) 00000000000024D0 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HDOWNFIFO_RESET
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0	WOX	WOX		hdnfifo_reset

Acknowledging EndOfTransfer (EOT)
Addr:	0000000000002435 (FSI) 00000000000024D4 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HDOWNFIFO_ACK_EOT
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0	WOX	WOX		hdnfifo_ack_EOT

Limits the 32bit data word transfer through the Host downstream FIFO
Addr:	0000000000002436 (FSI) 00000000000024D8 (FSI_BYTE) 00000000000B0036 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HDOWNFIFO_MTC
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.SBE_FIFO_INST2.Q_DNFIFO_MTC_LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	RWX	HDNFIFO_MCT: Host Max Transfer Counter

SBE2FSI Interrupt Status Register
Addr:	0000000000002470 (FSI) 00000000000025C0 (FSI_BYTE) 00000000000B0070 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.SBE2FSI_INTR_STATUS
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.Q_SBE2FSI_INTR_LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	ROX	SBE2FSI_INTR_STATUS_VEC: Displays SBE-triggered interrupts

ACKnowledge/CLEAR SBE2FSI Interrupt
Addr:	0000000000002472 (FSI) 00000000000025C8 (FSI_BYTE)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.SBE2FSI_INTR_CLEAR
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.Q_SBE2FSI_INTR_LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE		Dial: Description
0:31	WO_CLEAR	WO_CLEAR		SBE2FSI_INTR_STATUS_VEC: Displays SBE-triggered interrupts

CBS Control/Status register
Addr:	0000000000002801 (FSI) 0000000000002804 (FSI_BYTE) 0000000000050001 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBS_CS
Constant(s):	PERV_CBS_CS
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBSREG.CBS_CS_LATCH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	RWX	RWX	RWX	CBS_CS_START_BOOT_SEQUENCER: Start Boot Sequencer explicitly
1	RWX	RWX	RWX	CBS_CS_1_UNUSED: unused.
2	RWX	RWX	RWX	CBS_CS_OPTION_SKIP_SCAN0_CLOCKSTART: If set to then scan0 and clockstart command is skipped. Used for memory preserved reIPL.
3	RWX	RWX	RWX	CBS_CS_OPTION_PREVENT_SBE_START: If set then start of SBE is suppressed
4	ROX	ROX	ROX	CBS_CS_SECURE_ACCESS_BIT: Secure access bit (SAB)
5	ROX	ROX	ROX	CBS_CS_SAMPLED_SMD_PIN: Sampled state of Secure Mode Disable c4 pin (SMD)
6:15	RWX	RWX	RWX	CBS_CS_STATE_MACHINE_TRANSITION_DELAY: Defines transition delay of boot sequencer state machine (in FSI clock cycles). default value=128+32 FSI cycles
16:31	NCX	NCX	NCX	CBS_CS_INTERNAL_STATE_VECTOR: current state of CBS state machine

CBS Trace register
Addr:	0000000000002802 (FSI) 0000000000002808 (FSI_BYTE) 0000000000050002 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBS_TR
Constant(s):	PERV_CBS_TR
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBSREG.CBS_TR_LATCH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:15	ROX	ROX	ROX	CBS_TR_SIGNATURE: CBS signature holds the visited states of the last boot sequence
16:21	ROX	ROX	ROX	CBS_TR_UNUSED: unused
22:31	ROX	ROX	ROX	CBS_TR_TRANS_DELAY: programmed transition delay of last boot sequence

CBS Event Log register
Addr:	0000000000002803 (FSI) 000000000000280C (FSI_BYTE) 0000000000050003 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBS_EL
Constant(s):	PERV_CBS_EL
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:19	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBSREG.EVENTLOG_LATCH.FSILAT.LATCH.LATC.L2(0:19) [00000000000000000000]
	24	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBSREG.EVENTLOG_LATCH.FSILAT.LATCH.LATC.L2(24) [0]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:15	ROX	ROX	ROX	CBS_EL_ENVSTAT_CHANGE: C4 pin state changed since CBS was triggered (see CBS_ENVSTAT / 2804 for meanings of individual bits)
16	ROX	ROX	ROX	CBS_EL_PGOOD_DROP_DURING_CBS: VDN PGOOD dropped during CBS sequence
17	ROX	ROX	ROX	CBS_EL_PGOOD_DROP_AFTER_CBS: VDN PGOOD dropped after CBS was done
18	ROX	ROX	ROX	CBS_EL_CTRL_WRITE_DURING_CBS: ROOT/PERV_CTRL register write occurred during CBS sequence
19	ROX	ROX	ROX	CBS_EL_INVALID_STATE: The CBS state machine visited an invalid state
20:23	RO	RO	RO	constant=0b0000
24	ROX	ROX	ROX	CBS_EL_PGOOD_LOW_WHILE_UNFENCED: VDN PGOOD was low while one of the FSI protections was lowered - possible Xstate propagation into CFAM
25:31	RO	RO	RO	constant=0b0000000

CBS Environment Status Register
Addr:	0000000000002804 (FSI) 0000000000002810 (FSI_BYTE) 0000000000050004 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBS_ENVSTAT
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBSREG.ENV_STAT_LATCH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	ROX	ROX	ROX	CBS_ENVSTAT_C4_TEST_ENABLE: Displays current state of test_enable c4 pin
1	ROX	ROX	ROX	CBS_ENVSTAT_C4_CARD_TEST_BSC: Displays current state of CARD_TEST_BSC c4 pin
2	ROX	ROX	ROX	CBS_ENVSTAT_C4_VDN_PGOOD: Displays current state of VDN_PGOOD c4 pin
3	ROX	ROX	ROX	CBS_ENVSTAT_C4_FSI_IN_ENA: Displays current state of FSI_IN_ENA c4 pin
4	ROX	ROX	ROX	CBS_ENVSTAT_C4_CHIP_MASTER: Displays current state of CHIP_MASTER c4 pin
5	ROX	ROX	ROX	CBS_ENVSTAT_C4_SMD: Displays current state of SMD c4 pin
6	ROX	ROX	ROX	CBS_ENVSTAT_C4_JTAG_TMS: Displays current state of JTAG TMS c4 pin
7:23	ROX	ROX	ROX	cbs_envstat_remainder
24:27	ROX	ROX	ROX	CBS_ENVSTAT_MAJOR_EC: Chip major EC, mirrored from CFAM Chip ID bits 0:3
28:31	ROX	ROX	ROX	CBS_ENVSTAT_MINOR_EC: Chip minor EC, mirrored from CFAM Chip ID bits 8:11

CBS Trace of previeous boot
Addr:	0000000000002805 (FSI) 0000000000002814 (FSI_BYTE) 0000000000050005 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBS_TR_HIST
Constant(s):	PERV_CBS_TR_HIST
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBSREG.CBS_TR_HIST_LATCH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	ROX

CBS Event Log of previous boot
Addr:	0000000000002806 (FSI) 0000000000002818 (FSI_BYTE) 0000000000050006 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBS_EL_HIST
Constant(s):	PERV_CBS_EL_HIST
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBSREG.EVENTLOG_HIST_LATCH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	ROX

Selfboot Control/Status register
Addr:	0000000000002808 (FSI) 0000000000002820 (FSI_BYTE) 0000000000050008 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SB_CS
Constant(s):	PERV_SB_CS
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBSREG.SB_CS_LATCH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	RWX_WOR	RWX_WOR	RWX_WOR	SB_CS_SECURE_DEBUG_MODE: sticky bit:Secure Debug Mode (SDM)
1:11	RW	RW	RW
12	RWX	RWX	RWX	SB_CS_START_RESTART_VECTOR0: SBE Start or restart IPL code execution
13	RWX	RWX	RWX	SB_CS_START_RESTART_VECTOR1: SBE Start or restart RUNTIME code execution
14	RWX	RWX	RWX	SB_CS_INTERRUPT_S0: SBE Interrupt S0
15	RWX	RWX	RWX	SB_CS_INTERRUPT_S1: SBE Interrupt S1
16	RWX	RWX	RWX	SB_CS_BYPASSING_RESET_SEQUENCE_PIB_I2CM: If set then PIB I2CM reset command is skipped
17	RWX	RWX	RWX	SB_CS_SELECT_SECONDARY_SEEPROM: Select BOOT SEEPROM: 0b0 = Primary SEEPROM 0b1 = Secondary SEEPROM
18	RWX	RWX	RWX	SB_CS_SELECT_SECONDARY_MEAS_SEEPROM: Select Measurement SEEPROM: 0b0 = Primary SEEPROM (MEASUREMENT) 0b1 = Secondary SEEPROM (MVPD)
19:31	RW	RW	RW

Selfboot Message register
Addr:	0000000000002809 (FSI) 0000000000002824 (FSI_BYTE) 0000000000050009 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SB_MSG
Constant(s):	PERV_SB_MSG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBSREG.SB_MSG_LATCH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	RWX

Debug CBS Pervasive Clock Controller
Addr:	000000000000280B (FSI) 000000000000282C (FSI_BYTE) 000000000005000B (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBS_STAT
Constant(s):	PERV_CBS_STAT
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBSREG.CBS_STAT_LATCH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	ROX	ROX	ROX	CBS_STAT_DBG_RESET_EP: Reset Endpoint - Is the CC and CTRL in reset state.
1	ROX	ROX	ROX	CBS_STAT_DBG_OPCG_IP: OPCG in progress, not in idle.
2	ROX	ROX	ROX	CBS_STAT_DBG_VITL_CLKOFF: VITL HLD stopped, when enabled, need plat-depth cycles to switch this latch.
3	ROX	ROX	ROX	CBS_STAT_DBG_TEST_ENABLE: Test Enable.
4	ROX	ROX	ROX	CBS_STAT_DBG_CBS_REQ: CBS Interface - Request (Latched).
5:7	ROX	ROX	ROX	CBS_STAT_DBG_CBS_CMD: CBS Interface - Command (Latched)
8:12	ROX	ROX	ROX	CBS_STAT_DBG_CBS_STATE: CBS Command State Machine 00000=Idle.
13	ROX	ROX	ROX	CBS_STAT_DBG_SECURITY_DEBUG_MODE: status of the security mode bit
14	ROX	ROX	ROX	CBS_STAT_DBG_PROTOCOL_ERROR: CBS Protocol Error - REQ raised, although state machine is not in IDLE - need reset_ep to clear this bit. No impact on IPL.
15	ROX	ROX	ROX	CBS_STAT_DBG_PCB_IDLE: PCB interface in IDLE state.
16:19	ROX	ROX	ROX	CBS_STAT_DBG_CURRENT_OPCG_MODE: current / latest OPCG MODE - 0=NOP, 1=LBIST, 2=ABIST, 3=RUNN, 4=SCAN0, 5=SCAN, 6=SCAN rotate, 7=SCAN w UpdateDR, 8=SCAN w CaptureDR, 9=nonblocking SCAN, 10=CLK Change Request, 10-15=unused
20:23	ROX	ROX	ROX	CBS_STAT_DBG_LAST_OPCG_MODE: previous OPCG mode
24	ROX	ROX	ROX	CBS_STAT_DBG_PCB_ERROR: PCB Interface Error, read CC Error Reg or set CBS_CMD=001 to switch FSI CBS Debug Information to CC Error Register.
25	ROX	ROX	ROX	CBS_STAT_DBG_PARITY_ERROR: Any Parity Error, non PCB Parity - read CC Error Reg or set CBS_CMD=001 to switch FSI CBS Debug Information to CC Error Register.
26	ROX	ROX	ROX	CBS_STAT_DBG_CC_ERROR: Any other CC Error - read CC Error Reg or set CBS_CMD=001 to switch FSI CBS Debug Information to CC Error Register.
27	ROX	ROX	ROX	CBS_STAT_DBG_CHIPLET_IS_ALIGNED: is at 1 when the valid align pulse was sent out
28	ROX	ROX	ROX	CBS_STAT_DBG_PCB_REQUEST_SINCE_RESET: reset will clear that bit and the first PCB request will set it.
29	ROX	ROX	ROX	CBS_STAT_DBG_PARANOIA_TEST_ENABLE_CHANGE: rising or falling edge on test enable after reset. Needs a reset_endpoint to clear. No impact on IPL
30	ROX	ROX	ROX	CBS_STAT_DBG_PARANOIA_VITL_CLKOFF_CHANGE: rising or falling edge on vitl_clkoff after reset. Needs a reset_endpoint to clear. No impact on IPL
31	ROX	ROX	ROX	CBS_STAT_DBG_TP_TPFSI_CBS_ACK: representation of CC ACK going to FSI

ROOT CONTROL 0 register
Addr:	0000000000002810 (FSI) 0000000000002840 (FSI_BYTE) 0000000000050010 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL0
Constant(s):	PERV_ROOT_CTRL0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL0_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	RW	RW	RW	CFAM_PROTECTION_0_DC: CFAM protection 0 for RCS interface
1	RW	RW	RW	ROOT_CTRL0_1_SPARE: Not used
2	RW	RW	RW	TPFSI_TPI2C_BUS_FENCE_DC: I2C master bus fence
3:5	RW	RW	RW	TPCFSI_OPB_SW0_FENCE_DC: OPB0 ARBITER (FSI0 side): Fence off arbitration requests from OPB master: bit3 : FSI slave0 bit4 : PIB2OPB Host bit5 : PIB2OPB none-Host
6:7	RW	RW	RW	ROOT_CTRL0_6_7_SPARE: Not used.
8	RW	RW	RW	CFAM_PROTECTION_1_DC: CFAM protection 1 for CBS/VITL interface
9	RW	RW	RW	CFAM_PROTECTION_2_DC: CFAM protection 2 for PIB_master/slave interfaces
10	RW	RW	RW	CFAM_PIB_SLV_RESET_DC: Functionally resets all PIB slave instances on CFAM
11	RW	RW	RW	ROOT_CTRL0_11_SPARE: Not used.
12	RW	RW	RW	ROOT_CTRL0_12_SPARE: Not used.
13	RW	RW	RW	ROOT_CTRL0_13_SPARE: Not used.
14	RW	RW	RW	SPARE_FENCE_CONTROL: Not used
15	RW	RW	RW	VDD2VIO_LVL_FENCE_DC: PLL fence enable 0b0 = not fenced 0b1 = fenced
16	RW	RW	RW	FSI2PCB_DC: Directly connects FSI2PIB engine to pervasive chiplet (bypassing PIB and PCB)
17	RW	RW	RW	OOB_MUX: Select OOB (Out of Band) multiplexer
18	RW	RW	RW	PIB2PCB_DC: Directly connects SBE engine to pervasive chiplet (bypassing PCB)
19	RW	RW	RW	PCB2PCB_DC: Connects SBE engine to pervasive chiplet through PIB/PCB
20	RW	RW	RW	FSI_CC_VSB_CBS_REQ: CBS interface: Request signal from FSI to PERV_CC
21:23	RW	RW	RW	FSI_CC_VSB_CBS_CMD: CBS interface: Command from FSI to PERV_CC: 0b000 = NOP - could be used to test if clocks in PERV chiplet are available 0b001 = RESET - reset PERV_CC only to init values 0b010 = SCAN0 - trigger scan0 on all regions 0b011 = CLK START - SBE region will be started 0b100 = CLK STOP - SBE region will be stopped 0b101 = NOP - unused 0b110 = NOP - unused 0b111 = SCAN0 & CLK START - used by CFAM Boot Sequencer (CBS)
24	RW	RW	RW	ROOT_CTRL0_24_SPARE_CBS_CONTROL: Not used
25	RW	RW	RW	ROOT_CTRL0_25_SPARE_CBS_CONTROL: Not used
26	RW	RW	RW	ROOT_CTRL0_26_SPARE_CBS_CONTROL: Not used
27	RW	RW	RW	ROOT_CTRL0_27_SPARE_CBS_CONTROL: Not used
28	RW	RW	RW	ROOT_CTRL0_28_SPARE_RESET: Not used
29	RW	RW	RW	TPFSI_IO_OCMB_RESET_EN: OCMB Reset Control: 0b0 = Disable OCMB reset 0b1 = Enable OCMB reset
30	RW	RW	RW	PCB_RESET_DC: PERV chiplet PCB interface reset - requires OOB mux to be selected
31	RW	RW	RW	GLOBAL_EP_RESET_DC: Global endpoint reset - asynchonously reset ALL chiplet vital logic except PERV

ROOT CONTROL 1 register
Addr:	0000000000002811 (FSI) 0000000000002844 (FSI_BYTE) 0000000000050011 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL1
Constant(s):	PERV_ROOT_CTRL1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL1_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:3	RW	RW	RW	TP_PROBE0_SEL_DC: PROBE0 select
4:7	RW	RW	RW	TP_PROBE1_SEL_DC: PROBE1 select
8	RW	RW	RW	TP_PROBE_MESH_SEL_DC: PROBE MESH select
9	RW	RW	RW	TP_PROBE_DRV_EN_DC: PROBE drive enable
10	RW	RW	RW	ROOT_CTRL1_10_SPARE: Not used
11:12	RW	RW	RW	TP_FSI_PROBE_SEL_DC: FSI PROBE select
13	RW	RW	RW	TP_AN_PROBE_DRVR_MCPRECOMP0_DC: Tune high speed probe I/Os
14	RW	RW	RW	TP_AN_PROBE_DRVR_MCPRECOMP1_DC: Tune high speed probe I/Os
15	RW	RW	RW	TP_AN_PROBE_DRVR_MCPRECOMP2_DC: Tune high speed probe I/Os
16	RW	RW	RW	TP_IDDQ_DC: IDDQ test (leakage)
17	RW	RW	RW	SPARE_RI_CONTROL: Not used
18	RW	RW	RW	SPARE_DI_CONTROL: Not used
19	RW	RW	RW	TP_RI_DC_B: Receiver inhibit (RI) of I/O books 0b0 = receiver disabled 0b1 = receiver enabled
20	RW	RW	RW	TP_DI1_DC_B: Driver inhibit (DI1) of I/O books: 0b0 = driver1 disabled 0b1 = driver1 enabled
21	RW	RW	RW	TP_DI2_DC_B: Driver inhibit (DI2) of I/O books 0b0 = driver2 disabled 0b1 = driver2 enabled
22	RW	RW	RW	TP_TPM_DI1_DC_B: Driver inhibit (DI1) of TPM I/O books: 0b0 = TPM driver1 disabled 0b1 = TPM driver1 enabled
23	RW	RW	RW	ROOT_CTRL1_23_SPARE_TEST: Not used
24	RW	RW	RW	TP_TEST_BURNIN_MODE_DC: Burn-in mode
25	RW	RW	RW	TPFSI_ARRAY_SET_VBL_TO_VDD_DC: Set array voltage block line to VDD
26	RW	RW	RW	TPFSI_TP_GLB_PERST_OVR_DC: Global PERST# override control. At '1', all PCI reset outputs will be forced low (active). Set to '0' to allow PHB control.
27	RW	RW	RW	ROOT_CTRL1_27_SPARE:
28	RW	RW	RW	ROOT_CTRL1_28_SPARE_TEST_CONTROL: Not used
29	RW	RW	RW	ROOT_CTRL1_29_SPARE_TEST_CONTROL: Not used
30	RW	RW	RW	ROOT_CTRL1_30_SPARE_TEST_CONTROL: Not used
31	RW	RW	RW	ROOT_CTRL1_31_SPARE_TEST_CONTROL: Not used

ROOT CONTROL 2 register
Addr:	0000000000002812 (FSI) 0000000000002848 (FSI_BYTE) 0000000000050012 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL2
Constant(s):	PERV_ROOT_CTRL2
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL2_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	RW	RW	RW	ROOT_CTRL2_0_SPARE: Not used.
1	RW	RW	RW	TPFSI_TP_DBG_PCB_DATA_PAR_DIS_DC: Debug only: PCB data parity disable
2	RW	RW	RW	TPFSI_TP_DBG_PCB_TYPE_PAR_DIS_DC: Debug only: PCB type parity disable
3	RW	RW	RW	ROOT_CTRL2_3_SPARE: Not used.
4	RW	RW	RW	TP_PIB_DISABLE_PARITY_DC: Disable parity check for PIB
5	RW	RW	RW	TP_PIB_TRACE_MODE_DATA_DC: PIB trace mode 0: traces addresses only 1: additionally trace request and response data - uses more trace entries
6	RW	RW	RW	TP_PIB_VSB_SBE_TRACE_MODE: SBE trace mode to SBE - forces SBE into a specific trace bus configuration
7	RW	RW	RW	TP_TPCPERV_VSB_TRACE_STOP: Trace stop signal to DBG macro.
8:10	RW	RW	RW	TP_GPIO_PIB_TIMEOUT: Timeout of PIB arbiter: PIB clock cycles 0b110 = 256 0b100 = 1024 0b010 = 8192 0b000 = 32768 0b--1 = not available (timeout function disabled)
11	RW	RW	RW	SPARE_PIB_CONTROL: Not used
12	RW	RW	RW	TPCFSI_OPB_SW_RESET_DC: Reset of OPB arbiter
13	RW	RW	RW	ROOT_CTRL2_13_SPARE_OPB_CONTROL: Not used
14	RW	RW	RW	ROOT_CTRL2_14_SPARE_OPB_CONTROL: Not used
15	RW	RW	RW	ROOT_CTRL2_15_SPARE_OPB_CONTROL: Not used
16	RW	RW	RW	ROOT_CTRL2_16_SPARE: Not used
17	RW	RW	RW	ROOT_CTRL2_17_SPARE: Not used.
18	RW	RW	RW	ROOT_CTRL2_18_SPARE: Not used
19	RW	RW	RW	ROOT_CTRL2_19_SPARE: Not used
20	RW	RW	RW	ROOT_CTRL2_20_SPARE: Not used.
21	RW	RW	RW	ROOT_CTRL2_21_FREE_USAGE: Not used
22	RW	RW	RW	ROOT_CTRL2_22_FREE_USAGE: Not used
23	RW	RW	RW	ROOT_CTRL2_23_FREE_USAGE: Not used
24	RW	RW	RW	ROOT_CTRL2_24_FREE_USAGE: Not used.
25	RW	RW	RW	ROOT_CTRL2_25_FREE_USAGE: Not used.
26	RW	RW	RW	ROOT_CTRL2_26_FREE_USAGE: Not used
27	RW	RW	RW	ROOT_CTRL2_27_FREE_USAGE: Not used
28	RW	RW	RW	ROOT_CTRL2_28_FREE_USAGE: Not used
29	RW	RW	RW	ROOT_CTRL2_29_FREE_USAGE: Not used
30	RW	RW	RW	ROOT_CTRL2_30_FREE_USAGE: Not used.
31	RW	RW	RW	ROOT_CTRL2_31_FREE_USAGE: Not used.

ROOT CONTROL 3 register
Addr:	0000000000002813 (FSI) 000000000000284C (FSI_BYTE) 0000000000050013 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL3
Constant(s):	PERV_ROOT_CTRL3
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL3_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	RW	RW	RW	TP_PLLCLKSW1_RESET_DC: PLLCLKSW1 reset
1	RW	RW	RW	TP_PLLCLKSW1_BYPASS_EN_DC: PLLCLKSW1 bypass
2	RW	RW	RW	TP_PLLCLKSW1_TEST_EN_DC: PLLCLKSW1 test enable
3	RW	RW	RW	TP_PLLCLKSW1_ALTREFCLK_SEL_DC: Use alternate refclk for PLLCLKSW1 - 0=OSC0 differential, 1=OSC1 single-ended
4	RW	RW	RW	TP_PLLCLKSW2_RESET_DC: PLLCLKSW2 reset
5	RW	RW	RW	TP_PLLCLKSW2_BYPASS_EN_DC: PLLCLKSW2 bypass
6	RW	RW	RW	TP_PLLCLKSW2_TEST_EN_DC: PLLCLKSW2 test enable
7	RW	RW	RW	TP_PLLCLKSW2_ALTREFCLK_SEL_DC: Use alternate refclk for PLLCLKSW2 - 0=OSC1 differential, 1=OSC0 single-ended
8	RW	RW	RW	TP_PLLTODFLT_RESET_DC: TOD filter PLL reset
9	RW	RW	RW	TP_PLLTODFLT_BYPASS_EN_DC: TOD filter PLL bypass
10	RW	RW	RW	TP_PLLTODFLT_TEST_EN_DC: TOD filter PLL test enable
11	RW	RW	RW	SPARE_PLLTODFLT: Not used
12	RW	RW	RW	TP_PLLNESTFLT_RESET_DC: Nest Filter PLL test enable
13	RW	RW	RW	TP_PLLNESTFLT_BYPASS_EN_DC: Nest Filter PLL bypass
14	RW	RW	RW	TP_PLLNESTFLT_TEST_EN_DC: Nest Filter PLL test enable
15	RW	RW	RW	SPARE_PLLNESTFLT: Not used
16	RW	RW	RW	TP_PLLIOFLT_RESET_DC: IO Filter PLL reset
17	RW	RW	RW	TP_PLLIOFLT_BYPASS_EN_DC: IO Filter PLL bypass
18	RW	RW	RW	TP_PLLIOFLT_TEST_EN_DC: IO Filter PLL test enable
19	RW	RW	RW	SPARE_PLLIOFLT: Not used
20	RW	RW	RW	TP_PLLIOSSFLT_RESET_DC: IO Spread Filter PLL reset
21	RW	RW	RW	TP_PLLIOSSFLT_BYPASS_EN_DC: IO Spread Filter PLL bypass
22	RW	RW	RW	TP_PLLIOSSFLT_TEST_EN_DC: IO Spread Filter PLL test enable
23	RW	RW	RW	SPARE_PLLIOSSFLT: Not used
24	RW	RW	RW	TP_PAU_DPLL_RESET_DC: PAU DPLL reset
25	RW	RW	RW	TP_PAU_DPLL_BYPASS_EN_DC: PAU DPLL bypass
26	RW	RW	RW	TP_PAU_DPLL_TEST_EN_DC: PAU DPLL test enable
27	RW	RW	RW	TP_PAU_DPLL_FUNC_CLKSEL_DC: PAU DPLL func clock select
28	RW	RW	RW	TP_NEST_DPLL_RESET_DC: NEST DPLL reset
29	RW	RW	RW	TP_NEST_DPLL_BYPASS_EN_DC: NEST DPLL bypass
30	RW	RW	RW	TP_NEST_DPLL_TEST_EN_DC: NEST DPLL test enable
31	RW	RW	RW	TP_NEST_DPLL_FUNC_CLKSEL_DC: NEST DPLL func clock select

ROOT CONTROL 4 register
Addr:	0000000000002814 (FSI) 0000000000002850 (FSI_BYTE) 0000000000050014 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL4
Constant(s):	PERV_ROOT_CTRL4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL4_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:1	RW	RW	RW	TP_AN_REFCLK_CLKMUX0A_CLKIN_SEL_DC: PLLTODFLT input selection: 00: SYS refclock 0 01: RCS async out 1x: RCS sync out
2:3	RW	RW	RW	TP_AN_REFCLK_CLKMUX0B_CLKIN_SEL_DC: PLLNESTFLT input selection: 00: SYS refclock 0 01: RCS async out 1x: RCS sync out
4:5	RW	RW	RW	TP_AN_REFCLK_CLKMUX0C_CLKIN_SEL_DC: PLLIOFLT input selection: 00: SYS refclock 0 01: RCS async out 1x: RCS sync out
6:7	RW	RW	RW	TP_AN_REFCLK_CLKMUX0D_CLKIN_SEL_DC: PLLIOSSFLT input selection: 00: SYS refclock 0 01: RCS async out 1x: RCS sync out
8	RW	RW	RW	TP_AN_REFCLK_CLKMUX10_CLKIN_SEL_DC: PAU DPLL input selection: 0: PLLIOSSFLT output 1: PLLIOFLT output
9	RW	RW	RW	TP_AN_REFCLK_CLKMUX11_CLKIN_SEL_DC: Nest DPLL input selection: 0: PLLIOSSFLT output 1: PLLIOFLT output
10:11	RW	RW	RW	TP_AN_REFCLK_CLKMUX12_CLKIN_SEL_DC: OMI PLL input selection: 00: PLLTODFLT output 01: PLLNESTFLT output 1x: PLLIOFLT output
12:13	RW	RW	RW	TP_AN_REFCLK_CLKMUX13_CLKIN_SEL_DC: AXON 133 MHz input selection: 00: PLLTODFLT output 01: PLLNESTFLT output 1x: PLLIOFLT output
14	RW	RW	RW	TP_AN_REFCLK_CLKMUX14_CLKIN_SEL_DC: AXON 156 MHz input selection: 0: PLLNESTFLT output 1: PLLIOFLT output
15:16	RW	RW	RW	TP_AN_REFCLK_CLKMUX23_CLKIN_SEL_DC: PCI PLL 100MHz input pre-selection (feeds per-chiplet muxes): 00: PLLTODFLT output 01: PLLIOSSFLT output 1x: MUX0D output / PLLIOSSFLT input
17	RW	RW	RW	TP_AN_TOD_LPC_MUX_SEL_DC: TOD input clock selection: 0: 32 MHz LPC clock 1: 16 MHz from PLLTODFLT
18	RW	RW	RW	ROOT_CTRL4_18_SPARE: Not used
19	RW	RW	RW	ROOT_CTRL4_19_SPARE: Not used
20	RW	RW	RW	TP_MUX1_CLKIN_SEL_DC: PAU/NEST input selection: 0: MUX10 output 1: TCK
21	RW	RW	RW	TP_MUX2A_CLKIN_SEL_DC: PAU input selection: 0: PAU DPLL output 1: MUX1 output
22	RW	RW	RW	TP_MUX2B_CLKIN_SEL_DC: Nest input selection 1: 0: PAU DPLL output 1: MUX1 output
23	RW	RW	RW	TP_MUX3_CLKIN_SEL_DC: Nest input selection 2: 0: Nest DPLL output 1: MUX2B output
24	RW	RW	RW	TP_MUX4A_CLKIN_SEL_DC: Nest/Cache mesh division ratio compared to core: 0: Divide by 2 1: No division
25	RW	RW	RW	TP_AN_CLKGLM_NEST_ASYNC_RESET_DC: Hold Nest mesh in reset if 1, enable Nest mesh if 0
26	RW	RW	RW	TP_AN_NEST_DIV2_ASYNC_RESET_DC: Reset Nest/Cache 2:1 dividers. Unstaged, so release before enabling Nest/Core/Cache meshes!
27	RW	RW	RW	TPFSI_ALTREFCLK_SEL: Force all chiplet PLLs into altrefclk mode
28	RW	RW	RW	ROOT_CTRL4_28_SPARE: Not used.
29	RW	RW	RW	TP_PLL_FORCE_OUT_EN_DC: Enable the chip level filter PLL outputs
30	RW	RW	RW	DPLL_FREEZE_DC: Set to 1 to make the Nest and PAU DPLLs ignore changes to their control inputs, e.g. for scanning the DPLL controllers
31	RW	RW	RW	TP_AN_MUX3_ASYNC_RESET_DC: Hold Nest/Core/Cache meshes in reset if 1, enable them if 0

ROOT CONTROL 5 register
Addr:	0000000000002815 (FSI) 0000000000002854 (FSI_BYTE) 0000000000050015 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL5
Constant(s):	PERV_ROOT_CTRL5
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL5_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	RW	RW	RW	TPFSI_RCS_RESET_DC: RCS reset
1	RW	RW	RW	TPFSI_RCS_BYPASS_DC: RCS bypass
2	RW	RW	RW	TPFSI_RCS_FORCE_BYPASS_CLKSEL_DC: RCS bypass clock select - 0: osc0, 1: osc1
3	RW	RW	RW	TPFSI_RCS_CLK_TEST_IN_DC: RCS clock test latch input - outputs in SNS1LTH (address 281D)
4	RW	RW	RW	SWO_FORCE_LOW: Used with FORCE_BYPASS_CLKSEL to manually force a switch over to alternate clk for concurrent maintenance
5	RW	RW	RW	BLOCK_SWO: Block error_a/b from switching over to the B/A side
6	RW	RW	RW	CLEAR_CLK_ERROR_A: Clear detected Path A clock error
7	RW	RW	RW	CLEAR_CLK_ERROR_B: Clear detected Path B clock error
8	RW	RW	RW	SEL_DEL: Error detector sample clock delay 0 = 156.25ps, 1 = 312.5ps
9:11	RW	RW	RW	RCS_CONTROL_10_8: RCS spare input CONTROL(10 downto 8)
12:15	RW	RW	RW	FILT: 6B Up/Dwn counter filter depth
16	RW	RW	RW	PFD_PW_SEL: Phase Freq Detector PW_SEL which extends INC/DEC signal widths
17	RW	RW	RW	FORCE_ERROR_HIGH: Force input high to check for stuck low error detect
18	RW	RW	RW	TESTOUT_EN: Enable CMOS output that connects to C4 mux
19:21	RW	RW	RW	TESTOUT_SEL: Select which of REFCLK_P/N or ASYNC_OUT_P/N or Input Clock CMOS output that connects to C4 mux
22	RW	RW	RW	EN_OVERRIDE_A: Enable ripple counter output bits override on the A side
23	RW	RW	RW	EN_OVERRIDE_B: Enable ripple counter output bits override on the B side
24:29	RW	RW	RW	OVRBIT: Ripple counter override output bits
30	RW	RW	RW	EN_REFCLK: Enable REFCLK output
31	RW	RW	RW	EN_ASYNC_OUT: Enable ASYNC_OUT output

ROOT CONTROL 6 register
Addr:	0000000000002816 (FSI) 0000000000002858 (FSI_BYTE) 0000000000050016 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL6
Constant(s):	PERV_ROOT_CTRL6
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL6_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:3	RW	RW	RW	ROOT_CTRL6_0_3: Not used
4:5	RW	RW	RW	TP_AN_PCI0_RX_REFCLK_TERM: PCI0 refclock receiver termination: 0b00 = 100 Ohm differential termination 0b10 = 50 Ohm to GND 0b01 = no termination 0b11 = no termination Dial enums: HUNDRED_OHM_DIFF=>0b00 FIFTY_OHM_SE=>0b10 NO_TERM=>0b11
6:7	RW	RW	RW	TP_AN_PCI1_RX_REFCLK_TERM: PCI1 refclock receiver termination: 0b00 = 100 Ohm differential termination 0b10 = 50 Ohm to GND 0b01 = no termination 0b11 = no termination Dial enums: HUNDRED_OHM_DIFF=>0b00 FIFTY_OHM_SE=>0b10 NO_TERM=>0b11
8	RW	RW	RW	CHKSW_DD1_HW547515_RCS_EVENTLOG: Chickenswitch for RCS eventLog: 0b0 = RCS eventLog logic is full functional and is able to capture up to 4 different states 0b1 = RCS eventLog logic is just able to capture one state (ie. install dd1 issue)
9:15	RW	RW	RW	ROOT_CTRL6_9_15: Not used
16:19	RW	RW	RW	DESKEW_SEL_A: Deskew value to align 100MHz REFCLK_A with 6.4GHz clock at shiftreg input
20:23	RW	RW	RW	DESKEW_SEL_B: Deskew value to align 100MHz REFCLK_A with 6.4GHz clock at shiftreg input
24:27	RW	RW	RW	RCS_CONTROL_7_4: RCS spare input CONTROL(7 downto 4)
28	RW	RW	RW	CHKSW_JUMP_FORWARD: RCS spare input CONTROL(3) - Jump forward chicken switch
29:30	RW	RW	RW	SEL_RES_AMP: RCS spare input CONTROL(2 downto 1) - SEL_RES inputs to adjust output amplitude
31	RW	RW	RW	MASK_UNLOCKDET: RCS spare input CONTROL(0) - Mask UNLOCKDET_* outputs

ROOT CONTROL 7 register
Addr:	0000000000002817 (FSI) 000000000000285C (FSI_BYTE) 0000000000050017 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL7
Constant(s):	PERV_ROOT_CTRL7
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL7_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	RW	RW	RW	TP_MEM0_REFCLK_DRVR_EN_DC: MEM0 reference clock driver enable
1	RW	RW	RW	TP_MEM1_REFCLK_DRVR_EN_DC: MEM1 reference clock driver enable
2	RW	RW	RW	TP_MEM2_REFCLK_DRVR_EN_DC: MEM2 reference clock driver enable
3	RW	RW	RW	TP_MEM3_REFCLK_DRVR_EN_DC: MEM3 reference clock driver enable
4	RW	RW	RW	TP_MEM4_REFCLK_DRVR_EN_DC: MEM4 reference clock driver enable
5	RW	RW	RW	TP_MEM5_REFCLK_DRVR_EN_DC: MEM5 reference clock driver enable
6	RW	RW	RW	TP_MEM6_REFCLK_DRVR_EN_DC: MEM6 reference clock driver enable
7	RW	RW	RW	TP_MEM7_REFCLK_DRVR_EN_DC: MEM7 reference clock driver enable
8	RW	RW	RW	TP_MEM8_REFCLK_DRVR_EN_DC: MEM8 reference clock driver enable
9	RW	RW	RW	TP_MEM9_REFCLK_DRVR_EN_DC: MEM9 reference clock driver enable
10	RW	RW	RW	TP_MEMA_REFCLK_DRVR_EN_DC: MEMa reference clock driver enable
11	RW	RW	RW	TP_MEMB_REFCLK_DRVR_EN_DC: MEMb reference clock driver enable
12	RW	RW	RW	TP_MEMC_REFCLK_DRVR_EN_DC: MEMc reference clock driver enable
13	RW	RW	RW	TP_MEMD_REFCLK_DRVR_EN_DC: MEMd reference clock driver enable
14	RW	RW	RW	TP_MEME_REFCLK_DRVR_EN_DC: MEMe reference clock driver enable
15	RW	RW	RW	TP_MEMF_REFCLK_DRVR_EN_DC: MEMf reference clock driver enable
16	RW	RW	RW	TP_OP0A_REFCLK_DRVR_EN_DC: OP0a reference clock driver enable
17	RW	RW	RW	TP_OP0B_REFCLK_DRVR_EN_DC: OP0b reference clock driver enable
18	RW	RW	RW	TP_OP3A_REFCLK_DRVR_EN_DC: OP3a reference clock driver enable
19	RW	RW	RW	TP_OP3B_REFCLK_DRVR_EN_DC: OP3b reference clock driver enable
20	RW	RW	RW	TP_OP4_REFCLK_DRVR_EN_DC: OP4 reference clock driver enable
21	RW	RW	RW	TP_OP5_REFCLK_DRVR_EN_DC: OP5 reference clock driver enable
22	RW	RW	RW	TP_OP6_REFCLK_DRVR_EN_DC: OP6 reference clock driver enable
23	RW	RW	RW	TP_OP7_REFCLK_DRVR_EN_DC: OP7 reference clock driver enable
24	RW	RW	RW	TP_OP_DRVR_2X_CUR_EN_DC: Optical Clock Driver 2x Current Enable
25	RW	RW	RW	TP_E0A_DRVR_2X_CUR_EN_DC: PCIE0 A Slot Clock Driver 2x Current Enable
26	RW	RW	RW	TP_E0B_DRVR_2X_CUR_EN_DC: PCIE0 B Slot Clock Driver 2x Current Enable
27	RW	RW	RW	TP_E0C_DRVR_2X_CUR_EN_DC: PCIE0 C Slot Clock Driver 2x Current Enable
28	RW	RW	RW	TP_E1A_DRVR_2X_CUR_EN_DC: PCIE1 A Slot Clock Driver 2x Current Enable
29	RW	RW	RW	TP_E1B_DRVR_2X_CUR_EN_DC: PCIE1 B/C Slot Clock Driver 2x Current Enable
30	RW	RW	RW	TP_E1C_DRVR_2X_CUR_EN_DC: Global clock driver near-end termination enable
31	RW	RW	RW	ROOT_CTRL7_31_SPARE_RESONANT_CLOCKING_CONTROL: Not used

ROOT CONTROL 8 register
Addr:	0000000000002818 (FSI) 0000000000002860 (FSI_BYTE) 0000000000050018 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL8
Constant(s):	PERV_ROOT_CTRL8
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL8_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	RW	RW	RW	TPFSI_SPIMST0_PORT_MUX_SEL_DC: Select SPIM_0 for BOOT0 SEEPROM: 0b0 = select PIB SPIM_0 (default) 0b1 = select FSI SPIM_0
1	RW	RW	RW	TPFSI_SPIMST1_PORT_MUX_SEL_DC: Select SPIM_1 for BOOT1 SEEPROM: 0b0 = select PIB SPIM_1 (default) 0b1 = select FSI SPIM_1
2	RW	RW	RW	TPFSI_SPIMST2_PORT_MUX_SEL_DC: Select SPIM_2 for MVPD/KEYSTORE SEEPROM: 0b0 = select PIB SPIM_2 (default) 0b1 = select FSI SPIM_2
3	RW	RW	RW	TPFSI_SPIMST3_PORT_MUX_SEL_DC: Select SPIM_3 for MEASUREMENT ROM: 0b0 = select PIB SPIM_3 (default) 0b1 = select FSI SPIM_3
4:15	RW	RW	RW	ROOT_CTRL8_4_15: Not used
16	RW	RW	RW	TP_FSI_FENCE_DC: FSI chiplet fence
17	RW	RW	RW	TCFSI_VITL_FENCE_DC: FSI clock region fence for VITL
18	RW	RW	RW	TCFSI_FSI0_FENCE_DC: FSI clock region fence for FSI0
19	RW	RW	RW	TCFSI_FSI0LL_FENCE_DC: FSI clock region fence for FSI0LL
20	RW	RW	RW	TCFSI_FSI0INV_FENCE_DC: FSI clock region fence for FSI0INV
21	RW	RW	RW	TCFSI_FSI1_FENCE_DC: FSI clock region fence for FSI1
22	RW	RW	RW	TCFSI_FSI1LL_FENCE_DC: FSI clock region fence for FSI1LL
23	RW	RW	RW	TCFSI_FSIA_FENCE_DC: FSI clock region fence for FSIA
24:31	RW	RW	RW	ROOT_CTRL8_24_31: Not used

PERVASIVE CONTROL 0 register
Addr:	000000000000281A (FSI) 0000000000002868 (FSI_BYTE) 000000000005001A (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL0
Constant(s):	PERV_PERV_CTRL0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.PERV_CTRL0_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	RW	RW	RW	TP_TCPERV_CHIPLET_EN_DC: Chiplet enable.
1	RW	RW	RW	TP_TCPERV_PCB_EP_RESET_DC: PCB endpoint reset
2	RW	RW	RW	TP_AN_CLKGLM_TEST_TCK_ASYNC_RESET: Hold TP_CONST and NEST meshes in reset if 1, enable TP_CONST mesh if 0. See ROOT_CTRL4(25) for NEST meshes.
3:6	RW	RW	RW	PERV_CTRL0_3_6_RESERVED: Not used.
7	RW	RW	RW	TP_TCPERV_VITL_SCIN_DC: Scan in for the chiplet VITAL domain
8	RW	RW	RW	PERV_CTRL0_8_RESERVED: Not used.
9	RW	RW	RW	TP_TCPERV_FLUSH_ALIGN_OVERWRITE: Override flush, align in chiplet to 1
10:12	RW	RW	RW	PERV_CTRL0_10_12_RESERVED: Not used.
13	RW	RW	RW	TP_TCPERV_SBE_CG_DIS: Disable clock gating on SBE
14	RW	RW	RW	TP_TCPERV_VITL_CG_DIS: Disable clock gating on VITAL
15	RW	RW	RW	TP_TCPERV_VITL_FFDLYLCK_DC: Enable FF delay on VITAL
16	RW	RW	RW	TP_VITL_CLKOFF_DC: Disable VITAL clocks if 1
17	RW	RW	RW	PERV_CTRL0_17_RESERVED: Not used.
18	RW	RW	RW	TP_FENCE_EN_DC: Fencing signal for PERV chiplet
19:21	RW	RW	RW	PERV_CTRL0_19_21_RESERVED: Not used.
22	RW	RW	RW	TP_OTP_SCOM_FUSED_CORE_MODE: Enable or disable fused core mode. Only functional if OTP fuses allow it.
23	RW	RW	RW	PERV_CTRL0_23_RESERVED: Not used
24	RW	RW	RW	TCPERV_UNIT_FUNC_CLK_GATE_LCB_TEST_EDIS_DC:
25	RW	RW	RW	TP_FENCE_PCB_DC: PERV chiplet PCB fence: Fences PCB signals coming back from chiplet
26:27	RW	RW	RW	PERV_CTRL0_26_27_RESERVED: Not used.
28	RW	RW	RW	TP_SPI_MVPD0_PROTECT: Disables write access to MVPD SEEPROM
29	RW	RW	RW	PERV_CTRL0_29_RESERVED: Not used.
30	RW	RW	RW	TP_EX_SINGLE_LPAR_EN_DC: Enable single LPAR on EX chiplet
31	RW	RW	RW	PERV_CTRL0_31_SPARE: Not used

PERVASIVE CONTROL 1 register
Addr:	000000000000281B (FSI) 000000000000286C (FSI_BYTE) 000000000005001B (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL1
Constant(s):	PERV_PERV_CTRL1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.PERV_CTRL1_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	RW	RW	RW	PERV_CTRL1_0_RESERVED: Not used
1	RW	RW	RW	TP_CHIPLET_CLK_DCC_BYPASS_EN_DC: Enable DCC bypass
2	RW	RW	RW	TP_CHIPLET_CLK_PDLY_BYPASS_EN_DC: Enable Pdly bypass
3:15	RW	RW	RW	PERV_CTRL1_3_15_RESERVED: Not used
16:19	RW	RW	RW	TP_SEC_BUF_DRV_STRENGTH_DC: Sector buffer strength: 0b0000 = xx% strength 0b1111 = yy% strength
20:31	RW	RW	RW	PERV_CTRL1_20_31_RESERVED: Not used

RCS Sense 1 register
Addr:	000000000000281D (FSI) 0000000000002874 (FSI_BYTE) 000000000005001D (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SNS1LTH
Constant(s):	PERV_SNS1LTH
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ASYNCH_SNS1.FSILAT.FSILAT2X.LATC.CSDFFSRPQ1.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	ROX	ROX	ROX	CLK_ERROR_A: Indicates a missing edge was detected on the A path 100MHz clock, can be cleared by CLEAR_CLK_ERROR_A signal
1	ROX	ROX	ROX	CLK_ERROR_B: Indicates a missing edge was detected on the B path 100MHz clock, can be cleared by CLEAR_CLK_ERROR_B signal
2	ROX	ROX	ROX	UNLOCKDET_A: Indicates the other side is not locked and ready to switch to if there is an error detected
3	ROX	ROX	ROX	UNLOCKDET_B: Indicates the other side is not locked and ready to switch to if there is an error detected
4	ROX	ROX	ROX	REFCLK_DATA_OUT_A: Path A data output from 100MHz reference clock toggle detector. Sampled from FSI clock domain
5	ROX	ROX	ROX	REFCLK_DATA_OUT_B: Path B data output from 100MHz reference clock toggle detector. Sampled from FSI clock domain
6	ROX	ROX	ROX	CHECK_ERROR_0_A: Output of latch checking for stuck 0 on A side
7	ROX	ROX	ROX	CHECK_ERROR_1_A: Output of latch checking for stuck 1 on A side
8	ROX	ROX	ROX	CHECK_ERROR_0_B: Output of latch checking for stuck 0 on B side
9	ROX	ROX	ROX	CHECK_ERROR_1_B: Output of latch checking for stuck 1 on B side
10	ROX	ROX	ROX	MUXSEL_BYP_A: muxsel_byp signal on A side
11	ROX	ROX	ROX	MUXSEL_BYP_B: muxsel_byp signal on B side
12	ROX	ROX	ROX	MUXSEL_CLK_A: muxsel_clk signal on A side. This controls final output mux
13	ROX	ROX	ROX	MUXSEL_CLK_B: muxsel_clk signal on B side. This controls final output mux
14	ROX	ROX	ROX	UNLOCK_UNSTICKY_A: Not sticky version of UNLOCKDET_A
15	ROX	ROX	ROX	UNLOCK_UNSTICKY_B: Not sticky version of UNLOCKDET_B
16	ROX	ROX	ROX	SWITCHED: Indicates when RCS has switched from one side to the other
17	ROX	ROX	ROX	RESET_INT_A: Internal Reset signal on A side
18	ROX	ROX	ROX	RESET_INT_B: Internal Reset signal on B side
19	ROX	ROX	ROX	RESET_OR_INT_A: Internal Reset OR'd with Clear Error on A side
20	ROX	ROX	ROX	RESET_OR_INT_B: Internal Reset OR'd with Clear Error on B side
21	ROX	ROX	ROX	FORCE_CLK_INT_A: Internal Force signal on A side
22	ROX	ROX	ROX	FORCE_CLK_INT_B: Internal Force signal on B side
23	ROX	ROX	ROX	BYPASS_INT_A: Internal Bypass signal on A side
24	ROX	ROX	ROX	BYPASS_INT_B: Internal Bypass signal on B side
25	ROX	ROX	ROX	SWITCHOVER_INT_A: Internal Switchover on A side
26	ROX	ROX	ROX	SWITCHOVER_INT_B: Internal Switchover on B side
27	ROX	ROX	ROX	CLEAR_CLK_ERROR_INT_A: Internal Clear Error on A side
28	ROX	ROX	ROX	CLEAR_CLK_ERROR_INT_B: Internal Clear Error on B side
29	ROX	ROX	ROX	SET_BYPASS_A: Output of error detector set_bypass signal on A side
30	ROX	ROX	ROX	SET_BYPASS_B: Output of error detector set_bypass signal on B side
31	ROX	ROX	ROX	tpfsi_rcs_sense_dc_0_31

RCS Sense 2 register
Addr:	000000000000281E (FSI) 0000000000002878 (FSI_BYTE) 000000000005001E (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SNS2LTH
Constant(s):	PERV_SNS2LTH
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ASYNCH_SNS2.FSILAT.FSILAT2X.LATC.CSDFFSRPQ1.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:5	ROX	ROX	ROX	UP_DWN_OUT_A: Output of up/dwn counter on A side
6:11	ROX	ROX	ROX	UP_DWN_OUT_B: Output of up/dwn counter on B side
12	ROX	ROX	ROX	UP_DWN_MUX_CNTL_A: mux_control signal inside up/dwn counter on A side
13	ROX	ROX	ROX	UP_DWN_MUX_CNTL_B: mux_control signal inside up/dwn counter on B side
14:31	ROX	ROX	ROX	tpfsi_rcs_sense_dc_32_63

GP write protection register
Addr:	000000000000281F (FSI) 000000000000287C (FSI_BYTE) 000000000005001F (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPWRP
Constant(s):	PERV_GPWRP
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.WRITE_PROT_COOKIE_LATCH.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:15	RWX	RWX	RWX	MAGIC_COOKIE: It needs to be programmed to 0x4453 for enabling write protection
16:31	RWX	RWX	RWX	EN_OR_DIS_WRITE_PROTECTION: If equal to 0xFFFF disabled write protection If it is unequal to 0xFFFF then this part along with magic cookie forms the if equal to 0x0000 : register number of ROOT CONTROL 0 if equal to 0x0001 : register number of ROOT CONTROL 1 if equal to 0x0002 : register number of ROOT CONTROL 2 if equal to 0x0003 : register number of ROOT CONTROL 3 if equal to 0x0004 : register number of ROOT CONTROL 4 if equal to 0x0005 : register number of ROOT CONTROL 5 if equal to 0x0006 : register number of ROOT CONTROL 6 if equal to 0x0007 : register number of ROOT CONTROL 7 if equal to 0x0008 : register number of ROOT CONTROL 8 if equal to 0x000A : register number of PERV CONTROL 0 if equal to 0x000B : register number of PERV CONTROL 1

hold the header/command information for the doorbell
Addr:	0000000000002821 (FSI) 0000000000002884 (FSI_BYTE) 0000000000050021 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_HEADER_COMMAND_0_A
Constant(s):	PERV_MAILBOX_1_HEADER_COMMAND_0_A
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.Q_GMB284.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	M1HC0A_MAILBOX_1_HEADER_COMMAND_0_A: Mailbox 1 Header/Command 0 A Information

hold the header/command information for the doorbell
Addr:	0000000000002822 (FSI) 0000000000002888 (FSI_BYTE) 0000000000050022 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_HEADER_COMMAND_1_A
Constant(s):	PERV_MAILBOX_1_HEADER_COMMAND_1_A
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.Q_GMB288.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	M1HC1A_MAILBOX_1_HEADER_COMMAND_1_A: Mailbox 1 Header/Command 1 A Information

hold the header/command information for the doorbell
Addr:	0000000000002823 (FSI) 000000000000288C (FSI_BYTE) 0000000000050023 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_HEADER_COMMAND_2_A
Constant(s):	PERV_MAILBOX_1_HEADER_COMMAND_2_A
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.Q_GMB28C.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	M1HC2A_MAILBOX_1_HEADER_COMMAND_2_A: Mailbox 1 Header/Command 2 A Information

used to control the doorbell 1 and indicate status
Addr:	0000000000002824 (FSI) 0000000000002890 (FSI_BYTE) 0000000000050020 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.DOORBELL_STATUS_CONTROL_1A
Constant(s):	PERV_DOORBELL_STATUS_CONTROL_1A
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.Q_GMB280_A.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	RWX	RWX	RWX	DSC1_PERMISSION_TO_SEND_DOORBELL_1: Permission to Send Doorbell 1
1	RWX	RWX	RWX	DSC1_ABORT_DOORBELL_1: Abort Doorbell 1
2	RWX	RWX	RWX	DSC1_LBUS_SLAVE_1B_PENDING: FSI/lbus slave-B Pending Doorbell 1
3	RWX_WCLEAR	RWX_WCLEAR	RWX_WCLEAR	DSC1_PIB_SLAVE_1A_PENDING: Host/pib slave-A Pending Doorbell 1
4	ROX	ROX	ROX	DSC1_UNUSED_1A_27: Reserved
5	RWX	RWX	RWX	DSC1_XDN_DOORBELL_1: Xdn Doorbell 1
6	RWX_WCLEAR	RWX_WCLEAR	RWX_WCLEAR	DSC1_XUP_DOORBELL_1: Xup Doorbell 1
7	ROX	ROX	ROX	DSC1_UNUSED_1A_24: Reserved
8:11	RWX	RWX	RWX	DSC1_HEADER_COUNT_1A: Header count (Host/pib slave-A)
12:19	RWX	RWX	RWX	DSC1_DATA_COUNT_1A: Data count (Host/pib slave-A)
20:23	RWX_WCLEAR	RWX_WCLEAR	RWX_WCLEAR	DSC1_HEADER_COUNT_1B: Header count (FSI/lbus slave-B)
24:31	RWX_WCLEAR	RWX_WCLEAR	RWX_WCLEAR	DSC1_DATA_COUNT_1B: Data count (FSI/lbus slave-B)

hold the header/command information for the doorbell
Addr:	0000000000002825 (FSI) 0000000000002894 (FSI_BYTE) 0000000000050025 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_HEADER_COMMAND_0_B
Constant(s):	PERV_MAILBOX_1_HEADER_COMMAND_0_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.Q_GMB294.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	M1HC0B_MAILBOX_1_HEADER_COMMAND_0_B: Mailbox 1 Header/Command 0 B Information

hold the header/command information for the doorbell
Addr:	0000000000002826 (FSI) 0000000000002898 (FSI_BYTE) 0000000000050026 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_HEADER_COMMAND_1_B
Constant(s):	PERV_MAILBOX_1_HEADER_COMMAND_1_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.Q_GMB298.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	M1HC1B_MAILBOX_1_HEADER_COMMAND_1_B: Mailbox 1 Header/Command 1 B Information

hold the header/command information for the doorbell
Addr:	0000000000002827 (FSI) 000000000000289C (FSI_BYTE) 0000000000050027 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_HEADER_COMMAND_2_B
Constant(s):	PERV_MAILBOX_1_HEADER_COMMAND_2_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.Q_GMB29C.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	M1HC2B_MAILBOX_1_HEADER_COMMAND_2_B: Mailbox 1 Header/Command 2 B Information

hold the header/command information for the doorbell
Addr:	0000000000002829 (FSI) 00000000000028A4 (FSI_BYTE) 0000000000050029 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_2_HEADER_COMMAND_0_A
Constant(s):	PERV_MAILBOX_2_HEADER_COMMAND_0_A
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.Q_GMB2A4.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	M2HC0A_MAILBOX_2_HEADER_COMMAND_0_A: Mailbox 2 Header/Command 0 A Information

hold the header/command information for the doorbell
Addr:	000000000000282A (FSI) 00000000000028A8 (FSI_BYTE) 000000000005002A (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_2_HEADER_COMMAND_1_A
Constant(s):	PERV_MAILBOX_2_HEADER_COMMAND_1_A
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.Q_GMB2A8.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	M2HC1A_MAILBOX_2_HEADER_COMMAND_1_A: Mailbox 2 Header/Command 1 A Information

hold the header/command information for the doorbell
Addr:	000000000000282B (FSI) 00000000000028AC (FSI_BYTE) 000000000005002B (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_2_HEADER_COMMAND_2_A
Constant(s):	PERV_MAILBOX_2_HEADER_COMMAND_2_A
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.Q_GMB2AC.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	M2HC2A_MAILBOX_2_HEADER_COMMAND_2_A: Mailbox 2 Header/Command 2 A Information

used to control the doorbell 2 and indicate status
Addr:	000000000000282C (FSI) 00000000000028B0 (FSI_BYTE) 0000000000050028 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.DOORBELL_STATUS_CONTROL_2A
Constant(s):	PERV_DOORBELL_STATUS_CONTROL_2A
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.Q_GMB2A0_A.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	RWX	RWX	RWX	DSC2_PERMISSION_TO_SEND_DOORBELL_2: Permission to Send Doorbell 1
1	RWX	RWX	RWX	DSC2_ABORT_DOORBELL_2: Abort Doorbell 1
2	RWX	RWX	RWX	DSC2_LBUS_SLAVE_2B_PENDING: FSI/lbus slave-B Pending Doorbell 1
3	RWX_WCLEAR	RWX_WCLEAR	RWX_WCLEAR	DSC2_PIB_SLAVE_2A_PENDING: Host/pib slave-A Pending Doorbell 1
4	ROX	ROX	ROX	DSC2_UNUSED_2A_27: Reserved
5	RWX	RWX	RWX	DSC2_XDN_DOORBELL_2: Xdn Doorbell 1
6	RWX_WCLEAR	RWX_WCLEAR	RWX_WCLEAR	DSC2_XUP_DOORBELL_2: Xup Doorbell 1
7	ROX	ROX	ROX	DSC2_UNUSED_2A_24: Reserved
8:11	RWX	RWX	RWX	DSC2_HEADER_COUNT_2A: Header count (Host/pib slave-A)
12:19	RWX	RWX	RWX	DSC2_DATA_COUNT_2A: Data count (Host/pib slave-A)
20:23	RWX_WCLEAR	RWX_WCLEAR	RWX_WCLEAR	DSC2_HEADER_COUNT_2B: Header count (FSI/lbus slave-B)
24:31	RWX_WCLEAR	RWX_WCLEAR	RWX_WCLEAR	DSC2_DATA_COUNT_2B: Data count (FSI/lbus slave-B)

hold the header/command information for the doorbell
Addr:	000000000000282D (FSI) 00000000000028B4 (FSI_BYTE) 000000000005002D (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_2_HEADER_COMMAND_0_B
Constant(s):	PERV_MAILBOX_2_HEADER_COMMAND_0_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.Q_GMB2B4.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	M2HC0B_MAILBOX_2_HEADER_COMMAND_0_B: Mailbox 2 Header/Command 0 B Information

hold the header/command information for the doorbell
Addr:	000000000000282E (FSI) 00000000000028B8 (FSI_BYTE) 000000000005002E (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_2_HEADER_COMMAND_1_B
Constant(s):	PERV_MAILBOX_2_HEADER_COMMAND_1_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.Q_GMB2B8.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	M2HC1B_MAILBOX_2_HEADER_COMMAND_1_B: Mailbox 2 Header/Command 1 B Information

hold the header/command information for the doorbell
Addr:	000000000000282F (FSI) 00000000000028BC (FSI_BYTE) 000000000005002F (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_2_HEADER_COMMAND_2_B
Constant(s):	PERV_MAILBOX_2_HEADER_COMMAND_2_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.Q_GMB2BC.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	M2HC2B_MAILBOX_2_HEADER_COMMAND_2_B: Mailbox 2 Header/Command 2 B Information

contains the status of a failed doorbell operation
Addr:	0000000000002830 (FSI) 00000000000028C0 (FSI_BYTE) 0000000000050030 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS
Constant(s):	PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.Q_GMB2C0_A.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:3	ROX	ROX	ROX	MSBDES_UNUSED_B_31_28: Reserved
4	ROX	ROX	ROX	MSBDES_ILLEGAL_OPERATION_ATTEMPTED_1: Illegal Operation Attempted 1
5	ROX	ROX	ROX	MSBDES_WRITE_FULL_PIB_SLAVE_A_MAILBOX_ERROR_1: Write Full Host/pib slave-A Mailbox Error 1
6	ROX	ROX	ROX	MSBDES_READ_EMPTY_PIB_SLAVE_A_MAILBOX_ERROR_1: Read Empty Host/pib slave-A Mailbox Error 1
7	ROX	ROX	ROX	MSBDES_PIB_SLAVE_A_RAM_PARITY_ERROR_DETECTED_1: Host/pib slave-A RAM Parity Error Detected 1
8:14	ROX	ROX	ROX	MSBDES_ADDRESS_OF_PIB_PARITY_ERROR_1: Address of Host/pib slave-A RAM which caused Parity Error 1
15	ROX	ROX	ROX	MSBDES_CLEAR_STATUS_1: Clear Status error bit 27 downto 17, resets complete Gemini mailbox and arbiter state machine
16:19	ROX	ROX	ROX	MSBDES_UNUSED_B_15_12: Reserved
20	ROX	ROX	ROX	MSBDES_ILLEGAL_OPERATION_ATTEMPTED_2: Illegal Operation Attempted 2
21	ROX	ROX	ROX	MSBDES_WRITE_FULL_PIB_SLAVE_A_MAILBOX_ERROR_2: Write Full Host/pib slave-A Mailbox Error 2
22	ROX	ROX	ROX	MSBDES_READ_EMPTY_PIB_SLAVE_A_MAILBOX_ERROR_2: Read Empty Host/pib slave-A Mailbox Error 2
23	ROX	ROX	ROX	MSBDES_PIB_SLAVE_A_RAM_PARITY_ERROR_DETECTED_2: Host/pib slave-A RAM Parity Error Detected 2
24:30	ROX	ROX	ROX	MSBDES_ADDRESS_OF_PIB_PARITY_ERROR_2: Address of Host/pib slave-A RAM which caused Parity Error 2
31	ROX	ROX	ROX	MSBDES_CLEAR_STATUS_2: Clear Status errors bit 11 downto 1, resets complete Gemini mailbox and arbiter state machine

contains the status of a failed doorbell operation
Addr:	0000000000002831 (FSI) 00000000000028C4 (FSI_BYTE) 0000000000050031 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS
Constant(s):	PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.Q_GMB2C4_A.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:3	ROX	ROX	ROX	MSADES_UNUSED_A_31_28: Reserved
4	ROX	ROX	ROX	MSADES_ILLEGAL_OPERATION_ATTEMPTED_1: Illegal Operation Attempted 1
5	ROX	ROX	ROX	MSADES_WRITE_FULL_PIB_SLAVE_A_MAILBOX_ERROR_1: Write Full Host/pib slave-A Mailbox Error 1
6	ROX	ROX	ROX	MSADES_READ_EMPTY_PIB_SLAVE_A_MAILBOX_ERROR_1: Read Empty Host/pib slave-A Mailbox Error 1
7	ROX	ROX	ROX	MSADES_LBUS_SLAVE_B_RAM_PARITY_ERROR_DETECTED_1: Host/pib slave-A RAM Parity Error Detected 1
8:14	ROX	ROX	ROX	MSADES_ADDRESS_OF_LBUS_PARITY_ERROR_1: Address of FSI/lbus slave-B RAM which caused Parity Error 1
15	ROX	ROX	ROX	MSADES_CLEAR_STATUS_1: Clear Status errors bit 27 downto 17, resets complete Gemini mailbox and arbiter state machine
16:19	ROX	ROX	ROX	MSADES_UNUSED_A_15_12: Reserved
20	ROX	ROX	ROX	MSADES_ILLEGAL_OPERATION_ATTEMPTED_2: Illegal Operation Attempted 2
21	ROX	ROX	ROX	MSADES_WRITE_FULL_PIB_SLAVE_A_MAILBOX_ERROR_2: Write Full Host/pib slave-A Mailbox Error 2
22	ROX	ROX	ROX	MSADES_READ_EMPTY_PIB_SLAVE_A_MAILBOX_ERROR_2: Read Empty Host/pib slave-A Mailbox Error 2
23	ROX	ROX	ROX	MSADES_LBUS_SLAVE_B_RAM_PARITY_ERROR_DETECTED_2: Host/pib slave-A RAM Parity Error Detected 2
24:30	ROX	ROX	ROX	MSADES_ADDRESS_OF_LBUS_PARITY_ERROR_2: Address of FSI/lbus slave-B RAM which caused Parity Error 2
31	ROX	ROX	ROX	MSADES_CLEAR_STATUS_2: Clear Status errors bit 11 downto 1, resets complete Gemini mailbox and arbiter state machine

register is used to interrupt Host/pib slave-A
Addr:	0000000000002832 (FSI) 00000000000028C8 (FSI_BYTE) 0000000000050032 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_SLAVE_A_DOORBELL_INTERRUPT
Constant(s):	PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.Q_GMB2C8_A.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:2	ROX	ROX	RWX_WCLEAR	MSADI_UNUSED_31_11:
3:7	ROX	ROX	ROX	MSADI_UNUSED_31_11:
8:10	ROX	ROX	RWX_WCLEAR	MSADI_UNUSED_31_11:
11:20	ROX	ROX	ROX	MSADI_UNUSED_31_11:
21	ROX	ROX	ROX	MSADI_PIB_SLAVE_A_DOORBELL_ERROR_MAILBOX_2: Host/pib slave-A Doorbell Error Mailbox 2
22	ROX	ROX	ROX	MSADI_XUP_MAILBOX_2: Xup Mailbox 2
23	ROX	ROX	ROX	MSADI_PIB_SLAVE_A_PENDING_MAILBOX_2: Host/pib slave-A Pending Mailbox 2
24:28	ROX	ROX	ROX	MSADI_UNUSED_7_3:
29	ROX	ROX	ROX	MSADI_PIB_SLAVE_A_DOORBELL_ERROR_MAILBOX_1: Host/pib slave-A Doorbell Error Mailbox 1
30	ROX	ROX	ROX	MSADI_XUP_MAILBOX_1: Xup Mailbox 1
31	ROX	ROX	ROX	MSADI_PIB_SLAVE_A_PENDING_MAILBOX_1: Host/pib slave-A Pending Mailbox 1

contains the mask bits for the Host/pib slave-A doorbell interrupts
Addr:	0000000000002833 (FSI) 00000000000028CC (FSI_BYTE) 0000000000050033 (SCOM) 0000000000050034 (SCOM1)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1
Constant(s):	PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	29:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.Q_GMB2CC_B.FSILAT.LATCH.LATC.L2(0:2) [000]
Bit(s)	FSI	FSI_BYTE	SCOM	SCOM1	Dial: Description
0:28	RO	RO	RO	RO	constant=0b00000000000000000000000000000
29	ROX	ROX	RWX_WOR	WOX_CLEAR	M1SASIM1_ENABLE_PIB_SLAVE_A_DOORBELL_ERROR_MAILBOX_1: Enable Host/pib slave-A Doorbell Error Mailbox 1
30	ROX	ROX	RWX_WOR	WOX_CLEAR	M1SASIM1_ENABLE_XUP_MAILBOX_1: Enable Xup Mailbox 1
31	ROX	ROX	RWX_WOR	WOX_CLEAR	M1SASIM1_ENABLE_PIB_SLAVE_A_PENDING_MAILBOX_1: Enable Host/pib slave-A Pending Mailbox 1

register is used to interrupt FSI/lbus slave-b
Addr:	0000000000002835 (FSI) 00000000000028D4 (FSI_BYTE) 0000000000050035 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_SLAVE_B_DOORBELL_INTERRUPT
Constant(s):	PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.Q_GMB2D4.FSILAT.LATCH.LATC.L2(0:7) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:23	RO	RO	RO	constant=0b000000000000000000000000
24	ROX	ROX	ROX	msbdi_abort_mailbox_2
25	ROX	ROX	ROX	msbdi_abort_mailbox_1
26	ROX	ROX	ROX	MSBDI_LBUS_SLAVE_B_DOORBELL_ERROR_MAILBOX_2: FSI/lbus slave-B Doorbell Error Mailbox 2
27	ROX	ROX	ROX	MSBDI_LBUS_SLAVE_B_DOORBELL_ERROR_MAILBOX_1: FSI/lbus slave-B Doorbell Error Mailbox 1
28	ROX	ROX	ROX	MSBDI_XDN_MAILBOX_2: Xdn Mailbox 2
29	ROX	ROX	ROX	MSBDI_XDN_MAILBOX_1: Xdn Mailbox 1
30	ROX	ROX	ROX	MSBDI_LBUS_SLAVE_B_PENDING_MAILBOX_2: FSI/lbus slave-B Pending Mailbox 2
31	ROX	ROX	ROX	MSBDI_LBUS_SLAVE_B_PENDING_MAILBOX_1: FSI/lbus slave-B Pending Mailbox 1

contains the mask bits for the FSI/lbus slave-B doorbell interrupts
Addr:	0000000000002836 (FSI) 0000000000002837 (FSI0) 00000000000028D8 (FSI_BYTE) 0000000000050036 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1
Constant(s):	PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.Q_GMB2D8.FSILAT.LATCH.LATC.L2(0:7) [00000000]
Bit(s)	FSI	FSI0	FSI_BYTE	SCOM	Dial: Description
0:23	RO	RO	RO	RO	constant=0b000000000000000000000000
24	RWX_WOR	WOX_CLEAR	RWX_WOR	ROX	MSBDIM1_ENABLE_ABORT_MAILBOX_2: Enable Abort Mailbox 2
25	RWX_WOR	WOX_CLEAR	RWX_WOR	ROX	MSBDIM1_ENABLE_ABORT_MAILBOX_1: Enable Abort Mailbox 1
26	RWX_WOR	WOX_CLEAR	RWX_WOR	ROX	MSBDIM1_ENABLE_LBUS_SLAVE_B_DOORBELL_ERROR_MAILBOX_2: Enable FSI/lbus slave-B Doorbell Error Mailbox 2
27	RWX_WOR	WOX_CLEAR	RWX_WOR	ROX	MSBDIM1_ENABLE_LBUS_SLAVE_B_DOORBELL_ERROR_MAILBOX_1: Enable FSI/lbus slave-B Doorbell Error Mailbox 1
28	RWX_WOR	WOX_CLEAR	RWX_WOR	ROX	MSBDIM1_ENABLE_XDN_MAILBOX_2: Enable Xdn Mailbox 2
29	RWX_WOR	WOX_CLEAR	RWX_WOR	ROX	MSBDIM1_ENABLE_XDN_MAILBOX_1: Enable Xdn Mailbox 1
30	RWX_WOR	WOX_CLEAR	RWX_WOR	ROX	MSBDIM1_ENABLE_LBUS_SLAVE_B_PENDING_MAILBOX_2: FSI/lbus slave-B Pending Mailbox 2
31	RWX_WOR	WOX_CLEAR	RWX_WOR	ROX	MSBDIM1_ENABLE_LBUS_SLAVE_B_PENDING_MAILBOX_1: FSI/lbus slave-B Pending Mailbox 1

scratch register number 1
Addr:	0000000000002838 (FSI) 00000000000028E0 (FSI_BYTE) 0000000000050038 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_1
Constant(s):	PERV_SCRATCH_REGISTER_1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.Q_GMB2E0.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	RWX	SR_SCRATCH_REGISTER_1: Scratch 1 register

scratch register number 2
Addr:	0000000000002839 (FSI) 00000000000028E4 (FSI_BYTE) 0000000000050039 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_2
Constant(s):	PERV_SCRATCH_REGISTER_2
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.Q_GMB2E4.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	RWX	SR_SCRATCH_REGISTER_2: Scratch 2 register

scratch register number 3
Addr:	000000000000283A (FSI) 00000000000028E8 (FSI_BYTE) 000000000005003A (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_3
Constant(s):	PERV_SCRATCH_REGISTER_3
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.Q_GMB2E8.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	RWX	SR_SCRATCH_REGISTER_3: Scratch 3 register

scratch register number 4
Addr:	000000000000283B (FSI) 00000000000028EC (FSI_BYTE) 000000000005003B (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_4
Constant(s):	PERV_SCRATCH_REGISTER_4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.Q_GMB2EC.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	RWX	SR_SCRATCH_REGISTER_4: Scratch 4 register

scratch register number 5
Addr:	000000000000283C (FSI) 00000000000028F0 (FSI_BYTE) 000000000005003C (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_5
Constant(s):	PERV_SCRATCH_REGISTER_5
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.Q_GMB2F0.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	RWX	SR_SCRATCH_REGISTER_5: Scratch 5 register

scratch register number 6
Addr:	000000000000283D (FSI) 00000000000028F4 (FSI_BYTE) 000000000005003D (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_6
Constant(s):	PERV_SCRATCH_REGISTER_6
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.Q_GMB2F4.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	RWX	SR_SCRATCH_REGISTER_6: Scratch 6 register

scratch register number 7
Addr:	000000000000283E (FSI) 00000000000028F8 (FSI_BYTE) 000000000005003E (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_7
Constant(s):	PERV_SCRATCH_REGISTER_7
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.Q_GMB2F8.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	RWX	SR_SCRATCH_REGISTER_7: Scratch 7 register

scratch register number 8
Addr:	000000000000283F (FSI) 00000000000028FC (FSI_BYTE) 000000000005003F (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_8
Constant(s):	PERV_SCRATCH_REGISTER_8
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.Q_GMB2FC.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	RWX	SR_SCRATCH_REGISTER_8: Scratch 8 register

Mailbox 1 Data Area (Host) Register 0
Addr:	0000000000002840 (FSI) 0000000000002900 (FSI_BYTE) 0000000000050040 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_0
Constant(s):	PERV_M1A_DATA_AREA_0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_0.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_0.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_0.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_0.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m1a_data_area_0

Mailbox 1 Data Area (Host) Register 1
Addr:	0000000000002841 (FSI) 0000000000002904 (FSI_BYTE) 0000000000050041 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_1
Constant(s):	PERV_M1A_DATA_AREA_1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_1.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_1.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_1.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_1.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m1a_data_area_1

Mailbox 1 Data Area (Host) Register 2
Addr:	0000000000002842 (FSI) 0000000000002908 (FSI_BYTE) 0000000000050042 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_2
Constant(s):	PERV_M1A_DATA_AREA_2
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_2.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_2.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_2.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_2.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m1a_data_area_2

Mailbox 1 Data Area (Host) Register 3
Addr:	0000000000002843 (FSI) 000000000000290C (FSI_BYTE) 0000000000050043 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_3
Constant(s):	PERV_M1A_DATA_AREA_3
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_3.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_3.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_3.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_3.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m1a_data_area_3

Mailbox 1 Data Area (Host) Register 4
Addr:	0000000000002844 (FSI) 0000000000002910 (FSI_BYTE) 0000000000050044 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_4
Constant(s):	PERV_M1A_DATA_AREA_4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_4.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_4.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_4.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_4.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m1a_data_area_4

Mailbox 1 Data Area (Host) Register 5
Addr:	0000000000002845 (FSI) 0000000000002914 (FSI_BYTE) 0000000000050045 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_5
Constant(s):	PERV_M1A_DATA_AREA_5
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_5.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_5.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_5.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_5.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m1a_data_area_5

Mailbox 1 Data Area (Host) Register 6
Addr:	0000000000002846 (FSI) 0000000000002918 (FSI_BYTE) 0000000000050046 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_6
Constant(s):	PERV_M1A_DATA_AREA_6
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_6.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_6.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_6.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_6.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m1a_data_area_6

Mailbox 1 Data Area (Host) Register 7
Addr:	0000000000002847 (FSI) 000000000000291C (FSI_BYTE) 0000000000050047 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_7
Constant(s):	PERV_M1A_DATA_AREA_7
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_7.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_7.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_7.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_7.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m1a_data_area_7

Mailbox 1 Data Area (Host) Register 8
Addr:	0000000000002848 (FSI) 0000000000002920 (FSI_BYTE) 0000000000050048 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_8
Constant(s):	PERV_M1A_DATA_AREA_8
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_8.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_8.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_8.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_8.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m1a_data_area_8

Mailbox 1 Data Area (Host) Register 9
Addr:	0000000000002849 (FSI) 0000000000002924 (FSI_BYTE) 0000000000050049 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_9
Constant(s):	PERV_M1A_DATA_AREA_9
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_9.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_9.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_9.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_9.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m1a_data_area_9

Mailbox 1 Data Area (Host) Register 10
Addr:	000000000000284A (FSI) 0000000000002928 (FSI_BYTE) 000000000005004A (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_10
Constant(s):	PERV_M1A_DATA_AREA_10
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_10.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_10.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_10.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_10.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m1a_data_area_10

Mailbox 1 Data Area (Host) Register 11
Addr:	000000000000284B (FSI) 000000000000292C (FSI_BYTE) 000000000005004B (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_11
Constant(s):	PERV_M1A_DATA_AREA_11
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_11.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_11.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_11.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_11.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m1a_data_area_11

Mailbox 1 Data Area (Host) Register 12
Addr:	000000000000284C (FSI) 0000000000002930 (FSI_BYTE) 000000000005004C (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_12
Constant(s):	PERV_M1A_DATA_AREA_12
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_12.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_12.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_12.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_12.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m1a_data_area_12

Mailbox 1 Data Area (Host) Register 13
Addr:	000000000000284D (FSI) 0000000000002934 (FSI_BYTE) 000000000005004D (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_13
Constant(s):	PERV_M1A_DATA_AREA_13
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_13.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_13.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_13.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_13.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m1a_data_area_13

Mailbox 1 Data Area (Host) Register 14
Addr:	000000000000284E (FSI) 0000000000002938 (FSI_BYTE) 000000000005004E (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_14
Constant(s):	PERV_M1A_DATA_AREA_14
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_14.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_14.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_14.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_14.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m1a_data_area_14

Mailbox 1 Data Area (Host) Register 15
Addr:	000000000000284F (FSI) 000000000000293C (FSI_BYTE) 000000000005004F (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_15
Constant(s):	PERV_M1A_DATA_AREA_15
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_15.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_15.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_15.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U1_15.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m1a_data_area_15

Mailbox 1 Data Area (Fsi) Register 0
Addr:	0000000000002880 (FSI) 0000000000002A00 (FSI_BYTE) 0000000000050080 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_0
Constant(s):	PERV_M1B_DATA_AREA_0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_0.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_0.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_0.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_0.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m1b_data_area_0

Mailbox 1 Data Area (Fsi) Register 1
Addr:	0000000000002881 (FSI) 0000000000002A04 (FSI_BYTE) 0000000000050081 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_1
Constant(s):	PERV_M1B_DATA_AREA_1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_1.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_1.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_1.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_1.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m1b_data_area_1

Mailbox 1 Data Area (Fsi) Register 2
Addr:	0000000000002882 (FSI) 0000000000002A08 (FSI_BYTE) 0000000000050082 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_2
Constant(s):	PERV_M1B_DATA_AREA_2
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_2.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_2.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_2.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_2.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m1b_data_area_2

Mailbox 1 Data Area (Fsi) Register 3
Addr:	0000000000002883 (FSI) 0000000000002A0C (FSI_BYTE) 0000000000050083 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_3
Constant(s):	PERV_M1B_DATA_AREA_3
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_3.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_3.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_3.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_3.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m1b_data_area_3

Mailbox 1 Data Area (Fsi) Register 4
Addr:	0000000000002884 (FSI) 0000000000002A10 (FSI_BYTE) 0000000000050084 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_4
Constant(s):	PERV_M1B_DATA_AREA_4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_4.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_4.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_4.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_4.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m1b_data_area_4

Mailbox 1 Data Area (Fsi) Register 5
Addr:	0000000000002885 (FSI) 0000000000002A14 (FSI_BYTE) 0000000000050085 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_5
Constant(s):	PERV_M1B_DATA_AREA_5
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_5.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_5.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_5.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_5.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m1b_data_area_5

Mailbox 1 Data Area (Fsi) Register 6
Addr:	0000000000002886 (FSI) 0000000000002A18 (FSI_BYTE) 0000000000050086 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_6
Constant(s):	PERV_M1B_DATA_AREA_6
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_6.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_6.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_6.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_6.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m1b_data_area_6

Mailbox 1 Data Area (Fsi) Register 7
Addr:	0000000000002887 (FSI) 0000000000002A1C (FSI_BYTE) 0000000000050087 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_7
Constant(s):	PERV_M1B_DATA_AREA_7
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_7.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_7.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_7.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_7.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m1b_data_area_7

Mailbox 1 Data Area (Fsi) Register 8
Addr:	0000000000002888 (FSI) 0000000000002A20 (FSI_BYTE) 0000000000050088 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_8
Constant(s):	PERV_M1B_DATA_AREA_8
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_8.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_8.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_8.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_8.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m1b_data_area_8

Mailbox 1 Data Area (Fsi) Register 9
Addr:	0000000000002889 (FSI) 0000000000002A24 (FSI_BYTE) 0000000000050089 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_9
Constant(s):	PERV_M1B_DATA_AREA_9
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_9.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_9.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_9.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_9.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m1b_data_area_9

Mailbox 1 Data Area (Fsi) Register 10
Addr:	000000000000288A (FSI) 0000000000002A28 (FSI_BYTE) 000000000005008A (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_10
Constant(s):	PERV_M1B_DATA_AREA_10
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_10.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_10.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_10.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_10.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m1b_data_area_10

Mailbox 1 Data Area (Fsi) Register 11
Addr:	000000000000288B (FSI) 0000000000002A2C (FSI_BYTE) 000000000005008B (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_11
Constant(s):	PERV_M1B_DATA_AREA_11
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_11.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_11.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_11.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_11.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m1b_data_area_11

Mailbox 1 Data Area (Fsi) Register 12
Addr:	000000000000288C (FSI) 0000000000002A30 (FSI_BYTE) 000000000005008C (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_12
Constant(s):	PERV_M1B_DATA_AREA_12
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_12.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_12.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_12.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_12.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m1b_data_area_12

Mailbox 1 Data Area (Fsi) Register 13
Addr:	000000000000288D (FSI) 0000000000002A34 (FSI_BYTE) 000000000005008D (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_13
Constant(s):	PERV_M1B_DATA_AREA_13
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_13.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_13.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_13.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_13.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m1b_data_area_13

Mailbox 1 Data Area (Fsi) Register 14
Addr:	000000000000288E (FSI) 0000000000002A38 (FSI_BYTE) 000000000005008E (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_14
Constant(s):	PERV_M1B_DATA_AREA_14
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_14.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_14.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_14.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_14.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m1b_data_area_14

Mailbox 1 Data Area (Fsi) Register 15
Addr:	000000000000288F (FSI) 0000000000002A3C (FSI_BYTE) 000000000005008F (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_15
Constant(s):	PERV_M1B_DATA_AREA_15
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_15.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_15.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_15.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U2_15.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m1b_data_area_15

Mailbox 2 Data Area (Host) Register 0
Addr:	00000000000028C0 (FSI) 0000000000002B00 (FSI_BYTE) 00000000000500C0 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_0
Constant(s):	PERV_M2A_DATA_AREA_0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_0.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_0.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_0.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_0.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m2a_data_area_0

Mailbox 2 Data Area (Host) Register 1
Addr:	00000000000028C1 (FSI) 0000000000002B04 (FSI_BYTE) 00000000000500C1 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_1
Constant(s):	PERV_M2A_DATA_AREA_1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_1.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_1.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_1.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_1.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m2a_data_area_1

Mailbox 2 Data Area (Host) Register 2
Addr:	00000000000028C2 (FSI) 0000000000002B08 (FSI_BYTE) 00000000000500C2 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_2
Constant(s):	PERV_M2A_DATA_AREA_2
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_2.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_2.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_2.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_2.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m2a_data_area_2

Mailbox 2 Data Area (Host) Register 3
Addr:	00000000000028C3 (FSI) 0000000000002B0C (FSI_BYTE) 00000000000500C3 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_3
Constant(s):	PERV_M2A_DATA_AREA_3
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_3.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_3.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_3.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_3.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m2a_data_area_3

Mailbox 2 Data Area (Host) Register 4
Addr:	00000000000028C4 (FSI) 0000000000002B10 (FSI_BYTE) 00000000000500C4 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_4
Constant(s):	PERV_M2A_DATA_AREA_4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_4.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_4.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_4.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_4.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m2a_data_area_4

Mailbox 2 Data Area (Host) Register 5
Addr:	00000000000028C5 (FSI) 0000000000002B14 (FSI_BYTE) 00000000000500C5 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_5
Constant(s):	PERV_M2A_DATA_AREA_5
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_5.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_5.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_5.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_5.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m2a_data_area_5

Mailbox 2 Data Area (Host) Register 6
Addr:	00000000000028C6 (FSI) 0000000000002B18 (FSI_BYTE) 00000000000500C6 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_6
Constant(s):	PERV_M2A_DATA_AREA_6
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_6.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_6.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_6.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_6.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m2a_data_area_6

Mailbox 2 Data Area (Host) Register 7
Addr:	00000000000028C7 (FSI) 0000000000002B1C (FSI_BYTE) 00000000000500C7 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_7
Constant(s):	PERV_M2A_DATA_AREA_7
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_7.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_7.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_7.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_7.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m2a_data_area_7

Mailbox 2 Data Area (Host) Register 8
Addr:	00000000000028C8 (FSI) 0000000000002B20 (FSI_BYTE) 00000000000500C8 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_8
Constant(s):	PERV_M2A_DATA_AREA_8
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_8.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_8.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_8.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_8.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m2a_data_area_8

Mailbox 2 Data Area (Host) Register 9
Addr:	00000000000028C9 (FSI) 0000000000002B24 (FSI_BYTE) 00000000000500C9 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_9
Constant(s):	PERV_M2A_DATA_AREA_9
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_9.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_9.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_9.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_9.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m2a_data_area_9

Mailbox 2 Data Area (Host) Register 10
Addr:	00000000000028CA (FSI) 0000000000002B28 (FSI_BYTE) 00000000000500CA (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_10
Constant(s):	PERV_M2A_DATA_AREA_10
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_10.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_10.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_10.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_10.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m2a_data_area_10

Mailbox 2 Data Area (Host) Register 11
Addr:	00000000000028CB (FSI) 0000000000002B2C (FSI_BYTE) 00000000000500CB (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_11
Constant(s):	PERV_M2A_DATA_AREA_11
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_11.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_11.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_11.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_11.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m2a_data_area_11

Mailbox 2 Data Area (Host) Register 12
Addr:	00000000000028CC (FSI) 0000000000002B30 (FSI_BYTE) 00000000000500CC (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_12
Constant(s):	PERV_M2A_DATA_AREA_12
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_12.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_12.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_12.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_12.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m2a_data_area_12

Mailbox 2 Data Area (Host) Register 13
Addr:	00000000000028CD (FSI) 0000000000002B34 (FSI_BYTE) 00000000000500CD (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_13
Constant(s):	PERV_M2A_DATA_AREA_13
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_13.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_13.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_13.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_13.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m2a_data_area_13

Mailbox 2 Data Area (Host) Register 14
Addr:	00000000000028CE (FSI) 0000000000002B38 (FSI_BYTE) 00000000000500CE (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_14
Constant(s):	PERV_M2A_DATA_AREA_14
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_14.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_14.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_14.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_14.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m2a_data_area_14

Mailbox 2 Data Area (Host) Register 15
Addr:	00000000000028CF (FSI) 0000000000002B3C (FSI_BYTE) 00000000000500CF (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_15
Constant(s):	PERV_M2A_DATA_AREA_15
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_15.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_15.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_15.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U3_15.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	ROX	ROX	RWX	mda_m2a_data_area_15

Mailbox 2 Data Area (Fsi) Register 0
Addr:	0000000000002900 (FSI) 0000000000002C00 (FSI_BYTE) 0000000000050100 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_0
Constant(s):	PERV_M2B_DATA_AREA_0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_0.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_0.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_0.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_0.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m2b_data_area_0

Mailbox 2 Data Area (Fsi) Register 1
Addr:	0000000000002901 (FSI) 0000000000002C04 (FSI_BYTE) 0000000000050101 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_1
Constant(s):	PERV_M2B_DATA_AREA_1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_1.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_1.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_1.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_1.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m2b_data_area_1

Mailbox 2 Data Area (Fsi) Register 2
Addr:	0000000000002902 (FSI) 0000000000002C08 (FSI_BYTE) 0000000000050102 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_2
Constant(s):	PERV_M2B_DATA_AREA_2
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_2.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_2.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_2.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_2.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m2b_data_area_2

Mailbox 2 Data Area (Fsi) Register 3
Addr:	0000000000002903 (FSI) 0000000000002C0C (FSI_BYTE) 0000000000050103 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_3
Constant(s):	PERV_M2B_DATA_AREA_3
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_3.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_3.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_3.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_3.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m2b_data_area_3

Mailbox 2 Data Area (Fsi) Register 4
Addr:	0000000000002904 (FSI) 0000000000002C10 (FSI_BYTE) 0000000000050104 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_4
Constant(s):	PERV_M2B_DATA_AREA_4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_4.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_4.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_4.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_4.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m2b_data_area_4

Mailbox 2 Data Area (Fsi) Register 5
Addr:	0000000000002905 (FSI) 0000000000002C14 (FSI_BYTE) 0000000000050105 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_5
Constant(s):	PERV_M2B_DATA_AREA_5
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_5.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_5.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_5.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_5.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m2b_data_area_5

Mailbox 2 Data Area (Fsi) Register 6
Addr:	0000000000002906 (FSI) 0000000000002C18 (FSI_BYTE) 0000000000050106 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_6
Constant(s):	PERV_M2B_DATA_AREA_6
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_6.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_6.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_6.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_6.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m2b_data_area_6

Mailbox 2 Data Area (Fsi) Register 7
Addr:	0000000000002907 (FSI) 0000000000002C1C (FSI_BYTE) 0000000000050107 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_7
Constant(s):	PERV_M2B_DATA_AREA_7
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_7.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_7.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_7.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_7.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m2b_data_area_7

Mailbox 2 Data Area (Fsi) Register 8
Addr:	0000000000002908 (FSI) 0000000000002C20 (FSI_BYTE) 0000000000050108 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_8
Constant(s):	PERV_M2B_DATA_AREA_8
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_8.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_8.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_8.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_8.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m2b_data_area_8

Mailbox 2 Data Area (Fsi) Register 9
Addr:	0000000000002909 (FSI) 0000000000002C24 (FSI_BYTE) 0000000000050109 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_9
Constant(s):	PERV_M2B_DATA_AREA_9
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_9.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_9.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_9.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_9.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m2b_data_area_9

Mailbox 2 Data Area (Fsi) Register 10
Addr:	000000000000290A (FSI) 0000000000002C28 (FSI_BYTE) 000000000005010A (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_10
Constant(s):	PERV_M2B_DATA_AREA_10
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_10.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_10.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_10.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_10.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m2b_data_area_10

Mailbox 2 Data Area (Fsi) Register 11
Addr:	000000000000290B (FSI) 0000000000002C2C (FSI_BYTE) 000000000005010B (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_11
Constant(s):	PERV_M2B_DATA_AREA_11
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_11.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_11.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_11.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_11.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m2b_data_area_11

Mailbox 2 Data Area (Fsi) Register 12
Addr:	000000000000290C (FSI) 0000000000002C30 (FSI_BYTE) 000000000005010C (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_12
Constant(s):	PERV_M2B_DATA_AREA_12
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_12.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_12.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_12.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_12.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m2b_data_area_12

Mailbox 2 Data Area (Fsi) Register 13
Addr:	000000000000290D (FSI) 0000000000002C34 (FSI_BYTE) 000000000005010D (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_13
Constant(s):	PERV_M2B_DATA_AREA_13
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_13.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_13.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_13.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_13.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m2b_data_area_13

Mailbox 2 Data Area (Fsi) Register 14
Addr:	000000000000290E (FSI) 0000000000002C38 (FSI_BYTE) 000000000005010E (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_14
Constant(s):	PERV_M2B_DATA_AREA_14
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_14.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_14.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_14.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_14.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m2b_data_area_14

Mailbox 2 Data Area (Fsi) Register 15
Addr:	000000000000290F (FSI) 0000000000002C3C (FSI_BYTE) 000000000005010F (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_15
Constant(s):	PERV_M2B_DATA_AREA_15
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_15.FSILAT.LATCH.LATC.L2(1:8) [00000000]
	8:15	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_15.FSILAT.LATCH.LATC.L2(10:17) [00000000]
	16:23	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_15.FSILAT.LATCH.LATC.L2(19:26) [00000000]
	24:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.LBUS_MAILBOX.U4_15.FSILAT.LATCH.LATC.L2(28:35) [00000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	ROX	mda_m2b_data_area_15

ROOT CONTROL COPY 0 register
Addr:	0000000000002910 (FSI) 0000000000002C40 (FSI_BYTE) 0000000000050110 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL0_COPY
Constant(s):	PERV_ROOT_CTRL0_COPY
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL0_INST.CCFG_COPY_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RW	RW	RW	root_ctrl0_copy_reg

COPY ROOT CONTROL COPY 1 register
Addr:	0000000000002911 (FSI) 0000000000002C44 (FSI_BYTE) 0000000000050111 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL1_COPY
Constant(s):	PERV_ROOT_CTRL1_COPY
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL1_INST.CCFG_COPY_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RW	RW	RW	root_ctrl1_copy_reg

COPY ROOT CONTROL COPY 2 register
Addr:	0000000000002912 (FSI) 0000000000002C48 (FSI_BYTE) 0000000000050112 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL2_COPY
Constant(s):	PERV_ROOT_CTRL2_COPY
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL2_INST.CCFG_COPY_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RW	RW	RW	root_ctrl2_copy_reg

COPY ROOT CONTROL COPY 3 register
Addr:	0000000000002913 (FSI) 0000000000002C4C (FSI_BYTE) 0000000000050113 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL3_COPY
Constant(s):	PERV_ROOT_CTRL3_COPY
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL3_INST.CCFG_COPY_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RW	RW	RW	root_ctrl3_copy_reg

COPY ROOT CONTROL COPY 4 register
Addr:	0000000000002914 (FSI) 0000000000002C50 (FSI_BYTE) 0000000000050114 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL4_COPY
Constant(s):	PERV_ROOT_CTRL4_COPY
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL4_INST.CCFG_COPY_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RW	RW	RW	root_ctrl4_copy_reg

COPY ROOT CONTROL COPY 5 register
Addr:	0000000000002915 (FSI) 0000000000002C54 (FSI_BYTE) 0000000000050115 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL5_COPY
Constant(s):	PERV_ROOT_CTRL5_COPY
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL5_INST.CCFG_COPY_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RW	RW	RW	root_ctrl5_copy_reg

COPY ROOT CONTROL COPY 6 register
Addr:	0000000000002916 (FSI) 0000000000002C58 (FSI_BYTE) 0000000000050116 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL6_COPY
Constant(s):	PERV_ROOT_CTRL6_COPY
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL6_INST.CCFG_COPY_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RW	RW	RW	root_ctrl6_copy_reg

COPY ROOT CONTROL COPY 7 register
Addr:	0000000000002917 (FSI) 0000000000002C5C (FSI_BYTE) 0000000000050117 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL7_COPY
Constant(s):	PERV_ROOT_CTRL7_COPY
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL7_INST.CCFG_COPY_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RW	RW	RW	root_ctrl7_copy_reg

COPY ROOT CONTROL COPY 8 register
Addr:	0000000000002918 (FSI) 0000000000002C60 (FSI_BYTE) 0000000000050118 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL8_COPY
Constant(s):	PERV_ROOT_CTRL8_COPY
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL8_INST.CCFG_COPY_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RW	RW	RW	root_ctrl8_copy_reg

COPY PERV CONTROL COPY 0 register
Addr:	000000000000291A (FSI) 0000000000002C68 (FSI_BYTE) 000000000005011A (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL0_COPY
Constant(s):	PERV_PERV_CTRL0_COPY
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.PERV_CTRL0_INST.CCFG_COPY_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RW	RW	RW	perv_ctrl0_copy_reg

COPY PERV CONTROL COPY 1 register
Addr:	000000000000291B (FSI) 0000000000002C6C (FSI_BYTE) 000000000005011B (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL1_COPY
Constant(s):	PERV_PERV_CTRL1_COPY
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.PERV_CTRL1_INST.CCFG_COPY_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RW	RW	RW	perv_ctrl1_copy_reg

SET function of ROOT CONTROL 0 register
Addr:	0000000000002920 (FSI) 0000000000002C80 (FSI_BYTE) 0000000000050120 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL0_SET
Constant(s):	PERV_ROOT_CTRL0_SET
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL0_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	WO_OR	WO_OR	WO_OR	CFAM_PROTECTION_0_DC: CFAM protection 0 for RCS interface
1	WO_OR	WO_OR	WO_OR	ROOT_CTRL0_1_SPARE: Not used
2	WO_OR	WO_OR	WO_OR	TPFSI_TPI2C_BUS_FENCE_DC: I2C master bus fence
3:5	WO_OR	WO_OR	WO_OR	TPCFSI_OPB_SW0_FENCE_DC: OPB0 ARBITER (FSI0 side): Fence off arbitration requests from OPB master: bit3 : FSI slave0 bit4 : PIB2OPB Host bit5 : PIB2OPB none-Host
6:7	WO_OR	WO_OR	WO_OR	ROOT_CTRL0_6_7_SPARE: Not used.
8	WO_OR	WO_OR	WO_OR	CFAM_PROTECTION_1_DC: CFAM protection 1 for CBS/VITL interface
9	WO_OR	WO_OR	WO_OR	CFAM_PROTECTION_2_DC: CFAM protection 2 for PIB_master/slave interfaces
10	WO_OR	WO_OR	WO_OR	CFAM_PIB_SLV_RESET_DC: Functionally resets all PIB slave instances on CFAM
11	WO_OR	WO_OR	WO_OR	ROOT_CTRL0_11_SPARE: Not used.
12	WO_OR	WO_OR	WO_OR	ROOT_CTRL0_12_SPARE: Not used.
13	WO_OR	WO_OR	WO_OR	ROOT_CTRL0_13_SPARE: Not used.
14	WO_OR	WO_OR	WO_OR	SPARE_FENCE_CONTROL: Not used
15	WO_OR	WO_OR	WO_OR	VDD2VIO_LVL_FENCE_DC: PLL fence enable 0b0 = not fenced 0b1 = fenced
16	WO_OR	WO_OR	WO_OR	FSI2PCB_DC: Directly connects FSI2PIB engine to pervasive chiplet (bypassing PIB and PCB)
17	WO_OR	WO_OR	WO_OR	OOB_MUX: Select OOB (Out of Band) multiplexer
18	WO_OR	WO_OR	WO_OR	PIB2PCB_DC: Directly connects SBE engine to pervasive chiplet (bypassing PCB)
19	WO_OR	WO_OR	WO_OR	PCB2PCB_DC: Connects SBE engine to pervasive chiplet through PIB/PCB
20	WO_OR	WO_OR	WO_OR	FSI_CC_VSB_CBS_REQ: CBS interface: Request signal from FSI to PERV_CC
21:23	WO_OR	WO_OR	WO_OR	FSI_CC_VSB_CBS_CMD: CBS interface: Command from FSI to PERV_CC: 0b000 = NOP - could be used to test if clocks in PERV chiplet are available 0b001 = RESET - reset PERV_CC only to init values 0b010 = SCAN0 - trigger scan0 on all regions 0b011 = CLK START - SBE region will be started 0b100 = CLK STOP - SBE region will be stopped 0b101 = NOP - unused 0b110 = NOP - unused 0b111 = SCAN0 & CLK START - used by CFAM Boot Sequencer (CBS)
24	WO_OR	WO_OR	WO_OR	ROOT_CTRL0_24_SPARE_CBS_CONTROL: Not used
25	WO_OR	WO_OR	WO_OR	ROOT_CTRL0_25_SPARE_CBS_CONTROL: Not used
26	WO_OR	WO_OR	WO_OR	ROOT_CTRL0_26_SPARE_CBS_CONTROL: Not used
27	WO_OR	WO_OR	WO_OR	ROOT_CTRL0_27_SPARE_CBS_CONTROL: Not used
28	WO_OR	WO_OR	WO_OR	ROOT_CTRL0_28_SPARE_RESET: Not used
29	WO_OR	WO_OR	WO_OR	TPFSI_IO_OCMB_RESET_EN: OCMB Reset Control: 0b0 = Disable OCMB reset 0b1 = Enable OCMB reset
30	WO_OR	WO_OR	WO_OR	PCB_RESET_DC: PERV chiplet PCB interface reset - requires OOB mux to be selected
31	WO_OR	WO_OR	WO_OR	GLOBAL_EP_RESET_DC: Global endpoint reset - asynchonously reset ALL chiplet vital logic except PERV

SET function of ROOT CONTROL 1 register
Addr:	0000000000002921 (FSI) 0000000000002C84 (FSI_BYTE) 0000000000050121 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL1_SET
Constant(s):	PERV_ROOT_CTRL1_SET
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL1_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:3	WO_OR	WO_OR	WO_OR	TP_PROBE0_SEL_DC: PROBE0 select
4:7	WO_OR	WO_OR	WO_OR	TP_PROBE1_SEL_DC: PROBE1 select
8	WO_OR	WO_OR	WO_OR	TP_PROBE_MESH_SEL_DC: PROBE MESH select
9	WO_OR	WO_OR	WO_OR	TP_PROBE_DRV_EN_DC: PROBE drive enable
10	WO_OR	WO_OR	WO_OR	ROOT_CTRL1_10_SPARE: Not used
11:12	WO_OR	WO_OR	WO_OR	TP_FSI_PROBE_SEL_DC: FSI PROBE select
13	WO_OR	WO_OR	WO_OR	TP_AN_PROBE_DRVR_MCPRECOMP0_DC: Tune high speed probe I/Os
14	WO_OR	WO_OR	WO_OR	TP_AN_PROBE_DRVR_MCPRECOMP1_DC: Tune high speed probe I/Os
15	WO_OR	WO_OR	WO_OR	TP_AN_PROBE_DRVR_MCPRECOMP2_DC: Tune high speed probe I/Os
16	WO_OR	WO_OR	WO_OR	TP_IDDQ_DC: IDDQ test (leakage)
17	WO_OR	WO_OR	WO_OR	SPARE_RI_CONTROL: Not used
18	WO_OR	WO_OR	WO_OR	SPARE_DI_CONTROL: Not used
19	WO_OR	WO_OR	WO_OR	TP_RI_DC_B: Receiver inhibit (RI) of I/O books 0b0 = receiver disabled 0b1 = receiver enabled
20	WO_OR	WO_OR	WO_OR	TP_DI1_DC_B: Driver inhibit (DI1) of I/O books: 0b0 = driver1 disabled 0b1 = driver1 enabled
21	WO_OR	WO_OR	WO_OR	TP_DI2_DC_B: Driver inhibit (DI2) of I/O books 0b0 = driver2 disabled 0b1 = driver2 enabled
22	WO_OR	WO_OR	WO_OR	TP_TPM_DI1_DC_B: Driver inhibit (DI1) of TPM I/O books: 0b0 = TPM driver1 disabled 0b1 = TPM driver1 enabled
23	WO_OR	WO_OR	WO_OR	ROOT_CTRL1_23_SPARE_TEST: Not used
24	WO_OR	WO_OR	WO_OR	TP_TEST_BURNIN_MODE_DC: Burn-in mode
25	WO_OR	WO_OR	WO_OR	TPFSI_ARRAY_SET_VBL_TO_VDD_DC: Set array voltage block line to VDD
26	WO_OR	WO_OR	WO_OR	TPFSI_TP_GLB_PERST_OVR_DC: Global PERST# override control. At '1', all PCI reset outputs will be forced low (active). Set to '0' to allow PHB control.
27	WO_OR	WO_OR	WO_OR	ROOT_CTRL1_27_SPARE:
28	WO_OR	WO_OR	WO_OR	ROOT_CTRL1_28_SPARE_TEST_CONTROL: Not used
29	WO_OR	WO_OR	WO_OR	ROOT_CTRL1_29_SPARE_TEST_CONTROL: Not used
30	WO_OR	WO_OR	WO_OR	ROOT_CTRL1_30_SPARE_TEST_CONTROL: Not used
31	WO_OR	WO_OR	WO_OR	ROOT_CTRL1_31_SPARE_TEST_CONTROL: Not used

SET function of ROOT CONTROL 2 register
Addr:	0000000000002922 (FSI) 0000000000002C88 (FSI_BYTE) 0000000000050122 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL2_SET
Constant(s):	PERV_ROOT_CTRL2_SET
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL2_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	WO_OR	WO_OR	WO_OR	ROOT_CTRL2_0_SPARE: Not used.
1	WO_OR	WO_OR	WO_OR	TPFSI_TP_DBG_PCB_DATA_PAR_DIS_DC: Debug only: PCB data parity disable
2	WO_OR	WO_OR	WO_OR	TPFSI_TP_DBG_PCB_TYPE_PAR_DIS_DC: Debug only: PCB type parity disable
3	WO_OR	WO_OR	WO_OR	ROOT_CTRL2_3_SPARE: Not used.
4	WO_OR	WO_OR	WO_OR	TP_PIB_DISABLE_PARITY_DC: Disable parity check for PIB
5	WO_OR	WO_OR	WO_OR	TP_PIB_TRACE_MODE_DATA_DC: PIB trace mode 0: traces addresses only 1: additionally trace request and response data - uses more trace entries
6	WO_OR	WO_OR	WO_OR	TP_PIB_VSB_SBE_TRACE_MODE: SBE trace mode to SBE - forces SBE into a specific trace bus configuration
7	WO_OR	WO_OR	WO_OR	TP_TPCPERV_VSB_TRACE_STOP: Trace stop signal to DBG macro.
8:10	WO_OR	WO_OR	WO_OR	TP_GPIO_PIB_TIMEOUT: Timeout of PIB arbiter: PIB clock cycles 0b110 = 256 0b100 = 1024 0b010 = 8192 0b000 = 32768 0b--1 = not available (timeout function disabled)
11	WO_OR	WO_OR	WO_OR	SPARE_PIB_CONTROL: Not used
12	WO_OR	WO_OR	WO_OR	TPCFSI_OPB_SW_RESET_DC: Reset of OPB arbiter
13	WO_OR	WO_OR	WO_OR	ROOT_CTRL2_13_SPARE_OPB_CONTROL: Not used
14	WO_OR	WO_OR	WO_OR	ROOT_CTRL2_14_SPARE_OPB_CONTROL: Not used
15	WO_OR	WO_OR	WO_OR	ROOT_CTRL2_15_SPARE_OPB_CONTROL: Not used
16	WO_OR	WO_OR	WO_OR	ROOT_CTRL2_16_SPARE: Not used
17	WO_OR	WO_OR	WO_OR	ROOT_CTRL2_17_SPARE: Not used.
18	WO_OR	WO_OR	WO_OR	ROOT_CTRL2_18_SPARE: Not used
19	WO_OR	WO_OR	WO_OR	ROOT_CTRL2_19_SPARE: Not used
20	WO_OR	WO_OR	WO_OR	ROOT_CTRL2_20_SPARE: Not used.
21	WO_OR	WO_OR	WO_OR	ROOT_CTRL2_21_FREE_USAGE: Not used
22	WO_OR	WO_OR	WO_OR	ROOT_CTRL2_22_FREE_USAGE: Not used
23	WO_OR	WO_OR	WO_OR	ROOT_CTRL2_23_FREE_USAGE: Not used
24	WO_OR	WO_OR	WO_OR	ROOT_CTRL2_24_FREE_USAGE: Not used.
25	WO_OR	WO_OR	WO_OR	ROOT_CTRL2_25_FREE_USAGE: Not used.
26	WO_OR	WO_OR	WO_OR	ROOT_CTRL2_26_FREE_USAGE: Not used
27	WO_OR	WO_OR	WO_OR	ROOT_CTRL2_27_FREE_USAGE: Not used
28	WO_OR	WO_OR	WO_OR	ROOT_CTRL2_28_FREE_USAGE: Not used
29	WO_OR	WO_OR	WO_OR	ROOT_CTRL2_29_FREE_USAGE: Not used
30	WO_OR	WO_OR	WO_OR	ROOT_CTRL2_30_FREE_USAGE: Not used.
31	WO_OR	WO_OR	WO_OR	ROOT_CTRL2_31_FREE_USAGE: Not used.

SET function of ROOT CONTROL 3 register
Addr:	0000000000002923 (FSI) 0000000000002C8C (FSI_BYTE) 0000000000050123 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL3_SET
Constant(s):	PERV_ROOT_CTRL3_SET
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL3_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	WO_OR	WO_OR	WO_OR	TP_PLLCLKSW1_RESET_DC: PLLCLKSW1 reset
1	WO_OR	WO_OR	WO_OR	TP_PLLCLKSW1_BYPASS_EN_DC: PLLCLKSW1 bypass
2	WO_OR	WO_OR	WO_OR	TP_PLLCLKSW1_TEST_EN_DC: PLLCLKSW1 test enable
3	WO_OR	WO_OR	WO_OR	TP_PLLCLKSW1_ALTREFCLK_SEL_DC: Use alternate refclk for PLLCLKSW1 - 0=OSC0 differential, 1=OSC1 single-ended
4	WO_OR	WO_OR	WO_OR	TP_PLLCLKSW2_RESET_DC: PLLCLKSW2 reset
5	WO_OR	WO_OR	WO_OR	TP_PLLCLKSW2_BYPASS_EN_DC: PLLCLKSW2 bypass
6	WO_OR	WO_OR	WO_OR	TP_PLLCLKSW2_TEST_EN_DC: PLLCLKSW2 test enable
7	WO_OR	WO_OR	WO_OR	TP_PLLCLKSW2_ALTREFCLK_SEL_DC: Use alternate refclk for PLLCLKSW2 - 0=OSC1 differential, 1=OSC0 single-ended
8	WO_OR	WO_OR	WO_OR	TP_PLLTODFLT_RESET_DC: TOD filter PLL reset
9	WO_OR	WO_OR	WO_OR	TP_PLLTODFLT_BYPASS_EN_DC: TOD filter PLL bypass
10	WO_OR	WO_OR	WO_OR	TP_PLLTODFLT_TEST_EN_DC: TOD filter PLL test enable
11	WO_OR	WO_OR	WO_OR	SPARE_PLLTODFLT: Not used
12	WO_OR	WO_OR	WO_OR	TP_PLLNESTFLT_RESET_DC: Nest Filter PLL test enable
13	WO_OR	WO_OR	WO_OR	TP_PLLNESTFLT_BYPASS_EN_DC: Nest Filter PLL bypass
14	WO_OR	WO_OR	WO_OR	TP_PLLNESTFLT_TEST_EN_DC: Nest Filter PLL test enable
15	WO_OR	WO_OR	WO_OR	SPARE_PLLNESTFLT: Not used
16	WO_OR	WO_OR	WO_OR	TP_PLLIOFLT_RESET_DC: IO Filter PLL reset
17	WO_OR	WO_OR	WO_OR	TP_PLLIOFLT_BYPASS_EN_DC: IO Filter PLL bypass
18	WO_OR	WO_OR	WO_OR	TP_PLLIOFLT_TEST_EN_DC: IO Filter PLL test enable
19	WO_OR	WO_OR	WO_OR	SPARE_PLLIOFLT: Not used
20	WO_OR	WO_OR	WO_OR	TP_PLLIOSSFLT_RESET_DC: IO Spread Filter PLL reset
21	WO_OR	WO_OR	WO_OR	TP_PLLIOSSFLT_BYPASS_EN_DC: IO Spread Filter PLL bypass
22	WO_OR	WO_OR	WO_OR	TP_PLLIOSSFLT_TEST_EN_DC: IO Spread Filter PLL test enable
23	WO_OR	WO_OR	WO_OR	SPARE_PLLIOSSFLT: Not used
24	WO_OR	WO_OR	WO_OR	TP_PAU_DPLL_RESET_DC: PAU DPLL reset
25	WO_OR	WO_OR	WO_OR	TP_PAU_DPLL_BYPASS_EN_DC: PAU DPLL bypass
26	WO_OR	WO_OR	WO_OR	TP_PAU_DPLL_TEST_EN_DC: PAU DPLL test enable
27	WO_OR	WO_OR	WO_OR	TP_PAU_DPLL_FUNC_CLKSEL_DC: PAU DPLL func clock select
28	WO_OR	WO_OR	WO_OR	TP_NEST_DPLL_RESET_DC: NEST DPLL reset
29	WO_OR	WO_OR	WO_OR	TP_NEST_DPLL_BYPASS_EN_DC: NEST DPLL bypass
30	WO_OR	WO_OR	WO_OR	TP_NEST_DPLL_TEST_EN_DC: NEST DPLL test enable
31	WO_OR	WO_OR	WO_OR	TP_NEST_DPLL_FUNC_CLKSEL_DC: NEST DPLL func clock select

SET function of ROOT CONTROL 4 register
Addr:	0000000000002924 (FSI) 0000000000002C90 (FSI_BYTE) 0000000000050124 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL4_SET
Constant(s):	PERV_ROOT_CTRL4_SET
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL4_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:1	WO_OR	WO_OR	WO_OR	TP_AN_REFCLK_CLKMUX0A_CLKIN_SEL_DC: PLLTODFLT input selection: 00: SYS refclock 0 01: RCS async out 1x: RCS sync out
2:3	WO_OR	WO_OR	WO_OR	TP_AN_REFCLK_CLKMUX0B_CLKIN_SEL_DC: PLLNESTFLT input selection: 00: SYS refclock 0 01: RCS async out 1x: RCS sync out
4:5	WO_OR	WO_OR	WO_OR	TP_AN_REFCLK_CLKMUX0C_CLKIN_SEL_DC: PLLIOFLT input selection: 00: SYS refclock 0 01: RCS async out 1x: RCS sync out
6:7	WO_OR	WO_OR	WO_OR	TP_AN_REFCLK_CLKMUX0D_CLKIN_SEL_DC: PLLIOSSFLT input selection: 00: SYS refclock 0 01: RCS async out 1x: RCS sync out
8	WO_OR	WO_OR	WO_OR	TP_AN_REFCLK_CLKMUX10_CLKIN_SEL_DC: PAU DPLL input selection: 0: PLLIOSSFLT output 1: PLLIOFLT output
9	WO_OR	WO_OR	WO_OR	TP_AN_REFCLK_CLKMUX11_CLKIN_SEL_DC: Nest DPLL input selection: 0: PLLIOSSFLT output 1: PLLIOFLT output
10:11	WO_OR	WO_OR	WO_OR	TP_AN_REFCLK_CLKMUX12_CLKIN_SEL_DC: OMI PLL input selection: 00: PLLTODFLT output 01: PLLNESTFLT output 1x: PLLIOFLT output
12:13	WO_OR	WO_OR	WO_OR	TP_AN_REFCLK_CLKMUX13_CLKIN_SEL_DC: AXON 133 MHz input selection: 00: PLLTODFLT output 01: PLLNESTFLT output 1x: PLLIOFLT output
14	WO_OR	WO_OR	WO_OR	TP_AN_REFCLK_CLKMUX14_CLKIN_SEL_DC: AXON 156 MHz input selection: 0: PLLNESTFLT output 1: PLLIOFLT output
15:16	WO_OR	WO_OR	WO_OR	TP_AN_REFCLK_CLKMUX23_CLKIN_SEL_DC: PCI PLL 100MHz input pre-selection (feeds per-chiplet muxes): 00: PLLTODFLT output 01: PLLIOSSFLT output 1x: MUX0D output / PLLIOSSFLT input
17	WO_OR	WO_OR	WO_OR	TP_AN_TOD_LPC_MUX_SEL_DC: TOD input clock selection: 0: 32 MHz LPC clock 1: 16 MHz from PLLTODFLT
18	WO_OR	WO_OR	WO_OR	ROOT_CTRL4_18_SPARE: Not used
19	WO_OR	WO_OR	WO_OR	ROOT_CTRL4_19_SPARE: Not used
20	WO_OR	WO_OR	WO_OR	TP_MUX1_CLKIN_SEL_DC: PAU/NEST input selection: 0: MUX10 output 1: TCK
21	WO_OR	WO_OR	WO_OR	TP_MUX2A_CLKIN_SEL_DC: PAU input selection: 0: PAU DPLL output 1: MUX1 output
22	WO_OR	WO_OR	WO_OR	TP_MUX2B_CLKIN_SEL_DC: Nest input selection 1: 0: PAU DPLL output 1: MUX1 output
23	WO_OR	WO_OR	WO_OR	TP_MUX3_CLKIN_SEL_DC: Nest input selection 2: 0: Nest DPLL output 1: MUX2B output
24	WO_OR	WO_OR	WO_OR	TP_MUX4A_CLKIN_SEL_DC: Nest/Cache mesh division ratio compared to core: 0: Divide by 2 1: No division
25	WO_OR	WO_OR	WO_OR	TP_AN_CLKGLM_NEST_ASYNC_RESET_DC: Hold Nest mesh in reset if 1, enable Nest mesh if 0
26	WO_OR	WO_OR	WO_OR	TP_AN_NEST_DIV2_ASYNC_RESET_DC: Reset Nest/Cache 2:1 dividers. Unstaged, so release before enabling Nest/Core/Cache meshes!
27	WO_OR	WO_OR	WO_OR	TPFSI_ALTREFCLK_SEL: Force all chiplet PLLs into altrefclk mode
28	WO_OR	WO_OR	WO_OR	ROOT_CTRL4_28_SPARE: Not used.
29	WO_OR	WO_OR	WO_OR	TP_PLL_FORCE_OUT_EN_DC: Enable the chip level filter PLL outputs
30	WO_OR	WO_OR	WO_OR	DPLL_FREEZE_DC: Set to 1 to make the Nest and PAU DPLLs ignore changes to their control inputs, e.g. for scanning the DPLL controllers
31	WO_OR	WO_OR	WO_OR	TP_AN_MUX3_ASYNC_RESET_DC: Hold Nest/Core/Cache meshes in reset if 1, enable them if 0

SET function of ROOT CONTROL 5 register
Addr:	0000000000002925 (FSI) 0000000000002C94 (FSI_BYTE) 0000000000050125 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL5_SET
Constant(s):	PERV_ROOT_CTRL5_SET
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL5_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	WO_OR	WO_OR	WO_OR	TPFSI_RCS_RESET_DC: RCS reset
1	WO_OR	WO_OR	WO_OR	TPFSI_RCS_BYPASS_DC: RCS bypass
2	WO_OR	WO_OR	WO_OR	TPFSI_RCS_FORCE_BYPASS_CLKSEL_DC: RCS bypass clock select - 0: osc0, 1: osc1
3	WO_OR	WO_OR	WO_OR	TPFSI_RCS_CLK_TEST_IN_DC: RCS clock test latch input - outputs in SNS1LTH (address 281D)
4	WO_OR	WO_OR	WO_OR	SWO_FORCE_LOW: Used with FORCE_BYPASS_CLKSEL to manually force a switch over to alternate clk for concurrent maintenance
5	WO_OR	WO_OR	WO_OR	BLOCK_SWO: Block error_a/b from switching over to the B/A side
6	WO_OR	WO_OR	WO_OR	CLEAR_CLK_ERROR_A: Clear detected Path A clock error
7	WO_OR	WO_OR	WO_OR	CLEAR_CLK_ERROR_B: Clear detected Path B clock error
8	WO_OR	WO_OR	WO_OR	SEL_DEL: Error detector sample clock delay 0 = 156.25ps, 1 = 312.5ps
9:11	WO_OR	WO_OR	WO_OR	RCS_CONTROL_10_8: RCS spare input CONTROL(10 downto 8)
12:15	WO_OR	WO_OR	WO_OR	FILT: 6B Up/Dwn counter filter depth
16	WO_OR	WO_OR	WO_OR	PFD_PW_SEL: Phase Freq Detector PW_SEL which extends INC/DEC signal widths
17	WO_OR	WO_OR	WO_OR	FORCE_ERROR_HIGH: Force input high to check for stuck low error detect
18	WO_OR	WO_OR	WO_OR	TESTOUT_EN: Enable CMOS output that connects to C4 mux
19:21	WO_OR	WO_OR	WO_OR	TESTOUT_SEL: Select which of REFCLK_P/N or ASYNC_OUT_P/N or Input Clock CMOS output that connects to C4 mux
22	WO_OR	WO_OR	WO_OR	EN_OVERRIDE_A: Enable ripple counter output bits override on the A side
23	WO_OR	WO_OR	WO_OR	EN_OVERRIDE_B: Enable ripple counter output bits override on the B side
24:29	WO_OR	WO_OR	WO_OR	OVRBIT: Ripple counter override output bits
30	WO_OR	WO_OR	WO_OR	EN_REFCLK: Enable REFCLK output
31	WO_OR	WO_OR	WO_OR	EN_ASYNC_OUT: Enable ASYNC_OUT output

SET function of ROOT CONTROL 6 register
Addr:	0000000000002926 (FSI) 0000000000002C98 (FSI_BYTE) 0000000000050126 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL6_SET
Constant(s):	PERV_ROOT_CTRL6_SET
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL6_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:3	WO_OR	WO_OR	WO_OR	ROOT_CTRL6_0_3: Not used
4:5	WO_OR	WO_OR	WO_OR	TP_AN_PCI0_RX_REFCLK_TERM: PCI0 refclock receiver termination: 0b00 = 100 Ohm differential termination 0b10 = 50 Ohm to GND 0b01 = no termination 0b11 = no termination Dial enums: HUNDRED_OHM_DIFF=>0b00 FIFTY_OHM_SE=>0b10 NO_TERM=>0b11
6:7	WO_OR	WO_OR	WO_OR	TP_AN_PCI1_RX_REFCLK_TERM: PCI1 refclock receiver termination: 0b00 = 100 Ohm differential termination 0b10 = 50 Ohm to GND 0b01 = no termination 0b11 = no termination Dial enums: HUNDRED_OHM_DIFF=>0b00 FIFTY_OHM_SE=>0b10 NO_TERM=>0b11
8	WO_OR	WO_OR	WO_OR	CHKSW_DD1_HW547515_RCS_EVENTLOG: Chickenswitch for RCS eventLog: 0b0 = RCS eventLog logic is full functional and is able to capture up to 4 different states 0b1 = RCS eventLog logic is just able to capture one state (ie. install dd1 issue)
9:15	WO_OR	WO_OR	WO_OR	ROOT_CTRL6_9_15: Not used
16:19	WO_OR	WO_OR	WO_OR	DESKEW_SEL_A: Deskew value to align 100MHz REFCLK_A with 6.4GHz clock at shiftreg input
20:23	WO_OR	WO_OR	WO_OR	DESKEW_SEL_B: Deskew value to align 100MHz REFCLK_A with 6.4GHz clock at shiftreg input
24:27	WO_OR	WO_OR	WO_OR	RCS_CONTROL_7_4: RCS spare input CONTROL(7 downto 4)
28	WO_OR	WO_OR	WO_OR	CHKSW_JUMP_FORWARD: RCS spare input CONTROL(3) - Jump forward chicken switch
29:30	WO_OR	WO_OR	WO_OR	SEL_RES_AMP: RCS spare input CONTROL(2 downto 1) - SEL_RES inputs to adjust output amplitude
31	WO_OR	WO_OR	WO_OR	MASK_UNLOCKDET: RCS spare input CONTROL(0) - Mask UNLOCKDET_* outputs

SET function of ROOT CONTROL 7 register
Addr:	0000000000002927 (FSI) 0000000000002C9C (FSI_BYTE) 0000000000050127 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL7_SET
Constant(s):	PERV_ROOT_CTRL7_SET
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL7_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	WO_OR	WO_OR	WO_OR	TP_MEM0_REFCLK_DRVR_EN_DC: MEM0 reference clock driver enable
1	WO_OR	WO_OR	WO_OR	TP_MEM1_REFCLK_DRVR_EN_DC: MEM1 reference clock driver enable
2	WO_OR	WO_OR	WO_OR	TP_MEM2_REFCLK_DRVR_EN_DC: MEM2 reference clock driver enable
3	WO_OR	WO_OR	WO_OR	TP_MEM3_REFCLK_DRVR_EN_DC: MEM3 reference clock driver enable
4	WO_OR	WO_OR	WO_OR	TP_MEM4_REFCLK_DRVR_EN_DC: MEM4 reference clock driver enable
5	WO_OR	WO_OR	WO_OR	TP_MEM5_REFCLK_DRVR_EN_DC: MEM5 reference clock driver enable
6	WO_OR	WO_OR	WO_OR	TP_MEM6_REFCLK_DRVR_EN_DC: MEM6 reference clock driver enable
7	WO_OR	WO_OR	WO_OR	TP_MEM7_REFCLK_DRVR_EN_DC: MEM7 reference clock driver enable
8	WO_OR	WO_OR	WO_OR	TP_MEM8_REFCLK_DRVR_EN_DC: MEM8 reference clock driver enable
9	WO_OR	WO_OR	WO_OR	TP_MEM9_REFCLK_DRVR_EN_DC: MEM9 reference clock driver enable
10	WO_OR	WO_OR	WO_OR	TP_MEMA_REFCLK_DRVR_EN_DC: MEMa reference clock driver enable
11	WO_OR	WO_OR	WO_OR	TP_MEMB_REFCLK_DRVR_EN_DC: MEMb reference clock driver enable
12	WO_OR	WO_OR	WO_OR	TP_MEMC_REFCLK_DRVR_EN_DC: MEMc reference clock driver enable
13	WO_OR	WO_OR	WO_OR	TP_MEMD_REFCLK_DRVR_EN_DC: MEMd reference clock driver enable
14	WO_OR	WO_OR	WO_OR	TP_MEME_REFCLK_DRVR_EN_DC: MEMe reference clock driver enable
15	WO_OR	WO_OR	WO_OR	TP_MEMF_REFCLK_DRVR_EN_DC: MEMf reference clock driver enable
16	WO_OR	WO_OR	WO_OR	TP_OP0A_REFCLK_DRVR_EN_DC: OP0a reference clock driver enable
17	WO_OR	WO_OR	WO_OR	TP_OP0B_REFCLK_DRVR_EN_DC: OP0b reference clock driver enable
18	WO_OR	WO_OR	WO_OR	TP_OP3A_REFCLK_DRVR_EN_DC: OP3a reference clock driver enable
19	WO_OR	WO_OR	WO_OR	TP_OP3B_REFCLK_DRVR_EN_DC: OP3b reference clock driver enable
20	WO_OR	WO_OR	WO_OR	TP_OP4_REFCLK_DRVR_EN_DC: OP4 reference clock driver enable
21	WO_OR	WO_OR	WO_OR	TP_OP5_REFCLK_DRVR_EN_DC: OP5 reference clock driver enable
22	WO_OR	WO_OR	WO_OR	TP_OP6_REFCLK_DRVR_EN_DC: OP6 reference clock driver enable
23	WO_OR	WO_OR	WO_OR	TP_OP7_REFCLK_DRVR_EN_DC: OP7 reference clock driver enable
24	WO_OR	WO_OR	WO_OR	TP_OP_DRVR_2X_CUR_EN_DC: Optical Clock Driver 2x Current Enable
25	WO_OR	WO_OR	WO_OR	TP_E0A_DRVR_2X_CUR_EN_DC: PCIE0 A Slot Clock Driver 2x Current Enable
26	WO_OR	WO_OR	WO_OR	TP_E0B_DRVR_2X_CUR_EN_DC: PCIE0 B Slot Clock Driver 2x Current Enable
27	WO_OR	WO_OR	WO_OR	TP_E0C_DRVR_2X_CUR_EN_DC: PCIE0 C Slot Clock Driver 2x Current Enable
28	WO_OR	WO_OR	WO_OR	TP_E1A_DRVR_2X_CUR_EN_DC: PCIE1 A Slot Clock Driver 2x Current Enable
29	WO_OR	WO_OR	WO_OR	TP_E1B_DRVR_2X_CUR_EN_DC: PCIE1 B/C Slot Clock Driver 2x Current Enable
30	WO_OR	WO_OR	WO_OR	TP_E1C_DRVR_2X_CUR_EN_DC: Global clock driver near-end termination enable
31	WO_OR	WO_OR	WO_OR	ROOT_CTRL7_31_SPARE_RESONANT_CLOCKING_CONTROL: Not used

SET function of ROOT CONTROL 8 register
Addr:	0000000000002928 (FSI) 0000000000002CA0 (FSI_BYTE) 0000000000050128 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL8_SET
Constant(s):	PERV_ROOT_CTRL8_SET
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL8_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	WO_OR	WO_OR	WO_OR	TPFSI_SPIMST0_PORT_MUX_SEL_DC: Select SPIM_0 for BOOT0 SEEPROM: 0b0 = select PIB SPIM_0 (default) 0b1 = select FSI SPIM_0
1	WO_OR	WO_OR	WO_OR	TPFSI_SPIMST1_PORT_MUX_SEL_DC: Select SPIM_1 for BOOT1 SEEPROM: 0b0 = select PIB SPIM_1 (default) 0b1 = select FSI SPIM_1
2	WO_OR	WO_OR	WO_OR	TPFSI_SPIMST2_PORT_MUX_SEL_DC: Select SPIM_2 for MVPD/KEYSTORE SEEPROM: 0b0 = select PIB SPIM_2 (default) 0b1 = select FSI SPIM_2
3	WO_OR	WO_OR	WO_OR	TPFSI_SPIMST3_PORT_MUX_SEL_DC: Select SPIM_3 for MEASUREMENT ROM: 0b0 = select PIB SPIM_3 (default) 0b1 = select FSI SPIM_3
4:15	WO_OR	WO_OR	WO_OR	ROOT_CTRL8_4_15: Not used
16	WO_OR	WO_OR	WO_OR	TP_FSI_FENCE_DC: FSI chiplet fence
17	WO_OR	WO_OR	WO_OR	TCFSI_VITL_FENCE_DC: FSI clock region fence for VITL
18	WO_OR	WO_OR	WO_OR	TCFSI_FSI0_FENCE_DC: FSI clock region fence for FSI0
19	WO_OR	WO_OR	WO_OR	TCFSI_FSI0LL_FENCE_DC: FSI clock region fence for FSI0LL
20	WO_OR	WO_OR	WO_OR	TCFSI_FSI0INV_FENCE_DC: FSI clock region fence for FSI0INV
21	WO_OR	WO_OR	WO_OR	TCFSI_FSI1_FENCE_DC: FSI clock region fence for FSI1
22	WO_OR	WO_OR	WO_OR	TCFSI_FSI1LL_FENCE_DC: FSI clock region fence for FSI1LL
23	WO_OR	WO_OR	WO_OR	TCFSI_FSIA_FENCE_DC: FSI clock region fence for FSIA
24:31	WO_OR	WO_OR	WO_OR	ROOT_CTRL8_24_31: Not used

SET function of PERV CONTROL 0 register
Addr:	000000000000292A (FSI) 0000000000002CA8 (FSI_BYTE) 000000000005012A (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL0_SET
Constant(s):	PERV_PERV_CTRL0_SET
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.PERV_CTRL0_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	WO_OR	WO_OR	WO_OR	TP_TCPERV_CHIPLET_EN_DC: Chiplet enable.
1	WO_OR	WO_OR	WO_OR	TP_TCPERV_PCB_EP_RESET_DC: PCB endpoint reset
2	WO_OR	WO_OR	WO_OR	TP_AN_CLKGLM_TEST_TCK_ASYNC_RESET: Hold TP_CONST and NEST meshes in reset if 1, enable TP_CONST mesh if 0. See ROOT_CTRL4(25) for NEST meshes.
3:6	WO_OR	WO_OR	WO_OR	PERV_CTRL0_3_6_RESERVED: Not used.
7	WO_OR	WO_OR	WO_OR	TP_TCPERV_VITL_SCIN_DC: Scan in for the chiplet VITAL domain
8	WO_OR	WO_OR	WO_OR	PERV_CTRL0_8_RESERVED: Not used.
9	WO_OR	WO_OR	WO_OR	TP_TCPERV_FLUSH_ALIGN_OVERWRITE: Override flush, align in chiplet to 1
10:12	WO_OR	WO_OR	WO_OR	PERV_CTRL0_10_12_RESERVED: Not used.
13	WO_OR	WO_OR	WO_OR	TP_TCPERV_SBE_CG_DIS: Disable clock gating on SBE
14	WO_OR	WO_OR	WO_OR	TP_TCPERV_VITL_CG_DIS: Disable clock gating on VITAL
15	WO_OR	WO_OR	WO_OR	TP_TCPERV_VITL_FFDLYLCK_DC: Enable FF delay on VITAL
16	WO_OR	WO_OR	WO_OR	TP_VITL_CLKOFF_DC: Disable VITAL clocks if 1
17	WO_OR	WO_OR	WO_OR	PERV_CTRL0_17_RESERVED: Not used.
18	WO_OR	WO_OR	WO_OR	TP_FENCE_EN_DC: Fencing signal for PERV chiplet
19:21	WO_OR	WO_OR	WO_OR	PERV_CTRL0_19_21_RESERVED: Not used.
22	WO_OR	WO_OR	WO_OR	TP_OTP_SCOM_FUSED_CORE_MODE: Enable or disable fused core mode. Only functional if OTP fuses allow it.
23	WO_OR	WO_OR	WO_OR	PERV_CTRL0_23_RESERVED: Not used
24	WO_OR	WO_OR	WO_OR	TCPERV_UNIT_FUNC_CLK_GATE_LCB_TEST_EDIS_DC:
25	WO_OR	WO_OR	WO_OR	TP_FENCE_PCB_DC: PERV chiplet PCB fence: Fences PCB signals coming back from chiplet
26:27	WO_OR	WO_OR	WO_OR	PERV_CTRL0_26_27_RESERVED: Not used.
28	WO_OR	WO_OR	WO_OR	TP_SPI_MVPD0_PROTECT: Disables write access to MVPD SEEPROM
29	WO_OR	WO_OR	WO_OR	PERV_CTRL0_29_RESERVED: Not used.
30	WO_OR	WO_OR	WO_OR	TP_EX_SINGLE_LPAR_EN_DC: Enable single LPAR on EX chiplet
31	WO_OR	WO_OR	WO_OR	PERV_CTRL0_31_SPARE: Not used

SET function of PERV CONTROL 1 register
Addr:	000000000000292B (FSI) 0000000000002CAC (FSI_BYTE) 000000000005012B (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL1_SET
Constant(s):	PERV_PERV_CTRL1_SET
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.PERV_CTRL1_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	WO_OR	WO_OR	WO_OR	PERV_CTRL1_0_RESERVED: Not used
1	WO_OR	WO_OR	WO_OR	TP_CHIPLET_CLK_DCC_BYPASS_EN_DC: Enable DCC bypass
2	WO_OR	WO_OR	WO_OR	TP_CHIPLET_CLK_PDLY_BYPASS_EN_DC: Enable Pdly bypass
3:15	WO_OR	WO_OR	WO_OR	PERV_CTRL1_3_15_RESERVED: Not used
16:19	WO_OR	WO_OR	WO_OR	TP_SEC_BUF_DRV_STRENGTH_DC: Sector buffer strength: 0b0000 = xx% strength 0b1111 = yy% strength
20:31	WO_OR	WO_OR	WO_OR	PERV_CTRL1_20_31_RESERVED: Not used

CLEAR function of ROOT CONTROL 0 register
Addr:	0000000000002930 (FSI) 0000000000002CC0 (FSI_BYTE) 0000000000050130 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL0_CLEAR
Constant(s):	PERV_ROOT_CTRL0_CLEAR
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL0_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	WO_CLEAR	WO_CLEAR	WO_CLEAR	CFAM_PROTECTION_0_DC: CFAM protection 0 for RCS interface
1	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL0_1_SPARE: Not used
2	WO_CLEAR	WO_CLEAR	WO_CLEAR	TPFSI_TPI2C_BUS_FENCE_DC: I2C master bus fence
3:5	WO_CLEAR	WO_CLEAR	WO_CLEAR	TPCFSI_OPB_SW0_FENCE_DC: OPB0 ARBITER (FSI0 side): Fence off arbitration requests from OPB master: bit3 : FSI slave0 bit4 : PIB2OPB Host bit5 : PIB2OPB none-Host
6:7	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL0_6_7_SPARE: Not used.
8	WO_CLEAR	WO_CLEAR	WO_CLEAR	CFAM_PROTECTION_1_DC: CFAM protection 1 for CBS/VITL interface
9	WO_CLEAR	WO_CLEAR	WO_CLEAR	CFAM_PROTECTION_2_DC: CFAM protection 2 for PIB_master/slave interfaces
10	WO_CLEAR	WO_CLEAR	WO_CLEAR	CFAM_PIB_SLV_RESET_DC: Functionally resets all PIB slave instances on CFAM
11	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL0_11_SPARE: Not used.
12	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL0_12_SPARE: Not used.
13	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL0_13_SPARE: Not used.
14	WO_CLEAR	WO_CLEAR	WO_CLEAR	SPARE_FENCE_CONTROL: Not used
15	WO_CLEAR	WO_CLEAR	WO_CLEAR	VDD2VIO_LVL_FENCE_DC: PLL fence enable 0b0 = not fenced 0b1 = fenced
16	WO_CLEAR	WO_CLEAR	WO_CLEAR	FSI2PCB_DC: Directly connects FSI2PIB engine to pervasive chiplet (bypassing PIB and PCB)
17	WO_CLEAR	WO_CLEAR	WO_CLEAR	OOB_MUX: Select OOB (Out of Band) multiplexer
18	WO_CLEAR	WO_CLEAR	WO_CLEAR	PIB2PCB_DC: Directly connects SBE engine to pervasive chiplet (bypassing PCB)
19	WO_CLEAR	WO_CLEAR	WO_CLEAR	PCB2PCB_DC: Connects SBE engine to pervasive chiplet through PIB/PCB
20	WO_CLEAR	WO_CLEAR	WO_CLEAR	FSI_CC_VSB_CBS_REQ: CBS interface: Request signal from FSI to PERV_CC
21:23	WO_CLEAR	WO_CLEAR	WO_CLEAR	FSI_CC_VSB_CBS_CMD: CBS interface: Command from FSI to PERV_CC: 0b000 = NOP - could be used to test if clocks in PERV chiplet are available 0b001 = RESET - reset PERV_CC only to init values 0b010 = SCAN0 - trigger scan0 on all regions 0b011 = CLK START - SBE region will be started 0b100 = CLK STOP - SBE region will be stopped 0b101 = NOP - unused 0b110 = NOP - unused 0b111 = SCAN0 & CLK START - used by CFAM Boot Sequencer (CBS)
24	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL0_24_SPARE_CBS_CONTROL: Not used
25	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL0_25_SPARE_CBS_CONTROL: Not used
26	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL0_26_SPARE_CBS_CONTROL: Not used
27	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL0_27_SPARE_CBS_CONTROL: Not used
28	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL0_28_SPARE_RESET: Not used
29	WO_CLEAR	WO_CLEAR	WO_CLEAR	TPFSI_IO_OCMB_RESET_EN: OCMB Reset Control: 0b0 = Disable OCMB reset 0b1 = Enable OCMB reset
30	WO_CLEAR	WO_CLEAR	WO_CLEAR	PCB_RESET_DC: PERV chiplet PCB interface reset - requires OOB mux to be selected
31	WO_CLEAR	WO_CLEAR	WO_CLEAR	GLOBAL_EP_RESET_DC: Global endpoint reset - asynchonously reset ALL chiplet vital logic except PERV

CLEAR function of ROOT CONTROL 1 register
Addr:	0000000000002931 (FSI) 0000000000002CC4 (FSI_BYTE) 0000000000050131 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL1_CLEAR
Constant(s):	PERV_ROOT_CTRL1_CLEAR
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL1_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:3	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PROBE0_SEL_DC: PROBE0 select
4:7	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PROBE1_SEL_DC: PROBE1 select
8	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PROBE_MESH_SEL_DC: PROBE MESH select
9	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PROBE_DRV_EN_DC: PROBE drive enable
10	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL1_10_SPARE: Not used
11:12	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_FSI_PROBE_SEL_DC: FSI PROBE select
13	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_AN_PROBE_DRVR_MCPRECOMP0_DC: Tune high speed probe I/Os
14	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_AN_PROBE_DRVR_MCPRECOMP1_DC: Tune high speed probe I/Os
15	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_AN_PROBE_DRVR_MCPRECOMP2_DC: Tune high speed probe I/Os
16	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_IDDQ_DC: IDDQ test (leakage)
17	WO_CLEAR	WO_CLEAR	WO_CLEAR	SPARE_RI_CONTROL: Not used
18	WO_CLEAR	WO_CLEAR	WO_CLEAR	SPARE_DI_CONTROL: Not used
19	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_RI_DC_B: Receiver inhibit (RI) of I/O books 0b0 = receiver disabled 0b1 = receiver enabled
20	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_DI1_DC_B: Driver inhibit (DI1) of I/O books: 0b0 = driver1 disabled 0b1 = driver1 enabled
21	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_DI2_DC_B: Driver inhibit (DI2) of I/O books 0b0 = driver2 disabled 0b1 = driver2 enabled
22	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_TPM_DI1_DC_B: Driver inhibit (DI1) of TPM I/O books: 0b0 = TPM driver1 disabled 0b1 = TPM driver1 enabled
23	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL1_23_SPARE_TEST: Not used
24	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_TEST_BURNIN_MODE_DC: Burn-in mode
25	WO_CLEAR	WO_CLEAR	WO_CLEAR	TPFSI_ARRAY_SET_VBL_TO_VDD_DC: Set array voltage block line to VDD
26	WO_CLEAR	WO_CLEAR	WO_CLEAR	TPFSI_TP_GLB_PERST_OVR_DC: Global PERST# override control. At '1', all PCI reset outputs will be forced low (active). Set to '0' to allow PHB control.
27	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL1_27_SPARE:
28	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL1_28_SPARE_TEST_CONTROL: Not used
29	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL1_29_SPARE_TEST_CONTROL: Not used
30	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL1_30_SPARE_TEST_CONTROL: Not used
31	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL1_31_SPARE_TEST_CONTROL: Not used

CLEAR function of ROOT CONTROL 2 register
Addr:	0000000000002932 (FSI) 0000000000002CC8 (FSI_BYTE) 0000000000050132 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL2_CLEAR
Constant(s):	PERV_ROOT_CTRL2_CLEAR
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL2_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL2_0_SPARE: Not used.
1	WO_CLEAR	WO_CLEAR	WO_CLEAR	TPFSI_TP_DBG_PCB_DATA_PAR_DIS_DC: Debug only: PCB data parity disable
2	WO_CLEAR	WO_CLEAR	WO_CLEAR	TPFSI_TP_DBG_PCB_TYPE_PAR_DIS_DC: Debug only: PCB type parity disable
3	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL2_3_SPARE: Not used.
4	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PIB_DISABLE_PARITY_DC: Disable parity check for PIB
5	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PIB_TRACE_MODE_DATA_DC: PIB trace mode 0: traces addresses only 1: additionally trace request and response data - uses more trace entries
6	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PIB_VSB_SBE_TRACE_MODE: SBE trace mode to SBE - forces SBE into a specific trace bus configuration
7	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_TPCPERV_VSB_TRACE_STOP: Trace stop signal to DBG macro.
8:10	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_GPIO_PIB_TIMEOUT: Timeout of PIB arbiter: PIB clock cycles 0b110 = 256 0b100 = 1024 0b010 = 8192 0b000 = 32768 0b--1 = not available (timeout function disabled)
11	WO_CLEAR	WO_CLEAR	WO_CLEAR	SPARE_PIB_CONTROL: Not used
12	WO_CLEAR	WO_CLEAR	WO_CLEAR	TPCFSI_OPB_SW_RESET_DC: Reset of OPB arbiter
13	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL2_13_SPARE_OPB_CONTROL: Not used
14	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL2_14_SPARE_OPB_CONTROL: Not used
15	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL2_15_SPARE_OPB_CONTROL: Not used
16	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL2_16_SPARE: Not used
17	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL2_17_SPARE: Not used.
18	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL2_18_SPARE: Not used
19	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL2_19_SPARE: Not used
20	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL2_20_SPARE: Not used.
21	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL2_21_FREE_USAGE: Not used
22	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL2_22_FREE_USAGE: Not used
23	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL2_23_FREE_USAGE: Not used
24	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL2_24_FREE_USAGE: Not used.
25	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL2_25_FREE_USAGE: Not used.
26	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL2_26_FREE_USAGE: Not used
27	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL2_27_FREE_USAGE: Not used
28	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL2_28_FREE_USAGE: Not used
29	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL2_29_FREE_USAGE: Not used
30	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL2_30_FREE_USAGE: Not used.
31	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL2_31_FREE_USAGE: Not used.

CLEAR function of ROOT CONTROL 3 register
Addr:	0000000000002933 (FSI) 0000000000002CCC (FSI_BYTE) 0000000000050133 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL3_CLEAR
Constant(s):	PERV_ROOT_CTRL3_CLEAR
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL3_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PLLCLKSW1_RESET_DC: PLLCLKSW1 reset
1	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PLLCLKSW1_BYPASS_EN_DC: PLLCLKSW1 bypass
2	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PLLCLKSW1_TEST_EN_DC: PLLCLKSW1 test enable
3	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PLLCLKSW1_ALTREFCLK_SEL_DC: Use alternate refclk for PLLCLKSW1 - 0=OSC0 differential, 1=OSC1 single-ended
4	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PLLCLKSW2_RESET_DC: PLLCLKSW2 reset
5	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PLLCLKSW2_BYPASS_EN_DC: PLLCLKSW2 bypass
6	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PLLCLKSW2_TEST_EN_DC: PLLCLKSW2 test enable
7	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PLLCLKSW2_ALTREFCLK_SEL_DC: Use alternate refclk for PLLCLKSW2 - 0=OSC1 differential, 1=OSC0 single-ended
8	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PLLTODFLT_RESET_DC: TOD filter PLL reset
9	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PLLTODFLT_BYPASS_EN_DC: TOD filter PLL bypass
10	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PLLTODFLT_TEST_EN_DC: TOD filter PLL test enable
11	WO_CLEAR	WO_CLEAR	WO_CLEAR	SPARE_PLLTODFLT: Not used
12	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PLLNESTFLT_RESET_DC: Nest Filter PLL test enable
13	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PLLNESTFLT_BYPASS_EN_DC: Nest Filter PLL bypass
14	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PLLNESTFLT_TEST_EN_DC: Nest Filter PLL test enable
15	WO_CLEAR	WO_CLEAR	WO_CLEAR	SPARE_PLLNESTFLT: Not used
16	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PLLIOFLT_RESET_DC: IO Filter PLL reset
17	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PLLIOFLT_BYPASS_EN_DC: IO Filter PLL bypass
18	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PLLIOFLT_TEST_EN_DC: IO Filter PLL test enable
19	WO_CLEAR	WO_CLEAR	WO_CLEAR	SPARE_PLLIOFLT: Not used
20	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PLLIOSSFLT_RESET_DC: IO Spread Filter PLL reset
21	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PLLIOSSFLT_BYPASS_EN_DC: IO Spread Filter PLL bypass
22	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PLLIOSSFLT_TEST_EN_DC: IO Spread Filter PLL test enable
23	WO_CLEAR	WO_CLEAR	WO_CLEAR	SPARE_PLLIOSSFLT: Not used
24	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PAU_DPLL_RESET_DC: PAU DPLL reset
25	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PAU_DPLL_BYPASS_EN_DC: PAU DPLL bypass
26	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PAU_DPLL_TEST_EN_DC: PAU DPLL test enable
27	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PAU_DPLL_FUNC_CLKSEL_DC: PAU DPLL func clock select
28	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_NEST_DPLL_RESET_DC: NEST DPLL reset
29	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_NEST_DPLL_BYPASS_EN_DC: NEST DPLL bypass
30	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_NEST_DPLL_TEST_EN_DC: NEST DPLL test enable
31	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_NEST_DPLL_FUNC_CLKSEL_DC: NEST DPLL func clock select

CLEAR function of ROOT CONTROL 4 register
Addr:	0000000000002934 (FSI) 0000000000002CD0 (FSI_BYTE) 0000000000050134 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL4_CLEAR
Constant(s):	PERV_ROOT_CTRL4_CLEAR
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL4_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:1	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_AN_REFCLK_CLKMUX0A_CLKIN_SEL_DC: PLLTODFLT input selection: 00: SYS refclock 0 01: RCS async out 1x: RCS sync out
2:3	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_AN_REFCLK_CLKMUX0B_CLKIN_SEL_DC: PLLNESTFLT input selection: 00: SYS refclock 0 01: RCS async out 1x: RCS sync out
4:5	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_AN_REFCLK_CLKMUX0C_CLKIN_SEL_DC: PLLIOFLT input selection: 00: SYS refclock 0 01: RCS async out 1x: RCS sync out
6:7	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_AN_REFCLK_CLKMUX0D_CLKIN_SEL_DC: PLLIOSSFLT input selection: 00: SYS refclock 0 01: RCS async out 1x: RCS sync out
8	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_AN_REFCLK_CLKMUX10_CLKIN_SEL_DC: PAU DPLL input selection: 0: PLLIOSSFLT output 1: PLLIOFLT output
9	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_AN_REFCLK_CLKMUX11_CLKIN_SEL_DC: Nest DPLL input selection: 0: PLLIOSSFLT output 1: PLLIOFLT output
10:11	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_AN_REFCLK_CLKMUX12_CLKIN_SEL_DC: OMI PLL input selection: 00: PLLTODFLT output 01: PLLNESTFLT output 1x: PLLIOFLT output
12:13	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_AN_REFCLK_CLKMUX13_CLKIN_SEL_DC: AXON 133 MHz input selection: 00: PLLTODFLT output 01: PLLNESTFLT output 1x: PLLIOFLT output
14	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_AN_REFCLK_CLKMUX14_CLKIN_SEL_DC: AXON 156 MHz input selection: 0: PLLNESTFLT output 1: PLLIOFLT output
15:16	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_AN_REFCLK_CLKMUX23_CLKIN_SEL_DC: PCI PLL 100MHz input pre-selection (feeds per-chiplet muxes): 00: PLLTODFLT output 01: PLLIOSSFLT output 1x: MUX0D output / PLLIOSSFLT input
17	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_AN_TOD_LPC_MUX_SEL_DC: TOD input clock selection: 0: 32 MHz LPC clock 1: 16 MHz from PLLTODFLT
18	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL4_18_SPARE: Not used
19	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL4_19_SPARE: Not used
20	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_MUX1_CLKIN_SEL_DC: PAU/NEST input selection: 0: MUX10 output 1: TCK
21	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_MUX2A_CLKIN_SEL_DC: PAU input selection: 0: PAU DPLL output 1: MUX1 output
22	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_MUX2B_CLKIN_SEL_DC: Nest input selection 1: 0: PAU DPLL output 1: MUX1 output
23	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_MUX3_CLKIN_SEL_DC: Nest input selection 2: 0: Nest DPLL output 1: MUX2B output
24	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_MUX4A_CLKIN_SEL_DC: Nest/Cache mesh division ratio compared to core: 0: Divide by 2 1: No division
25	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_AN_CLKGLM_NEST_ASYNC_RESET_DC: Hold Nest mesh in reset if 1, enable Nest mesh if 0
26	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_AN_NEST_DIV2_ASYNC_RESET_DC: Reset Nest/Cache 2:1 dividers. Unstaged, so release before enabling Nest/Core/Cache meshes!
27	WO_CLEAR	WO_CLEAR	WO_CLEAR	TPFSI_ALTREFCLK_SEL: Force all chiplet PLLs into altrefclk mode
28	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL4_28_SPARE: Not used.
29	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_PLL_FORCE_OUT_EN_DC: Enable the chip level filter PLL outputs
30	WO_CLEAR	WO_CLEAR	WO_CLEAR	DPLL_FREEZE_DC: Set to 1 to make the Nest and PAU DPLLs ignore changes to their control inputs, e.g. for scanning the DPLL controllers
31	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_AN_MUX3_ASYNC_RESET_DC: Hold Nest/Core/Cache meshes in reset if 1, enable them if 0

CLEAR function of ROOT CONTROL 5 register
Addr:	0000000000002935 (FSI) 0000000000002CD4 (FSI_BYTE) 0000000000050135 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL5_CLEAR
Constant(s):	PERV_ROOT_CTRL5_CLEAR
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL5_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	WO_CLEAR	WO_CLEAR	WO_CLEAR	TPFSI_RCS_RESET_DC: RCS reset
1	WO_CLEAR	WO_CLEAR	WO_CLEAR	TPFSI_RCS_BYPASS_DC: RCS bypass
2	WO_CLEAR	WO_CLEAR	WO_CLEAR	TPFSI_RCS_FORCE_BYPASS_CLKSEL_DC: RCS bypass clock select - 0: osc0, 1: osc1
3	WO_CLEAR	WO_CLEAR	WO_CLEAR	TPFSI_RCS_CLK_TEST_IN_DC: RCS clock test latch input - outputs in SNS1LTH (address 281D)
4	WO_CLEAR	WO_CLEAR	WO_CLEAR	SWO_FORCE_LOW: Used with FORCE_BYPASS_CLKSEL to manually force a switch over to alternate clk for concurrent maintenance
5	WO_CLEAR	WO_CLEAR	WO_CLEAR	BLOCK_SWO: Block error_a/b from switching over to the B/A side
6	WO_CLEAR	WO_CLEAR	WO_CLEAR	CLEAR_CLK_ERROR_A: Clear detected Path A clock error
7	WO_CLEAR	WO_CLEAR	WO_CLEAR	CLEAR_CLK_ERROR_B: Clear detected Path B clock error
8	WO_CLEAR	WO_CLEAR	WO_CLEAR	SEL_DEL: Error detector sample clock delay 0 = 156.25ps, 1 = 312.5ps
9:11	WO_CLEAR	WO_CLEAR	WO_CLEAR	RCS_CONTROL_10_8: RCS spare input CONTROL(10 downto 8)
12:15	WO_CLEAR	WO_CLEAR	WO_CLEAR	FILT: 6B Up/Dwn counter filter depth
16	WO_CLEAR	WO_CLEAR	WO_CLEAR	PFD_PW_SEL: Phase Freq Detector PW_SEL which extends INC/DEC signal widths
17	WO_CLEAR	WO_CLEAR	WO_CLEAR	FORCE_ERROR_HIGH: Force input high to check for stuck low error detect
18	WO_CLEAR	WO_CLEAR	WO_CLEAR	TESTOUT_EN: Enable CMOS output that connects to C4 mux
19:21	WO_CLEAR	WO_CLEAR	WO_CLEAR	TESTOUT_SEL: Select which of REFCLK_P/N or ASYNC_OUT_P/N or Input Clock CMOS output that connects to C4 mux
22	WO_CLEAR	WO_CLEAR	WO_CLEAR	EN_OVERRIDE_A: Enable ripple counter output bits override on the A side
23	WO_CLEAR	WO_CLEAR	WO_CLEAR	EN_OVERRIDE_B: Enable ripple counter output bits override on the B side
24:29	WO_CLEAR	WO_CLEAR	WO_CLEAR	OVRBIT: Ripple counter override output bits
30	WO_CLEAR	WO_CLEAR	WO_CLEAR	EN_REFCLK: Enable REFCLK output
31	WO_CLEAR	WO_CLEAR	WO_CLEAR	EN_ASYNC_OUT: Enable ASYNC_OUT output

CLEAR function of ROOT CONTROL 6 register
Addr:	0000000000002936 (FSI) 0000000000002CD8 (FSI_BYTE) 0000000000050136 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL6_CLEAR
Constant(s):	PERV_ROOT_CTRL6_CLEAR
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL6_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:3	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL6_0_3: Not used
4:5	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_AN_PCI0_RX_REFCLK_TERM: PCI0 refclock receiver termination: 0b00 = 100 Ohm differential termination 0b10 = 50 Ohm to GND 0b01 = no termination 0b11 = no termination Dial enums: HUNDRED_OHM_DIFF=>0b00 FIFTY_OHM_SE=>0b10 NO_TERM=>0b11
6:7	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_AN_PCI1_RX_REFCLK_TERM: PCI1 refclock receiver termination: 0b00 = 100 Ohm differential termination 0b10 = 50 Ohm to GND 0b01 = no termination 0b11 = no termination Dial enums: HUNDRED_OHM_DIFF=>0b00 FIFTY_OHM_SE=>0b10 NO_TERM=>0b11
8	WO_CLEAR	WO_CLEAR	WO_CLEAR	CHKSW_DD1_HW547515_RCS_EVENTLOG: Chickenswitch for RCS eventLog: 0b0 = RCS eventLog logic is full functional and is able to capture up to 4 different states 0b1 = RCS eventLog logic is just able to capture one state (ie. install dd1 issue)
9:15	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL6_9_15: Not used
16:19	WO_CLEAR	WO_CLEAR	WO_CLEAR	DESKEW_SEL_A: Deskew value to align 100MHz REFCLK_A with 6.4GHz clock at shiftreg input
20:23	WO_CLEAR	WO_CLEAR	WO_CLEAR	DESKEW_SEL_B: Deskew value to align 100MHz REFCLK_A with 6.4GHz clock at shiftreg input
24:27	WO_CLEAR	WO_CLEAR	WO_CLEAR	RCS_CONTROL_7_4: RCS spare input CONTROL(7 downto 4)
28	WO_CLEAR	WO_CLEAR	WO_CLEAR	CHKSW_JUMP_FORWARD: RCS spare input CONTROL(3) - Jump forward chicken switch
29:30	WO_CLEAR	WO_CLEAR	WO_CLEAR	SEL_RES_AMP: RCS spare input CONTROL(2 downto 1) - SEL_RES inputs to adjust output amplitude
31	WO_CLEAR	WO_CLEAR	WO_CLEAR	MASK_UNLOCKDET: RCS spare input CONTROL(0) - Mask UNLOCKDET_* outputs

CLEAR function of ROOT CONTROL 7 register
Addr:	0000000000002937 (FSI) 0000000000002CDC (FSI_BYTE) 0000000000050137 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL7_CLEAR
Constant(s):	PERV_ROOT_CTRL7_CLEAR
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL7_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_MEM0_REFCLK_DRVR_EN_DC: MEM0 reference clock driver enable
1	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_MEM1_REFCLK_DRVR_EN_DC: MEM1 reference clock driver enable
2	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_MEM2_REFCLK_DRVR_EN_DC: MEM2 reference clock driver enable
3	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_MEM3_REFCLK_DRVR_EN_DC: MEM3 reference clock driver enable
4	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_MEM4_REFCLK_DRVR_EN_DC: MEM4 reference clock driver enable
5	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_MEM5_REFCLK_DRVR_EN_DC: MEM5 reference clock driver enable
6	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_MEM6_REFCLK_DRVR_EN_DC: MEM6 reference clock driver enable
7	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_MEM7_REFCLK_DRVR_EN_DC: MEM7 reference clock driver enable
8	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_MEM8_REFCLK_DRVR_EN_DC: MEM8 reference clock driver enable
9	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_MEM9_REFCLK_DRVR_EN_DC: MEM9 reference clock driver enable
10	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_MEMA_REFCLK_DRVR_EN_DC: MEMa reference clock driver enable
11	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_MEMB_REFCLK_DRVR_EN_DC: MEMb reference clock driver enable
12	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_MEMC_REFCLK_DRVR_EN_DC: MEMc reference clock driver enable
13	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_MEMD_REFCLK_DRVR_EN_DC: MEMd reference clock driver enable
14	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_MEME_REFCLK_DRVR_EN_DC: MEMe reference clock driver enable
15	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_MEMF_REFCLK_DRVR_EN_DC: MEMf reference clock driver enable
16	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_OP0A_REFCLK_DRVR_EN_DC: OP0a reference clock driver enable
17	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_OP0B_REFCLK_DRVR_EN_DC: OP0b reference clock driver enable
18	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_OP3A_REFCLK_DRVR_EN_DC: OP3a reference clock driver enable
19	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_OP3B_REFCLK_DRVR_EN_DC: OP3b reference clock driver enable
20	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_OP4_REFCLK_DRVR_EN_DC: OP4 reference clock driver enable
21	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_OP5_REFCLK_DRVR_EN_DC: OP5 reference clock driver enable
22	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_OP6_REFCLK_DRVR_EN_DC: OP6 reference clock driver enable
23	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_OP7_REFCLK_DRVR_EN_DC: OP7 reference clock driver enable
24	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_OP_DRVR_2X_CUR_EN_DC: Optical Clock Driver 2x Current Enable
25	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_E0A_DRVR_2X_CUR_EN_DC: PCIE0 A Slot Clock Driver 2x Current Enable
26	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_E0B_DRVR_2X_CUR_EN_DC: PCIE0 B Slot Clock Driver 2x Current Enable
27	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_E0C_DRVR_2X_CUR_EN_DC: PCIE0 C Slot Clock Driver 2x Current Enable
28	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_E1A_DRVR_2X_CUR_EN_DC: PCIE1 A Slot Clock Driver 2x Current Enable
29	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_E1B_DRVR_2X_CUR_EN_DC: PCIE1 B/C Slot Clock Driver 2x Current Enable
30	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_E1C_DRVR_2X_CUR_EN_DC: Global clock driver near-end termination enable
31	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL7_31_SPARE_RESONANT_CLOCKING_CONTROL: Not used

CLEAR function of ROOT CONTROL 8 register
Addr:	0000000000002938 (FSI) 0000000000002CE0 (FSI_BYTE) 0000000000050138 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL8_CLEAR
Constant(s):	PERV_ROOT_CTRL8_CLEAR
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.ROOT_CTRL8_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	WO_CLEAR	WO_CLEAR	WO_CLEAR	TPFSI_SPIMST0_PORT_MUX_SEL_DC: Select SPIM_0 for BOOT0 SEEPROM: 0b0 = select PIB SPIM_0 (default) 0b1 = select FSI SPIM_0
1	WO_CLEAR	WO_CLEAR	WO_CLEAR	TPFSI_SPIMST1_PORT_MUX_SEL_DC: Select SPIM_1 for BOOT1 SEEPROM: 0b0 = select PIB SPIM_1 (default) 0b1 = select FSI SPIM_1
2	WO_CLEAR	WO_CLEAR	WO_CLEAR	TPFSI_SPIMST2_PORT_MUX_SEL_DC: Select SPIM_2 for MVPD/KEYSTORE SEEPROM: 0b0 = select PIB SPIM_2 (default) 0b1 = select FSI SPIM_2
3	WO_CLEAR	WO_CLEAR	WO_CLEAR	TPFSI_SPIMST3_PORT_MUX_SEL_DC: Select SPIM_3 for MEASUREMENT ROM: 0b0 = select PIB SPIM_3 (default) 0b1 = select FSI SPIM_3
4:15	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL8_4_15: Not used
16	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_FSI_FENCE_DC: FSI chiplet fence
17	WO_CLEAR	WO_CLEAR	WO_CLEAR	TCFSI_VITL_FENCE_DC: FSI clock region fence for VITL
18	WO_CLEAR	WO_CLEAR	WO_CLEAR	TCFSI_FSI0_FENCE_DC: FSI clock region fence for FSI0
19	WO_CLEAR	WO_CLEAR	WO_CLEAR	TCFSI_FSI0LL_FENCE_DC: FSI clock region fence for FSI0LL
20	WO_CLEAR	WO_CLEAR	WO_CLEAR	TCFSI_FSI0INV_FENCE_DC: FSI clock region fence for FSI0INV
21	WO_CLEAR	WO_CLEAR	WO_CLEAR	TCFSI_FSI1_FENCE_DC: FSI clock region fence for FSI1
22	WO_CLEAR	WO_CLEAR	WO_CLEAR	TCFSI_FSI1LL_FENCE_DC: FSI clock region fence for FSI1LL
23	WO_CLEAR	WO_CLEAR	WO_CLEAR	TCFSI_FSIA_FENCE_DC: FSI clock region fence for FSIA
24:31	WO_CLEAR	WO_CLEAR	WO_CLEAR	ROOT_CTRL8_24_31: Not used

CLEAR function of PERV CONTROL 0 register
Addr:	000000000000293A (FSI) 0000000000002CE8 (FSI_BYTE) 000000000005013A (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL0_CLEAR
Constant(s):	PERV_PERV_CTRL0_CLEAR
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.PERV_CTRL0_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_TCPERV_CHIPLET_EN_DC: Chiplet enable.
1	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_TCPERV_PCB_EP_RESET_DC: PCB endpoint reset
2	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_AN_CLKGLM_TEST_TCK_ASYNC_RESET: Hold TP_CONST and NEST meshes in reset if 1, enable TP_CONST mesh if 0. See ROOT_CTRL4(25) for NEST meshes.
3:6	WO_CLEAR	WO_CLEAR	WO_CLEAR	PERV_CTRL0_3_6_RESERVED: Not used.
7	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_TCPERV_VITL_SCIN_DC: Scan in for the chiplet VITAL domain
8	WO_CLEAR	WO_CLEAR	WO_CLEAR	PERV_CTRL0_8_RESERVED: Not used.
9	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_TCPERV_FLUSH_ALIGN_OVERWRITE: Override flush, align in chiplet to 1
10:12	WO_CLEAR	WO_CLEAR	WO_CLEAR	PERV_CTRL0_10_12_RESERVED: Not used.
13	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_TCPERV_SBE_CG_DIS: Disable clock gating on SBE
14	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_TCPERV_VITL_CG_DIS: Disable clock gating on VITAL
15	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_TCPERV_VITL_FFDLYLCK_DC: Enable FF delay on VITAL
16	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_VITL_CLKOFF_DC: Disable VITAL clocks if 1
17	WO_CLEAR	WO_CLEAR	WO_CLEAR	PERV_CTRL0_17_RESERVED: Not used.
18	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_FENCE_EN_DC: Fencing signal for PERV chiplet
19:21	WO_CLEAR	WO_CLEAR	WO_CLEAR	PERV_CTRL0_19_21_RESERVED: Not used.
22	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_OTP_SCOM_FUSED_CORE_MODE: Enable or disable fused core mode. Only functional if OTP fuses allow it.
23	WO_CLEAR	WO_CLEAR	WO_CLEAR	PERV_CTRL0_23_RESERVED: Not used
24	WO_CLEAR	WO_CLEAR	WO_CLEAR	TCPERV_UNIT_FUNC_CLK_GATE_LCB_TEST_EDIS_DC:
25	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_FENCE_PCB_DC: PERV chiplet PCB fence: Fences PCB signals coming back from chiplet
26:27	WO_CLEAR	WO_CLEAR	WO_CLEAR	PERV_CTRL0_26_27_RESERVED: Not used.
28	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_SPI_MVPD0_PROTECT: Disables write access to MVPD SEEPROM
29	WO_CLEAR	WO_CLEAR	WO_CLEAR	PERV_CTRL0_29_RESERVED: Not used.
30	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_EX_SINGLE_LPAR_EN_DC: Enable single LPAR on EX chiplet
31	WO_CLEAR	WO_CLEAR	WO_CLEAR	PERV_CTRL0_31_SPARE: Not used

CLEAR function of PERV CONTROL 1 register
Addr:	000000000000293B (FSI) 0000000000002CEC (FSI_BYTE) 000000000005013B (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL1_CLEAR
Constant(s):	PERV_PERV_CTRL1_CLEAR
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.PERV_CTRL1_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0	WO_CLEAR	WO_CLEAR	WO_CLEAR	PERV_CTRL1_0_RESERVED: Not used
1	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_CHIPLET_CLK_DCC_BYPASS_EN_DC: Enable DCC bypass
2	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_CHIPLET_CLK_PDLY_BYPASS_EN_DC: Enable Pdly bypass
3:15	WO_CLEAR	WO_CLEAR	WO_CLEAR	PERV_CTRL1_3_15_RESERVED: Not used
16:19	WO_CLEAR	WO_CLEAR	WO_CLEAR	TP_SEC_BUF_DRV_STRENGTH_DC: Sector buffer strength: 0b0000 = xx% strength 0b1111 = yy% strength
20:31	WO_CLEAR	WO_CLEAR	WO_CLEAR	PERV_CTRL1_20_31_RESERVED: Not used

RCS Eventlog_0 Register
Addr:	0000000000002940 (FSI) 0000000000002D00 (FSI_BYTE) 0000000000050140 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.RCS_EL0
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.RCS_EVENTLOG0_LATCH_INST.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:16	ROX	ROX	ROX	RCS_EVENTLOG_0_SNS: 4th captured event: Captured value of RCS Sense bits 0 to 17 Writing arbitrary data to this register clears all four event log registers and sensitizes logic for automatic event capturing. Reading from it retrieves the 4th captured event.
17:20	ROX	ROX	ROX	RCS_EVENTLOG_0_ERR: 4th captured event: Captured value of RCS Error bits before 4th event
21:31	ROX	ROX	ROX	RCS_EVENTLOG_0_TIME: 4th captured event: Elapsed time since the 1st captured event, in FSI clock cycles. An all-1 value indicates overflow.

RCS Eventlog_1 Register
Addr:	0000000000002941 (FSI) 0000000000002D04 (FSI_BYTE) 0000000000050141 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.RCS_EL1
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.RCS_EVENTLOG1_LATCH_INST.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:16	ROX	ROX	ROX	RCS_EVENTLOG_1_SNS: 3rd captured event: Captured value of RCS Sense bits 0 to 17 before 3rd event
17:20	ROX	ROX	ROX	RCS_EVENTLOG_1_ERR: 3rd captured event: Captured value of RCS Error bits before 3rd event
21:31	ROX	ROX	ROX	RCS_EVENTLOG_1_TIME: 3rd captured event: Elapsed time since the 1st captured event, in FSI clock cycles. An all-1 value indicates overflow.

RCS Eventlog_2 Register
Addr:	0000000000002942 (FSI) 0000000000002D08 (FSI_BYTE) 0000000000050142 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.RCS_EL2
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.RCS_EVENTLOG2_LATCH_INST.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:16	ROX	ROX	ROX	RCS_EVENTLOG_2_SNS: 2nd captured event: Captured value of RCS Sense bits 0 to 17 before 2nd event
17:20	ROX	ROX	ROX	RCS_EVENTLOG_2_ERR: 2nd captured event: Captured value of RCS Error bits before 2nd event
21:31	ROX	ROX	ROX	RCS_EVENTLOG_2_TIME: 2nd captured event: Elapsed time since the 1st captured event, in FSI clock cycles. An all-1 value indicates overflow.

RCS Eventlog_3 Register
Addr:	0000000000002943 (FSI) 0000000000002D0C (FSI_BYTE) 0000000000050143 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.RCS_EL3
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.RCS_EVENTLOG3_LATCH_INST.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:16	ROX	ROX	ROX	RCS_EVENTLOG_3_SNS: 1st captured event: Captured value of RCS Sense bits 0 to 17 before 1st event
17:20	ROX	ROX	ROX	RCS_EVENTLOG_3_ERR: 1st captured event: Captured value of RCS Error bits before 1st event
21:31	ROX	ROX	ROX	RCS_EVENTLOG_3_TIME: 1st captured event: Elapsed time since the 1st captured event, in FSI clock cycles. Probably zero ;)

scratch register number 9
Addr:	0000000000002980 (FSI) 0000000000002E00 (FSI_BYTE) 0000000000050180 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_9
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.SCR9_INST.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	RWX	SR_SCRATCH_REGISTER_9: Scratch 9 register

scratch register number 10
Addr:	0000000000002981 (FSI) 0000000000002E04 (FSI_BYTE) 0000000000050181 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_10
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.SCR10_INST.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	RWX	SR_SCRATCH_REGISTER_10: Scratch 10 register

scratch register number 11
Addr:	0000000000002982 (FSI) 0000000000002E08 (FSI_BYTE) 0000000000050182 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_11
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.SCR11_INST.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	RWX	SR_SCRATCH_REGISTER_11: Scratch 11 register

scratch register number 12
Addr:	0000000000002983 (FSI) 0000000000002E0C (FSI_BYTE) 0000000000050183 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_12
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.SCR12_INST.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	RWX	SR_SCRATCH_REGISTER_12: Scratch 12 register

scratch register number 13
Addr:	0000000000002984 (FSI) 0000000000002E10 (FSI_BYTE) 0000000000050184 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_13
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.SCR13_INST.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	RWX	SR_SCRATCH_REGISTER_13: Scratch 13 register

scratch register number 14
Addr:	0000000000002985 (FSI) 0000000000002E14 (FSI_BYTE) 0000000000050185 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_14
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.SCR14_INST.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	RWX	SR_SCRATCH_REGISTER_14: Scratch 14 register

scratch register number 15
Addr:	0000000000002986 (FSI) 0000000000002E18 (FSI_BYTE) 0000000000050186 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_15
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.SCR15_INST.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	RWX	SR_SCRATCH_REGISTER_15: Scratch 15 register

scratch register number 16
Addr:	0000000000002987 (FSI) 0000000000002E1C (FSI_BYTE) 0000000000050187 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_16
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.SCR16_INST.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSI	FSI_BYTE	SCOM	Dial: Description
0:31	RWX	RWX	RWX	SR_SCRATCH_REGISTER_16: Scratch 16 register

COMMAND REGISTER FAST MODE
Addr:	0000000000010000 (SCOM)
Name:	TP.TPCHIP.PIB.OTP.OTPC_M.COMMAND_REGISTER
Constant(s):	PU_COMMAND_REGISTER
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.OTP_CMD_REG_LT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			CMD_REG_BIT_WITHSTART: To initiate operation, Don't care for OTP ROM Controller
1	RW			CMD_REG_BIT_WITHADDR: To initiate operation, Don't care for OTP ROM Controller
2	RW			CMD_REG_BIT_READCONT: To initiate operation, Don't care for OTP ROM Controller
3	RW			CMD_REG_BIT_WITHSTOP: To initiate operation, Don't care for OTP ROM Controller
4:7	RW			CMD_REG_LENGTH: Length of real data excluding register address.Permitted values are only 4 and 8. 4- Requesting for four bytes of read data 8- Requesting for eight bytes of read data.Maximum_read = 8, Only permitted value
8:14	RW			UNUSED_8_14: reserved, not used
15	RW			CMD_REG_BIT_RNW: To enable read, program '1'. '0' is invalid option
16:22	RW			UNUSED_16_22: reserved not used
23:25	RW			REG_ADDR_LEN:  000= Address increment if Address field is '0' 001= 1 Byte of CMD_REG_ADDR is Valid 010= 2 Bytes of CMD_REG_ADDR are Valid 011= 3 Bytes of CMD_REG_ADDR are Valid 111= 4 Bytes of CMD_REG_ADDR are Valid
26:31	RW			UNUSED_26_31: reserved, not used
32:39	RW			CMD_REG_ADDR_1: Address to read from, First Byte
40:47	RW			CMD_REG_ADDR_2: Address to read from, Second Byte
48:55	RW			CMD_REG_ADDR_3: Address to read from, Third Byte
56:63	RW			CMD_REG_ADDR_4: Address to read from, Fourth Byte

RESET REGISTER
Addr:	0000000000010001 (SCOM)
Name:	TP.TPCHIP.PIB.OTP.OTPC_M.RESET_REGISTER
Constant(s):	PU_RESET_REGISTER
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.OTP_RESET_REG_LT_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	WO			CHICKEN_SWITCH: To enable/disable AR012 PIB error reporting enhancemnt feature, 0 - enable 1- disable

STATUS REGISTER
Addr:	0000000000010002 (SCOM)
Name:	TP.TPCHIP.PIB.OTP.OTPC_M.STATUS_REGISTER
Constant(s):	PU_STATUS_REGISTER
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:37	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.OTP_STATUS_REG_LT_INST.LATC.L2(0:37) [00000000000000000000000000000000000000]
	39:63	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.OTP_STATUS_REG_LT_INST.LATC.L2(38:62) [0000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	ROX			STATUS_ADDR_NVLD: Address invalid
1	ROX			STATUS_WRITE_NVLD: Write invalid
2	ROX			STATUS_READ_NVLD: Read invalid
3	ROX			STATUS_INVLD_CMD_ERR: Invalid command register fields programmed
4	ROX			STATUS_CORR_ERR: ECC Correctable error
5	ROX			STATUS_UNCORR_ERROR: ECC Uncorrectable error
6:37	ROX			STATUS_DATA_REG_0_31: First 4 bytes of read Data Register (0 to 31)
38	RO			constant=0b0
39:43	ROX			STATUS_UNUSED_39_43: Unused
44	ROX			STATUS_CTRL_BUSY: OTP ROM Controller Busy
45	ROX			STATUS_DCOMP_ERR: Decompression Engine Error
46	ROX			STATUS_INVLD_PRGM_ERR: Invalid Program Operation error
47:51	ROX			STATUS_UNUSED_47_51: Unused
52	ROX			STATUS_COMMAND_COMPLETE: Operation Complete - Fast Mode Read Operation/Programming Operation
53	ROX			STATUS_UNUSED_53: Unused
54	ROX			STATUS_RDWR_OP_BUSY: RdWr Op Controller Logic Busy
55	ROX			STATUS_DCOMP_ENGINE_BUSY: Decompression Engine Busy
56:63	ROX			STATUS_RD_DATA_COUNT: Valid Read Data Count - 0x08 For OTP ROM

DATA REGISTER for Fast Mode Read data
Addr:	0000000000010003 (SCOM)
Name:	TP.TPCHIP.PIB.OTP.OTPC_M.DATA_REGISTER
Constant(s):	PU_DATA_REGISTER
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.OTP_DATA_REG_LT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	ROX			OTP_DATA_REGISTER: Fast Mode Read Data

Security Switch Register - For Secure boot features
Addr:	0000000000010005 (SCOM) 0000000000010006 (SCOM1)
Name:	TP.TPCHIP.PIB.OTP.OTPC_M.SECURITY_SWITCH_REGISTER
Constant(s):	PU_SECURITY_SWITCH_REGISTER
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:28	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.SEC_ENA.INT_DOUT_INST.LATC.L2(0:28) [00000000000000000000000000000]
Bit(s)	SCOM	SCOM1		Dial: Description
0	RO	RO		SECURITY_SWITCH_SECURE_ACCESS: Indicates status of secure access bit from FSI Mailbox.Used by the CFAM to disable the FSI2PIB (SCOM) and SHIFT (SCAN & DMA) engines. Also used to disable the CFAM I2CM access to the SBE SEEPROMs and emulated JTAG access path to OCC PowerPC.
1	RW_WOR	WO_CLEAR		SECURITY_SWITCH_LATE_LAUNCH_PRIMARY: Late launch Primary security - To check which chip is initiating DRTM late launch seq
2	RW_WOR	WO_CLEAR		SECURITY_SWITCH_LATE_LAUNCH_SECONDARY: Late lauch secondary security - To check which chip is initiating DRTM late lauch seq
3	RW_WOR	WO_CLEAR		SECURITY_SWITCH_LOCAL_QUIESCE_ACHIEVED: Local quiesce achieved - To check whether chip has been successfully quiesced.RESET by local SBE/HFW during DRTM late launch code.
4	RW_WOR	NCX		SECURITY_SWITCH_SEEPROM_UPDATE_LOCK: Prevent write access to SEEPROM and prevent reset of SAB in FSI mailbox by PIB(Sticky!)
5	RW_WOR	WO_CLEAR		SECURITY_SWITCH_LOCALITY_4_ACCESS: Used by PIB SPIM to gate all write access to TPMD.Set by the local SBE as soon as all chips in system have been evaluated as quiesced.
6	RO	RO		SECURITY_SWITCH_SECURE_DEBUG: Indicates Secure chip debug mode- From FSI Mailbox.Used by FSI2PIB engine to enable FSP SCOM access to the SBE. And used by SBE to switch PPE into debug mode which restricts PPE capabilities to read-out internal register space only.
7	RW_WOR	WO_CLEAR		SECURITY_SWITCH_SPARE0: Spare
8	RW_WOR	NCX		SECURITY_SWITCH_ABUS_SECURITY_LOCK: Consumed by ABUS logic(PB) and protects maillbox access(Sticky!).
9	RW_WOR	NCX		SECURITY_SWITCH_NX_RAND_NUM_GEN_LOCK: Consumed by NX random generator lock(Sticky!)
10	RW_WOR	WO_CLEAR		SECURITY_SWITCH_PROT_EX_SPARE0: Spare going to EX
11	RW_WOR	WO_CLEAR		SECURITY_SWITCH_PROT_EX_SPARE1: Spare going to EX
12	RW_WOR	WO_CLEAR		SECURITY_SWITCH_SPIMST_TPM_DECONFIG_PROTECT: Security switch to control access to all 5 write I2C device IDs of the TPM
13	RW_WOR	WO_CLEAR		SECURITY_SWITCH_I2CM_SECURE_OCMB_LOCK: Provides secure write access to OCMB chips via PIB I2CM Engine E
14	RW_WOR	WO_CLEAR		SECURITY_SWITCH_PROT_TP_SPARE0: TP Spare
15	RW_WOR	WO_CLEAR		SECURITY_SWITCH_PROT_TP_SPARE1: TP Spare
16	RW_WOR	NCX		SECURITY_SWITCH_SPIM_SECURE_KEY_LOCK0_WRITE_PROTECT: Provides secure write access to Measurement SEEPROM's(Sticky!)
17	RW_WOR	NCX		SECURITY_SWITCH_SPIM_SECURE_KEY_LOCK0_READ_PROTECT: Provides secure read access to Measurement SEEPROM's(Sticky!)
18	RW_WOR	NCX		SECURITY_SWITCH_SPIM_SECURE_KEY_LOCK1_WRITE_PROTECT: Provides secure write access to Measurement SEEPROM's(Sticky!)
19	RW_WOR	NCX		SECURITY_SWITCH_SPIM_SECURE_KEY_LOCK1_READ_PROTECT: Provides secure read access to Measurement SEEPROM's(Sticky!)
20	RW_WOR	NCX		SECURITY_SWITCH_SPIM_SECURE_KEY_LOCK2_WRITE_PROTECT: Provides secure write access to Measurement SEEPROM's(Sticky!)
21	RW_WOR	NCX		SECURITY_SWITCH_SPIM_SECURE_KEY_LOCK2_READ_PROTECT: Provides secure read access to Measurement SEEPROM's(Sticky!)
22	RW_WOR	NCX		SECURITY_SWITCH_SPIM_SECURE_KEY_LOCK3_WRITE_PROTECT: Provides secure write access to Measurement SEEPROM's(Sticky!)
23	RW_WOR	NCX		SECURITY_SWITCH_SPIM_SECURE_KEY_LOCK3_READ_PROTECT: Provides secure read access to Measurement SEEPROM's(Sticky!)
24	RW_WOR	NCX		SECURITY_SWITCH_SPIM_SECURE_KEY_LOCK4_WRITE_PROTECT: Provides secure write access to Measurement SEEPROM's(Sticky!)
25	RW_WOR	NCX		SECURITY_SWITCH_SPIM_SECURE_KEY_LOCK4_READ_PROTECT: Provides secure read access to Measurement SEEPROM's(Sticky!)
26	RW_WOR	NCX		SECURITY_SWITCH_SPIM_SECURE_KEY_LOCK_SPARE0_PROTECT: Provides secure write access to Measurement SEEPROM's(Sticky!)
27	RW_WOR	NCX		SECURITY_SWITCH_SPIM_SECURE_KEY_LOCK_SPARE1_PROTECT: Provides secure read access to Measurement SEEPROM's(Sticky!)
28	RW_WOR	NCX		SECURITY_SWITCH_MC_MEMORY_ENCRYPTION_LOCK: Memory Encryption lock signal to MC unit(Sticky!)

Mode Register to Enable features - Decomp Engine Enable, ECC Checking, Programming Enable
Addr:	0000000000010008 (SCOM)
Name:	TP.TPCHIP.PIB.OTP.OTPC_M.MODE_REGISTER
Constant(s):	PU_MODE_REGISTER
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.OTP_MODE_REG_LT_0_INST.LATC.L2(0:3) [0000]
	4:31	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.OTP_MODE_REG_LT_4_INST.LATC.L2(4:31) [0000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			MODE_DCOMP_ENABLE: To Enable Decompression Engine, Default value is '0'
1	RW			MODE_ECC_ENABLE: Enable ECC checking(Only for read operation). Default value ='1' if ECC_Enable generic set to '1' else '0'.Note that if it set to '1', it assumes ECC is stored in OTPROMs and follows ECC enabled addressing. For debug purposes, set this bit to '0' to dump the all locations contents of OTPROM(s).
2	RW			MODE_UNUSED_2: Enable Unused
3	RW			MODE_ECC_CHK_DISABLE: Set to '1' disables only ECC check. Set to '0' enables ECC check. Default value is '0'.(Note that this bit is valid only when bit_1 in this register set to'1' and ECC_ENABLE generic set to true).
4:31	RW			MODE_UNUSED_4_31: Unused

Export regulation control register
Addr:	0000000000010009 (SCOM)
Name:	TP.TPCHIP.PIB.OTP.OTPC_M.EXPORT_REGL_STATUS
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:20	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.EXP_REG_STATUS_LT_INST.LATC.L2(0:20) [000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RO			EXPORT_STATUS_TP_NX_ALLOW_CRYPTO_DC: presents tp_x_allow_crypto_dc value
1	RO			EXPORT_STATUS_TP_EX_FUSE_VMX_CRYPTO_DIS_DC: presents tp_ex_fuse_vmx_crypto_dis_dc value
2	RO			EXPORT_STATUS_TP_EX_EFUSE_EXTENDED_MEMORY_DISABLE_DC: presents tp_ex_fuse_fp_throttle_en_dc value
3	RO			EXPORT_STATUS_TP_PB_FUSE_TOPOLOGY_2CHIP: presents tp_pb_fuse_topology value
4:5	RO			EXPORT_STATUS_TP_PB_FUSE_TOPOLOGY_GROUP: presents tp_pb_fuse_topology_group value
6	RO			EXPORT_STATUS_TP_NP_NVLINK_DISABLE: presents tp_nvlink_disable_dc value
7	RO			EXPORT_STATUS_OTP_PCBMS_HW_MODE_SEL_DC: presents otp_pcbms_hw_mode_sel_dc value
8	RO			EXPORT_STATUS_OTP_PCBMS_FUSED_CORE_MODE_SEL0_DC: presents otp_pcbms_fused_core_mode_sel0_dc value
9	RO			EXPORT_STATUS_OTP_PCBMS_FUSED_CORE_MODE_SEL1_DC: presents otp_pcbms_fused_core_mode_sel1_dc value
10	RO			EXPORT_STATUS_TP_EX_FUSE_SMT8_CTYPE_EN_DC: presents tp_ex_fuse_smt8_ctype_dc value
11	RO			EXPORT_STATUS_TP_MC_ALLOW_CRYPTO_DC: presents tp_mc_allow_crypto_dc value
12	RO			EXPORT_STATUS_OTP_SPIM_MEAS_SEEPROM_LOCK_DC: presents otp_psim_meas_seeprom_lock value
13:18	RO			EXPORT_STATUS_TP_PAU_POWER_HEADER_DISABLE_DC: presents tp_pau_power_header_disable_dc value
19:20	RO			EXPORT_STATUS_TP_EX_FUSE_FLOP_THROTTLE_EN_DC: presents tp_ex_fuse_flop_throttle_en_dc value

Export regulation control register
Addr:	000000000001000E (SCOM)
Name:	TP.TPCHIP.PIB.OTP.OTPC_M.EXPORT_REGL_CTRL
Constant(s):	PU_EXPORT_REGL_CTRL
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:19	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.OTP_EXPORT_REGULATION_CTRL_REG_LT_INST.LATC.L2(0:19) [00000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			EXPORT_CTRL_TP_NX_ALLOW_CRYPTO_DC: Set to -'1', replicates the behavior of fuses are blown for tp_nx_allow_cyrpto_dc irrespective fuse content.Set to '0', Allows the fuse to control the fuse bit.Init value - '1'
1	RW			EXPORT_CTRL_TP_EX_FUSE_VMX_CRYPTO_DIS_DC: Set to -'1', replicates the behavior of fuses are blown for tp_ex_fuse_mvx_crypto_dis_dc irrespective fuse content.Set to '0' Export regulation content based on the fuse content.Init value - '0'
2	RW			EXPORT_CTRL_TP_EX_EFUSE_EXTENDED_MEMORY_DISABLE_DC: Set to -'1', replicates the behavior of fuses are blown for tp_ex_fuse_fp_throttle_en_dc irrespective fuse content.Set to '0',--> Export regulation output is based on fuse content.Init value- '0'
3	RW			EXPORT_CTRL_TP_PB_FUSE_TOPOLOGY_2CHIP: To apply limits on chip topology without fuse burnt.Set to -'1', replicates the behavior of fuses are blown for tp_pb_fuse_topology_2chip irrespective fuse content. Set to '0', export regulation output are based on fuse content. Init value - '0'
4:5	RW			EXPORT_CTRL_TP_PB_FUSE_TOPOLOGY_GROUP: To apply limits on chip topology without fuse burnt.Set to '1' replicates the behavior of fuses are blown for tp_pb_fuse_topology_group(0:1) irrespective fuse content. Set to '0',Export regulation output is based on fuse content.
6	RW			EXPORT_CTRL_TP_NP_NVLINK_DISABLE: Set to '1' replicates the behavior fuses are blown for tp_np_nvlink_disable export regulation output. Set to '0' � Export regulation output is based on fuse content.
7	RW			EXPORT_CTRL_OTP_PCBMS_HW_MODE_SEL_DC: SCOM overwrite is dependednt on tp_ex_fuse_scom_overwrite_disable_dc export regulation bit. if tp_ex_fuse_scom_overwrite_disable_dc is '1', scom overwrite through export regulation reg(7) is disabled else setting this bit will replicates the behabior fuses are blown for otp_pcbms_hw_mode_sel_dc export regulation output. When otp_pcbms_hw_mode_sel_dc is set, the fused_core_mode_sel(0:1) controls smt8_ctype_en else controlled by perv_ctrl0 reg bit 23
8	RW			EXPORT_CTRL_OTP_PCBMS_FUSED_CORE_MODE_SEL0_DC: SCOM overwrite is dependednt on tp_ex_fuse_scom_overwrite_disable_dc export regulation bit. if tp_ex_fuse_scom_overwrite_disable_dc is '1', scom overwrite through export regulation reg(8) is disabled else setting this bit will replicates the behabior fuses are blown for otp_pcbms_fused_core_mode_sel0_dc export regulation output.When otp_pcbms_hw_mode_sel_dc is set, the fused_core_mode_sel(0:1) controls smt8_ctype_en
9	RW			EXPORT_CTRL_OTP_PCBMS_FUSED_CORE_MODE_SEL1_DC: SCOM overwrite is dependednt on tp_ex_fuse_scom_overwrite_disable_dc export regulation bit. if tp_ex_fuse_scom_overwrite_disable_dc is '1', scom overwrite through export regulation reg(9) is disabled else setting this bit will replicates the behabior fuses are blown for otp_pcbms_fused_core_mode_sel1_dc export regulation output.When otp_pcbms_hw_mode_sel_dc is set, the fused_core_mode_sel(0:1) controls smt8_ctype_en
10	RW			EXPORT_CTRL_TP_MC_ALLOW_CRYPTO_DC: Set to -'1', replicates the behavior of fuses are blown for tp_mc_allow_cyrpto_dc irrespective fuse content.Set to '0', Allows the fuse to control the fuse bit.Init value - '1'
11	RW			EXPORT_CTRL_OTP_SPIM_MEAS_SEEPROM_LOCK_DC: Set to -'1', replicates the behavior of fuses are blown for otp_spim_meas_seeprom_lock_dc irrespective fuse content.Set to '0', Allows the fuse to control the fuse bit.Init value - '0'
12:17	RW			EXPORT_CTRL_TP_PAU_POWER_HEADER_DISABLE_DC: Set to -'1', replicates the behavior of fuses are blown for tp_pau_power_header_disable irrespective fuse content.Set to '0', Allows the fuse to control the fuse bit.Init value - '111111'
18:19	RW			EXPORT_CTRL_TP_EX_FUSE_FLOP_THROTTLE_EN_DC: Set to -'1', replicates the behavior of fuses are blown for tp_ex_fuse_flop_throttle_en_dc irrespective fuse content.Set to '0', Allows the fuse to control the fuse bit.Init value - '00'

SBE Measurement reg0
Addr:	0000000000010010 (SCOM)
Name:	TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG0
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.MEAS_REGS_GENERATE#0.MEAS_REGS.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			SEEPROM_MEASUREMENT0_DATA: Data from Measurement SEEPROM

SBE Measurement reg1
Addr:	0000000000010011 (SCOM)
Name:	TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG1
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.MEAS_REGS_GENERATE#1.MEAS_REGS.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			SEEPROM_MEASUREMENT1_DATA: Data from Measurement SEEPROM

SBE Measurement reg2
Addr:	0000000000010012 (SCOM)
Name:	TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG2
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.MEAS_REGS_GENERATE#2.MEAS_REGS.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			SEEPROM_MEASUREMENT2_DATA: Data from Measurement SEEPROM

SBE Measurement reg3
Addr:	0000000000010013 (SCOM)
Name:	TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG3
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.MEAS_REGS_GENERATE#3.MEAS_REGS.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			SEEPROM_MEASUREMENT3_DATA: Data from Measurement SEEPROM

SBE Measurement reg4
Addr:	0000000000010014 (SCOM)
Name:	TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG4
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.MEAS_REGS_GENERATE#4.MEAS_REGS.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			SEEPROM_MEASUREMENT4_DATA: Data from Measurement SEEPROM

SBE Measurement reg5
Addr:	0000000000010015 (SCOM)
Name:	TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG5
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.MEAS_REGS_GENERATE#5.MEAS_REGS.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			SEEPROM_MEASUREMENT5_DATA: Data from Measurement SEEPROM

SBE Measurement reg6
Addr:	0000000000010016 (SCOM)
Name:	TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG6
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.MEAS_REGS_GENERATE#6.MEAS_REGS.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			SEEPROM_MEASUREMENT6_DATA: Data from Measurement SEEPROM

SBE Measurement reg7
Addr:	0000000000010017 (SCOM)
Name:	TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG7
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.MEAS_REGS_GENERATE#7.MEAS_REGS.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			SEEPROM_MEASUREMENT7_DATA: Data from Measurement SEEPROM

SBE Measurement reg8
Addr:	0000000000010018 (SCOM)
Name:	TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG8
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.MEAS_REGS_GENERATE#8.MEAS_REGS.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			SEEPROM_MEASUREMENT8_DATA: Data from Measurement SEEPROM

SBE Measurement reg9
Addr:	0000000000010019 (SCOM)
Name:	TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG9
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.MEAS_REGS_GENERATE#9.MEAS_REGS.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			SEEPROM_MEASUREMENT9_DATA: Data from Measurement SEEPROM

SBE Measurement reg10
Addr:	000000000001001A (SCOM)
Name:	TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG10
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.MEAS_REGS_GENERATE#10.MEAS_REGS.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			SEEPROM_MEASUREMENT10_DATA: Data from Measurement SEEPROM

SBE Measurement reg11
Addr:	000000000001001B (SCOM)
Name:	TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG11
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.MEAS_REGS_GENERATE#11.MEAS_REGS.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			SEEPROM_MEASUREMENT11_DATA: Data from Measurement SEEPROM

SBE Measurement reg12
Addr:	000000000001001C (SCOM)
Name:	TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG12
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.MEAS_REGS_GENERATE#12.MEAS_REGS.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			SEEPROM_MEASUREMENT12_DATA: Data from Measurement SEEPROM

SBE Measurement reg13
Addr:	000000000001001D (SCOM)
Name:	TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG13
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.MEAS_REGS_GENERATE#13.MEAS_REGS.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			SEEPROM_MEASUREMENT13_DATA: Data from Measurement SEEPROM

SBE Measurement reg14
Addr:	000000000001001E (SCOM)
Name:	TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG14
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.MEAS_REGS_GENERATE#14.MEAS_REGS.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			SEEPROM_MEASUREMENT14_DATA: Data from Measurement SEEPROM

SBE Measurement reg15
Addr:	000000000001001F (SCOM)
Name:	TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG15
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.MEAS_REGS_GENERATE#15.MEAS_REGS.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			SEEPROM_MEASUREMENT15_DATA: Data from Measurement SEEPROM

i2cm configuration register for engine B
Addr:	0000000000010020 (SCOM)
Name:	TP.TPCHIP.PIB.OTP.OTPC_M.I2CM_SLVID_CONFIG_REG_B
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.SEC_ENA.OCMB_SEC_REG_ENGB_LT_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:17	RW			PORT_PROTECTION_B: Protected Port vector for engine B
18:24	RW			SLV_ID_B: Protected slave id for engine B
25:31	RW			MASK_ID_B: Mask ID for engine B

i2cm configuration register for engine C
Addr:	0000000000010021 (SCOM)
Name:	TP.TPCHIP.PIB.OTP.OTPC_M.I2CM_SLVID_CONFIG_REG_C
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.SEC_ENA.OCMB_SEC_REG_ENGC_LT_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:17	RW			PORT_PROTECTION_C: Protected Port vector for engine C
18:24	RW			SLV_ID_C: Protected slave id for engine C
25:31	RW			MASK_ID_C: Mask ID for engine C

i2cm configuration register for engine E
Addr:	0000000000010022 (SCOM)
Name:	TP.TPCHIP.PIB.OTP.OTPC_M.I2CM_SLVID_CONFIG_REG_E
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.OTP.OTPC_M.OTPC_C.ADDR_HANDLER.SEC_ENA.OCMB_SEC_REG_ENGE_LT_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:17	RW			PORT_PROTECTION_E: Protected Port vector for engine E
18:24	RW			SLV_ID_E: Protected slave id for engine E
25:31	RW			MASK_ID_E: Mask ID for engine E

OTPROM REG 0
Addr:	0000000000018000 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG0
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(63) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(62) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(61) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(60) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(59) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(58) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(57) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(56) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(55) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(54) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(53) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(52) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(51) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(50) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(49) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(48) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(47) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(46) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(45) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(44) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(43) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(42) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(41) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(40) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(39) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(38) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(37) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(36) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(35) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(34) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(33) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(32) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(31) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(30) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(29) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(28) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(27) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(26) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(25) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(24) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(23) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(22) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(21) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(20) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(19) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(18) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(17) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(16) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(15) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(14) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(13) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(12) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(11) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(10) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(9) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1:0) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER0: ROM location 0

OTPROM REG 1
Addr:	0000000000018001 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG1
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(127) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(126) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(125) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(124) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(123) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(122) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(121) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(120) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(119) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(118) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(117) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(116) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(115) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(114) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(113) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(112) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(111) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(110) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(109) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(108) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(107) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(106) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(105) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(104) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(103) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(102) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(101) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(100) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(99) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(98) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(97) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(96) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(95) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(94) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(93) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(92) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(91) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(90) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(89) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(88) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(87) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(86) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(85) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(84) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(83) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(82) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(81) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(80) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(79) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(78) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(77) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(76) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(75) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(74) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(73) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(72) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(71) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(70) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(69) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(68) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(67) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(66) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(65:66) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER1: ROM location 1

OTPROM REG 2
Addr:	0000000000018002 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG2
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(191) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(190) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(189) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(188) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(187) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(186) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(185) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(184) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(183) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(182) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(181) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(180) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(179) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(178) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(177) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(176) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(175) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(174) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(173) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(172) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(171) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(170) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(169) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(168) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(167) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(166) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(165) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(164) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(163) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(162) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(161) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(160) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(159) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(158) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(157) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(156) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(155) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(154) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(153) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(152) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(151) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(150) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(149) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(148) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(147) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(146) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(145) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(144) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(143) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(142) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(141) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(140) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(139) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(138) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(137) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(136) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(135) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(134) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(133) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(132) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(131) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(130) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(129:130) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER2: ROM location 2

OTPROM REG 3
Addr:	0000000000018003 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG3
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(255) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(254) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(253) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(252) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(251) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(250) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(249) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(248) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(247) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(246) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(245) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(244) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(243) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(242) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(241) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(240) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(239) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(238) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(237) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(236) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(235) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(234) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(233) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(232) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(231) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(230) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(229) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(228) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(227) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(226) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(225) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(224) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(223) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(222) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(221) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(220) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(219) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(218) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(217) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(216) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(215) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(214) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(213) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(212) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(211) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(210) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(209) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(208) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(207) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(206) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(205) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(204) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(203) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(202) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(201) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(200) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(199) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(198) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(197) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(196) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(195) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(194) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(193:194) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER3: ROM location 3

OTPROM REG 4
Addr:	0000000000018004 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG4
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(319) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(318) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(317) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(316) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(315) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(314) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(313) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(312) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(311) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(310) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(309) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(308) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(307) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(306) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(305) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(304) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(303) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(302) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(301) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(300) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(299) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(298) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(297) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(296) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(295) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(294) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(293) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(292) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(291) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(290) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(289) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(288) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(287) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(286) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(285) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(284) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(283) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(282) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(281) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(280) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(279) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(278) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(277) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(276) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(275) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(274) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(273) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(272) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(271) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(270) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(269) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(268) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(267) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(266) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(265) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(264) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(263) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(262) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(261) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(260) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(259) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(258) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(257:258) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER4: ROM location 4

OTPROM REG 5
Addr:	0000000000018005 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG5
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(383) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(382) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(381) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(380) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(379) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(378) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(377) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(376) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(375) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(374) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(373) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(372) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(371) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(370) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(369) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(368) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(367) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(366) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(365) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(364) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(363) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(362) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(361) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(360) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(359) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(358) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(357) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(356) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(355) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(354) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(353) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(352) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(351) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(350) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(349) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(348) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(347) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(346) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(345) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(344) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(343) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(342) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(341) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(340) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(339) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(338) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(337) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(336) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(335) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(334) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(333) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(332) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(331) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(330) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(329) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(328) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(327) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(326) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(325) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(324) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(323) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(322) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(321:322) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER5: ROM location 5

OTPROM REG 6
Addr:	0000000000018006 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG6
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(447) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(446) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(445) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(444) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(443) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(442) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(441) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(440) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(439) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(438) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(437) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(436) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(435) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(434) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(433) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(432) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(431) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(430) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(429) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(428) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(427) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(426) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(425) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(424) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(423) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(422) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(421) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(420) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(419) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(418) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(417) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(416) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(415) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(414) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(413) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(412) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(411) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(410) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(409) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(408) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(407) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(406) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(405) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(404) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(403) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(402) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(401) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(400) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(399) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(398) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(397) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(396) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(395) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(394) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(393) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(392) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(391) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(390) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(389) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(388) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(387) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(386) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(385:386) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER6: ROM location 6

OTPROM REG 7
Addr:	0000000000018007 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG7
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(511) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(510) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(509) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(508) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(507) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(506) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(505) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(504) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(503) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(502) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(501) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(500) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(499) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(498) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(497) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(496) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(495) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(494) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(493) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(492) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(491) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(490) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(489) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(488) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(487) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(486) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(485) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(484) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(483) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(482) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(481) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(480) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(479) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(478) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(477) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(476) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(475) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(474) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(473) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(472) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(471) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(470) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(469) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(468) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(467) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(466) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(465) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(464) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(463) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(462) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(461) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(460) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(459) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(458) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(457) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(456) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(455) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(454) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(453) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(452) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(451) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(450) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(449:450) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER7: ROM location 7

OTPROM REG 8
Addr:	0000000000018008 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG8
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(575) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(574) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(573) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(572) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(571) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(570) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(569) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(568) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(567) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(566) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(565) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(564) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(563) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(562) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(561) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(560) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(559) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(558) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(557) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(556) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(555) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(554) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(553) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(552) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(551) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(550) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(549) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(548) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(547) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(546) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(545) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(544) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(543) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(542) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(541) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(540) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(539) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(538) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(537) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(536) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(535) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(534) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(533) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(532) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(531) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(530) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(529) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(528) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(527) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(526) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(525) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(524) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(523) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(522) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(521) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(520) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(519) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(518) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(517) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(516) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(515) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(514) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(513:514) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER8: ROM location 8

OTPROM REG 9
Addr:	0000000000018009 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG9
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(639) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(638) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(637) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(636) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(635) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(634) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(633) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(632) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(631) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(630) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(629) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(628) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(627) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(626) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(625) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(624) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(623) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(622) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(621) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(620) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(619) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(618) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(617) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(616) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(615) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(614) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(613) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(612) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(611) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(610) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(609) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(608) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(607) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(606) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(605) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(604) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(603) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(602) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(601) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(600) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(599) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(598) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(597) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(596) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(595) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(594) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(593) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(592) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(591) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(590) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(589) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(588) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(587) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(586) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(585) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(584) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(583) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(582) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(581) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(580) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(579) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(578) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(577:578) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER9: ROM location 9

OTPROM REG 10
Addr:	000000000001800A (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG10
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(703) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(702) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(701) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(700) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(699) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(698) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(697) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(696) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(695) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(694) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(693) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(692) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(691) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(690) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(689) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(688) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(687) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(686) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(685) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(684) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(683) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(682) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(681) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(680) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(679) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(678) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(677) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(676) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(675) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(674) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(673) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(672) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(671) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(670) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(669) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(668) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(667) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(666) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(665) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(664) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(663) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(662) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(661) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(660) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(659) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(658) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(657) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(656) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(655) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(654) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(653) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(652) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(651) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(650) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(649) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(648) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(647) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(646) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(645) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(644) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(643) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(642) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(641:642) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER10: ROM location 10

OTPROM REG 11
Addr:	000000000001800B (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG11
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(767) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(766) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(765) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(764) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(763) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(762) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(761) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(760) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(759) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(758) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(757) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(756) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(755) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(754) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(753) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(752) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(751) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(750) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(749) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(748) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(747) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(746) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(745) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(744) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(743) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(742) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(741) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(740) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(739) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(738) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(737) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(736) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(735) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(734) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(733) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(732) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(731) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(730) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(729) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(728) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(727) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(726) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(725) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(724) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(723) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(722) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(721) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(720) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(719) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(718) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(717) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(716) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(715) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(714) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(713) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(712) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(711) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(710) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(709) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(708) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(707) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(706) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(705:706) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER11: ROM location 11

OTPROM REG 12
Addr:	000000000001800C (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG12
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(831) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(830) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(829) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(828) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(827) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(826) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(825) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(824) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(823) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(822) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(821) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(820) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(819) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(818) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(817) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(816) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(815) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(814) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(813) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(812) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(811) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(810) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(809) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(808) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(807) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(806) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(805) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(804) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(803) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(802) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(801) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(800) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(799) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(798) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(797) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(796) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(795) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(794) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(793) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(792) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(791) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(790) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(789) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(788) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(787) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(786) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(785) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(784) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(783) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(782) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(781) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(780) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(779) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(778) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(777) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(776) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(775) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(774) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(773) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(772) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(771) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(770) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(769:770) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER12: ROM location 12

OTPROM REG 13
Addr:	000000000001800D (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG13
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(895) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(894) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(893) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(892) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(891) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(890) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(889) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(888) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(887) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(886) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(885) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(884) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(883) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(882) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(881) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(880) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(879) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(878) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(877) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(876) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(875) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(874) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(873) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(872) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(871) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(870) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(869) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(868) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(867) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(866) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(865) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(864) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(863) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(862) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(861) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(860) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(859) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(858) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(857) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(856) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(855) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(854) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(853) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(852) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(851) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(850) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(849) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(848) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(847) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(846) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(845) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(844) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(843) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(842) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(841) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(840) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(839) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(838) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(837) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(836) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(835) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(834) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(833:834) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER13: ROM location 13

OTPROM REG 14
Addr:	000000000001800E (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG14
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(959) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(958) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(957) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(956) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(955) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(954) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(953) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(952) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(951) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(950) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(949) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(948) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(947) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(946) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(945) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(944) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(943) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(942) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(941) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(940) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(939) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(938) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(937) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(936) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(935) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(934) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(933) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(932) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(931) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(930) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(929) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(928) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(927) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(926) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(925) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(924) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(923) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(922) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(921) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(920) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(919) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(918) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(917) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(916) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(915) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(914) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(913) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(912) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(911) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(910) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(909) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(908) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(907) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(906) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(905) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(904) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(903) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(902) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(901) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(900) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(899) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(898) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(897:898) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER14: ROM location 14

OTPROM REG 15
Addr:	000000000001800F (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG15
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1023) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1022) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1021) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1020) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1019) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1018) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1017) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1016) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1015) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1014) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1013) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1012) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1011) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1010) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1009) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1008) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1007) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1006) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1005) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1004) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1003) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1002) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1001) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1000) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(999) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(998) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(997) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(996) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(995) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(994) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(993) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(992) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(991) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(990) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(989) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(988) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(987) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(986) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(985) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(984) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(983) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(982) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(981) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(980) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(979) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(978) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(977) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(976) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(975) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(974) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(973) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(972) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(971) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(970) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(969) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(968) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(967) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(966) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(965) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(964) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(963) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(962) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(961:962) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER15: ROM location 15

OTPROM REG 16
Addr:	0000000000018010 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG16
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1087) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1086) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1085) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1084) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1083) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1082) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1081) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1080) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1079) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1078) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1077) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1076) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1075) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1074) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1073) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1072) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1071) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1070) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1069) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1068) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1067) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1066) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1065) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1064) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1063) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1062) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1061) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1060) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1059) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1058) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1057) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1056) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1055) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1054) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1053) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1052) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1051) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1050) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1049) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1048) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1047) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1046) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1045) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1044) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1043) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1042) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1041) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1040) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1039) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1038) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1037) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1036) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1035) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1034) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1033) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1032) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1031) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1030) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1029) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1028) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1027) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1026) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1025:1026) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER16: ROM location 16

OTPROM REG 17
Addr:	0000000000018011 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG17
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1151) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1150) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1149) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1148) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1147) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1146) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1145) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1144) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1143) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1142) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1141) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1140) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1139) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1138) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1137) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1136) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1135) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1134) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1133) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1132) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1131) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1130) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1129) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1128) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1127) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1126) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1125) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1124) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1123) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1122) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1121) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1120) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1119) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1118) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1117) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1116) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1115) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1114) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1113) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1112) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1111) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1110) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1109) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1108) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1107) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1106) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1105) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1104) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1103) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1102) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1101) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1100) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1099) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1098) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1097) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1096) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1095) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1094) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1093) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1092) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1091) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1090) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1089:1090) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER17: ROM location 17

OTPROM REG 18
Addr:	0000000000018012 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG18
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1215) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1214) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1213) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1212) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1211) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1210) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1209) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1208) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1207) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1206) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1205) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1204) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1203) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1202) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1201) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1200) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1199) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1198) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1197) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1196) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1195) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1194) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1193) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1192) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1191) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1190) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1189) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1188) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1187) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1186) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1185) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1184) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1183) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1182) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1181) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1180) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1179) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1178) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1177) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1176) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1175) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1174) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1173) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1172) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1171) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1170) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1169) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1168) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1167) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1166) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1165) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1164) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1163) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1162) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1161) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1160) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1159) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1158) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1157) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1156) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1155) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1154) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1153:1154) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER18: ROM location 18

OTPROM REG 19
Addr:	0000000000018013 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG19
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1279) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1278) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1277) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1276) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1275) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1274) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1273) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1272) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1271) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1270) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1269) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1268) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1267) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1266) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1265) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1264) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1263) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1262) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1261) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1260) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1259) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1258) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1257) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1256) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1255) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1254) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1253) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1252) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1251) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1250) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1249) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1248) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1247) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1246) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1245) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1244) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1243) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1242) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1241) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1240) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1239) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1238) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1237) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1236) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1235) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1234) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1233) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1232) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1231) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1230) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1229) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1228) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1227) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1226) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1225) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1224) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1223) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1222) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1221) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1220) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1219) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1218) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1217:1218) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER19: ROM location 19

OTPROM REG 20
Addr:	0000000000018014 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG20
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1343) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1342) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1341) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1340) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1339) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1338) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1337) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1336) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1335) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1334) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1333) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1332) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1331) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1330) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1329) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1328) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1327) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1326) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1325) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1324) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1323) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1322) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1321) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1320) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1319) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1318) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1317) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1316) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1315) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1314) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1313) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1312) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1311) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1310) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1309) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1308) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1307) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1306) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1305) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1304) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1303) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1302) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1301) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1300) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1299) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1298) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1297) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1296) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1295) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1294) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1293) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1292) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1291) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1290) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1289) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1288) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1287) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1286) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1285) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1284) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1283) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1282) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1281:1282) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER20: ROM location 20

OTPROM REG 21
Addr:	0000000000018015 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG21
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1407) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1406) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1405) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1404) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1403) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1402) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1401) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1400) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1399) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1398) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1397) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1396) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1395) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1394) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1393) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1392) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1391) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1390) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1389) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1388) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1387) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1386) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1385) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1384) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1383) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1382) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1381) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1380) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1379) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1378) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1377) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1376) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1375) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1374) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1373) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1372) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1371) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1370) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1369) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1368) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1367) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1366) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1365) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1364) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1363) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1362) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1361) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1360) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1359) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1358) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1357) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1356) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1355) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1354) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1353) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1352) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1351) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1350) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1349) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1348) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1347) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1346) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1345:1346) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER21: ROM location 21

OTPROM REG 22
Addr:	0000000000018016 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG22
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1471) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1470) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1469) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1468) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1467) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1466) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1465) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1464) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1463) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1462) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1461) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1460) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1459) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1458) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1457) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1456) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1455) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1454) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1453) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1452) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1451) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1450) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1449) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1448) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1447) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1446) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1445) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1444) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1443) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1442) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1441) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1440) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1439) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1438) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1437) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1436) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1435) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1434) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1433) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1432) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1431) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1430) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1429) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1428) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1427) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1426) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1425) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1424) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1423) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1422) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1421) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1420) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1419) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1418) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1417) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1416) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1415) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1414) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1413) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1412) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1411) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1410) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1409:1410) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER22: ROM location 22

OTPROM REG 23
Addr:	0000000000018017 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG23
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1535) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1534) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1533) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1532) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1531) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1530) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1529) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1528) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1527) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1526) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1525) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1524) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1523) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1522) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1521) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1520) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1519) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1518) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1517) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1516) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1515) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1514) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1513) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1512) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1511) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1510) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1509) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1508) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1507) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1506) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1505) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1504) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1503) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1502) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1501) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1500) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1499) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1498) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1497) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1496) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1495) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1494) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1493) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1492) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1491) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1490) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1489) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1488) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1487) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1486) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1485) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1484) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1483) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1482) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1481) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1480) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1479) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1478) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1477) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1476) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1475) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1474) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1473:1474) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER23: ROM location 23

OTPROM REG 24
Addr:	0000000000018018 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG24
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1599) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1598) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1597) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1596) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1595) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1594) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1593) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1592) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1591) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1590) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1589) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1588) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1587) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1586) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1585) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1584) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1583) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1582) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1581) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1580) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1579) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1578) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1577) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1576) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1575) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1574) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1573) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1572) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1571) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1570) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1569) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1568) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1567) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1566) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1565) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1564) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1563) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1562) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1561) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1560) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1559) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1558) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1557) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1556) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1555) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1554) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1553) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1552) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1551) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1550) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1549) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1548) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1547) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1546) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1545) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1544) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1543) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1542) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1541) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1540) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1539) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1538) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1537:1538) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER24: ROM location 24

OTPROM REG 25
Addr:	0000000000018019 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG25
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1663) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1662) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1661) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1660) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1659) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1658) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1657) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1656) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1655) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1654) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1653) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1652) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1651) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1650) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1649) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1648) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1647) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1646) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1645) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1644) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1643) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1642) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1641) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1640) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1639) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1638) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1637) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1636) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1635) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1634) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1633) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1632) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1631) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1630) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1629) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1628) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1627) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1626) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1625) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1624) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1623) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1622) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1621) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1620) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1619) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1618) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1617) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1616) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1615) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1614) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1613) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1612) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1611) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1610) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1609) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1608) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1607) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1606) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1605) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1604) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1603) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1602) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1601:1602) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER25: ROM location 25

OTPROM REG 26
Addr:	000000000001801A (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG26
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1727) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1726) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1725) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1724) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1723) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1722) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1721) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1720) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1719) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1718) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1717) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1716) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1715) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1714) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1713) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1712) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1711) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1710) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1709) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1708) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1707) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1706) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1705) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1704) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1703) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1702) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1701) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1700) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1699) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1698) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1697) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1696) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1695) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1694) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1693) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1692) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1691) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1690) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1689) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1688) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1687) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1686) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1685) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1684) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1683) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1682) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1681) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1680) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1679) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1678) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1677) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1676) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1675) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1674) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1673) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1672) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1671) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1670) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1669) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1668) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1667) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1666) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1665:1666) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER26: ROM location 26

OTPROM REG 27
Addr:	000000000001801B (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG27
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1791) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1790) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1789) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1788) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1787) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1786) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1785) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1784) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1783) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1782) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1781) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1780) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1779) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1778) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1777) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1776) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1775) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1774) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1773) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1772) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1771) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1770) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1769) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1768) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1767) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1766) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1765) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1764) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1763) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1762) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1761) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1760) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1759) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1758) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1757) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1756) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1755) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1754) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1753) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1752) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1751) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1750) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1749) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1748) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1747) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1746) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1745) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1744) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1743) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1742) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1741) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1740) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1739) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1738) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1737) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1736) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1735) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1734) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1733) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1732) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1731) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1730) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1729:1730) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER27: ROM location 27

OTPROM REG 28
Addr:	000000000001801C (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG28
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1855) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1854) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1853) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1852) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1851) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1850) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1849) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1848) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1847) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1846) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1845) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1844) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1843) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1842) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1841) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1840) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1839) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1838) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1837) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1836) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1835) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1834) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1833) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1832) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1831) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1830) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1829) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1828) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1827) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1826) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1825) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1824) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1823) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1822) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1821) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1820) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1819) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1818) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1817) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1816) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1815) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1814) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1813) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1812) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1811) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1810) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1809) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1808) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1807) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1806) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1805) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1804) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1803) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1802) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1801) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1800) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1799) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1798) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1797) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1796) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1795) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1794) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1793:1794) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER28: ROM location 28

OTPROM REG 29
Addr:	000000000001801D (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG29
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1919) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1918) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1917) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1916) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1915) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1914) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1913) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1912) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1911) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1910) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1909) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1908) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1907) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1906) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1905) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1904) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1903) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1902) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1901) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1900) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1899) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1898) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1897) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1896) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1895) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1894) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1893) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1892) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1891) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1890) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1889) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1888) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1887) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1886) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1885) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1884) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1883) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1882) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1881) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1880) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1879) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1878) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1877) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1876) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1875) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1874) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1873) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1872) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1871) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1870) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1869) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1868) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1867) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1866) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1865) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1864) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1863) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1862) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1861) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1860) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1859) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1858) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1857:1858) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER29: ROM location 29

OTPROM REG 30
Addr:	000000000001801E (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG30
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1983) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1982) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1981) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1980) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1979) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1978) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1977) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1976) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1975) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1974) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1973) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1972) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1971) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1970) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1969) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1968) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1967) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1966) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1965) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1964) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1963) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1962) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1961) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1960) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1959) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1958) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1957) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1956) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1955) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1954) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1953) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1952) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1951) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1950) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1949) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1948) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1947) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1946) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1945) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1944) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1943) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1942) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1941) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1940) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1939) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1938) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1937) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1936) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1935) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1934) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1933) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1932) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1931) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1930) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1929) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1928) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1927) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1926) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1925) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1924) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1923) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1922) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1921:1922) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER30: ROM location 30

OTPROM REG 31
Addr:	000000000001801F (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG31
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2047) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2046) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2045) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2044) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2043) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2042) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2041) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2040) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2039) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2038) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2037) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2036) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2035) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2034) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2033) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2032) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2031) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2030) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2029) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2028) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2027) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2026) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2025) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2024) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2023) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2022) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2021) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2020) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2019) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2018) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2017) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2016) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2015) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2014) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2013) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2012) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2011) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2010) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2009) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2008) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2007) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2006) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2005) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2004) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2003) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2002) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2001) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2000) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1999) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1998) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1997) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1996) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1995) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1994) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1993) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1992) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1991) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1990) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1989) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1988) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1987) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1986) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(1985:1986) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER31: ROM location 31

OTPROM REG 32
Addr:	0000000000018020 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG32
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2111) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2110) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2109) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2108) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2107) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2106) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2105) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2104) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2103) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2102) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2101) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2100) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2099) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2098) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2097) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2096) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2095) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2094) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2093) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2092) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2091) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2090) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2089) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2088) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2087) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2086) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2085) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2084) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2083) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2082) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2081) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2080) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2079) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2078) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2077) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2076) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2075) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2074) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2073) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2072) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2071) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2070) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2069) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2068) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2067) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2066) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2065) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2064) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2063) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2062) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2061) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2060) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2059) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2058) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2057) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2056) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2055) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2054) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2053) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2052) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2051) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2050) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2049:2050) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER32: ROM location 32

OTPROM REG 33
Addr:	0000000000018021 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG33
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2175) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2174) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2173) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2172) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2171) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2170) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2169) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2168) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2167) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2166) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2165) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2164) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2163) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2162) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2161) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2160) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2159) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2158) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2157) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2156) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2155) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2154) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2153) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2152) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2151) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2150) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2149) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2148) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2147) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2146) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2145) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2144) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2143) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2142) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2141) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2140) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2139) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2138) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2137) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2136) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2135) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2134) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2133) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2132) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2131) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2130) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2129) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2128) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2127) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2126) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2125) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2124) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2123) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2122) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2121) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2120) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2119) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2118) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2117) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2116) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2115) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2114) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2113:2114) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER33: ROM location 33

OTPROM REG 34
Addr:	0000000000018022 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG34
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2239) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2238) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2237) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2236) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2235) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2234) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2233) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2232) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2231) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2230) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2229) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2228) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2227) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2226) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2225) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2224) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2223) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2222) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2221) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2220) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2219) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2218) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2217) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2216) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2215) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2214) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2213) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2212) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2211) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2210) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2209) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2208) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2207) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2206) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2205) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2204) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2203) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2202) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2201) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2200) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2199) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2198) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2197) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2196) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2195) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2194) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2193) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2192) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2191) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2190) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2189) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2188) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2187) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2186) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2185) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2184) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2183) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2182) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2181) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2180) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2179) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2178) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2177:2178) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER34: ROM location 34

OTPROM REG 35
Addr:	0000000000018023 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG35
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2303) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2302) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2301) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2300) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2299) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2298) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2297) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2296) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2295) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2294) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2293) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2292) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2291) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2290) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2289) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2288) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2287) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2286) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2285) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2284) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2283) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2282) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2281) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2280) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2279) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2278) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2277) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2276) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2275) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2274) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2273) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2272) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2271) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2270) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2269) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2268) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2267) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2266) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2265) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2264) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2263) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2262) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2261) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2260) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2259) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2258) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2257) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2256) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2255) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2254) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2253) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2252) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2251) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2250) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2249) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2248) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2247) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2246) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2245) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2244) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2243) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2242) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2241:2242) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER35: ROM location 35

OTPROM REG 36
Addr:	0000000000018024 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG36
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2367) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2366) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2365) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2364) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2363) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2362) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2361) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2360) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2359) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2358) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2357) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2356) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2355) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2354) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2353) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2352) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2351) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2350) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2349) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2348) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2347) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2346) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2345) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2344) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2343) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2342) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2341) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2340) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2339) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2338) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2337) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2336) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2335) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2334) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2333) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2332) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2331) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2330) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2329) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2328) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2327) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2326) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2325) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2324) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2323) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2322) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2321) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2320) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2319) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2318) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2317) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2316) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2315) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2314) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2313) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2312) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2311) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2310) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2309) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2308) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2307) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2306) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2305:2306) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER36: ROM location 36

OTPROM REG 37
Addr:	0000000000018025 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG37
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2431) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2430) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2429) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2428) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2427) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2426) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2425) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2424) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2423) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2422) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2421) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2420) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2419) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2418) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2417) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2416) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2415) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2414) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2413) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2412) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2411) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2410) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2409) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2408) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2407) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2406) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2405) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2404) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2403) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2402) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2401) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2400) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2399) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2398) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2397) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2396) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2395) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2394) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2393) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2392) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2391) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2390) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2389) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2388) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2387) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2386) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2385) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2384) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2383) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2382) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2381) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2380) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2379) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2378) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2377) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2376) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2375) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2374) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2373) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2372) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2371) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2370) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2369:2370) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER37: ROM location 37

OTPROM REG 38
Addr:	0000000000018026 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG38
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2495) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2494) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2493) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2492) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2491) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2490) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2489) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2488) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2487) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2486) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2485) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2484) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2483) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2482) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2481) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2480) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2479) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2478) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2477) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2476) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2475) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2474) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2473) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2472) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2471) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2470) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2469) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2468) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2467) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2466) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2465) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2464) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2463) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2462) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2461) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2460) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2459) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2458) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2457) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2456) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2455) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2454) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2453) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2452) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2451) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2450) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2449) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2448) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2447) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2446) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2445) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2444) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2443) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2442) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2441) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2440) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2439) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2438) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2437) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2436) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2435) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2434) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2433:2434) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER38: ROM location 38

OTPROM REG 39
Addr:	0000000000018027 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG39
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2559) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2558) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2557) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2556) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2555) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2554) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2553) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2552) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2551) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2550) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2549) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2548) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2547) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2546) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2545) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2544) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2543) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2542) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2541) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2540) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2539) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2538) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2537) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2536) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2535) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2534) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2533) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2532) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2531) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2530) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2529) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2528) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2527) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2526) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2525) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2524) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2523) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2522) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2521) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2520) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2519) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2518) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2517) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2516) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2515) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2514) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2513) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2512) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2511) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2510) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2509) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2508) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2507) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2506) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2505) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2504) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2503) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2502) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2501) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2500) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2499) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2498) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2497:2498) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER39: ROM location 39

OTPROM REG 40
Addr:	0000000000018028 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG40
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2623) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2622) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2621) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2620) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2619) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2618) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2617) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2616) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2615) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2614) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2613) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2612) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2611) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2610) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2609) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2608) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2607) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2606) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2605) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2604) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2603) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2602) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2601) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2600) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2599) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2598) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2597) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2596) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2595) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2594) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2593) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2592) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2591) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2590) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2589) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2588) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2587) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2586) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2585) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2584) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2583) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2582) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2581) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2580) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2579) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2578) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2577) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2576) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2575) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2574) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2573) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2572) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2571) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2570) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2569) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2568) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2567) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2566) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2565) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2564) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2563) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2562) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2561:2562) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER40: ROM location 40

OTPROM REG 41
Addr:	0000000000018029 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG41
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2687) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2686) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2685) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2684) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2683) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2682) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2681) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2680) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2679) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2678) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2677) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2676) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2675) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2674) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2673) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2672) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2671) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2670) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2669) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2668) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2667) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2666) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2665) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2664) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2663) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2662) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2661) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2660) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2659) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2658) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2657) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2656) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2655) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2654) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2653) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2652) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2651) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2650) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2649) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2648) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2647) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2646) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2645) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2644) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2643) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2642) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2641) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2640) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2639) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2638) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2637) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2636) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2635) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2634) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2633) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2632) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2631) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2630) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2629) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2628) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2627) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2626) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2625:2626) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER41: ROM location 41

OTPROM REG 42
Addr:	000000000001802A (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG42
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2751) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2750) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2749) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2748) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2747) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2746) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2745) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2744) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2743) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2742) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2741) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2740) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2739) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2738) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2737) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2736) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2735) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2734) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2733) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2732) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2731) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2730) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2729) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2728) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2727) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2726) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2725) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2724) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2723) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2722) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2721) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2720) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2719) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2718) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2717) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2716) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2715) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2714) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2713) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2712) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2711) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2710) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2709) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2708) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2707) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2706) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2705) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2704) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2703) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2702) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2701) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2700) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2699) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2698) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2697) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2696) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2695) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2694) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2693) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2692) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2691) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2690) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2689:2690) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER42: ROM location 42

OTPROM REG 43
Addr:	000000000001802B (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG43
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2815) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2814) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2813) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2812) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2811) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2810) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2809) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2808) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2807) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2806) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2805) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2804) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2803) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2802) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2801) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2800) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2799) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2798) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2797) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2796) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2795) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2794) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2793) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2792) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2791) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2790) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2789) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2788) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2787) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2786) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2785) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2784) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2783) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2782) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2781) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2780) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2779) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2778) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2777) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2776) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2775) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2774) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2773) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2772) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2771) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2770) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2769) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2768) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2767) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2766) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2765) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2764) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2763) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2762) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2761) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2760) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2759) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2758) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2757) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2756) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2755) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2754) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2753:2754) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER43: ROM location 43

OTPROM REG 44
Addr:	000000000001802C (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG44
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2879) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2878) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2877) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2876) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2875) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2874) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2873) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2872) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2871) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2870) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2869) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2868) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2867) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2866) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2865) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2864) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2863) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2862) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2861) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2860) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2859) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2858) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2857) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2856) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2855) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2854) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2853) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2852) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2851) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2850) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2849) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2848) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2847) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2846) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2845) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2844) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2843) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2842) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2841) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2840) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2839) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2838) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2837) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2836) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2835) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2834) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2833) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2832) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2831) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2830) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2829) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2828) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2827) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2826) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2825) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2824) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2823) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2822) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2821) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2820) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2819) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2818) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2817:2818) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER44: ROM location 44

OTPROM REG 45
Addr:	000000000001802D (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG45
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2943) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2942) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2941) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2940) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2939) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2938) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2937) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2936) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2935) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2934) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2933) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2932) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2931) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2930) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2929) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2928) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2927) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2926) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2925) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2924) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2923) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2922) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2921) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2920) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2919) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2918) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2917) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2916) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2915) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2914) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2913) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2912) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2911) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2910) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2909) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2908) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2907) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2906) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2905) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2904) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2903) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2902) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2901) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2900) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2899) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2898) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2897) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2896) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2895) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2894) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2893) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2892) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2891) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2890) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2889) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2888) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2887) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2886) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2885) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2884) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2883) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2882) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2881:2882) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER45: ROM location 45

OTPROM REG 46
Addr:	000000000001802E (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG46
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3007) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3006) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3005) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3004) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3003) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3002) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3001) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3000) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2999) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2998) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2997) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2996) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2995) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2994) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2993) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2992) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2991) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2990) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2989) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2988) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2987) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2986) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2985) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2984) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2983) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2982) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2981) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2980) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2979) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2978) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2977) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2976) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2975) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2974) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2973) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2972) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2971) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2970) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2969) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2968) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2967) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2966) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2965) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2964) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2963) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2962) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2961) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2960) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2959) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2958) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2957) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2956) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2955) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2954) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2953) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2952) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2951) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2950) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2949) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2948) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2947) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2946) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(2945:2946) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER46: ROM location 46

OTPROM REG 47
Addr:	000000000001802F (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG47
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3071) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3070) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3069) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3068) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3067) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3066) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3065) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3064) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3063) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3062) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3061) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3060) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3059) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3058) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3057) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3056) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3055) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3054) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3053) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3052) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3051) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3050) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3049) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3048) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3047) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3046) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3045) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3044) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3043) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3042) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3041) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3040) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3039) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3038) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3037) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3036) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3035) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3034) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3033) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3032) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3031) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3030) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3029) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3028) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3027) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3026) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3025) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3024) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3023) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3022) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3021) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3020) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3019) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3018) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3017) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3016) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3015) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3014) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3013) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3012) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3011) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3010) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3009:3010) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER47: ROM location 47

OTPROM REG 48
Addr:	0000000000018030 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG48
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3135) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3134) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3133) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3132) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3131) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3130) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3129) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3128) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3127) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3126) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3125) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3124) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3123) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3122) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3121) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3120) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3119) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3118) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3117) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3116) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3115) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3114) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3113) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3112) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3111) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3110) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3109) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3108) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3107) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3106) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3105) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3104) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3103) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3102) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3101) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3100) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3099) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3098) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3097) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3096) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3095) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3094) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3093) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3092) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3091) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3090) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3089) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3088) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3087) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3086) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3085) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3084) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3083) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3082) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3081) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3080) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3079) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3078) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3077) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3076) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3075) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3074) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3073:3074) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER48: ROM location 48

OTPROM REG 49
Addr:	0000000000018031 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG49
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3199) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3198) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3197) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3196) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3195) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3194) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3193) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3192) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3191) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3190) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3189) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3188) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3187) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3186) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3185) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3184) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3183) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3182) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3181) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3180) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3179) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3178) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3177) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3176) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3175) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3174) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3173) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3172) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3171) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3170) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3169) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3168) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3167) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3166) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3165) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3164) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3163) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3162) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3161) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3160) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3159) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3158) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3157) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3156) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3155) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3154) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3153) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3152) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3151) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3150) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3149) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3148) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3147) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3146) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3145) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3144) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3143) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3142) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3141) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3140) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3139) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3138) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3137:3138) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER49: ROM location 49

OTPROM REG 50
Addr:	0000000000018032 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG50
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3263) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3262) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3261) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3260) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3259) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3258) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3257) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3256) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3255) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3254) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3253) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3252) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3251) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3250) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3249) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3248) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3247) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3246) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3245) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3244) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3243) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3242) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3241) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3240) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3239) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3238) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3237) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3236) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3235) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3234) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3233) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3232) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3231) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3230) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3229) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3228) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3227) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3226) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3225) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3224) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3223) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3222) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3221) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3220) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3219) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3218) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3217) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3216) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3215) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3214) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3213) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3212) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3211) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3210) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3209) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3208) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3207) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3206) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3205) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3204) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3203) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3202) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3201:3202) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER50: ROM location 50

OTPROM REG 51
Addr:	0000000000018033 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG51
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3327) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3326) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3325) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3324) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3323) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3322) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3321) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3320) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3319) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3318) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3317) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3316) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3315) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3314) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3313) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3312) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3311) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3310) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3309) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3308) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3307) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3306) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3305) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3304) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3303) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3302) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3301) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3300) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3299) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3298) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3297) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3296) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3295) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3294) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3293) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3292) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3291) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3290) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3289) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3288) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3287) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3286) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3285) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3284) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3283) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3282) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3281) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3280) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3279) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3278) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3277) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3276) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3275) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3274) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3273) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3272) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3271) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3270) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3269) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3268) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3267) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3266) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3265:3266) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER51: ROM location 51

OTPROM REG 52
Addr:	0000000000018034 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG52
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3391) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3390) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3389) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3388) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3387) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3386) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3385) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3384) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3383) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3382) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3381) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3380) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3379) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3378) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3377) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3376) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3375) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3374) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3373) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3372) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3371) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3370) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3369) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3368) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3367) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3366) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3365) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3364) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3363) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3362) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3361) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3360) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3359) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3358) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3357) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3356) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3355) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3354) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3353) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3352) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3351) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3350) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3349) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3348) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3347) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3346) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3345) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3344) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3343) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3342) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3341) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3340) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3339) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3338) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3337) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3336) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3335) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3334) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3333) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3332) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3331) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3330) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3329:3330) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER52: ROM location 52

OTPROM REG 53
Addr:	0000000000018035 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG53
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3455) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3454) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3453) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3452) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3451) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3450) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3449) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3448) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3447) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3446) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3445) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3444) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3443) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3442) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3441) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3440) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3439) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3438) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3437) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3436) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3435) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3434) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3433) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3432) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3431) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3430) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3429) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3428) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3427) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3426) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3425) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3424) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3423) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3422) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3421) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3420) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3419) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3418) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3417) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3416) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3415) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3414) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3413) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3412) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3411) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3410) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3409) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3408) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3407) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3406) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3405) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3404) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3403) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3402) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3401) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3400) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3399) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3398) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3397) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3396) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3395) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3394) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3393:3394) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER53: ROM location 53

OTPROM REG 54
Addr:	0000000000018036 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG54
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3519) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3518) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3517) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3516) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3515) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3514) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3513) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3512) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3511) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3510) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3509) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3508) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3507) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3506) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3505) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3504) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3503) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3502) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3501) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3500) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3499) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3498) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3497) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3496) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3495) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3494) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3493) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3492) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3491) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3490) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3489) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3488) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3487) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3486) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3485) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3484) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3483) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3482) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3481) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3480) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3479) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3478) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3477) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3476) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3475) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3474) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3473) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3472) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3471) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3470) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3469) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3468) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3467) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3466) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3465) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3464) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3463) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3462) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3461) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3460) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3459) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3458) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3457:3458) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER54: ROM location 54

OTPROM REG 55
Addr:	0000000000018037 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG55
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3583) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3582) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3581) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3580) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3579) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3578) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3577) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3576) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3575) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3574) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3573) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3572) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3571) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3570) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3569) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3568) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3567) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3566) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3565) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3564) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3563) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3562) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3561) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3560) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3559) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3558) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3557) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3556) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3555) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3554) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3553) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3552) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3551) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3550) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3549) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3548) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3547) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3546) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3545) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3544) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3543) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3542) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3541) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3540) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3539) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3538) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3537) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3536) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3535) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3534) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3533) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3532) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3531) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3530) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3529) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3528) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3527) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3526) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3525) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3524) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3523) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3522) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3521:3522) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER55: ROM location 55

OTPROM REG 56
Addr:	0000000000018038 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG56
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3647) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3646) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3645) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3644) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3643) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3642) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3641) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3640) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3639) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3638) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3637) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3636) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3635) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3634) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3633) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3632) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3631) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3630) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3629) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3628) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3627) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3626) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3625) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3624) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3623) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3622) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3621) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3620) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3619) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3618) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3617) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3616) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3615) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3614) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3613) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3612) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3611) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3610) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3609) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3608) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3607) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3606) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3605) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3604) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3603) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3602) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3601) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3600) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3599) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3598) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3597) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3596) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3595) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3594) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3593) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3592) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3591) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3590) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3589) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3588) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3587) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3586) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3585:3586) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER56: ROM location 56

OTPROM REG 57
Addr:	0000000000018039 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG57
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3711) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3710) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3709) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3708) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3707) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3706) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3705) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3704) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3703) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3702) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3701) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3700) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3699) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3698) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3697) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3696) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3695) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3694) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3693) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3692) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3691) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3690) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3689) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3688) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3687) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3686) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3685) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3684) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3683) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3682) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3681) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3680) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3679) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3678) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3677) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3676) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3675) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3674) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3673) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3672) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3671) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3670) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3669) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3668) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3667) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3666) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3665) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3664) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3663) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3662) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3661) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3660) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3659) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3658) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3657) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3656) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3655) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3654) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3653) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3652) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3651) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3650) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3649:3650) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER57: ROM location 57

OTPROM REG 58
Addr:	000000000001803A (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG58
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3775) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3774) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3773) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3772) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3771) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3770) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3769) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3768) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3767) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3766) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3765) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3764) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3763) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3762) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3761) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3760) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3759) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3758) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3757) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3756) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3755) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3754) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3753) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3752) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3751) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3750) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3749) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3748) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3747) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3746) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3745) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3744) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3743) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3742) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3741) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3740) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3739) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3738) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3737) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3736) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3735) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3734) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3733) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3732) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3731) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3730) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3729) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3728) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3727) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3726) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3725) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3724) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3723) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3722) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3721) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3720) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3719) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3718) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3717) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3716) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3715) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3714) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3713:3714) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER58: ROM location 58

OTPROM REG 59
Addr:	000000000001803B (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG59
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3839) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3838) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3837) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3836) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3835) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3834) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3833) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3832) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3831) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3830) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3829) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3828) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3827) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3826) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3825) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3824) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3823) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3822) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3821) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3820) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3819) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3818) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3817) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3816) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3815) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3814) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3813) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3812) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3811) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3810) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3809) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3808) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3807) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3806) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3805) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3804) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3803) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3802) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3801) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3800) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3799) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3798) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3797) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3796) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3795) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3794) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3793) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3792) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3791) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3790) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3789) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3788) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3787) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3786) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3785) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3784) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3783) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3782) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3781) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3780) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3779) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3778) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3777:3778) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER59: ROM location 59

OTPROM REG 60
Addr:	000000000001803C (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG60
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3903) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3902) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3901) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3900) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3899) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3898) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3897) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3896) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3895) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3894) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3893) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3892) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3891) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3890) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3889) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3888) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3887) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3886) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3885) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3884) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3883) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3882) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3881) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3880) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3879) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3878) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3877) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3876) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3875) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3874) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3873) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3872) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3871) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3870) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3869) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3868) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3867) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3866) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3865) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3864) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3863) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3862) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3861) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3860) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3859) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3858) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3857) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3856) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3855) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3854) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3853) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3852) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3851) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3850) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3849) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3848) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3847) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3846) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3845) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3844) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3843) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3842) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3841:3842) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER60: ROM location 60

OTPROM REG 61
Addr:	000000000001803D (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG61
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3967) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3966) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3965) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3964) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3963) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3962) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3961) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3960) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3959) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3958) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3957) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3956) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3955) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3954) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3953) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3952) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3951) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3950) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3949) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3948) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3947) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3946) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3945) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3944) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3943) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3942) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3941) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3940) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3939) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3938) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3937) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3936) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3935) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3934) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3933) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3932) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3931) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3930) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3929) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3928) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3927) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3926) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3925) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3924) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3923) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3922) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3921) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3920) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3919) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3918) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3917) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3916) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3915) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3914) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3913) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3912) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3911) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3910) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3909) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3908) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3907) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3906) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3905:3906) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER61: ROM location 61

OTPROM REG 62
Addr:	000000000001803E (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG62
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4031) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4030) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4029) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4028) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4027) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4026) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4025) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4024) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4023) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4022) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4021) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4020) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4019) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4018) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4017) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4016) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4015) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4014) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4013) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4012) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4011) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4010) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4009) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4008) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4007) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4006) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4005) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4004) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4003) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4002) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4001) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4000) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3999) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3998) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3997) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3996) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3995) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3994) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3993) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3992) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3991) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3990) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3989) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3988) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3987) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3986) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3985) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3984) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3983) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3982) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3981) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3980) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3979) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3978) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3977) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3976) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3975) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3974) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3973) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3972) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3971) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3970) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(3969:3970) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER62: ROM location 62

OTPROM REG 63
Addr:	000000000001803F (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG63
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4095) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4094) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4093) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4092) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4091) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4090) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4089) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4088) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4087) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4086) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4085) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4084) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4083) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4082) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4081) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4080) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4079) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4078) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4077) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4076) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4075) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4074) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4073) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4072) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4071) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4070) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4069) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4068) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4067) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4066) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4065) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4064) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4063) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4062) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4061) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4060) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4059) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4058) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4057) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4056) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4055) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4054) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4053) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4052) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4051) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4050) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4049) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4048) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4047) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4046) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4045) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4044) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4043) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4042) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4041) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4040) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4039) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4038) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4037) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4036) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4035) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4034) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4033:4034) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER63: ROM location 63

OTPROM REG 64
Addr:	0000000000018040 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG64
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4159) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4158) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4157) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4156) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4155) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4154) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4153) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4152) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4151) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4150) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4149) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4148) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4147) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4146) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4145) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4144) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4143) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4142) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4141) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4140) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4139) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4138) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4137) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4136) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4135) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4134) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4133) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4132) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4131) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4130) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4129) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4128) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4127) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4126) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4125) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4124) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4123) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4122) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4121) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4120) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4119) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4118) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4117) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4116) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4115) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4114) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4113) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4112) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4111) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4110) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4109) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4108) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4107) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4106) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4105) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4104) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4103) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4102) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4101) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4100) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4099) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4098) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4097:4098) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER64: ROM location 64

OTPROM REG 65
Addr:	0000000000018041 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG65
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4223) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4222) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4221) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4220) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4219) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4218) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4217) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4216) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4215) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4214) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4213) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4212) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4211) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4210) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4209) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4208) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4207) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4206) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4205) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4204) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4203) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4202) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4201) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4200) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4199) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4198) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4197) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4196) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4195) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4194) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4193) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4192) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4191) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4190) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4189) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4188) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4187) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4186) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4185) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4184) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4183) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4182) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4181) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4180) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4179) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4178) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4177) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4176) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4175) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4174) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4173) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4172) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4171) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4170) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4169) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4168) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4167) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4166) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4165) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4164) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4163) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4162) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4161:4162) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER65: ROM location 65

OTPROM REG 66
Addr:	0000000000018042 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG66
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4287) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4286) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4285) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4284) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4283) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4282) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4281) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4280) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4279) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4278) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4277) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4276) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4275) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4274) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4273) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4272) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4271) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4270) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4269) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4268) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4267) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4266) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4265) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4264) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4263) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4262) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4261) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4260) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4259) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4258) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4257) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4256) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4255) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4254) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4253) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4252) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4251) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4250) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4249) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4248) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4247) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4246) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4245) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4244) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4243) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4242) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4241) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4240) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4239) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4238) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4237) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4236) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4235) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4234) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4233) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4232) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4231) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4230) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4229) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4228) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4227) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4226) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4225:4226) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER66: ROM location 66

OTPROM REG 67
Addr:	0000000000018043 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG67
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4351) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4350) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4349) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4348) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4347) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4346) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4345) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4344) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4343) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4342) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4341) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4340) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4339) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4338) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4337) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4336) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4335) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4334) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4333) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4332) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4331) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4330) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4329) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4328) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4327) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4326) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4325) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4324) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4323) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4322) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4321) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4320) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4319) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4318) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4317) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4316) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4315) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4314) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4313) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4312) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4311) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4310) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4309) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4308) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4307) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4306) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4305) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4304) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4303) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4302) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4301) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4300) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4299) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4298) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4297) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4296) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4295) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4294) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4293) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4292) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4291) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4290) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4289:4290) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER67: ROM location 67

OTPROM REG 68
Addr:	0000000000018044 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG68
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4415) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4414) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4413) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4412) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4411) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4410) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4409) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4408) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4407) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4406) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4405) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4404) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4403) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4402) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4401) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4400) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4399) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4398) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4397) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4396) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4395) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4394) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4393) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4392) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4391) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4390) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4389) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4388) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4387) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4386) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4385) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4384) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4383) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4382) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4381) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4380) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4379) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4378) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4377) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4376) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4375) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4374) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4373) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4372) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4371) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4370) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4369) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4368) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4367) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4366) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4365) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4364) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4363) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4362) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4361) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4360) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4359) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4358) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4357) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4356) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4355) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4354) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4353:4354) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER68: ROM location 68

OTPROM REG 69
Addr:	0000000000018045 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG69
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4479) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4478) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4477) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4476) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4475) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4474) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4473) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4472) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4471) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4470) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4469) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4468) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4467) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4466) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4465) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4464) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4463) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4462) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4461) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4460) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4459) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4458) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4457) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4456) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4455) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4454) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4453) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4452) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4451) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4450) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4449) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4448) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4447) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4446) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4445) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4444) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4443) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4442) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4441) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4440) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4439) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4438) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4437) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4436) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4435) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4434) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4433) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4432) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4431) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4430) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4429) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4428) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4427) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4426) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4425) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4424) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4423) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4422) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4421) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4420) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4419) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4418) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4417:4418) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER69: ROM location 69

OTPROM REG 70
Addr:	0000000000018046 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG70
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4543) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4542) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4541) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4540) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4539) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4538) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4537) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4536) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4535) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4534) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4533) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4532) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4531) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4530) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4529) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4528) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4527) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4526) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4525) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4524) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4523) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4522) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4521) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4520) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4519) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4518) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4517) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4516) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4515) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4514) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4513) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4512) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4511) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4510) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4509) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4508) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4507) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4506) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4505) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4504) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4503) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4502) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4501) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4500) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4499) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4498) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4497) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4496) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4495) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4494) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4493) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4492) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4491) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4490) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4489) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4488) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4487) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4486) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4485) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4484) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4483) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4482) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4481:4482) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER70: ROM location 70

OTPROM REG 71
Addr:	0000000000018047 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG71
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4607) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4606) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4605) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4604) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4603) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4602) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4601) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4600) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4599) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4598) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4597) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4596) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4595) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4594) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4593) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4592) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4591) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4590) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4589) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4588) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4587) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4586) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4585) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4584) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4583) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4582) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4581) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4580) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4579) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4578) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4577) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4576) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4575) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4574) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4573) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4572) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4571) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4570) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4569) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4568) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4567) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4566) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4565) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4564) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4563) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4562) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4561) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4560) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4559) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4558) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4557) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4556) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4555) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4554) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4553) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4552) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4551) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4550) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4549) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4548) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4547) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4546) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4545:4546) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER71: ROM location 71

OTPROM REG 72
Addr:	0000000000018048 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG72
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4671) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4670) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4669) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4668) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4667) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4666) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4665) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4664) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4663) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4662) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4661) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4660) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4659) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4658) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4657) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4656) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4655) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4654) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4653) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4652) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4651) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4650) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4649) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4648) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4647) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4646) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4645) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4644) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4643) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4642) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4641) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4640) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4639) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4638) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4637) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4636) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4635) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4634) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4633) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4632) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4631) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4630) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4629) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4628) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4627) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4626) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4625) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4624) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4623) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4622) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4621) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4620) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4619) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4618) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4617) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4616) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4615) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4614) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4613) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4612) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4611) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4610) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4609:4610) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER72: ROM location 72

OTPROM REG 73
Addr:	0000000000018049 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG73
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4735) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4734) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4733) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4732) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4731) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4730) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4729) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4728) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4727) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4726) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4725) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4724) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4723) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4722) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4721) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4720) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4719) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4718) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4717) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4716) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4715) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4714) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4713) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4712) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4711) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4710) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4709) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4708) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4707) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4706) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4705) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4704) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4703) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4702) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4701) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4700) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4699) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4698) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4697) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4696) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4695) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4694) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4693) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4692) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4691) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4690) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4689) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4688) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4687) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4686) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4685) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4684) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4683) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4682) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4681) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4680) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4679) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4678) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4677) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4676) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4675) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4674) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4673:4674) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER73: ROM location 73

OTPROM REG 74
Addr:	000000000001804A (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG74
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4799) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4798) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4797) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4796) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4795) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4794) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4793) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4792) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4791) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4790) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4789) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4788) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4787) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4786) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4785) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4784) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4783) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4782) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4781) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4780) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4779) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4778) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4777) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4776) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4775) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4774) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4773) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4772) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4771) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4770) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4769) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4768) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4767) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4766) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4765) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4764) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4763) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4762) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4761) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4760) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4759) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4758) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4757) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4756) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4755) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4754) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4753) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4752) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4751) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4750) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4749) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4748) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4747) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4746) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4745) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4744) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4743) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4742) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4741) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4740) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4739) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4738) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4737:4738) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER74: ROM location 74

OTPROM REG 75
Addr:	000000000001804B (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG75
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4863) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4862) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4861) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4860) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4859) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4858) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4857) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4856) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4855) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4854) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4853) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4852) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4851) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4850) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4849) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4848) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4847) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4846) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4845) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4844) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4843) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4842) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4841) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4840) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4839) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4838) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4837) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4836) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4835) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4834) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4833) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4832) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4831) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4830) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4829) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4828) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4827) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4826) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4825) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4824) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4823) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4822) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4821) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4820) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4819) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4818) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4817) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4816) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4815) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4814) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4813) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4812) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4811) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4810) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4809) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4808) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4807) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4806) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4805) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4804) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4803) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4802) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4801:4802) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER75: ROM location 75

OTPROM REG 76
Addr:	000000000001804C (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG76
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4927) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4926) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4925) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4924) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4923) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4922) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4921) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4920) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4919) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4918) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4917) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4916) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4915) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4914) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4913) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4912) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4911) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4910) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4909) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4908) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4907) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4906) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4905) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4904) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4903) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4902) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4901) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4900) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4899) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4898) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4897) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4896) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4895) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4894) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4893) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4892) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4891) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4890) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4889) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4888) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4887) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4886) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4885) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4884) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4883) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4882) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4881) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4880) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4879) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4878) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4877) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4876) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4875) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4874) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4873) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4872) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4871) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4870) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4869) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4868) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4867) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4866) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4865:4866) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER76: ROM location 76

OTPROM REG 77
Addr:	000000000001804D (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG77
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4991) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4990) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4989) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4988) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4987) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4986) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4985) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4984) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4983) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4982) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4981) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4980) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4979) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4978) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4977) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4976) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4975) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4974) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4973) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4972) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4971) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4970) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4969) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4968) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4967) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4966) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4965) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4964) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4963) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4962) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4961) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4960) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4959) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4958) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4957) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4956) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4955) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4954) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4953) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4952) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4951) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4950) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4949) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4948) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4947) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4946) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4945) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4944) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4943) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4942) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4941) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4940) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4939) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4938) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4937) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4936) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4935) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4934) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4933) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4932) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4931) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4930) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4929:4930) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER77: ROM location 77

OTPROM REG 78
Addr:	000000000001804E (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG78
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5055) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5054) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5053) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5052) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5051) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5050) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5049) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5048) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5047) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5046) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5045) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5044) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5043) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5042) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5041) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5040) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5039) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5038) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5037) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5036) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5035) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5034) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5033) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5032) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5031) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5030) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5029) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5028) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5027) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5026) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5025) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5024) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5023) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5022) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5021) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5020) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5019) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5018) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5017) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5016) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5015) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5014) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5013) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5012) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5011) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5010) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5009) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5008) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5007) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5006) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5005) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5004) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5003) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5002) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5001) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5000) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4999) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4998) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4997) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4996) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4995) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4994) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(4993:4994) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER78: ROM location 78

OTPROM REG 79
Addr:	000000000001804F (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG79
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5119) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5118) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5117) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5116) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5115) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5114) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5113) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5112) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5111) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5110) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5109) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5108) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5107) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5106) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5105) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5104) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5103) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5102) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5101) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5100) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5099) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5098) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5097) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5096) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5095) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5094) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5093) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5092) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5091) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5090) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5089) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5088) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5087) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5086) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5085) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5084) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5083) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5082) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5081) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5080) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5079) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5078) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5077) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5076) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5075) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5074) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5073) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5072) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5071) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5070) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5069) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5068) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5067) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5066) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5065) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5064) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5063) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5062) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5061) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5060) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5059) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5058) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5057:5058) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER79: ROM location 79

OTPROM REG 80
Addr:	0000000000018050 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG80
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5183) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5182) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5181) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5180) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5179) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5178) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5177) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5176) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5175) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5174) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5173) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5172) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5171) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5170) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5169) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5168) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5167) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5166) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5165) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5164) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5163) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5162) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5161) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5160) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5159) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5158) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5157) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5156) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5155) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5154) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5153) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5152) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5151) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5150) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5149) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5148) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5147) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5146) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5145) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5144) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5143) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5142) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5141) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5140) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5139) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5138) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5137) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5136) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5135) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5134) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5133) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5132) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5131) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5130) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5129) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5128) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5127) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5126) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5125) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5124) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5123) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5122) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5121:5122) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER80: ROM location 80

OTPROM REG 81
Addr:	0000000000018051 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG81
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5247) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5246) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5245) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5244) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5243) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5242) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5241) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5240) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5239) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5238) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5237) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5236) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5235) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5234) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5233) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5232) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5231) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5230) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5229) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5228) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5227) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5226) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5225) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5224) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5223) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5222) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5221) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5220) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5219) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5218) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5217) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5216) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5215) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5214) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5213) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5212) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5211) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5210) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5209) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5208) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5207) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5206) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5205) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5204) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5203) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5202) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5201) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5200) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5199) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5198) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5197) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5196) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5195) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5194) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5193) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5192) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5191) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5190) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5189) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5188) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5187) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5186) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5185:5186) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER81: ROM location 81

OTPROM REG 82
Addr:	0000000000018052 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG82
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5311) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5310) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5309) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5308) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5307) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5306) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5305) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5304) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5303) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5302) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5301) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5300) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5299) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5298) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5297) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5296) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5295) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5294) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5293) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5292) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5291) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5290) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5289) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5288) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5287) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5286) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5285) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5284) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5283) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5282) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5281) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5280) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5279) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5278) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5277) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5276) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5275) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5274) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5273) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5272) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5271) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5270) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5269) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5268) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5267) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5266) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5265) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5264) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5263) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5262) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5261) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5260) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5259) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5258) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5257) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5256) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5255) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5254) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5253) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5252) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5251) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5250) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5249:5250) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER82: ROM location 82

OTPROM REG 83
Addr:	0000000000018053 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG83
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5375) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5374) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5373) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5372) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5371) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5370) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5369) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5368) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5367) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5366) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5365) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5364) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5363) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5362) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5361) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5360) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5359) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5358) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5357) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5356) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5355) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5354) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5353) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5352) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5351) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5350) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5349) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5348) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5347) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5346) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5345) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5344) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5343) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5342) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5341) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5340) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5339) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5338) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5337) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5336) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5335) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5334) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5333) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5332) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5331) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5330) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5329) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5328) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5327) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5326) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5325) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5324) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5323) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5322) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5321) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5320) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5319) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5318) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5317) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5316) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5315) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5314) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5313:5314) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER83: ROM location 83

OTPROM REG 84
Addr:	0000000000018054 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG84
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5439) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5438) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5437) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5436) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5435) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5434) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5433) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5432) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5431) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5430) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5429) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5428) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5427) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5426) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5425) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5424) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5423) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5422) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5421) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5420) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5419) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5418) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5417) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5416) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5415) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5414) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5413) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5412) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5411) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5410) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5409) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5408) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5407) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5406) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5405) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5404) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5403) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5402) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5401) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5400) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5399) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5398) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5397) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5396) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5395) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5394) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5393) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5392) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5391) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5390) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5389) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5388) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5387) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5386) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5385) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5384) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5383) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5382) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5381) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5380) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5379) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5378) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5377:5378) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER84: ROM location 84

OTPROM REG 85
Addr:	0000000000018055 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG85
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5503) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5502) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5501) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5500) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5499) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5498) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5497) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5496) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5495) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5494) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5493) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5492) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5491) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5490) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5489) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5488) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5487) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5486) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5485) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5484) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5483) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5482) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5481) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5480) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5479) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5478) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5477) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5476) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5475) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5474) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5473) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5472) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5471) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5470) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5469) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5468) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5467) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5466) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5465) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5464) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5463) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5462) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5461) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5460) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5459) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5458) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5457) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5456) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5455) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5454) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5453) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5452) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5451) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5450) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5449) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5448) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5447) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5446) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5445) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5444) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5443) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5442) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5441:5442) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER85: ROM location 85

OTPROM REG 86
Addr:	0000000000018056 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG86
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5567) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5566) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5565) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5564) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5563) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5562) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5561) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5560) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5559) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5558) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5557) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5556) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5555) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5554) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5553) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5552) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5551) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5550) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5549) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5548) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5547) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5546) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5545) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5544) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5543) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5542) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5541) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5540) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5539) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5538) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5537) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5536) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5535) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5534) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5533) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5532) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5531) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5530) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5529) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5528) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5527) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5526) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5525) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5524) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5523) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5522) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5521) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5520) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5519) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5518) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5517) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5516) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5515) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5514) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5513) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5512) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5511) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5510) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5509) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5508) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5507) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5506) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5505:5506) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER86: ROM location 86

OTPROM REG 87
Addr:	0000000000018057 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG87
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5631) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5630) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5629) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5628) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5627) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5626) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5625) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5624) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5623) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5622) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5621) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5620) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5619) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5618) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5617) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5616) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5615) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5614) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5613) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5612) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5611) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5610) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5609) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5608) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5607) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5606) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5605) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5604) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5603) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5602) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5601) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5600) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5599) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5598) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5597) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5596) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5595) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5594) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5593) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5592) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5591) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5590) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5589) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5588) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5587) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5586) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5585) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5584) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5583) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5582) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5581) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5580) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5579) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5578) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5577) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5576) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5575) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5574) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5573) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5572) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5571) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5570) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5569:5570) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER87: ROM location 87

OTPROM REG 88
Addr:	0000000000018058 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG88
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5695) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5694) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5693) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5692) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5691) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5690) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5689) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5688) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5687) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5686) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5685) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5684) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5683) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5682) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5681) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5680) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5679) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5678) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5677) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5676) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5675) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5674) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5673) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5672) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5671) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5670) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5669) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5668) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5667) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5666) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5665) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5664) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5663) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5662) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5661) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5660) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5659) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5658) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5657) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5656) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5655) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5654) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5653) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5652) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5651) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5650) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5649) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5648) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5647) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5646) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5645) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5644) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5643) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5642) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5641) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5640) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5639) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5638) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5637) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5636) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5635) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5634) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5633:5634) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER88: ROM location 88

OTPROM REG 89
Addr:	0000000000018059 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG89
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5759) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5758) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5757) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5756) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5755) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5754) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5753) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5752) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5751) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5750) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5749) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5748) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5747) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5746) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5745) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5744) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5743) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5742) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5741) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5740) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5739) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5738) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5737) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5736) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5735) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5734) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5733) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5732) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5731) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5730) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5729) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5728) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5727) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5726) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5725) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5724) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5723) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5722) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5721) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5720) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5719) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5718) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5717) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5716) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5715) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5714) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5713) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5712) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5711) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5710) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5709) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5708) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5707) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5706) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5705) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5704) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5703) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5702) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5701) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5700) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5699) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5698) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5697:5698) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER89: ROM location 89

OTPROM REG 90
Addr:	000000000001805A (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG90
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5823) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5822) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5821) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5820) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5819) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5818) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5817) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5816) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5815) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5814) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5813) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5812) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5811) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5810) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5809) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5808) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5807) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5806) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5805) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5804) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5803) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5802) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5801) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5800) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5799) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5798) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5797) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5796) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5795) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5794) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5793) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5792) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5791) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5790) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5789) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5788) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5787) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5786) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5785) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5784) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5783) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5782) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5781) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5780) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5779) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5778) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5777) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5776) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5775) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5774) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5773) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5772) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5771) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5770) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5769) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5768) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5767) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5766) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5765) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5764) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5763) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5762) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5761:5762) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER90: ROM location 90

OTPROM REG 91
Addr:	000000000001805B (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG91
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5887) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5886) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5885) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5884) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5883) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5882) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5881) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5880) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5879) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5878) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5877) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5876) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5875) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5874) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5873) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5872) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5871) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5870) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5869) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5868) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5867) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5866) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5865) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5864) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5863) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5862) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5861) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5860) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5859) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5858) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5857) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5856) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5855) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5854) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5853) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5852) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5851) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5850) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5849) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5848) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5847) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5846) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5845) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5844) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5843) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5842) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5841) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5840) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5839) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5838) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5837) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5836) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5835) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5834) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5833) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5832) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5831) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5830) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5829) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5828) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5827) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5826) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5825:5826) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER91: ROM location 91

OTPROM REG 92
Addr:	000000000001805C (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG92
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5951) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5950) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5949) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5948) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5947) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5946) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5945) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5944) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5943) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5942) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5941) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5940) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5939) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5938) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5937) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5936) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5935) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5934) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5933) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5932) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5931) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5930) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5929) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5928) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5927) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5926) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5925) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5924) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5923) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5922) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5921) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5920) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5919) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5918) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5917) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5916) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5915) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5914) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5913) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5912) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5911) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5910) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5909) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5908) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5907) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5906) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5905) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5904) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5903) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5902) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5901) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5900) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5899) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5898) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5897) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5896) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5895) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5894) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5893) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5892) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5891) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5890) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5889:5890) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER92: ROM location 92

OTPROM REG 93
Addr:	000000000001805D (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG93
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6015) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6014) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6013) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6012) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6011) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6010) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6009) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6008) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6007) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6006) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6005) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6004) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6003) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6002) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6001) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6000) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5999) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5998) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5997) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5996) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5995) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5994) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5993) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5992) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5991) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5990) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5989) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5988) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5987) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5986) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5985) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5984) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5983) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5982) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5981) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5980) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5979) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5978) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5977) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5976) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5975) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5974) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5973) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5972) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5971) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5970) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5969) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5968) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5967) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5966) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5965) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5964) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5963) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5962) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5961) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5960) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5959) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5958) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5957) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5956) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5955) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5954) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(5953:5954) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER93: ROM location 93

OTPROM REG 94
Addr:	000000000001805E (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG94
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6079) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6078) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6077) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6076) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6075) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6074) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6073) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6072) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6071) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6070) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6069) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6068) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6067) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6066) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6065) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6064) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6063) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6062) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6061) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6060) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6059) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6058) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6057) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6056) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6055) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6054) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6053) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6052) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6051) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6050) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6049) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6048) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6047) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6046) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6045) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6044) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6043) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6042) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6041) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6040) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6039) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6038) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6037) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6036) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6035) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6034) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6033) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6032) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6031) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6030) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6029) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6028) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6027) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6026) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6025) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6024) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6023) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6022) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6021) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6020) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6019) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6018) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6017:6018) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER94: ROM location 94

OTPROM REG 95
Addr:	000000000001805F (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG95
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6143) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6142) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6141) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6140) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6139) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6138) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6137) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6136) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6135) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6134) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6133) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6132) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6131) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6130) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6129) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6128) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6127) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6126) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6125) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6124) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6123) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6122) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6121) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6120) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6119) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6118) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6117) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6116) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6115) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6114) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6113) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6112) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6111) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6110) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6109) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6108) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6107) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6106) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6105) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6104) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6103) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6102) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6101) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6100) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6099) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6098) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6097) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6096) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6095) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6094) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6093) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6092) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6091) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6090) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6089) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6088) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6087) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6086) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6085) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6084) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6083) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6082) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6081:6082) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER95: ROM location 95

OTPROM REG 96
Addr:	0000000000018060 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG96
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6207) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6206) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6205) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6204) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6203) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6202) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6201) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6200) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6199) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6198) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6197) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6196) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6195) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6194) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6193) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6192) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6191) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6190) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6189) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6188) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6187) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6186) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6185) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6184) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6183) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6182) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6181) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6180) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6179) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6178) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6177) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6176) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6175) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6174) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6173) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6172) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6171) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6170) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6169) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6168) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6167) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6166) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6165) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6164) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6163) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6162) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6161) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6160) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6159) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6158) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6157) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6156) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6155) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6154) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6153) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6152) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6151) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6150) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6149) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6148) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6147) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6146) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6145:6146) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER96: ROM location 96

OTPROM REG 97
Addr:	0000000000018061 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG97
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6271) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6270) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6269) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6268) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6267) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6266) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6265) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6264) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6263) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6262) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6261) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6260) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6259) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6258) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6257) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6256) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6255) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6254) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6253) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6252) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6251) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6250) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6249) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6248) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6247) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6246) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6245) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6244) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6243) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6242) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6241) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6240) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6239) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6238) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6237) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6236) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6235) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6234) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6233) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6232) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6231) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6230) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6229) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6228) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6227) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6226) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6225) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6224) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6223) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6222) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6221) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6220) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6219) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6218) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6217) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6216) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6215) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6214) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6213) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6212) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6211) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6210) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6209:6210) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER97: ROM location 97

OTPROM REG 98
Addr:	0000000000018062 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG98
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6335) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6334) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6333) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6332) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6331) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6330) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6329) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6328) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6327) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6326) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6325) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6324) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6323) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6322) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6321) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6320) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6319) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6318) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6317) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6316) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6315) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6314) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6313) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6312) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6311) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6310) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6309) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6308) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6307) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6306) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6305) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6304) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6303) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6302) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6301) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6300) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6299) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6298) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6297) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6296) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6295) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6294) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6293) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6292) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6291) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6290) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6289) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6288) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6287) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6286) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6285) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6284) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6283) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6282) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6281) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6280) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6279) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6278) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6277) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6276) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6275) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6274) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6273:6274) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER98: ROM location 98

OTPROM REG 99
Addr:	0000000000018063 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG99
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6399) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6398) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6397) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6396) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6395) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6394) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6393) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6392) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6391) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6390) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6389) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6388) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6387) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6386) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6385) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6384) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6383) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6382) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6381) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6380) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6379) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6378) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6377) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6376) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6375) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6374) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6373) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6372) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6371) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6370) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6369) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6368) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6367) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6366) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6365) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6364) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6363) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6362) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6361) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6360) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6359) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6358) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6357) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6356) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6355) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6354) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6353) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6352) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6351) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6350) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6349) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6348) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6347) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6346) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6345) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6344) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6343) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6342) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6341) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6340) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6339) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6338) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6337:6338) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER99: ROM location 99

OTPROM REG 100
Addr:	0000000000018064 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG100
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6463) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6462) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6461) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6460) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6459) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6458) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6457) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6456) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6455) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6454) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6453) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6452) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6451) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6450) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6449) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6448) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6447) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6446) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6445) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6444) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6443) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6442) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6441) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6440) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6439) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6438) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6437) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6436) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6435) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6434) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6433) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6432) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6431) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6430) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6429) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6428) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6427) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6426) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6425) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6424) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6423) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6422) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6421) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6420) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6419) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6418) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6417) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6416) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6415) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6414) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6413) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6412) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6411) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6410) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6409) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6408) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6407) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6406) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6405) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6404) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6403) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6402) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6401:6402) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER100: ROM location 100

OTPROM REG 101
Addr:	0000000000018065 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG101
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6527) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6526) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6525) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6524) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6523) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6522) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6521) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6520) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6519) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6518) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6517) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6516) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6515) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6514) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6513) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6512) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6511) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6510) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6509) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6508) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6507) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6506) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6505) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6504) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6503) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6502) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6501) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6500) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6499) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6498) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6497) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6496) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6495) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6494) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6493) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6492) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6491) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6490) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6489) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6488) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6487) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6486) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6485) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6484) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6483) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6482) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6481) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6480) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6479) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6478) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6477) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6476) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6475) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6474) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6473) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6472) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6471) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6470) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6469) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6468) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6467) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6466) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6465:6466) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER101: ROM location 101

OTPROM REG 102
Addr:	0000000000018066 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG102
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6591) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6590) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6589) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6588) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6587) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6586) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6585) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6584) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6583) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6582) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6581) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6580) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6579) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6578) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6577) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6576) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6575) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6574) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6573) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6572) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6571) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6570) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6569) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6568) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6567) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6566) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6565) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6564) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6563) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6562) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6561) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6560) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6559) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6558) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6557) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6556) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6555) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6554) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6553) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6552) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6551) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6550) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6549) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6548) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6547) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6546) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6545) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6544) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6543) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6542) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6541) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6540) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6539) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6538) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6537) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6536) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6535) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6534) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6533) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6532) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6531) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6530) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6529:6530) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER102: ROM location 102

OTPROM REG 103
Addr:	0000000000018067 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG103
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6655) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6654) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6653) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6652) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6651) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6650) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6649) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6648) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6647) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6646) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6645) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6644) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6643) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6642) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6641) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6640) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6639) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6638) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6637) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6636) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6635) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6634) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6633) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6632) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6631) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6630) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6629) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6628) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6627) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6626) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6625) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6624) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6623) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6622) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6621) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6620) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6619) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6618) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6617) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6616) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6615) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6614) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6613) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6612) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6611) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6610) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6609) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6608) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6607) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6606) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6605) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6604) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6603) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6602) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6601) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6600) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6599) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6598) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6597) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6596) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6595) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6594) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6593:6594) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER103: ROM location 103

OTPROM REG 104
Addr:	0000000000018068 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG104
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6719) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6718) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6717) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6716) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6715) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6714) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6713) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6712) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6711) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6710) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6709) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6708) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6707) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6706) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6705) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6704) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6703) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6702) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6701) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6700) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6699) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6698) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6697) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6696) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6695) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6694) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6693) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6692) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6691) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6690) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6689) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6688) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6687) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6686) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6685) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6684) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6683) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6682) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6681) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6680) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6679) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6678) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6677) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6676) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6675) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6674) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6673) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6672) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6671) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6670) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6669) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6668) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6667) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6666) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6665) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6664) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6663) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6662) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6661) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6660) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6659) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6658) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6657:6658) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER104: ROM location 104

OTPROM REG 105
Addr:	0000000000018069 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG105
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6783) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6782) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6781) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6780) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6779) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6778) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6777) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6776) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6775) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6774) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6773) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6772) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6771) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6770) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6769) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6768) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6767) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6766) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6765) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6764) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6763) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6762) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6761) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6760) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6759) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6758) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6757) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6756) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6755) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6754) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6753) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6752) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6751) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6750) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6749) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6748) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6747) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6746) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6745) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6744) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6743) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6742) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6741) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6740) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6739) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6738) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6737) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6736) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6735) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6734) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6733) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6732) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6731) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6730) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6729) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6728) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6727) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6726) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6725) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6724) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6723) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6722) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6721:6722) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER105: ROM location 105

OTPROM REG 106
Addr:	000000000001806A (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG106
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6847) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6846) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6845) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6844) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6843) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6842) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6841) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6840) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6839) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6838) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6837) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6836) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6835) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6834) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6833) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6832) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6831) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6830) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6829) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6828) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6827) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6826) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6825) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6824) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6823) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6822) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6821) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6820) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6819) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6818) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6817) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6816) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6815) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6814) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6813) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6812) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6811) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6810) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6809) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6808) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6807) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6806) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6805) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6804) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6803) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6802) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6801) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6800) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6799) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6798) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6797) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6796) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6795) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6794) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6793) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6792) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6791) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6790) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6789) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6788) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6787) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6786) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6785:6786) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER106: ROM location 106

OTPROM REG 107
Addr:	000000000001806B (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG107
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6911) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6910) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6909) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6908) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6907) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6906) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6905) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6904) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6903) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6902) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6901) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6900) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6899) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6898) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6897) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6896) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6895) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6894) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6893) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6892) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6891) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6890) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6889) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6888) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6887) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6886) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6885) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6884) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6883) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6882) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6881) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6880) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6879) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6878) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6877) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6876) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6875) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6874) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6873) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6872) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6871) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6870) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6869) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6868) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6867) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6866) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6865) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6864) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6863) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6862) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6861) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6860) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6859) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6858) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6857) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6856) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6855) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6854) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6853) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6852) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6851) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6850) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6849:6850) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER107: ROM location 107

OTPROM REG 108
Addr:	000000000001806C (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG108
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6975) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6974) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6973) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6972) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6971) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6970) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6969) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6968) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6967) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6966) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6965) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6964) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6963) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6962) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6961) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6960) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6959) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6958) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6957) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6956) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6955) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6954) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6953) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6952) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6951) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6950) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6949) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6948) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6947) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6946) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6945) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6944) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6943) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6942) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6941) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6940) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6939) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6938) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6937) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6936) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6935) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6934) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6933) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6932) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6931) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6930) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6929) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6928) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6927) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6926) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6925) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6924) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6923) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6922) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6921) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6920) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6919) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6918) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6917) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6916) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6915) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6914) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6913:6914) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER108: ROM location 108

OTPROM REG 109
Addr:	000000000001806D (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG109
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7039) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7038) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7037) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7036) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7035) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7034) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7033) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7032) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7031) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7030) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7029) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7028) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7027) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7026) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7025) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7024) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7023) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7022) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7021) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7020) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7019) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7018) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7017) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7016) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7015) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7014) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7013) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7012) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7011) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7010) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7009) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7008) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7007) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7006) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7005) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7004) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7003) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7002) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7001) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7000) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6999) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6998) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6997) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6996) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6995) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6994) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6993) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6992) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6991) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6990) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6989) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6988) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6987) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6986) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6985) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6984) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6983) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6982) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6981) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6980) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6979) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6978) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(6977:6978) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER109: ROM location 109

OTPROM REG 110
Addr:	000000000001806E (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG110
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7103) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7102) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7101) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7100) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7099) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7098) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7097) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7096) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7095) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7094) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7093) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7092) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7091) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7090) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7089) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7088) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7087) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7086) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7085) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7084) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7083) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7082) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7081) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7080) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7079) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7078) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7077) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7076) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7075) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7074) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7073) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7072) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7071) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7070) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7069) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7068) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7067) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7066) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7065) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7064) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7063) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7062) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7061) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7060) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7059) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7058) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7057) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7056) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7055) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7054) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7053) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7052) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7051) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7050) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7049) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7048) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7047) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7046) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7045) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7044) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7043) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7042) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7041:7042) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER110: ROM location 110

OTPROM REG 111
Addr:	000000000001806F (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG111
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7167) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7166) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7165) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7164) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7163) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7162) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7161) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7160) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7159) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7158) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7157) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7156) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7155) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7154) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7153) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7152) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7151) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7150) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7149) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7148) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7147) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7146) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7145) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7144) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7143) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7142) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7141) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7140) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7139) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7138) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7137) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7136) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7135) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7134) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7133) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7132) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7131) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7130) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7129) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7128) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7127) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7126) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7125) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7124) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7123) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7122) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7121) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7120) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7119) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7118) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7117) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7116) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7115) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7114) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7113) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7112) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7111) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7110) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7109) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7108) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7107) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7106) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7105:7106) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER111: ROM location 111

OTPROM REG 112
Addr:	0000000000018070 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG112
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7231) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7230) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7229) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7228) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7227) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7226) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7225) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7224) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7223) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7222) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7221) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7220) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7219) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7218) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7217) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7216) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7215) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7214) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7213) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7212) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7211) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7210) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7209) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7208) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7207) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7206) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7205) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7204) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7203) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7202) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7201) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7200) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7199) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7198) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7197) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7196) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7195) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7194) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7193) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7192) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7191) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7190) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7189) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7188) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7187) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7186) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7185) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7184) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7183) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7182) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7181) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7180) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7179) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7178) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7177) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7176) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7175) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7174) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7173) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7172) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7171) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7170) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7169:7170) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER112: ROM location 112

OTPROM REG 113
Addr:	0000000000018071 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG113
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7295) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7294) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7293) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7292) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7291) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7290) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7289) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7288) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7287) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7286) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7285) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7284) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7283) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7282) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7281) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7280) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7279) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7278) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7277) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7276) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7275) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7274) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7273) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7272) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7271) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7270) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7269) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7268) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7267) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7266) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7265) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7264) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7263) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7262) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7261) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7260) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7259) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7258) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7257) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7256) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7255) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7254) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7253) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7252) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7251) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7250) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7249) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7248) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7247) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7246) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7245) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7244) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7243) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7242) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7241) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7240) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7239) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7238) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7237) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7236) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7235) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7234) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7233:7234) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER113: ROM location 113

OTPROM REG 114
Addr:	0000000000018072 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG114
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7359) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7358) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7357) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7356) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7355) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7354) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7353) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7352) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7351) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7350) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7349) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7348) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7347) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7346) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7345) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7344) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7343) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7342) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7341) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7340) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7339) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7338) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7337) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7336) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7335) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7334) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7333) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7332) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7331) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7330) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7329) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7328) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7327) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7326) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7325) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7324) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7323) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7322) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7321) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7320) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7319) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7318) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7317) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7316) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7315) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7314) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7313) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7312) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7311) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7310) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7309) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7308) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7307) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7306) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7305) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7304) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7303) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7302) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7301) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7300) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7299) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7298) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7297:7298) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER114: ROM location 114

OTPROM REG 115
Addr:	0000000000018073 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG115
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7423) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7422) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7421) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7420) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7419) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7418) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7417) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7416) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7415) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7414) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7413) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7412) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7411) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7410) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7409) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7408) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7407) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7406) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7405) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7404) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7403) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7402) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7401) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7400) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7399) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7398) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7397) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7396) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7395) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7394) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7393) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7392) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7391) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7390) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7389) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7388) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7387) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7386) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7385) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7384) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7383) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7382) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7381) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7380) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7379) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7378) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7377) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7376) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7375) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7374) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7373) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7372) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7371) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7370) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7369) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7368) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7367) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7366) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7365) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7364) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7363) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7362) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7361:7362) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER115: ROM location 115

OTPROM REG 116
Addr:	0000000000018074 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG116
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7487) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7486) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7485) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7484) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7483) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7482) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7481) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7480) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7479) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7478) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7477) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7476) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7475) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7474) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7473) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7472) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7471) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7470) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7469) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7468) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7467) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7466) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7465) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7464) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7463) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7462) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7461) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7460) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7459) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7458) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7457) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7456) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7455) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7454) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7453) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7452) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7451) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7450) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7449) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7448) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7447) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7446) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7445) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7444) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7443) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7442) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7441) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7440) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7439) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7438) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7437) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7436) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7435) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7434) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7433) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7432) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7431) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7430) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7429) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7428) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7427) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7426) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7425:7426) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER116: ROM location 116

OTPROM REG 117
Addr:	0000000000018075 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG117
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7551) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7550) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7549) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7548) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7547) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7546) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7545) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7544) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7543) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7542) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7541) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7540) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7539) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7538) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7537) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7536) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7535) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7534) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7533) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7532) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7531) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7530) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7529) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7528) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7527) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7526) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7525) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7524) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7523) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7522) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7521) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7520) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7519) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7518) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7517) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7516) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7515) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7514) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7513) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7512) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7511) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7510) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7509) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7508) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7507) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7506) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7505) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7504) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7503) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7502) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7501) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7500) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7499) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7498) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7497) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7496) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7495) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7494) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7493) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7492) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7491) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7490) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7489:7490) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER117: ROM location 117

OTPROM REG 118
Addr:	0000000000018076 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG118
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7615) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7614) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7613) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7612) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7611) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7610) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7609) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7608) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7607) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7606) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7605) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7604) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7603) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7602) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7601) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7600) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7599) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7598) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7597) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7596) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7595) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7594) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7593) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7592) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7591) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7590) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7589) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7588) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7587) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7586) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7585) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7584) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7583) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7582) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7581) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7580) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7579) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7578) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7577) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7576) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7575) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7574) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7573) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7572) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7571) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7570) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7569) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7568) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7567) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7566) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7565) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7564) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7563) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7562) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7561) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7560) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7559) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7558) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7557) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7556) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7555) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7554) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7553:7554) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER118: ROM location 118

OTPROM REG 119
Addr:	0000000000018077 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG119
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7679) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7678) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7677) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7676) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7675) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7674) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7673) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7672) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7671) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7670) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7669) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7668) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7667) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7666) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7665) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7664) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7663) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7662) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7661) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7660) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7659) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7658) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7657) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7656) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7655) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7654) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7653) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7652) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7651) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7650) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7649) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7648) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7647) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7646) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7645) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7644) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7643) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7642) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7641) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7640) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7639) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7638) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7637) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7636) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7635) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7634) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7633) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7632) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7631) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7630) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7629) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7628) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7627) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7626) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7625) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7624) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7623) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7622) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7621) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7620) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7619) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7618) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7617:7618) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER119: ROM location 119

OTPROM REG 120
Addr:	0000000000018078 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG120
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7743) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7742) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7741) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7740) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7739) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7738) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7737) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7736) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7735) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7734) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7733) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7732) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7731) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7730) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7729) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7728) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7727) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7726) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7725) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7724) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7723) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7722) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7721) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7720) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7719) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7718) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7717) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7716) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7715) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7714) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7713) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7712) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7711) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7710) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7709) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7708) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7707) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7706) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7705) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7704) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7703) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7702) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7701) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7700) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7699) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7698) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7697) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7696) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7695) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7694) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7693) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7692) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7691) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7690) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7689) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7688) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7687) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7686) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7685) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7684) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7683) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7682) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7681:7682) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER120: ROM location 120

OTPROM REG 121
Addr:	0000000000018079 (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG121
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7807) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7806) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7805) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7804) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7803) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7802) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7801) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7800) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7799) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7798) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7797) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7796) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7795) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7794) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7793) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7792) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7791) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7790) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7789) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7788) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7787) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7786) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7785) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7784) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7783) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7782) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7781) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7780) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7779) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7778) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7777) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7776) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7775) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7774) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7773) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7772) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7771) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7770) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7769) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7768) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7767) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7766) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7765) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7764) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7763) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7762) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7761) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7760) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7759) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7758) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7757) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7756) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7755) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7754) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7753) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7752) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7751) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7750) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7749) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7748) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7747) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7746) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7745:7746) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER121: ROM location 121

OTPROM REG 122
Addr:	000000000001807A (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG122
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7871) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7870) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7869) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7868) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7867) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7866) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7865) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7864) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7863) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7862) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7861) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7860) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7859) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7858) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7857) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7856) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7855) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7854) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7853) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7852) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7851) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7850) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7849) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7848) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7847) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7846) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7845) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7844) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7843) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7842) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7841) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7840) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7839) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7838) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7837) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7836) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7835) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7834) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7833) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7832) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7831) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7830) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7829) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7828) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7827) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7826) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7825) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7824) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7823) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7822) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7821) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7820) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7819) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7818) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7817) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7816) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7815) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7814) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7813) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7812) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7811) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7810) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7809:7810) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER122: ROM location 122

OTPROM REG 123
Addr:	000000000001807B (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG123
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7935) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7934) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7933) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7932) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7931) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7930) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7929) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7928) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7927) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7926) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7925) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7924) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7923) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7922) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7921) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7920) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7919) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7918) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7917) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7916) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7915) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7914) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7913) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7912) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7911) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7910) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7909) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7908) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7907) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7906) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7905) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7904) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7903) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7902) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7901) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7900) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7899) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7898) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7897) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7896) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7895) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7894) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7893) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7892) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7891) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7890) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7889) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7888) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7887) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7886) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7885) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7884) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7883) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7882) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7881) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7880) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7879) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7878) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7877) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7876) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7875) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7874) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7873:7874) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER123: ROM location 123

OTPROM REG 124
Addr:	000000000001807C (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG124
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7999) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7998) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7997) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7996) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7995) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7994) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7993) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7992) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7991) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7990) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7989) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7988) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7987) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7986) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7985) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7984) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7983) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7982) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7981) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7980) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7979) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7978) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7977) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7976) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7975) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7974) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7973) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7972) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7971) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7970) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7969) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7968) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7967) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7966) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7965) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7964) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7963) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7962) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7961) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7960) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7959) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7958) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7957) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7956) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7955) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7954) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7953) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7952) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7951) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7950) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7949) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7948) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7947) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7946) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7945) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7944) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7943) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7942) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7941) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7940) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7939) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7938) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(7937:7938) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER124: ROM location 124

OTPROM REG 125
Addr:	000000000001807D (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG125
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8063) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8062) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8061) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8060) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8059) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8058) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8057) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8056) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8055) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8054) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8053) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8052) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8051) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8050) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8049) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8048) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8047) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8046) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8045) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8044) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8043) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8042) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8041) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8040) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8039) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8038) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8037) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8036) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8035) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8034) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8033) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8032) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8031) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8030) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8029) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8028) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8027) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8026) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8025) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8024) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8023) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8022) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8021) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8020) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8019) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8018) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8017) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8016) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8015) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8014) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8013) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8012) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8011) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8010) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8009) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8008) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8007) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8006) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8005) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8004) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8003) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8002) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8001:8002) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER125: ROM location 125

OTPROM REG 126
Addr:	000000000001807E (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG126
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8127) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8126) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8125) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8124) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8123) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8122) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8121) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8120) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8119) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8118) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8117) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8116) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8115) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8114) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8113) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8112) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8111) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8110) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8109) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8108) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8107) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8106) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8105) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8104) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8103) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8102) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8101) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8100) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8099) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8098) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8097) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8096) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8095) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8094) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8093) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8092) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8091) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8090) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8089) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8088) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8087) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8086) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8085) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8084) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8083) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8082) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8081) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8080) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8079) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8078) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8077) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8076) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8075) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8074) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8073) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8072) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8071) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8070) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8069) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8068) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8067) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8066) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8065:8066) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER126: ROM location 126

OTPROM REG 127
Addr:	000000000001807F (SCOM)
Name:	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG127
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8191) [0]
	1	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8190) [0]
	2	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8189) [0]
	3	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8188) [0]
	4	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8187) [0]
	5	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8186) [0]
	6	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8185) [0]
	7	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8184) [0]
	8	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8183) [0]
	9	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8182) [0]
	10	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8181) [0]
	11	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8180) [0]
	12	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8179) [0]
	13	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8178) [0]
	14	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8177) [0]
	15	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8176) [0]
	16	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8175) [0]
	17	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8174) [0]
	18	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8173) [0]
	19	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8172) [0]
	20	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8171) [0]
	21	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8170) [0]
	22	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8169) [0]
	23	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8168) [0]
	24	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8167) [0]
	25	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8166) [0]
	26	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8165) [0]
	27	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8164) [0]
	28	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8163) [0]
	29	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8162) [0]
	30	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8161) [0]
	31	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8160) [0]
	32	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8159) [0]
	33	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8158) [0]
	34	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8157) [0]
	35	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8156) [0]
	36	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8155) [0]
	37	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8154) [0]
	38	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8153) [0]
	39	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8152) [0]
	40	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8151) [0]
	41	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8150) [0]
	42	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8149) [0]
	43	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8148) [0]
	44	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8147) [0]
	45	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8146) [0]
	46	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8145) [0]
	47	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8144) [0]
	48	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8143) [0]
	49	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8142) [0]
	50	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8141) [0]
	51	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8140) [0]
	52	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8139) [0]
	53	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8138) [0]
	54	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8137) [0]
	55	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8136) [0]
	56	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8135) [0]
	57	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8134) [0]
	58	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8133) [0]
	59	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8132) [0]
	60	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8131) [0]
	61	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8130) [0]
	62:63	TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.EFUSE.FUSE_DATA(8129:8130) [00]
Bit(s)	SCOM			Dial: Description
0:63	RO			REGISTER127: ROM location 127

FSI PIB2OPB command and write data
Addr:	0000000000020000 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.CMD_WRDAT
Constant(s):	PERV_PIB2OPB0_CMD_WRDAT
Comments:	pib2opb command/write-data register to access FSI Master ports via PIB FSI-0 Host access via ports / lower address is for host only
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.Q_CMD_REG.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.Q_WR_DATA_REG.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			WRITE_NOT_READ: write not read
1:31	RW			cmd
32:63	RW			wdata

FSI PIB2OPB Status and read data
Addr:	0000000000020001 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.STAT_RDDAT_ERRES
Constant(s):	PERV_PIB2OPB0_STAT_RDDAT_ERRES
Comments:	pib2opb status/read-data register to access FSI Master ports via PIB FSI-0 Host access via ports / lower address is for host only
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.STATUS_REG(0) [0]
	1:4	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.Q_PARITY_ERROR.FSILAT.LATCH.LATC.L2(0:3) [0000]
	5	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.CAP_ERR.L.FSILAT.LATCH.LATC.L2(0) [0]
	6	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.Q_PARITY_ERROR.FSILAT.LATCH.LATC.L2(4) [0]
	7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.Q_OPB_CMD_OVERRUN_ERROR.FSILAT.LATCH.LATC.L2(0) [0]
	8:9	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.CAP_ERR.L.FSILAT.LATCH.LATC.L2(1:2) [00]
	10	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.CAP_ERR.L.FSILAT.LATCH.LATC.L2(4) [0]
	11	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.CAP_ERR.L.FSILAT.LATCH.LATC.L2(3) [0]
	12	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.CAP_ERR.L.FSILAT.LATCH.LATC.L2(6) [0]
	13	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.CAP_ERR.L.FSILAT.LATCH.LATC.L2(5) [0]
	14	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.Q_RD_DATA_VALID.FSILAT.LATCH.LATC.L2(0) [0]
	15	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.Q_OPB_BUSY.FSILAT.LATCH.LATC.L2(0) [0]
	16:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.STATUS_REG(16:31) [0000000000000000]
	32:63	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.Q_RD_DATA_REG.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RO			any_error
1	RO			CMD_PARITY_ERROR: command parity check
2	RO			WR_DATA_PARITY_ERROR: write data parity check
3	RO			RD_DATA_PARITY_ERROR: read data parity check
4	RO			LCK_STATUS_PARITY_ERROR: locked status parity check
5	RO			FSM_PARITY_ERROR: OPB master protocol FSM parity check
6	RO
7	RO			OPB_command_overrun_error
8	RO			OPB_PARITY_ERROR: OPB read data parity check during valid
9	RO			OPB_protocol_error
10	RO			OPB_timeout_Bit
11	RO			OPB_errAck
12	RO			invalid_address
13	RO			port_is_fenced
14	RO			Read_data_valid
15	RO			OPB_busy_flag
16	RO			cM_any_master_error
17	RO			cM_any_port_interrupt
18	RO			cM_hot_plug_event
19	RO			cM_control_register_parity_interrupt
20	RO			cM_any_INTR_1_remote_slave_interrupt
21	RO			cM_any_INTR_2_remote_slave_interrupt
22:23	RO
24	RO			M_any_master_error
25	RO			M_any_port_interrupt
26	RO			M_hot_plug_event
27	RO			M_control_register_parity_interrupt
28	RO			M_any_INTR_1_remote_slave_interrupt
29	RO			M_any_INTR_2_remote_slave_interrupt
30:31	RO
32:63	RO			read_data

FSI PIB2OPB Locked status
Addr:	0000000000020002 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.LSTAT
Constant(s):	PERV_PIB2OPB0_LSTAT
Comments:	pib2opb FSI Master ports locked status via PIB FSI-0 Host access via ports / lower address is for host only
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.Q_LCK_STATUS_REG.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	RO
32:63	RO			constant=0b00000000000000000000000000000000

PIB2OPB unit reset
Addr:	0000000000020004 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.RESET
Constant(s):	PERV_PIB2OPB0_RESET
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WO_1P			reset Unit Reset

FSI PIB2OPB cMFSI Remote Slave Interrupt
Addr:	0000000000020005 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.CRSIC
Constant(s):	PERV_PIB2OPB0_CRSIC
Comments:	pib2opb Interrupts of cMFSI port attached FSI slaves read/clear via PIB FSI-0 Host access via ports / lower address is for host only
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.OB.L#0.Q_MST_REMOTE_SLV_INTR.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW_WCLEAR

FSI PIB2OPB cMFSI Remote Slave Interrupt Mask
Addr:	0000000000020006 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.CRSIM
Constant(s):	PERV_PIB2OPB0_CRSIM
Comments:	pib2opb Mask for Interrupts of cMFSI port attached FSI slaves read/write via PIB FSI-0 Host access via ports / lower address is for host only
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.OB.L#0.I_MASK_REGS.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW

FSI PIB2OPB cMFSI Remote Slave Interrupt Status
Addr:	0000000000020007 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.CRSIS
Constant(s):	PERV_PIB2OPB0_CRSIS
Comments:	pib2opb Status of Interrupts of cMFSI port attached FSI slaves PIB read via PIB FSI-0 Host access via ports / lower address is for host only
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.OPB_INT_DOUT(128:191) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RO

FSI PIB2OPB MFSI Remote Slave Interrupt
Addr:	0000000000020008 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.RSIC
Constant(s):	PERV_PIB2OPB0_RSIC
Comments:	pib2opb Interrupts of MFSI port attached FSI slaves read/clear via PIB FSI-0 Host access via ports / lower address is for host only
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.OB.L#1.Q_MST_REMOTE_SLV_INTR.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW_WCLEAR

FSI PIB2OPB MFSI Remote Slave Interrupt Mask
Addr:	0000000000020009 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.RSIM
Constant(s):	PERV_PIB2OPB0_RSIM
Comments:	pib2opb Mask for Interrupts of MFSI port attached FSI slaves read/write via PIB FSI-0 Host access via ports / lower address is for host only
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.OB.L#1.I_MASK_REGS.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW

FSI PIB2OPB MFSI Remote Slave Interrupt Status
Addr:	000000000002000A (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.RSIS
Constant(s):	PERV_PIB2OPB0_RSIS
Comments:	pib2opb Status of Interrupts of MFSI port attached FSI slaves PIB read via PIB FSI-0 Host access via ports / lower address is for host only
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.OPB_INT_DOUT(320:383) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RO

FSI PIB2OPB command and write data
Addr:	0000000000020010 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.CMD_WRDAT
Constant(s):	PERV_PIB2OPB1_CMD_WRDAT
Comments:	pib2opb command/write-data register to access FSI Master ports via PIB FSI-0 Host access via ports / lower address is for host only
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.Q_CMD_REG.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.Q_WR_DATA_REG.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			WRITE_NOT_READ: write not read
1:31	RW			cmd
32:63	RW			wdata

FSI PIB2OPB Status and read data
Addr:	0000000000020011 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.STAT_RDDAT_ERRES
Constant(s):	PERV_PIB2OPB1_STAT_RDDAT_ERRES
Comments:	pib2opb status/read-data register to access FSI Master ports via PIB FSI-0 Host access via ports / lower address is for host only
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.STATUS_REG(0) [0]
	1:4	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.Q_PARITY_ERROR.FSILAT.LATCH.LATC.L2(0:3) [0000]
	5	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.CAP_ERR.L.FSILAT.LATCH.LATC.L2(0) [0]
	6	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.Q_PARITY_ERROR.FSILAT.LATCH.LATC.L2(4) [0]
	7	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.Q_OPB_CMD_OVERRUN_ERROR.FSILAT.LATCH.LATC.L2(0) [0]
	8:9	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.CAP_ERR.L.FSILAT.LATCH.LATC.L2(1:2) [00]
	10	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.CAP_ERR.L.FSILAT.LATCH.LATC.L2(4) [0]
	11	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.CAP_ERR.L.FSILAT.LATCH.LATC.L2(3) [0]
	12	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.CAP_ERR.L.FSILAT.LATCH.LATC.L2(6) [0]
	13	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.CAP_ERR.L.FSILAT.LATCH.LATC.L2(5) [0]
	14	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.Q_RD_DATA_VALID.FSILAT.LATCH.LATC.L2(0) [0]
	15	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.Q_OPB_BUSY.FSILAT.LATCH.LATC.L2(0) [0]
	16:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.STATUS_REG(16:31) [0000000000000000]
	32:63	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.Q_RD_DATA_REG.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RO			any_error
1	RO			CMD_PARITY_ERROR: command parity check
2	RO			WR_DATA_PARITY_ERROR: write data parity check
3	RO			RD_DATA_PARITY_ERROR: read data parity check
4	RO			LCK_STATUS_PARITY_ERROR: locked status parity check
5	RO			FSM_PARITY_ERROR: OPB master protocol FSM parity check
6	RO
7	RO			OPB_command_overrun_error
8	RO			OPB_PARITY_ERROR: OPB read data parity check during valid
9	RO			OPB_protocol_error
10	RO			OPB_timeout_Bit
11	RO			OPB_errAck
12	RO			invalid_address
13	RO			port_is_fenced
14	RO			Read_data_valid
15	RO			OPB_busy_flag
16	RO			cM_any_master_error
17	RO			cM_any_port_interrupt
18	RO			cM_hot_plug_event
19	RO			cM_control_register_parity_interrupt
20	RO			cM_any_INTR_1_remote_slave_interrupt
21	RO			cM_any_INTR_2_remote_slave_interrupt
22:23	RO
24	RO			M_any_master_error
25	RO			M_any_port_interrupt
26	RO			M_hot_plug_event
27	RO			M_control_register_parity_interrupt
28	RO			M_any_INTR_1_remote_slave_interrupt
29	RO			M_any_INTR_2_remote_slave_interrupt
30:31	RO
32:63	RO			read_data

FSI PIB2OPB Locked status
Addr:	0000000000020012 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.LSTAT
Constant(s):	PERV_PIB2OPB1_LSTAT
Comments:	pib2opb FSI Master ports locked status via PIB FSI-0 Host access via ports / lower address is for host only
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.Q_LCK_STATUS_REG.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	RO
32:63	RO			constant=0b00000000000000000000000000000000

PIB2OPB unit reset
Addr:	0000000000020014 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.RESET
Constant(s):	PERV_PIB2OPB1_RESET
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WO_1P			reset Unit Reset

FSI PIB2OPB cMFSI Remote Slave Interrupt
Addr:	0000000000020015 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.CRSIC
Constant(s):	PERV_PIB2OPB1_CRSIC
Comments:	pib2opb Interrupts of cMFSI port attached FSI slaves read/clear via PIB FSI-0 Host access via ports / lower address is for host only
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.OB.L#0.Q_MST_REMOTE_SLV_INTR.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW_WCLEAR

FSI PIB2OPB cMFSI Remote Slave Interrupt Mask
Addr:	0000000000020016 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.CRSIM
Constant(s):	PERV_PIB2OPB1_CRSIM
Comments:	pib2opb Mask for Interrupts of cMFSI port attached FSI slaves read/write via PIB FSI-0 Host access via ports / lower address is for host only
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.OB.L#0.I_MASK_REGS.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW

FSI PIB2OPB cMFSI Remote Slave Interrupt Status
Addr:	0000000000020017 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.CRSIS
Constant(s):	PERV_PIB2OPB1_CRSIS
Comments:	pib2opb Status of Interrupts of cMFSI port attached FSI slaves PIB read via PIB FSI-0 Host access via ports / lower address is for host only
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.OPB_INT_DOUT(128:191) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RO

FSI PIB2OPB MFSI Remote Slave Interrupt
Addr:	0000000000020018 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.RSIC
Constant(s):	PERV_PIB2OPB1_RSIC
Comments:	pib2opb Interrupts of MFSI port attached FSI slaves read/clear via PIB FSI-0 Host access via ports / lower address is for host only
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.OB.L#1.Q_MST_REMOTE_SLV_INTR.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW_WCLEAR

FSI PIB2OPB MFSI Remote Slave Interrupt Mask
Addr:	0000000000020019 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.RSIM
Constant(s):	PERV_PIB2OPB1_RSIM
Comments:	pib2opb Mask for Interrupts of MFSI port attached FSI slaves read/write via PIB FSI-0 Host access via ports / lower address is for host only
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.OB.L#1.I_MASK_REGS.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW

FSI PIB2OPB MFSI Remote Slave Interrupt Status
Addr:	000000000002001A (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.RSIS
Constant(s):	PERV_PIB2OPB1_RSIS
Comments:	pib2opb Status of Interrupts of MFSI port attached FSI slaves PIB read via PIB FSI-0 Host access via ports / lower address is for host only
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.OPB_INT_DOUT(320:383) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RO

TOD: master paths control register: setup for: - oscillator validity - STEP alignment - SYNC pulse frequency - STEP check
Addr:	0000000000040000 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_M_PATH_CTRL_REG
Constant(s):	PERV_TOD_M_PATH_CTRL_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X00.LATCH_DATA.DATA_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			M_PATH_0_OSC_NOT_VALID: Master path-0: oscillator not valid OFF: valid oscillator is attached to master path-0 ON: no valid oscillator is attached to master path-0
1	RW			M_PATH_1_OSC_NOT_VALID: Master path-1: oscillator not valid OFF: valid oscillator is attached to master path-1 ON: no valid oscillator is attached to master path-1
2	RW			M_PATH_0_STEP_ALIGN_DISABLE: Master path-0: STEP alignment disable OFF: alignment of master path-0 STEP to master path-1 STEP is active ON: alignment of master path-0 STEP to master path-1 STEP is not active
3	RW			M_PATH_1_STEP_ALIGN_DISABLE: Master path-1: STEP alignment disable OFF: alignment of master path-1 STEP to master path-0 STEP is active ON: alignment of master path-1 STEP to master path-0 STEP is not active
4	RW			M_PATH_STEP_CREATE_DUAL_EDGE_DISABLE: Master path-01: STEP create: dual edge disable OFF: sample both edges of the oscillator ON: sample only the rising edge of the oscillator
5:7	RW			M_PATH_SYNC_CREATE_SPS_SELECT: Master path: SYNC create: Steps Per SYNC (SPS) select Number of STEP pulses per SYNC pulse. Dial enums: 512_STEPS=>0b000 128_STEPS=>0b001 64_STEPS=>0b010 32_STEPS=>0b011 4096_STEPS=>0b100 2048_STEPS=>0b101 1024_STEPS=>0b110 256_STEPS=>0b111
8:11	RW			M_PATH_0_STEP_CHECK_CPS_DEVIATION: Master path-0: STEP check: CPS deviation Dial enums: 00_00_PCENT=>0b0000 06_25_PCENT=>0b0001 12_50_PCENT=>0b0010 18_75_PCENT=>0b0011 25_00_PCENT=>0b0100 31_25_PCENT=>0b0101 37_50_PCENT=>0b0110 43_75_PCENT=>0b0111 50_00_PCENT=>0b1000 56_25_PCENT=>0b1001 62_50_PCENT=>0b1010 68_75_PCENT=>0b1011 75_00_PCENT=>0b1100 81_25_PCENT=>0b1101 87_50_PCENT=>0b1110 93_75_PCENT=>0b1111
12	RW			M_PATH_0_STEP_CHECK_CONSTANT_CPS_ENABLE: Master path-0: STEP check: constant CPS enable OFF: measured CPS is used for the STEP check CPS deviation ON: constant CPS is used for the STEP check CPS deviation
13:15	RW			M_PATH_0_STEP_CHECK_VALIDITY_COUNT: Master path-0: STEP check: validity count Defines the number of received STEPs before the STEP is declared as valid. Dial enums: 1_STEPS=>0b000 2_STEPS=>0b001 4_STEPS=>0b010 8_STEPS=>0b011 16_STEPS=>0b100 32_STEPS=>0b101 64_STEPS=>0b110 128_STEPS=>0b111
16:19	RW			M_PATH_1_STEP_CHECK_CPS_DEVIATION: Master path-1: STEP check: CPS deviation Dial enums: 00_00_PCENT=>0b0000 06_25_PCENT=>0b0001 12_50_PCENT=>0b0010 18_75_PCENT=>0b0011 25_00_PCENT=>0b0100 31_25_PCENT=>0b0101 37_50_PCENT=>0b0110 43_75_PCENT=>0b0111 50_00_PCENT=>0b1000 56_25_PCENT=>0b1001 62_50_PCENT=>0b1010 68_75_PCENT=>0b1011 75_00_PCENT=>0b1100 81_25_PCENT=>0b1101 87_50_PCENT=>0b1110 93_75_PCENT=>0b1111
20	RW			M_PATH_1_STEP_CHECK_CONSTANT_CPS_ENABLE: Master path-1: STEP check: constant CPS enable OFF: measured CPS is used for the STEP check CPS deviation ON: constant CPS is used for the STEP check CPS deviation
21:23	RW			M_PATH_1_STEP_CHECK_VALIDITY_COUNT: Master path-1: STEP check: validity count. Defines the number of received STEPs before the STEP is declared as valid. Dial enums: 1_STEPS=>0b000 2_STEPS=>0b001 4_STEPS=>0b010 8_STEPS=>0b011 16_STEPS=>0b100 32_STEPS=>0b101 64_STEPS=>0b110 128_STEPS=>0b111
24:25	RW			M_PATH_STEP_CHECK_CPS_DEVIATION_FACTOR: Master path-01: STEP check: CPS deviation factor Dial enums: 1=>0b00 2=>0b01 4=>0b10 8=>0b11
26	RW			M_PATH_0_LOCAL_STEP_MODE_ENABLE: Master path-0: local step mode: enable OFF: steps are generated from the 16MHz oscillator-0 ON: steps are generated locally using mesh-clock
27	RW			M_PATH_1_LOCAL_STEP_MODE_ENABLE: Master path-1: local step mode: enable OFF: steps are generated from the 16MHz oscillator-0 ON: steps are generated locally using mesh-clock
28	RW			M_PATH_0_STEP_STEER_ENABLE: Master path-0: step steering enable OFF: steering of master path-0 step is not active ON: steering of master path-0 step is active
29	RW			M_PATH_1_STEP_STEER_ENABLE: Master path-1: step steering enable OFF: steering of master path-1 step is not active ON: steering of master path-1 step is active
30	RW			M_PATH_0_STEP_ALIGN_CLKGATE_DISABLE: Master path-0: step align clock gating disable OFF: Reg_0x00(2) controls clock gating of step align component ON: Reg_0x00(2) does NOT control clock gating of step align component
31	RW			M_PATH_1_STEP_ALIGN_CLKGATE_DISABLE: Master path-0: step align clock gating disable OFF: Reg_0x00(3) controls clock gating of step align component ON: Reg_0x00(3) does NOT control clock gating of step align component
32:63	RO			constant=0b00000000000000000000000000000000

TOD: primary configuration: distribution port-0 control register
Addr:	0000000000040001 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_PRI_PORT_0_CTRL_REG
Constant(s):	PERV_TOD_PRI_PORT_0_CTRL_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:39	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X01.LATCH_DATA.DATA_Q_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:2	RW			PRI_PORT_0_RX_SELECT: Distribution: primary configuration: port-0 rx select: Dial enums: X0_PORT_0=>0b000 X1_PORT_0=>0b001 X2_PORT_0=>0b010 X3_PORT_0=>0b011 X4_PORT_0=>0b100 X5_PORT_0=>0b101 X6_PORT_0=>0b110 X7_PORT_0=>0b111
3	RW			REG_0X01_SPARE_03: spares
4:5	RWX			PRI_X0_PORT_0_TX_SELECT: Distribution: primary configuration: X0 port-0 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
6:7	RWX			PRI_X1_PORT_0_TX_SELECT: Distribution: primary configuration: X1 port-0 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
8:9	RWX			PRI_X2_PORT_0_TX_SELECT: Distribution: primary configuration: X2 port-0 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
10:11	RWX			PRI_X3_PORT_0_TX_SELECT: Distribution: primary configuration: X3 port-0 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
12:13	RWX			PRI_X4_PORT_0_TX_SELECT: Distribution: primary configuration: X4 port-0 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
14:15	RWX			PRI_X5_PORT_0_TX_SELECT: Distribution: primary configuration: X5 port-0 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
16:17	RWX			PRI_X6_PORT_0_TX_SELECT: Distribution: primary configuration: X6 port-0 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
18:19	RWX			PRI_X7_PORT_0_TX_SELECT: Distribution: primary configuration: X7 port-0 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
20	RW			PRI_X0_PORT_0_TX_ENABLE: Distribution: primary configuration: X0 port-0 tx enable OFF: port configured as receiver ON: port configured as sender
21	RW			PRI_X1_PORT_0_TX_ENABLE: Distribution: primary configuration: X1 port-0 tx enable OFF: port configured as receiver ON: port configured as sender
22	RW			PRI_X2_PORT_0_TX_ENABLE: Distribution: primary configuration: X2 port-0 tx enable OFF: port configured as receiver ON: port configured as sender
23	RW			PRI_X3_PORT_0_TX_ENABLE: Distribution: primary configuration: X3 port-0 tx enable OFF: port configured as receiver ON: port configured as sender
24	RW			PRI_X4_PORT_0_TX_ENABLE: Distribution: primary configuration: X4 port-0 tx enable OFF: port configured as receiver ON: port configured as sender
25	RW			PRI_X5_PORT_0_TX_ENABLE: Distribution: primary configuration: X5 port-0 tx enable OFF: port configured as receiver ON: port configured as sender
26	RW			PRI_X6_PORT_0_TX_ENABLE: Distribution: primary configuration: X6 port-0 tx enable OFF: port configured as receiver ON: port configured as sender
27	RW			PRI_X7_PORT_0_TX_ENABLE: Distribution: primary configuration: X7 port-0 tx enable OFF: port configured as receiver ON: port configured as sender
28:29	RW			REG_0X01_SPARE_28_29: Spares
30:39	RW			PRI_I_PATH_DELAY_VALUE: Internal path: primary configuration: delay value
40:63	RO			constant=0b000000000000000000000000

TOD: primary configuration: distribution port-1 control register
Addr:	0000000000040002 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_PRI_PORT_1_CTRL_REG
Constant(s):	PERV_TOD_PRI_PORT_1_CTRL_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X02.LATCH_DATA.DATA_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:2	RW			PRI_PORT_1_RX_SELECT: Distribution: primary configuration: port-1 rx select: Dial enums: X0_PORT_1=>0b000 X1_PORT_1=>0b001 X2_PORT_1=>0b010 X3_PORT_1=>0b011 X4_PORT_1=>0b100 X5_PORT_1=>0b101 X6_PORT_1=>0b110 X7_PORT_1=>0b111
3	RW			REG_0X02_SPARE_03: spares
4:5	RWX			PRI_X0_PORT_1_TX_SELECT: Distribution: primary configuration: X0 port-1 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
6:7	RWX			PRI_X1_PORT_1_TX_SELECT: Distribution: primary configuration: X1 port-1 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
8:9	RWX			PRI_X2_PORT_1_TX_SELECT: Distribution: primary configuration: X2 port-1 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
10:11	RWX			PRI_X3_PORT_1_TX_SELECT: Distribution: primary configuration: X3 port-1 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
12:13	RWX			PRI_X4_PORT_1_TX_SELECT: Distribution: primary configuration: X4 port-1 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
14:15	RWX			PRI_X5_PORT_1_TX_SELECT: Distribution: primary configuration: X5 port-1 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
16:17	RWX			PRI_X6_PORT_1_TX_SELECT: Distribution: primary configuration: X6 port-1 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
18:19	RWX			PRI_X7_PORT_1_TX_SELECT: Distribution: primary configuration: X7 port-1 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
20	RW			PRI_X0_PORT_1_TX_ENABLE: Distribution: primary configuration: X0 port-1 tx enable OFF: port configured as receiver ON: port configured as sender
21	RW			PRI_X1_PORT_1_TX_ENABLE: Distribution: primary configuration: X1 port-1 tx enable OFF: port configured as receiver ON: port configured as sender
22	RW			PRI_X2_PORT_1_TX_ENABLE: Distribution: primary configuration: X2 port-1 tx enable OFF: port configured as receiver ON: port configured as sender
23	RW			PRI_X3_PORT_1_TX_ENABLE: Distribution: primary configuration: X3 port-1 tx enable OFF: port configured as receiver ON: port configured as sender
24	RW			PRI_X4_PORT_1_TX_ENABLE: Distribution: primary configuration: X4 port-1 tx enable OFF: port configured as receiver ON: port configured as sender
25	RW			PRI_X5_PORT_1_TX_ENABLE: Distribution: primary configuration: X5 port-1 tx enable OFF: port configured as receiver ON: port configured as sender
26	RW			PRI_X6_PORT_1_TX_ENABLE: Distribution: primary configuration: X6 port-1 tx enable OFF: port configured as receiver ON: port configured as sender
27	RW			PRI_X7_PORT_1_TX_ENABLE: Distribution: primary configuration: X7 port-1 tx enable OFF: port configured as receiver ON: port configured as sender
28:31	RW			REG_0X02_SPARE_28_31: Spares
32:63	RO			constant=0b00000000000000000000000000000000

TOD: secondary configuration: distribution port-0 control register
Addr:	0000000000040003 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_SEC_PORT_0_CTRL_REG
Constant(s):	PERV_TOD_SEC_PORT_0_CTRL_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:39	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X03.LATCH_DATA.DATA_Q_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:2	RW			SEC_PORT_0_RX_SELECT: Distribution: secondary configuration: port-0 rx select: Dial enums: X0_PORT_0=>0b000 X1_PORT_0=>0b001 X2_PORT_0=>0b010 X3_PORT_0=>0b011 X4_PORT_0=>0b100 X5_PORT_0=>0b101 X6_PORT_0=>0b110 X7_PORT_0=>0b111
3	RW			REG_0X03_SPARE_03: spares
4:5	RWX			SEC_X0_PORT_0_TX_SELECT: Distribution: secondary configuration: X0 port-0 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
6:7	RWX			SEC_X1_PORT_0_TX_SELECT: Distribution: secondary configuration: X1 port-0 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
8:9	RWX			SEC_X2_PORT_0_TX_SELECT: Distribution: secondary configuration: X2 port-0 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
10:11	RWX			SEC_X3_PORT_0_TX_SELECT: Distribution: secondary configuration: X3 port-0 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
12:13	RWX			SEC_X4_PORT_0_TX_SELECT: Distribution: secondary configuration: X4 port-0 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
14:15	RWX			SEC_X5_PORT_0_TX_SELECT: Distribution: secondary configuration: X5 port-0 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
16:17	RWX			SEC_X6_PORT_0_TX_SELECT: Distribution: secondary configuration: X6 port-0 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
18:19	RWX			SEC_X7_PORT_0_TX_SELECT: Distribution: secondary configuration: X7 port-0 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
20	RW			SEC_X0_PORT_0_TX_ENABLE: Distribution: secondary configuration: X0 port-0 tx enable OFF: port configured as receiver ON: port configured as sender
21	RW			SEC_X1_PORT_0_TX_ENABLE: Distribution: secondary configuration: X1 port-0 tx enable OFF: port configured as receiver ON: port configured as sender
22	RW			SEC_X2_PORT_0_TX_ENABLE: Distribution: secondary configuration: X2 port-0 tx enable OFF: port configured as receiver ON: port configured as sender
23	RW			SEC_X3_PORT_0_TX_ENABLE: Distribution: secondary configuration: X3 port-0 tx enable OFF: port configured as receiver ON: port configured as sender
24	RW			SEC_X4_PORT_0_TX_ENABLE: Distribution: secondary configuration: X4 port-0 tx enable OFF: port configured as receiver ON: port configured as sender
25	RW			SEC_X5_PORT_0_TX_ENABLE: Distribution: secondary configuration: X5 port-0 tx enable OFF: port configured as receiver ON: port configured as sender
26	RW			SEC_X6_PORT_0_TX_ENABLE: Distribution: secondary configuration: X6 port-0 tx enable OFF: port configured as receiver ON: port configured as sender
27	RW			SEC_X7_PORT_0_TX_ENABLE: Distribution: secondary configuration: X7 port-0 tx enable OFF: port configured as receiver ON: port configured as sender
28:29	RW			REG_0X03_SPARE_28_29: Spares
30:39	RW			SEC_I_PATH_DELAY_VALUE: Internal path: secondary configuration: delay value
40:63	RO			constant=0b000000000000000000000000

TOD: secondary configuration: distribution port-1 control register
Addr:	0000000000040004 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_SEC_PORT_1_CTRL_REG
Constant(s):	PERV_TOD_SEC_PORT_1_CTRL_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X04.LATCH_DATA.DATA_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:2	RW			SEC_PORT_1_RX_SELECT: Distribution: secondary configuration: port-1 rx select: Dial enums: X0_PORT_0=>0b000 X1_PORT_0=>0b001 X2_PORT_0=>0b010 X3_PORT_0=>0b011 X4_PORT_0=>0b100 X5_PORT_0=>0b101 X6_PORT_0=>0b110 X7_PORT_0=>0b111
3	RW			REG_0X04_SPARE_03: spares
4:5	RWX			SEC_X0_PORT_1_TX_SELECT: Distribution: secondary configuration: X0 port-1 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
6:7	RWX			SEC_X1_PORT_1_TX_SELECT: Distribution: secondary configuration: X1 port-1 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
8:9	RWX			SEC_X2_PORT_1_TX_SELECT: Distribution: secondary configuration: X2 port-1 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
10:11	RWX			SEC_X3_PORT_1_TX_SELECT: Distribution: secondary configuration: X3 port-1 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
12:13	RWX			SEC_X4_PORT_1_TX_SELECT: Distribution: secondary configuration: X4 port-1 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
14:15	RWX			SEC_X5_PORT_1_TX_SELECT: Distribution: secondary configuration: X5 port-1 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
16:17	RWX			SEC_X6_PORT_1_TX_SELECT: Distribution: secondary configuration: X6 port-1 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
18:19	RWX			SEC_X7_PORT_1_TX_SELECT: Distribution: secondary configuration: X7 port-1 tx select: Dial enums: S_PATH_0=>0b00 S_PATH_1=>0b01 M_PATH_0=>0b10 M_PATH_1=>0b11
20	RW			SEC_X0_PORT_1_TX_ENABLE: Distribution: secondary configuration: X0 port-1 tx enable OFF: port configured as receiver ON: port configured as sender
21	RW			SEC_X1_PORT_1_TX_ENABLE: Distribution: secondary configuration: X1 port-1 tx enable OFF: port configured as receiver ON: port configured as sender
22	RW			SEC_X2_PORT_1_TX_ENABLE: Distribution: secondary configuration: X2 port-1 tx enable OFF: port configured as receiver ON: port configured as sender
23	RW			SEC_X3_PORT_1_TX_ENABLE: Distribution: secondary configuration: X3 port-1 tx enable OFF: port configured as receiver ON: port configured as sender
24	RW			SEC_X4_PORT_1_TX_ENABLE: Distribution: secondary configuration: X4 port-1 tx enable OFF: port configured as receiver ON: port configured as sender
25	RW			SEC_X5_PORT_1_TX_ENABLE: Distribution: secondary configuration: X5 port-1 tx enable OFF: port configured as receiver ON: port configured as sender
26	RW			SEC_X6_PORT_1_TX_ENABLE: Distribution: secondary configuration: X6 port-1 tx enable OFF: port configured as receiver ON: port configured as sender
27	RW			SEC_X7_PORT_1_TX_ENABLE: Distribution: secondary configuration: X7 port-1 tx enable OFF: port configured as receiver ON: port configured as sender
28:31	RW			REG_0X04_SPARE_28_31: Spares
32:63	RO			constant=0b00000000000000000000000000000000

TOD: slave path control register
Addr:	0000000000040005 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_S_PATH_CTRL_REG
Constant(s):	PERV_TOD_S_PATH_CTRL_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:39	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X05.LATCH_DATA.DATA_Q_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			PRI_S_PATH_SELECT: Primary configuration: slave path select
1	RW			REG_0X05_SPARE_01: spares
2	RW			S_PATH_M_PATH_CPS_ENABLE: Slave path-01: use of master path CPS: enable OFF: do not use master path CPS ON: use master path CPS
3	RW			S_PATH_REMOTE_SYNC_DISABLE: Slave path-01: remote SYNC: disable OFF: use SYNCs from maser TOD, STEPs are generated locally ON: use STEPsSYNCs from master TOD
4	RW			SEC_S_PATH_SELECT: Secondary configuration: slave path select
5	RW			REG_0X05_SPARE_05: spares
6:7	RW			S_PATH_STEP_CHECK_CPS_DEVIATION_FACTOR: Slave path-01: STEP check: CPS deviation factor Dial enums: 1=>0b00 2=>0b01 4=>0b10 8=>0b11
8:11	RW			S_PATH_0_STEP_CHECK_CPS_DEVIATION: Slave path-0: STEP check: CPS deviation Dial enums: 00_00_PCENT=>0b0000 06_25_PCENT=>0b0001 12_50_PCENT=>0b0010 18_75_PCENT=>0b0011 25_00_PCENT=>0b0100 31_25_PCENT=>0b0101 37_50_PCENT=>0b0110 43_75_PCENT=>0b0111 50_00_PCENT=>0b1000 56_25_PCENT=>0b1001 62_50_PCENT=>0b1010 68_75_PCENT=>0b1011 75_00_PCENT=>0b1100 81_25_PCENT=>0b1101 87_50_PCENT=>0b1110 93_75_PCENT=>0b1111
12	RW			S_PATH_0_STEP_CHECK_CONSTANT_CPS_ENABLE: Slave path-0: STEP check: constant CPS enable OFF: measured CPS is used for the STEP check CPS deviation ON: constant CPS is used for the STEP check CPS deviation
13:15	RW			S_PATH_0_STEP_CHECK_VALIDITY_COUNT: Slave path-0: STEP check: validity count. Defines the number of received STEPs before the STEP is declared as valid. is enabled. Dial enums: 1_STEPS=>0b000 2_STEPS=>0b001 4_STEPS=>0b010 8_STEPS=>0b011 16_STEPS=>0b100 32_STEPS=>0b101 64_STEPS=>0b110 128_STEPS=>0b111
16:19	RW			S_PATH_1_STEP_CHECK_CPS_DEVIATION: Slave path-1: STEP check: CPS deviation Dial enums: 00_00_PCENT=>0b0000 06_25_PCENT=>0b0001 12_50_PCENT=>0b0010 18_75_PCENT=>0b0011 25_00_PCENT=>0b0100 31_25_PCENT=>0b0101 37_50_PCENT=>0b0110 43_75_PCENT=>0b0111 50_00_PCENT=>0b1000 56_25_PCENT=>0b1001 62_50_PCENT=>0b1010 68_75_PCENT=>0b1011 75_00_PCENT=>0b1100 81_25_PCENT=>0b1101 87_50_PCENT=>0b1110 93_75_PCENT=>0b1111
20	RW			S_PATH_1_STEP_CHECK_CONSTANT_CPS_ENABLE: Slave path-1: STEP check: constant CPS enable OFF: measured CPS is used for the STEP check CPS deviation ON: constant CPS is used for the STEP check CPS deviation
21:23	RW			S_PATH_1_STEP_CHECK_VALIDITY_COUNT: Slave path-1: STEP check: validity count Defines the number of received STEPs before the STEP is declared as valid. Dial enums: 1_STEPS=>0b000 2_STEPS=>0b001 4_STEPS=>0b010 8_STEPS=>0b011 16_STEPS=>0b100 32_STEPS=>0b101 64_STEPS=>0b110 128_STEPS=>0b111
24	RW			S_PATH_REMOTE_SYNC_ERROR_DISABLE: Slave path-01: remote SYNC: error disable OFF: enable remote SYNC error as a STEP error ON: do not enable remote SYNC error as a STEP error
25	RW			S_PATH_REMOTE_SYNC_CHECK_M_CPS_DISABLE: Slave path-01: remote SYNC: SYNC-STEP check: disable use of master path CPS OFF: use master path CPS ON: do not use master path CPS
26:27	RW			S_PATH_REMOTE_SYNC_CHECK_CPS_DEVIATION_FACTOR: Slave path-01: remote SYNC: SYNC-STEP check: CPS deviation factor Dial enums: 1=>0b00 2=>0b01 4=>0b10 8=>0b11
28:31	RW			S_PATH_REMOTE_SYNC_CHECK_CPS_DEVIATION: Slave path-01: remote SYNC: SYNC-STEP check: CPS deviation Dial enums: 00_00_PCENT=>0b0000 06_25_PCENT=>0b0001 12_50_PCENT=>0b0010 18_75_PCENT=>0b0011 25_00_PCENT=>0b0100 31_25_PCENT=>0b0101 37_50_PCENT=>0b0110 43_75_PCENT=>0b0111 50_00_PCENT=>0b1000 56_25_PCENT=>0b1001 62_50_PCENT=>0b1010 68_75_PCENT=>0b1011 75_00_PCENT=>0b1100 81_25_PCENT=>0b1101 87_50_PCENT=>0b1110 93_75_PCENT=>0b1111
32:39	RW			S_PATH_REMOTE_SYNC_MISS_COUNT_MAX: Slave path-01: remote SYNC: maximum of SYNC miss counts: 0 - 255 SYNCs
40:63	RO			constant=0b000000000000000000000000

TOD: internal path control register
Addr:	0000000000040006 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_I_PATH_CTRL_REG
Constant(s):	PERV_TOD_I_PATH_CTRL_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:39	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X06.LATCH_DATA.DATA_Q_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			I_PATH_DELAY_DISABLE: internal path: delay disable OFF: delay enabled ON: delay disabled
1	RW			I_PATH_DELAY_ADJUST_DISABLE: internal path: delay adjust disable OFF: delay adjust enabled ON: delay adjust disabled
2:4	RW			REG_0X06_SPARE_02_04: spares
5	RW			I_PATH_STEP_CHECK_STEP_SELECT: internal path: STEP check: STEP select OFF: STEP from master or slave path is checked ON: STEP sent to the core is checked
6:7	RWX			I_PATH_STEP_CHECK_CPS_DEVIATION_FACTOR: internal path: STEP check: CPS deviation factor Dial enums: 1=>0b00 2=>0b01 4=>0b10 8=>0b11
8:11	RW			I_PATH_STEP_CHECK_CPS_DEVIATION: internal path: STEP check: CPS deviation Dial enums: 00_00_PCENT=>0b0000 06_25_PCENT=>0b0001 12_50_PCENT=>0b0010 18_75_PCENT=>0b0011 25_00_PCENT=>0b0100 31_25_PCENT=>0b0101 37_50_PCENT=>0b0110 43_75_PCENT=>0b0111 50_00_PCENT=>0b1000 56_25_PCENT=>0b1001 62_50_PCENT=>0b1010 68_75_PCENT=>0b1011 75_00_PCENT=>0b1100 81_25_PCENT=>0b1101 87_50_PCENT=>0b1110 93_75_PCENT=>0b1111
12	RW			I_PATH_STEP_CHECK_CONSTANT_CPS_ENABLE: internal path: STEP check: constant CPS enable OFF: measured CPS is used for the STEP check CPS deviation ON: constant CPS is used for the STEP check CPS deviation
13:15	RW			I_PATH_STEP_CHECK_VALIDITY_COUNT: internal path: STEP check: validity count Defines the number of received STEPs before the STEP is declared as valid. Dial enums: 1_STEPS=>0b000 2_STEPS=>0b001 4_STEPS=>0b010 8_STEPS=>0b011 16_STEPS=>0b100 32_STEPS=>0b101 64_STEPS=>0b110 128_STEPS=>0b111
16:21	RW			REG_0X06_SPARE_16_21: spares
22:31	ROX			I_PATH_DELAY_ADJUST_VALUE: internal path: adjusted delay value: if the adjustment is enable then the value indicates the adjusted delay value otherwise it indicates the raw delay(primary or secondary).
32:39	RWX			I_PATH_CPS: internal path: CPS: in write mode the value is used to load the CPS for the constant CPS for the STEP checker. in read mode the value shows the actual CPS in the internal path.
40:63	RO			constant=0b000000000000000000000000

TOD: primary/secondary configuration control register: - master/slave select - master path select - slave path select - STEP check setup
Addr:	0000000000040007 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_PSS_MSS_CTRL_REG
Constant(s):	PERV_TOD_PSS_MSS_CTRL_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X07.LATCH_DATA.DATA_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RWX			PRI_M_PATH_SELECT: Primary configuration: master path select. OFF: master path-0 is selected ON: master path-1 is selected
1	RWX			PRI_M_S_TOD_SELECT: Primary configuration: master-slave TOD select. OFF: TOD is slave ON: TOD is master
2	RWX			PRI_M_S_DRAWER_SELECT: Primary configuration: master-slave drawer select OFF: Drawer is slave ON = Drawer is master It is just used for TOD internal power gating.
3	RWX			PRI_S_PATH_1_STEP_CHECK_ENABLE: Primary configuration: slave path-1: STEP check enable OFF: STEP check disabled ON: STEP check enabled
4	RWX			PRI_M_PATH_0_STEP_CHECK_ENABLE: Primary configuration: master path-0: STEP check enable OFF: STEP check disabled ON: STEP check enabled
5	RWX			PRI_M_PATH_1_STEP_CHECK_ENABLE: Primary configuration: master path-1: STEP check enable OFF: STEP check disabled ON: STEP check enabled
6	RWX			PRI_S_PATH_0_STEP_CHECK_ENABLE: Primary configuration: slave path-0: STEP check enable OFF: STEP check disabled ON: STEP check enabled
7	RWX			PRI_I_PATH_STEP_CHECK_ENABLE: Primary configuration: internal path: STEP check enable OFF: STEP check disabled ON: STEP check enabled
8	RWX			SEC_M_PATH_SELECT: Secondary configuration: master path select OFF: master path-0 is selected ON: master path-1 is selected
9	RWX			SEC_M_S_TOD_SELECT: Secondary configuration: master-slave TOD select OFF: TOD is slave ON: TOD is master
10	RWX			SEC_M_S_DRAWER_SELECT: Secondary configuration: master-slave drawer select OFF: Drawer is slave ON = Drawer is master It is just used for TOD internal power gating.
11	RWX			SEC_S_PATH_1_STEP_CHECK_ENABLE: Secondary configuration: slave path-1: STEP check enable OFF: STEP check disabled ON: STEP check enabled
12	RWX			SEC_M_PATH_0_STEP_CHECK_ENABLE: Secondary configuration: master path-0: STEP check enable OFF: STEP check disabled ON: STEP check enabled
13	RWX			SEC_M_PATH_1_STEP_CHECK_ENABLE: Secondary configuration: master path-1: STEP check enable OFF: STEP check disabled ON: STEP check enabled
14	RWX			SEC_S_PATH_0_STEP_CHECK_ENABLE: Secondary configuration: slave path-0: STEP check enable OFF: STEP check disabled ON: STEP check enabled
15	RWX			SEC_I_PATH_STEP_CHECK_ENABLE: Secondary configuration: internal path: STEP check enable OFF: STEP check disabled ON: STEP check enabled
16	RW			PSS_SWITCH_SYNC_ERROR_DISABLE: Misc error SYNC hold mode OFF: gating of one SYNC on topology switch (ttype-01) to force TOD SYNC check error except for the backup TOD master. ON: disable SYNC-gating
17	RWX			I_PATH_STEP_CHECK_CPS_DEVIATION_X_DISABLE: Internal path: STEP check: enlarge CPS deviation: i.e. CPS deviation factor = 8 OFF: enabled ON: disabled
18	RW			STEP_CHECK_ENABLE_CHICKEN_SWITCH: TType-2: STEP check enable: chicken switch OFF: new behavior ON: old behavior (p7+)
19	RW			REG_0X07_SPARE_19: spares
20	RW			REG_0X07_SPARE_20: spares
21	RW			MISC_RESYNC_OSC_FROM_TOD: Misc: OFF: disable resynchronization of Master OSC SYNC pulse from TOD synchroniaztion bit ON: enable resynchronization of Master OSC SYNC pulse from TOD synchroniaztion bit Legacy*
22:31	RW			REG_0X07_SPARE_22_31: spares
32:63	RO			constant=0b00000000000000000000000000000000

TOD: primary/secondary configuration status register: - primary/secondary status - oscillator validity - master/slave status - selected master path - selected slave path - STEP validity
Addr:	0000000000040008 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_PSS_MSS_STATUS_REG
Constant(s):	PERV_TOD_PSS_MSS_STATUS_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X08.LATCH_DATA.DATA_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:2	RWX			PRI_SEC_SELECT: Primary secondary configuration select Dial enums: PRIMARY=>0b000 SECONDARY=>0b111
3	RW			REG_0X08_SPARE_03: spares
4	ROX			M_PATH_0_OSC_NOT_VALID_STATUS: Master path-0: oscillator not valid
5	ROX			M_PATH_1_OSC_NOT_VALID_STATUS: Master path-0: oscillator not valid
6	ROX			M_PATH_0_STEP_CHECK_VALID: Master path-0: STEP check: STEP valid
7	ROX			M_PATH_1_STEP_CHECK_VALID: Master path-1: STEP check: STEP valid
8	ROX			S_PATH_0_STEP_CHECK_VALID: Slave path-0: STEP check: STEP valid
9	ROX			I_PATH_STEP_CHECK_VALID: Internal path: STEP check: STEP valid
10	ROX			S_PATH_1_STEP_CHECK_VALID: Slave path-1: STEP check: STEP valid
11	ROX			IS_SPECIAL_STATUS: Control: backup master: status indicating take-over
12	ROX			PRI_M_PATH_SELECT_STATUS: Primary configuration: master path select
13	ROX			PRI_M_S_TOD_SELECT_STATUS: Primary configuration: master-slave TOD select
14	ROX			PRI_M_S_DRAWER_SELECT_STATUS: Primary configuration: master-slave drawer select
15	ROX			PRI_S_PATH_SELECT_STATUS: Primary configuration: slave path select
16	ROX			SEC_M_PATH_SELECT_STATUS: Secondary configuration: master path select
17	ROX			SEC_M_S_TOD_SELECT_STATUS: Secondary configuration: master-slave TOD select
18	ROX			SEC_M_S_DRAWER_SELECT_STATUS: Secondary configuration: master-slave drawer select
19	ROX			SEC_S_PATH_SELECT_STATUS: Secondary configuration: slave path select
20	ROX			IS_RUNNING: Status: TOD is running
21	ROX			IS_PRIMARY: Status: TOD is using primary configuration
22	ROX			IS_SECONDARY: Status: TOD is using secondary configuration
23	ROX			IS_ACTIVE_MASTER: Status: TOD is active master
24	ROX			IS_BACKUP_MASTER: Status: TOD is backup master
25	ROX			IS_SLAVE: Status: TOD is slave
26	ROX			M_PATH_SELECT: Status: TOD is using master path 0 or 1
27	ROX			S_PATH_SELECT: Status: TOD is using slave path 0 or 1
28	ROX			M_PATH_0_STEP_ALIGN_VALID_SWITCH: Master path-0: STEP alignment: valid switch flag
29	ROX			M_PATH_1_STEP_ALIGN_VALID_SWITCH: Master path-1: STEP alignment: valid switch flag
30	RW			REG_0X08_SPARE_30: spares
31	RWX			M_PATH_SWITCH_TRIGGER: Master path switch trigger
32:63	RO			constant=0b00000000000000000000000000000000

TOD: master path status register containing: - STEP alignment threshold - cycle-per-STEP (CPS) TOD reset triggering: a write into this register will trigger the following resets (if the corresponding enable bits in reg_0x0B are active): - Master path-0 STEP creation CPS counter reset - Master path-0 STEP alignment threshold reset - Master path-1 STEP creation CPS counter reset - Master path-1 STEP alignment threshold reset
Addr:	0000000000040009 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_M_PATH_STATUS_REG
Constant(s):	PERV_TOD_M_PATH_STATUS_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X09.LATCH_DATA.DATA_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:7	RWX			M_PATH_0_STEP_ALIGN_THRESHOLD: Master path-0: STEP align threshold
8:15	RWX			M_PATH_0_CPS: Master path-0: CPS In write mode the value is used to load the CPS for: - the local STEP generation - the constant CPS for the STEP checker
16:23	RWX			M_PATH_1_STEP_ALIGN_THRESHOLD: Master path-1: STEP align threshold
24:31	RWX			M_PATH_1_CPS: Master path-1: CPS In write mode the value is used to load the CPS for: - the local STEP generation - the constant CPS for the STEP checker
32:63	RO			constant=0b00000000000000000000000000000000

TOD: slave path status register containing: - cycle-per-STEP (CPS) TOD reset triggering: a write into this register will trigger the following resets (if the corresponding enable bits in reg_0x0B are active): - Master path-0 STEP alignment FSM reset - Master path-1 STEP alignment FSM reset - Slave path-0 STEP creation CPS counter reset - Slave path-1 STEP creation CPS counter reset
Addr:	000000000004000A (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_S_PATH_STATUS_REG
Constant(s):	PERV_TOD_S_PATH_STATUS_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:47	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X0A.LATCH_DATA.DATA_Q_INST.LATC.L2(0:47) [000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:3	RWX			M_PATH_0_STEP_ALIGN_FSM_STATE: Master path-0: STEP alignment: FSM state Dial enums: IDLE=>0b0000 REMOTE_LATE_2=>0b0001 LOCAL_FIRST=>0b0010 INCREMENT=>0b0011 VERIFY_REM_LATE=>0b0100 LOCAL_FIRST_2=>0b0101 REMOTE_LATE=>0b0110 JUMP_FROM_LOCAL2REMOTE=>0b0111 LOCAL_LATE_2=>0b1001 REMOTE_FIRST=>0b1010 DECREMENT=>0b1011 VERIFY_LOC_LATE=>0b1100 REMOTE_FIRST_2=>0b1101 LOCAL_LATE=>0b1110 JUMP_FROM_REMOTE2LOCAL=>0b1111
4:7	RWX			M_PATH_1_STEP_ALIGN_FSM_STATE: Master path-1: STEP alignment: FSM state Dial enums: IDLE=>0b0000 REMOTE_LATE_2=>0b0001 LOCAL_FIRST=>0b0010 INCREMENT=>0b0011 VERIFY_REM_LATE=>0b0100 LOCAL_FIRST_2=>0b0101 REMOTE_LATE=>0b0110 JUMP_FROM_LOCAL2REMOTE=>0b0111 LOCAL_LATE_2=>0b1001 REMOTE_FIRST=>0b1010 DECREMENT=>0b1011 VERIFY_LOC_LATE=>0b1100 REMOTE_FIRST_2=>0b1101 LOCAL_LATE=>0b1110 JUMP_FROM_REMOTE2LOCAL=>0b1111
8:12	RWX			I_PATH_DELAY_ADJUST_RATIO: Internal path: delay: adjustment ratio
13:15	RW			REG_0X0A_SPARE_13_15: spares
16:23	RWX			S_PATH_0_CPS: Slave path-0: CPS In write mode the value is used: - to load the CPS for the constant CPS for the STEP checker if this mode is enabled, see Section Master Path Unit: STEP checking mode - to load the CPS for the remote sync component if this mode is enabled, see Section Slave Path Unit: STEP creation component
24:31	RWX			S_PATH_1_CPS: Slave path-1: CPS In write mode the value is used to load the CPS for the constant CPS for the STEP checker
32:39	RWX			S_PATH_0_REMOTE_SYNC_LATE_SYNC_COUNT: Slave path-0: counter of mesh-clock cycles elapsed between locally created SYNC and remote SYNC.
40:47	RWX			S_PATH_1_REMOTE_SYNC_LATE_SYNC_COUNT: Slave path-1: counter of mesh-clock cycles elapsed between locally created SYNC and remote SYNC.
48:63	RO			constant=0b0000000000000000

TOD: miscellanous, TOD reset triggering: a write into this register will trigger the following resets (if the corresponding enable bits in reg_0x0B are active) - Master path-0 SYNC create counter reset - Master path-1 SYNC create counter reset
Addr:	000000000004000B (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_MISC_RESET_REG
Constant(s):	PERV_TOD_MISC_RESET_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:39	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X0B.LATCH_DATA.DATA_Q_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			M_PATH_0_STEP_CREATE_THRESHOLD_RESET_ENABLE: Master path-0: STEP create: threshold reset enable Master path-0: STEP alignment: FSM reset enable
1	RW			M_PATH_0_STEP_ALIGN_THRESHOLD_RESET_ENABLE: Master path-0: STEP alignment: threshold reset enable Master path-1: STEP alignment: FSM reset enable
2	RW			M_PATH_1_STEP_CREATE_THRESHOLD_RESET_ENABLE: Master path-1: STEP create: threshold reset enable Slave path-1: STEP RX: CPS reset enable Slave path-1: STEP RX: remote sync reset enable, if the remoty sync mode is enabled
3	RW			M_PATH_1_STEP_ALIGN_THRESHOLD_RESET_ENABLE: Master path-1: STEP alignment: threshold reset enable Slave path-0: STEP RX: CPS reset enable Slave path-0: STEP RX: remote sync reset enable, if the remoty sync mode is enabled
4:5	RW			REG_0X0B_SPARE_04_05: spares
6	RW			DISTR_STEP_SYNC_TX_SYNC_RESET_DISABLE: Distribution: stepsync TX synchronous reset disable OFF: enable stepsync TX synchronous reset ON: disable stepsync TX synchronous reset
7	RW			CORE_STEP_SYNC_TX_SYNC_RESET_DISABLE: Core: stepsync TX reset synchronous disable OFF: enable stepsync TX synchronous reset ON: disable stepsync TX synchronous reset
8	RW			PROBE_0_TOGGLE_ENABLE: Probe output-0: toggle enable
9	RW			PROBE_1_TOGGLE_ENABLE: Probe output-1: toggle enable
10	RW			PROBE_2_TOGGLE_ENABLE: Probe output-2: toggle enable
11	RW			PROBE_3_TOGGLE_ENABLE: Probe output-3: toggle enable
12	RW			DISTR_STEP_SYNC_TX_RESET_DISABLE: Distribution: stepsync TX reset disable OFF: enable stepsync TX reset ON: disable stepsync TX reset
13	RW			DISTR_STEP_SYNC_TX_RESET_TRIGGER: Distribution: stepsync TX reset triggering
14	RW			CORE_STEP_SYNC_TX_RESET_ENABLE: Core: stepsync TX reset enable OFF: disable stepsync TX reset ON: enable stepsync TX reset
15	RW			CORE_STEP_SYNC_TX_RESET_TRIGGER: Core: stepsync TX reset triggering
16	RW			TRACE_ENABLE: Trace: tracing enable
17	RW			REG_0X0B_SPARE_17: spares
18:19	RW			TRACE_DATA_SELECT: Trace: trace data select select one of the 4 blocks of 88-bit data
20	RW			M_PATH_0_SYNC_CREATE_COUNTER_RESET_ENABLE: Master path-0: SYNC create: counter reset enable
21	RW			M_PATH_1_SYNC_CREATE_COUNTER_RESET_ENABLE: Master path-1: SYNC create: counter reset enable
22	RWX			I_PATH_DELAY_TWOS_COMPL_LOAD: Internal path: delay: 2's complement load
23	RWX			I_PATH_DELAY_ADJUST_RESET: Internal path: delay: adjust reset
24:32	RWX			I_PATH_DELAY_TWOS_COMPL_LOAD_VALUE: Internal path: delay: 2's complement load value
33:39	RW			REG_0X0B_SPARE_33_39: spares
40:63	RO			constant=0b000000000000000000000000

TOD: probe data select register
Addr:	000000000004000C (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_PROBE_SELECT_REG
Constant(s):	PERV_TOD_PROBE_SELECT_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X0C.LATCH_DATA.DATA_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:7	RW			PROBE_0_DATA_SELECT: Probe-0: input data select
8:15	RW			PROBE_1_DATA_SELECT: Probe-1: input data select
16:23	RW			PROBE_2_DATA_SELECT: Probe-2: input data select
24:31	RW			PROBE_3_DATA_SELECT: Probe-3: input data select
32:63	RO			constant=0b00000000000000000000000000000000

TOD: timer register
Addr:	000000000004000D (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_TIMER_REG
Constant(s):	PERV_TOD_TIMER_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X0D.LATCH_DATA.DATA_Q_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:59	RW			TIMER_VALUE: Timer value
60	RW			TIMER_ENABLE0: Timer enable 0
61	RW			TIMER_ENABLE1: Timer enable 1
62	ROX			TIMER_STATUS0: Timer status 0 OFF: output 0 is OFF ON: output 0 is ON
63	ROX			TIMER_STATUS1: Timer status 1 OFF: output 1 is OFF ON: output 1 is ON

TOD: master path-0 step steering register - step steering configuration - step steering status Reading bits 33:63 will show the actual value of the step steering counter.
Addr:	000000000004000E (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_M_PATH_0_STEP_STEER_REG
Constant(s):	PERV_TOD_M_PATH_0_STEP_STEER_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X0E.LATCH_DATA.DATA_Q_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			M_PATH_0_STEP_STEER_MODE: Master path-0: step steering: mode OFF: increment mode, the STEP period will increase, the TOD will tick slower ON: decrement mode, the STEP period will decrease, the TOD will tick faster
1:31	RW			M_PATH_0_STEP_STEER_RATE: Master path-0: step steering: rate
32	RW			M_PATH_0_STEP_STEER_COUNTER_LOAD_FLAG: Master path-0: step steering: counter load flag OFF: disable loading of the steer counter with data specified in bits 32:63 ON: enable loading of the steer counter with data specified in bits 32:63
33:63	RWX			M_PATH_0_STEP_STEER_COUNTER_LOAD_VALUE: Master path-0: step steering: steer counter load value

TOD: master path-1 step steering register - step steering configuration - step steering status Reading bits 33:63 will show the actual value of the step steering counter.
Addr:	000000000004000F (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_M_PATH_1_STEP_STEER_REG
Constant(s):	PERV_TOD_M_PATH_1_STEP_STEER_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X0F.LATCH_DATA.DATA_Q_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			M_PATH_1_STEP_STEER_MODE: Master path-1: step steering: mode OFF: increment mode, the STEP period will increase, the TOD will tick slower ON: decrement mode, the STEP period will decrease, the TOD will tick faster
1:31	RW			M_PATH_1_STEP_STEER_RATE: Master path-1: step steering: rate
32	RW			M_PATH_1_STEP_STEER_COUNTER_LOAD_FLAG: Master path-1: step steering: counter load flag OFF: disable loading of the steer counter with data specified in bits 32:63 ON: enable loading of the steer counter with data specified in bits 32:63
33:63	RWX			M_PATH_1_STEP_STEER_COUNTER_LOAD_VALUE: Master path-1: step steering: steer counter load value

TOD: chip control register
Addr:	0000000000040010 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_CHIP_CTRL_REG
Constant(s):	PERV_TOD_CHIP_CTRL_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X10.LATCH_DATA.DATA_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			TIMEBASE_ENABLE: Timebase enable
1:3	RW			I_PATH_CORE_SYNC_PERIOD_SELECT: Internal path: core SYNC period select Dial enums: 8_US=>0b000 4_US=>0b001 2_US=>0b010 1_US=>0b011 128_US=>0b100 64_US=>0b101 32_US=>0b110 16_US=>0b111
4	RW			I_PATH_SYNC_CHECK_DISABLE: Internal path: SYNC check disable OFF: TOD SYNC check enable ON: TOD SYNC check disable
5	RW			TX_TTYPE_PIB_MST_FSM_STATE_DISABLE: TX TType: PIB master FSM state: enable OFF: disabled ON: enabled
6	RW			RX_TTYPE_1_ON_STEP_ENABLE: RX TType-1: enable the synchronization of the TType-1 on occurence of a STEP OFF: disable ON: enable
7	RW			MOVE_TOD_TO_TB_ON_2X_SYNC_ENABLE: Move-TOD-To-Timebase on 2x SYNC boundary: enable OFF: Move-TOD-To-Timebase on 1x SYNC boundary ON: Move-TOD-To-Timebase on 2x SYNC boundary
8	RW			USE_TB_SYNC_MECHANISM: Use Timebase SYNC mechanism OFF: Use eclipz SYNC mechanism ON: Use tb_enable signal as SYNC event
9	RW			USE_TB_STEP_SYNC: Use Timebase STEP SYNC OFF: Use STEPSYNC from the internal path ON: Use programmable cycle counter for STEP
10:15	RW			LOW_ORDER_STEP_VALUE: Low order STEP value needed for use_tb_step_SYNC as the programmable cycle counter for creating a STEP. Dial enums: INVALID=>0b000000 1_CYCLE_STEP=>0b000001 2_CYCLE_STEP=>0b000010 3_CYCLE_STEP=>0b000011 4_CYCLE_STEP=>0b000100
16	RW			DISTRIBUTION_BROADCAST_MODE_ENABLE: Distribution: enable broadcast mode. OFF: distribution is done by specific routing of the signals from one TOD(master or slave) to another slave. ON: distribution is done by broadcasting the signals from the active master to any slave in the system.
17:18	RW			REG_0X10_SPARE_17_18: spares
19:23	RW			REG_0X10_SPARE_19_23: spares
24:25	RW			REG_0X10_SPARE_24_25: spares
26	WO			TX_TTYPE_PIB_MST_IF_RESET: TX TType: PIB master interface reset Request a PIB master reset to the PIB arbiter The reset request is sent to the PIB arbiter after a delay of 4 STEPs
27	RW			REG_0X10_SPARE_27: spares
28	RW			M_PATH_CLOCK_OFF_ENABLE: Master path: clock gating enable OFF: disable ON: enable clock gating function of the oscillator valid bits TOD_M_PATH_CTRL_REG (@0x00[0:1])
29	RW			REG_0X10_SPARE_29: spares
30	RW			XSTOP_GATE: System checkstop gate: OFF: stop TOD when a system checkstop occurs ON: keep TOD running when a system checkstop occurs
31	RW			STICKY_ERROR_INJECT_ENABLE: Sticky error inject enable
32:63	RO			constant=0b00000000000000000000000000000000

TOD: TX TTYPE-0 triggering register
Addr:	0000000000040011 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_TX_TTYPE_0_REG
Constant(s):	PERV_TOD_TX_TTYPE_0_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X11.LATCH_DATA.DATA_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	WO			TX_TTYPE_0_TRIGGER: TX TTYPE-0 trigger
1:63	RO			constant=0b000000000000000000000000000000000000000000000000000000000000000

TOD: TX TTYPE-1 triggering register
Addr:	0000000000040012 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_TX_TTYPE_1_REG
Constant(s):	PERV_TOD_TX_TTYPE_1_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X12.LATCH_DATA.DATA_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	WO			TX_TTYPE_1_TRIGGER: TX TTYPE-1 trigger
1:63	RO			constant=0b000000000000000000000000000000000000000000000000000000000000000

TOD: TX TTYPE-2 triggering register
Addr:	0000000000040013 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_TX_TTYPE_2_REG
Constant(s):	PERV_TOD_TX_TTYPE_2_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X13.LATCH_DATA.DATA_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	WO			TX_TTYPE_2_TRIGGER: TX TTYPE-2 trigger
1:63	RO			constant=0b000000000000000000000000000000000000000000000000000000000000000

TOD: TX TTYPE-3 triggering register
Addr:	0000000000040014 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_TX_TTYPE_3_REG
Constant(s):	PERV_TOD_TX_TTYPE_3_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X14.LATCH_DATA.DATA_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	WO			TX_TTYPE_3_TRIGGER: TX TTYPE-3 trigger
1:63	RO			constant=0b000000000000000000000000000000000000000000000000000000000000000

TOD: TX TTYPE-4 triggering register
Addr:	0000000000040015 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_TX_TTYPE_4_REG
Constant(s):	PERV_TOD_TX_TTYPE_4_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X15.LATCH_DATA.DATA_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	WO			TX_TTYPE_4_TRIGGER: TX TTYPE-4 trigger
1:63	RO			constant=0b000000000000000000000000000000000000000000000000000000000000000

TOD: TX TTYPE-5 triggering register
Addr:	0000000000040016 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_TX_TTYPE_5_REG
Constant(s):	PERV_TOD_TX_TTYPE_5_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X16.LATCH_DATA.DATA_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	WO			TX_TTYPE_5_TRIGGER: TX TTYPE-5 trigger
1:63	RO			constant=0b000000000000000000000000000000000000000000000000000000000000000

TOD: Move-TOD-To-Timebase triggering register
Addr:	0000000000040017 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_MOVE_TOD_TO_TB_REG
Constant(s):	PERV_TOD_MOVE_TOD_TO_TB_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X17.LATCH_DATA.DATA_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	WO			MOVE_TOD_TO_TB_TRIGGER: Move TOD to Timebase trigger
1:63	RO			constant=0b000000000000000000000000000000000000000000000000000000000000000

TOD: Load-TOD-Mod triggering register set the FSM in NOT_SET state
Addr:	0000000000040018 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_LOAD_TOD_MOD_REG
Constant(s):	PERV_TOD_LOAD_TOD_MOD_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:1	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X18.LATCH_DATA.DATA_Q_INST.LATC.L2(0:1) [00]
Bit(s)	SCOM			Dial: Description
0	WO			FSM_LOAD_TOD_MOD_TRIGGER: FSM: load_tod_mod trigger
1	WO			FSM_LOAD_TOD_MOD_SYNC_ENABLE: FSM: load_tod_mod sync enable when the FSM is in NOT_SET state OFF: no sync sent to the core when the FSM is in NOT_SET state ON: sync sent to the core when the FSM is in NOT_SET state
2:63	RO			constant=0b00000000000000000000000000000000000000000000000000000000000000

TOD: trace data set-1 register
Addr:	000000000004001D (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_TRACE_DATA_1_REG
Constant(s):	PERV_TOD_TRACE_DATA_1_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X1D.LATCH_DATA.DATA_Q_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RWX			TRACE_DATA_SET_1: Trace: data set-1

TOD: trace data set-2 register
Addr:	000000000004001E (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_TRACE_DATA_2_REG
Constant(s):	PERV_TOD_TRACE_DATA_2_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X1E.LATCH_DATA.DATA_Q_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RWX			TRACE_DATA_SET_2: Trace: data set-2

TOD: trace data set-3 register
Addr:	000000000004001F (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_TRACE_DATA_3_REG
Constant(s):	PERV_TOD_TRACE_DATA_3_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X1F.LATCH_DATA.DATA_Q_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RWX			TRACE_DATA_SET_3: Trace: data set-3

TOD: time value register 60-bit TOD and 4-bit Who's-On-first(WOF) incrementers
Addr:	0000000000040020 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_VALUE_REG
Constant(s):	PERV_TOD_VALUE_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X20.LATCH_DATA.DATA_Q_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:59	ROX			TOD_VALUE: Internal path: Time-of-day register value
60:63	RWX			WOF_COUNTER_VALUE: Who's-On-first(WOF): counter value

TOD: load register TOD incrementer: 60-bit TOD and 4-bit WOF, on read: returns all ZEROS when TOD not Running, on write: go to Wait for SYNC state when DataBit(63)=0 (load TOD), else go to Stopped state (load TOD data63)
Addr:	0000000000040021 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_LOAD_TOD_REG
Constant(s):	PERV_TOD_LOAD_TOD_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X21.LATCH_DATA.DATA_Q_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:59	RWX			LOAD_TOD_VALUE: Internal path: load TOD value
60:63	RWX			WOF: Who's-On-first(WOF) incrementer

TOD: start TOD triggering register go to Running state when DataBit(02)=0, else go to Wait for SYNC state
Addr:	0000000000040022 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_START_TOD_REG
Constant(s):	PERV_TOD_START_TOD_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X22.LATCH_DATA.DATA_Q_INST.LATC.L2(0:7) [00000000]
Bit(s)	SCOM			Dial: Description
0	WO			FSM_START_TOD_TRIGGER: FSM: start_tod trigger
1	RW			REG_0X22_SPARE_01: spares
2	WO			FSM_START_TOD_DATA02: FSM: start_tod_data02 trigger
3:7	RW			REG_0X22_SPARE_03_07: spares
8:63	RO			constant=0b00000000000000000000000000000000000000000000000000000000

TOD: low order STEP register
Addr:	0000000000040023 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_LOW_ORDER_STEP_REG
Constant(s):	PERV_TOD_LOW_ORDER_STEP_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X23.LATCH_DATA.DATA_Q_INST.LATC.L2(0:7) [00000000]
Bit(s)	SCOM			Dial: Description
0:5	RWX			LOW_ORDER_STEP_COUNTER_VALUE: Low Order STEP: counter value used for USE_OSC_B cofiguration for internal STEP creation.
6:7	RW			REG_0X23_SPARE_06_07: spares
8:63	RO			constant=0b00000000000000000000000000000000000000000000000000000000

TOD: FSM register
Addr:	0000000000040024 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_FSM_REG
Constant(s):	PERV_TOD_FSM_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X24.LATCH_DATA.DATA_Q_INST.LATC.L2(0:7) [00000000]
Bit(s)	SCOM			Dial: Description
0:3	RWX			I_PATH_FSM_STATE: Internal path. TOD FSM state (TOD is running in the following states: x'02' , x'0A', x'0E') 0000 = ERROR Dial enums: NOT_SET=>0b0111 STOPPED=>0b0001 WAIT_FOR_SYNC=>0b1101 RUNNING_2=>0b0010 RUNNING_A=>0b1010 RUNNING_E=>0b1110
4	ROX			TOD_IS_RUNNING: TOD running indicator
5:7	RW			REG_0X24_SPARE_05_07: spares
8:63	RO			constant=0b00000000000000000000000000000000000000000000000000000000

TOD: TX TType control register
Addr:	0000000000040027 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_TX_TTYPE_CTRL_REG
Constant(s):	PERV_TOD_TX_TTYPE_CTRL_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:39	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X27.LATCH_DATA.DATA_Q_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:23	RW			MOVE_TOD_TO_TB_CORE_ADDRESS: TX TType: move TOD to timbase: Configuration of core address. Needs to be configured before issuing a move_chip_TOD_to_TB command. Bits[0:31] are used to configure the core address. This mode is activated by enabling bit[35].
24:31	RW			MOVE_TOD_TO_TB_CORE_ID: TX TType: move TOD to timbase: Configuration of core address. Needs to be configured before issuing a move_chip_TOD_to_TB command. 0: reserved 1: Multicast Bit (0b1 for multicast) 2-7: PIB slave address = 0b01xxxx where xxxx is the core id
32	RW			TX_TTYPE_4_SEND_MODE: TX TType: Ttype-4 send mode Qualifying of TType4 sent out via Fabric when receiving a TType-3 via Fabric. Needs to be configured before issuing a TType-3 command. OFF: send out TType-4 if TOD is master ON: send out TType-4 if enabled (bit-33)
33	RW			TX_TTYPE_4_SEND_ENABLE: TX TType: Ttype-4 send enable OFF: disabled to send out TType-4 ON: enabled to send out TType-4
34	RW			REG_0X27_SPARE_34: spares
35	RW			MOVE_TOD_TO_TB_CORE_ADDRESS_ENABLE: TX TType: move TOD to timbase: Enable the full configuration of the core address.
36	RW			REG_0X27_SPARE_36: spares
37:39	ROX			TX_TTYPE_PIB_FSM_STATE: TX TType: PIB master FSM state Dial enums: PS_IDLE=>0b000 PS_REQFBC=>0b100 PS_REQTOD=>0b101 PS_WAITFBC=>0b110 PS_WAITTOD=>0b111
40:63	RO			constant=0b000000000000000000000000 Dial enums: PS_IDLE=>0b000 PS_REQFBC=>0b100 PS_REQTOD=>0b101 PS_WAITFBC=>0b110 PS_WAITTOD=>0b111

TOD: RX TType control register Register used by the Alter-Display Unit (ADU) to transmit the TType data it receives from the PowerBus
Addr:	0000000000040029 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_RX_TTYPE_CTRL_REG
Constant(s):	PERV_TOD_RX_TTYPE_CTRL_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X29.LATCH_DATA.DATA_Q_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			RX_TTYPE_DATA: RX TType: data Refer to section TType Format of the workbook for the data format.

TOD: error and interrupt register
Addr:	0000000000040030 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_ERROR_REG
Constant(s):	PERV_TOD_ERROR_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X30.LATCH_DATA.DATA_Q_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RWX			REG_0X00_DATA_PARITY_ERROR: Error: master path control register (0x00): data parity error
1	RWX			M_PATH_0_PARITY_ERROR: Error: master path-0: parity error
2	RWX			M_PATH_1_PARITY_ERROR: Error: master path-1: parity error
3	RWX			REG_0X01_DATA_PARITY_ERROR: Error: port-0 primary configuration register (0x01): data parity error
4	RWX			REG_0X02_DATA_PARITY_ERROR: Error: port-1 primary configuration register (0x02): data parity error
5	RWX			REG_0X03_DATA_PARITY_ERROR: Error: port-0 secondary configuration register (0x03): data parity error
6	RWX			REG_0X04_DATA_PARITY_ERROR: Error: port-1 secondary configuration register (0x04): data parity error
7	RWX			REG_0X05_DATA_PARITY_ERROR: Error: slave path control register (0x05): data parity error
8	RWX			REG_0X06_DATA_PARITY_ERROR: Error: internal path control register (0x06): data parity error
9	RWX			REG_0X07_DATA_PARITY_ERROR: Error: primarysecondary masterslave control register (0x07): data parity error
10	RWX			S_PATH_0_PARITY_ERROR: Error: slave path-0: parity error
11	RWX			REG_0X08_DATA_PARITY_ERROR: Error: primarysecondary masterslave status register (0x07): data parity error
12	RWX			REG_0X09_DATA_PARITY_ERROR: Error: master path status register (0x09): data parity error
13	RWX			REG_0X0A_DATA_PARITY_ERROR: Error: slave path status register (0x0a): data parity error
14	RWX			M_PATH_0_STEP_CHECK_ERROR: Error: master path-0: STEP check error
15	RWX			M_PATH_1_STEP_CHECK_ERROR: Error: master path-1: STEP check error
16	RWX			S_PATH_0_STEP_CHECK_ERROR: Error: slave path-0: STEP check error
17	RWX			I_PATH_STEP_CHECK_ERROR: Error: internal path: STEP check error
18	RWX			PSS_HAM: Error: PSS Hamming Distance
19	RWX			REG_0X0B_DATA_PARITY_ERROR: Error: miscellaneous, reset register (0x0b): data parity error
20	RWX			S_PATH_1_PARITY_ERROR: Error: slave path-0: parity error
21	RWX			S_PATH_1_STEP_CHECK_ERROR: Error: slave path-1: STEP check error
22	RWX			I_PATH_DELAY_STEP_CHECK_PARITY_ERROR: Error: internal path: delay, STEP check components: parity error
23	RWX			REG_0X0C_DATA_PARITY_ERROR: Error: data parity error of the following registers: - probe data select register (0x0c) - timer register (0x0d)
24	RWX			REG_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY_ERROR: Error: data parity error on one of the following TX-TType trigger registers: - TX Ttype-0 triggering register (0x11) - TX Ttype-1 triggering register (0x12) - TX Ttype-2 triggering register (0x13) - TX Ttype-3 triggering register (0x14) - TX Ttype-4 triggering register (0x15) - TX Ttype-5 triggering register (0x16)
25	RWX			REG_0X17_0X18_0X21_0X22_DATA_PARITY_ERROR: Error: data parity error on one of the following trigger registers: - move-TOD-to-timebase triggering register (0x17) - load-TOD-mod register (0x18) - load register (0x21) - start-TOD register (0x22)
26	RWX			REG_0X1D_0X1E_0X1F_DATA_PARITY_ERROR: Error: data parity error on one of the following trace data registers: - trace data set-1 register (0x1d) - trace data set-2 register (0x1e) - trace data set-3 register (0x1f)
27	RWX			REG_0X20_DATA_PARITY_ERROR: Error: time value register (0x20): data parity error
28	RWX			REG_0X23_DATA_PARITY_ERROR: Error: low order STEP register (0x23): data parity error
29	RWX			REG_0X24_DATA_PARITY_ERROR: Error: FSM register (0x24): data parity error
30	RWX			REG_0X29_DATA_PARITY_ERROR: Error: RX-TType control register: data parity error
31	RWX			REG_0X30_0X31_0X32_0X33_DATA_PARITY_ERROR: Error: data parity error on one of the following error handling registers: - error register (0x30) - error inject register (0x31) - Error mask register (0x32) - core interrupt mask register (0x33)
32	RWX			REG_0X10_DATA_PARITY_ERROR: Error: chip control register (0x10): data parity error
33	RWX			I_PATH_SYNC_CHECK_ERROR: Error: internal path: SYNC check
34	RWX			I_PATH_FSM_STATE_PARITY_ERROR: Error: internal path: FSM state parity error
35	RWX			I_PATH_TIME_REG_PARITY_ERROR: Error: internal path. Time register parity error
36	RWX			I_PATH_TIME_REG_OVERFLOW: Error: internal path: time register overflow
37	RWX			WOF_LOW_ORDER_STEP_COUNTER_PARITY_ERROR: Error: WOF counter or Low-Order-STEP counter: parity error
38	RWX			RX_TTYPE_0: Status: received Ttype-0
39	RWX			RX_TTYPE_1: Status: received Ttype-1
40	RWX			RX_TTYPE_2: Status: received Ttype-2
41	RWX			RX_TTYPE_3: Status: received Ttype-3
42	RWX			RX_TTYPE_4: Status: received Ttype-4
43	RWX			RX_TTYPE_5: Status: received Ttype-5 when FSM is in running state
44	RWX			PIB_SLAVE_ADDR_INVALID_ERROR: Error: PIB slave: invalid address
45	RWX			PIB_SLAVE_WRITE_INVALID_ERROR: Error: PIB slave: invalid write
46	RWX			PIB_SLAVE_READ_INVALID_ERROR: Error: PIB slave: invalid read
47	RWX			PIB_SLAVE_ADDR_PARITY_ERROR: Error: PIB slave: address parity error
48	RWX			PIB_SLAVE_DATA_PARITY_ERROR: Error: PIB slave: data parity error
49	RWX			REG_0X27_DATA_PARITY_ERROR: Error: TType control register(0x27): data parity error
50:52	RWX			PIB_MASTER_RSP_INFO_ERROR: Error: PIB master: response infoerror info = 000: no error info > 000: error
53	RWX			RX_TTYPE_INVALID_ERROR: Error: received invalid TType via register 0x21
54	RWX			RX_TTYPE_4_DATA_PARITY_ERROR: Error: data parity error on received TType-4 via register 0x21
55	RWX			PIB_MASTER_REQUEST_ERROR: Error: PIB master; request while busy error
56	RWX			PIB_RESET_DURING_PIB_ACCESS_ERROR: Error: PIB reset received during a PIB master or PIB slave operation
57	RWX			EXTERNAL_XSTOP_ERROR: Error: TOD received an external checkstop
58	RWX			SPARE_ERROR_58: Error: spare
59	RWX			SPARE_ERROR_59: Error: spare
60	RWX			SPARE_ERROR_60: Error: spare
61	RWX			SPARE_ERROR_61: Error: spare
62	RWX			OSCSWITCH_INTERRUPT: Error: Interrupt from the oscillator switch
63	RWX			SPARE_ERROR_63: Error: spare

TOD: error and interrupt inject register
Addr:	0000000000040031 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_ERROR_INJECT_REG
Constant(s):	PERV_TOD_ERROR_INJECT_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X31.LATCH_DATA.DATA_Q_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	WO			REG_0X00_DATA_PARITY_ERROR_INJECT: Error inject: master path control register (0x00): data parity error
1	WO			M_PATH_0_PARITY_ERROR_INJECT: Error inject: master path-0: parity error
2	WO			M_PATH_1_PARITY_ERROR_INJECT: Error inject: master path-1: parity error
3	WO			REG_0X01_DATA_PARITY_ERROR_INJECT: Error inject: port-0 primary configuration register (0x01): data parity error
4	WO			REG_0X02_DATA_PARITY_ERROR_INJECT: Error inject: port-1 primary configuration register (0x02): data parity error
5	WO			REG_0X03_DATA_PARITY_ERROR_INJECT: Error inject: port-0 secondary configuration register (0x03): data parity error
6	WO			REG_0X04_DATA_PARITY_ERROR_INJECT: Error inject: port-1 secondary configuration register (0x04): data parity error
7	WO			REG_0X05_DATA_PARITY_ERROR_INJECT: Error inject: slave path control register (0x05): data parity error
8	WO			REG_0X06_DATA_PARITY_ERROR_INJECT: Error inject: internal path control register (0x06): data parity error
9	WO			REG_0X07_DATA_PARITY_ERROR_INJECT: Error inject: primarysecondary masterslave control register (0x07): data parity error
10	WO			S_PATH_0_PARITY_ERROR_INJECT: Error inject: slave path-0: parity error
11	WO			REG_0X08_DATA_PARITY_ERROR_INJECT: Error inject: primarysecondary masterslave status register (0x07): data parity error
12	WO			REG_0X09_DATA_PARITY_ERROR_INJECT: Error inject: master path status register (0x09): data parity error
13	WO			REG_0X0A_DATA_PARITY_ERROR_INJECT: Error inject: slave path status register (0x0a): data parity error
14	WO			M_PATH_0_STEP_CHECK_ERROR_INJECT: Error inject: master path-0: STEP check error
15	WO			M_PATH_1_STEP_CHECK_ERROR_INJECT: Error inject: master path-1: STEP check error
16	WO			S_PATH_0_STEP_CHECK_ERROR_INJECT: Error inject: slave path-0: STEP check error
17	WO			I_PATH_STEP_CHECK_ERROR_INJECT: Error inject: internal path: STEP check error
18	WO			PSS_HAM_INJECT: Error inject: PSS Hamming Distance
19	WO			REG_0X0B_DATA_PARITY_ERROR_INJECT: Error inject: miscellaneous, reset register (0x0b): data parity error
20	WO			S_PATH_1_PARITY_ERROR_INJECT: Error inject: slave path-0: parity error
21	WO			S_PATH_1_STEP_CHECK_ERROR_INJECT: Error inject: slave path-1: STEP check error
22	WO			I_PATH_DELAY_STEP_CHECK_PARITY_ERROR_INJECT: Error inject: internal path: delay, STEP check components: parity error
23	WO			REG_0X0C_DATA_PARITY_ERROR_INJECT: Error inject: data parity error of the following registers: - probe data select register (0x0c) - timer register (0x0D)
24	WO			REG_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY_ERROR_INJECT: Error inject: data parity error on the following TX-TType trigger registers: - TX Ttype-0 triggering register (0x11) - TX Ttype-1 triggering register (0x12) - TX Ttype-2 triggering register (0x13) - TX Ttype-3 triggering register (0x14) - TX Ttype-4 triggering register (0x15) - TX Ttype-5 triggering register (0x16)
25	WO			REG_0X17_0X18_0X21_0X22_DATA_PARITY_ERROR_INJECT: Error inject: data parity error on the following trigger registers: - move-TOD-to-timebase triggering register (0x17) - load-TOD-mod register (0x18) - load register (0x21) - start-TOD register (0x22)
26	WO			REG_0X1D_0X1E_0X1F_DATA_PARITY_ERROR_INJECT: Error inject: data parity error on the following trace data registers: - trace data set-1 register (0x1d) - trace data set-2 register (0x1e) - trace data set-3 register (0x1f)
27	WO			REG_0X20_DATA_PARITY_ERROR_INJECT: Error inject: time value register (0x20): data parity error
28	WO			REG_0X23_DATA_PARITY_ERROR_INJECT: Error inject: low order STEP register (0x23): data parity error
29	WO			REG_0X24_DATA_PARITY_ERROR_INJECT: Error inject: FSM register (0x24): data parity error
30	WO			REG_0X29_DATA_PARITY_ERROR_INJECT: Error inject: RX-TType control register: data parity error
31	WO			REG_0X30_0X31_0X32_0X33_DATA_PARITY_ERROR_INJECT: Error inject: data parity error on the following error handling registers: - error register (0x30) - Error mask register (0x32) - core interrupt mask register (0x33)
32	WO			REG_0X10_DATA_PARITY_ERROR_INJECT: Error inject: chip control register (0x10): data parity error
33	WO			I_PATH_SYNC_CHECK_ERROR_INJECT: Error inject: internal path: SYNC check
34	WO			I_PATH_FSM_STATE_PARITY_ERROR_INJECT: Error inject: internal path: FSM state parity error
35	WO			I_PATH_TIME_REG_PARITY_ERROR_INJECT: Error inject: time register: parity error
36	WO			I_PATH_TIME_REG_OVERFLOW_INJECT: Error inject: internal path: time register overflow
37	WO			WOF_LOW_ORDER_STEP_COUNTER_PARITY_ERROR_INJECT: Error inject: WOF counter or Low-Order-STEP counter: parity error
38	WO			RX_TTYPE_0_INJECT: Error inject: received Ttype-0
39	WO			RX_TTYPE_1_INJECT: Error inject: received Ttype-1
40	WO			RX_TTYPE_2_INJECT: Error inject: received Ttype-2
41	WO			RX_TTYPE_3_INJECT: Error inject: received Ttype-3
42	WO			RX_TTYPE_4_INJECT: Error inject: received Ttype-4
43	WO			RX_TTYPE_5_INJECT: Error inject: received Ttype-5 when FSM is in running state
44	WO			PIB_SLAVE_ADDR_INVALID_ERROR_INJECT: Error inject: PIB slave: invalid address
45	WO			PIB_SLAVE_WRITE_INVALID_ERROR_INJECT: Error inject: PIB slave: invalid write
46	WO			PIB_SLAVE_READ_INVALID_ERROR_INJECT: Error inject: PIB slave: invalid read
47	WO			PIB_SLAVE_ADDR_PARITY_ERROR_INJECT: Error inject: PIB slave: address parity error
48	WO			PIB_SLAVE_DATA_PARITY_ERROR_INJECT: Error inject: PIB slave: data parity error
49	WO			REG_0X27_DATA_PARITY_ERROR_INJECT: Error inject: TType control register(0x27): data parity error
50:52	WO			PIB_MASTER_RSP_INFO_ERROR_INJECT: Error inject: PIB master: response infoerror
53	WO			RX_TTYPE_INVALID_ERROR_INJECT: Error inject: received invalid TType via register 0x21
54	WO			RX_TTYPE_4_DATA_PARITY_ERROR_INJECT: Error inject: data parity error on received TType-4 via register 0x21
55	WO			PIB_MASTER_REQUEST_ERROR_INJECT: Error inject: PIB master; request while busy error
56	WO			PIB_RESET_DURING_PIB_ACCESS_ERROR_INJECT: Error inject: PIB reset received during a PIB master or PIB slave operation
57	WO			EXTERNAL_XSTOP_ERROR_INJECT: Error inject: TOD received an external checkstop
58	WO			SPARE_ERROR_INJECT_58: Error inject: spare
59	WO			SPARE_ERROR_INJECT_59: Error inject: spare
60	WO			SPARE_ERROR_INJECT_60: Error inject: spare
61	WO			SPARE_ERROR_INJECT_61: Error inject: spare
62	WO			OSCSWITCH_INTERRUPT_INJECT: Error inject: Interrupt from the oscillator switch
63	WO			CORE_STEP_ERROR_INJECT: Error inject: to suppress one STEP to core timebase

TOD: error mask register mask of the error reporting component (c_err_rpt)
Addr:	0000000000040032 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_ERROR_MASK_REG
Constant(s):	PERV_TOD_ERROR_MASK_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X32.LATCH_DATA.DATA_Q_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RWX			REG_0X00_DATA_PARITY_ERROR_MASK: Error mask: master path control register (0x00): data parity error
1	RWX			M_PATH_0_PARITY_ERROR_MASK: Error mask: master path-0: parity error
2	RWX			M_PATH_1_PARITY_ERROR_MASK: Error mask: master path-1: parity error
3	RWX			REG_0X01_DATA_PARITY_ERROR_MASK: Error mask: port-0 primary configuration register (0x01): data parity error
4	RWX			REG_0X02_DATA_PARITY_ERROR_MASK: Error mask: port-1 primary configuration register (0x02): data parity error
5	RWX			REG_0X03_DATA_PARITY_ERROR_MASK: Error mask: port-0 secondary configuration register (0x03): data parity error
6	RWX			REG_0X04_DATA_PARITY_ERROR_MASK: Error mask: port-1 secondary configuration register (0x04): data parity error
7	RWX			REG_0X05_DATA_PARITY_ERROR_MASK: Error mask: slave path control register (0x05): data parity error
8	RWX			REG_0X06_DATA_PARITY_ERROR_MASK: Error mask: internal path control register (0x06): data parity error
9	RWX			REG_0X07_DATA_PARITY_ERROR_MASK: Error mask: primarysecondary masterslave control register (0x07): data parity error
10	RWX			S_PATH_0_PARITY_ERROR_MASK: Error mask: slave path-0: parity error
11	RWX			REG_0X08_DATA_PARITY_ERROR_MASK: Error mask: primarysecondary masterslave status register (0x07): data parity error
12	RWX			REG_0X09_DATA_PARITY_ERROR_MASK: Error mask: master path status register (0x09): data parity error
13	RWX			REG_0X0A_DATA_PARITY_ERROR_MASK: Error mask: slave path status register (0x0a): data parity error
14	RWX			M_PATH_0_STEP_CHECK_ERROR_MASK: Error mask: master path-0: STEP check error
15	RWX			M_PATH_1_STEP_CHECK_ERROR_MASK: Error mask: master path-1: STEP check error
16	RWX			S_PATH_0_STEP_CHECK_ERROR_MASK: Error mask: slave path-0: STEP check error
17	RWX			I_PATH_STEP_CHECK_ERROR_MASK: Error mask: internal path: STEP check error
18	RWX			PSS_HAM_MASK: Error mask: PSS Hamming Distance
19	RWX			REG_0X0B_DATA_PARITY_ERROR_MASK: Error mask: miscellaneous, reset register (0x0b): data parity error
20	RWX			S_PATH_1_PARITY_ERROR_MASK: Error mask: slave path-0: parity error
21	RWX			S_PATH_1_STEP_CHECK_ERROR_MASK: Error mask: slave path-1: STEP check error
22	RWX			I_PATH_DELAY_STEP_CHECK_PARITY_ERROR_MASK: Error mask: internal path: delay , STEP check components: parity error
23	RWX			REG_0X0C_DATA_PARITY_ERROR_MASK: Error mask: data parity error of the following registers: - probe data select register (0x0c) - timer register (0x0D)
24	RWX			REG_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY_ERROR_MASK: Error mask: data parity error on one of the following TX-TType trigger registers: - TX Ttype-0 triggering register (0x11) - TX Ttype-1 triggering register (0x12) - TX Ttype-2 triggering register (0x13) - TX Ttype-3 triggering register (0x14) - TX Ttype-4 triggering register (0x15) - TX Ttype-5 triggering register (0x16)
25	RWX			REG_0X17_0X18_0X21_0X22_DATA_PARITY_ERROR_MASK: Error mask: data parity error on one of the following trigger registers: - move-TOD-to-timebase triggering register (0x17) - load-TOD-mod register (0x18) - load register (0x21) - start-TOD register (0x22)
26	RWX			REG_0X1D_0X1E_0X1F_DATA_PARITY_ERROR_MASK: Error mask: data parity error on one of the following trace data registers: - trace data set-1 register (0x1d) - trace data set-2 register (0x1e) - trace data set-3 register (0x1f)
27	RWX			REG_0X20_DATA_PARITY_ERROR_MASK: Error mask: time value register (0x20): data parity error
28	RWX			REG_0X23_DATA_PARITY_ERROR_MASK: Error mask: low order STEP register (0x23): data parity error
29	RWX			REG_0X24_DATA_PARITY_ERROR_MASK: Error mask: FSM register (0x24): data parity error
30	RWX			REG_0X29_DATA_PARITY_ERROR_MASK: Error mask: RX-TType control register: data parity error
31	RWX			REG_0X30_0X31_0X32_0X33_DATA_PARITY_ERROR_MASK: Error mask: data parity error on one of the following error handling registers: - error register (0x30) - error inject register (0x31) - error mask register (0x32) - core interrupt mask register (0x33)
32	RWX			REG_0X10_DATA_PARITY_ERROR_MASK: Error mask: chip control register (0x10): data parity error
33	RWX			I_PATH_SYNC_CHECK_ERROR_MASK: Error mask: internal path: SYNC check
34	RWX			I_PATH_FSM_STATE_PARITY_ERROR_MASK: Error mask: internal path: FSM state parity error
35	RWX			I_PATH_TIME_REG_PARITY_ERROR_MASK: Error mask: internal path: time register: parity error
36	RWX			I_PATH_TIME_REG_OVERFLOW_MASK: Error mask: internal path: time register overflow
37	RWX			WOF_LOW_ORDER_STEP_COUNTER_PARITY_ERROR_MASK: Error mask: WOF counter or Low-Order-STEP counter: parity error
38	RWX			RX_TTYPE_0_MASK: Error mask: received Ttype-0
39	RWX			RX_TTYPE_1_MASK: Error mask: received Ttype-1
40	RWX			RX_TTYPE_2_MASK: Error mask: received Ttype-2
41	RWX			RX_TTYPE_3_MASK: Error mask: received Ttype-3
42	RWX			RX_TTYPE_4_MASK: Error mask: received Ttype-4
43	RWX			RX_TTYPE_5_MASK: Error mask: received Ttype-5 when FSM is in running state
44	RWX			PIB_SLAVE_ADDR_INVALID_ERROR_MASK: Error mask: PIB slave: invalid address
45	RWX			PIB_SLAVE_WRITE_INVALID_ERROR_MASK: Error mask: PIB slave: invalid write
46	RWX			PIB_SLAVE_READ_INVALID_ERROR_MASK: Error mask: PIB slave: invalid read
47	RWX			PIB_SLAVE_ADDR_PARITY_ERROR_MASK: Error mask: PIB slave: address parity error
48	RWX			PIB_SLAVE_DATA_PARITY_ERROR_MASK: Error mask: PIB slave: data parity error
49	RWX			REG_0X27_DATA_PARITY_ERROR_MASK: Error mask: TType control register(0x27): data parity error
50:52	RWX			PIB_MASTER_RSP_INFO_ERROR_MASK: Error mask: PIB master: response infoerror
53	RWX			RX_TTYPE_INVALID_ERROR_MASK: Error mask: received invalid TType via register 0x21
54	RWX			RX_TTYPE_4_DATA_PARITY_ERROR_MASK: Error mask: data parity error on received TType-4 via register 0x21
55	RWX			PIB_MASTER_REQUEST_ERROR_MASK: Error mask: PIB master; request while busy error
56	RWX			PIB_RESET_DURING_PIB_ACCESS_ERROR_MASK: Error mask: PIB reset received during a PIB master or PIB slave operation
57	RWX			EXTERNAL_XSTOP_ERROR_MASK: Error mask: TOD received an external checkstop
58	RWX			SPARE_ERROR_MASK_58: Error mask: spare
59	RWX			SPARE_ERROR_MASK_59: Error mask: spare
60	RWX			SPARE_ERROR_MASK_60: Error mask: spare
61	RWX			SPARE_ERROR_MASK_61: Error mask: spare
62	RWX			OSCSWITCH_INTERRUPT_MASK: Error mask: Interrupt from the oscillator switch
63	RWX			SPARE_ERROR_MASK_63: Error mask: spare

TOD: to route specific errors either to the CORE or to the FIR
Addr:	0000000000040033 (SCOM)
Name:	TP.TPCHIP.PIB.TOD.TOD_ERROR_ROUTING_REG
Constant(s):	PERV_TOD_ERROR_ROUTING_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.TOD.CTRL_REG.REG_0X33.LATCH_DATA.DATA_Q_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			REG_0X00_DATA_PARITY_ERROR_ROUTING: Error routing: master path control register (0x00): data parity error
1	RW			M_PATH_0_PARITY_ERROR_ROUTING: Error routing: master path-0: parity error
2	RW			M_PATH_1_PARITY_ERROR_ROUTING: Error routing: master path-1: parity error
3	RW			REG_0X01_DATA_PARITY_ERROR_ROUTING: Error routing: port-0 primary configuration register (0x01): data parity error
4	RW			REG_0X02_DATA_PARITY_ERROR_ROUTING: Error routing: port-1 primary configuration register (0x02): data parity error
5	RW			REG_0X03_DATA_PARITY_ERROR_ROUTING: Error routing: port-0 secondary configuration register (0x03): data parity error
6	RW			REG_0X04_DATA_PARITY_ERROR_ROUTING: Error routing: port-1 secondary configuration register (0x04): data parity error
7	RW			REG_0X05_DATA_PARITY_ERROR_ROUTING: Error routing: slave path control register (0x05): data parity error
8	RW			REG_0X06_DATA_PARITY_ERROR_ROUTING: Error routing: internal path control register (0x06): data parity error
9	RW			REG_0X07_DATA_PARITY_ERROR_ROUTING: Error routing: primarysecondary masterslave control register (0x07): data parity error
10	RW			S_PATH_0_PARITY_ERROR_ROUTING: Error routing: slave path-0: parity error
11	RW			REG_0X08_DATA_PARITY_ERROR_ROUTING: Error routing: primarysecondary masterslave status register (0x07): data parity error
12	RW			REG_0X09_DATA_PARITY_ERROR_ROUTING: Error routing: master path status register (0x09): data parity error
13	RW			REG_0X0A_DATA_PARITY_ERROR_ROUTING: Error routing: slave path status register (0x0a): data parity error
14	RW			M_PATH_0_STEP_CHECK_ERROR_ROUTING: Error routing: master path-0: STEP check error
15	RW			M_PATH_1_STEP_CHECK_ERROR_ROUTING: Error routing: master path-1: STEP check error
16	RW			S_PATH_0_STEP_CHECK_ERROR_ROUTING: Error routing: slave path-0: STEP check error
17	RW			I_PATH_STEP_CHECK_ERROR_ROUTING: Error routing: internal path: STEP check error
18	RW			PSS_HAM_CORE_INTERRUPT_MASK: Error routing: PSS Hamming Distance
19	RW			REG_0X0B_DATA_PARITY_ERROR_ROUTING: Error routing: miscellaneous, reset register (0x0b): data parity error
20	RW			S_PATH_1_PARITY_ERROR_ROUTING: Error routing: slave path-0: parity error
21	RW			S_PATH_1_STEP_CHECK_ERROR_ROUTING: Error routing: slave path-1: STEP check error
22	RW			I_PATH_DELAY_STEP_CHECK_PARITY_ERROR_ROUTING: Error routing: internal path: delay, STEP check components: parity error
23	RW			REG_0X0C_DATA_PARITY_ERROR_ROUTING: Error routing: data parity error of the following registers: - probe data select register (0x0c) - timer register (0x0D)
24	RW			REG_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY_ERROR_ROUTING: Error routing: data parity error on one of the following TX-TType trigger registers: - TX Ttype-0 triggering register (0x11) - TX Ttype-1 triggering register (0x12) - TX Ttype-2 triggering register (0x13) - TX Ttype-3 triggering register (0x14) - TX Ttype-4 triggering register (0x15) - TX Ttype-5 triggering register (0x16)
25	RW			REG_0X17_0X18_0X21_0X22_DATA_PARITY_ERROR_ROUTING: Error routing: data parity error on one of the following trigger registers: - move-TOD-to-timebase triggering register (0x17) - load-TOD-mod register (0x18) - load register (0x21) - start-TOD register (0x22)
26	RW			REG_0X1D_0X1E_0X1F_DATA_PARITY_ERROR_ROUTING: Error routing: data parity error on one of the following trace data registers: - trace data set-1 register (0x1d) - trace data set-2 register (0x1e) - trace data set-3 register (0x1f)
27	RW			REG_0X20_DATA_PARITY_ERROR_ROUTING: Error routing: time value register (0x20): data parity error
28	RW			REG_0X23_DATA_PARITY_ERROR_ROUTING: Error routing: low order STEP register (0x23): data parity error
29	RW			REG_0X24_DATA_PARITY_ERROR_ROUTING: Error routing: FSM register (0x24): data parity error
30	RW			REG_0X29_DATA_PARITY_ERROR_ROUTING: Error routing: RX-TType control register: data parity error
31	RW			REG_0X30_0X31_0X32_0X33_DATA_PARITY_ERROR_ROUTING: Error routing: data parity error on one of the following error handling registers: - error register (0x30) - error inject register (0x31) - error mask register (0x32) - core interrupt mask register (0x33)
32	RW			REG_0X10_DATA_PARITY_ERROR_ROUTING: Error routing: chip control register (0x10): data parity error
33	RW			I_PATH_SYNC_CHECK_ERROR_ROUTING: Error routing: internal path: SYNC check
34	RW			I_PATH_FSM_STATE_PARITY_ERROR_ROUTING: Error routing: internal path: FSM state parity error
35	RW			I_PATH_TIME_REG_PARITY_ERROR_ROUTING: Error routing: internal path: time register: parity error
36	RW			I_PATH_TIME_REG_OVERFLOW_CORE_INTERRUPT: Error routing: internal path: time register overflow
37	RW			WOF_LOW_ORDER_STEP_COUNTER_PARITY_ERROR_ROUTING: Error routing: WOF counter or Low-Order-STEP counter: parity error
38	RW			RX_TTYPE_0_ERROR_ROUTING: Error routing: received Ttype-0
39	RW			RX_TTYPE_1_ERROR_ROUTING: Error routing: received Ttype-1
40	RW			RX_TTYPE_2_ERROR_ROUTING: Error routing: received Ttype-2
41	RW			RX_TTYPE_3_ERROR_ROUTING: Error routing: received Ttype-3
42	RW			RX_TTYPE_4_ERROR_ROUTING: Error routing: received Ttype-4
43	RW			RX_TTYPE_5_ERROR_ROUTING: Error routing: received Ttype-5 when FSM is in running state
44	RW			PIB_SLAVE_ADDR_INVALID_ERROR_ROUTING: Error routing: PIB slave: invalid address
45	RW			PIB_SLAVE_WRITE_INVALID_ERROR_ROUTING: Error routing: PIB slave: invalid write
46	RW			PIB_SLAVE_READ_INVALID_ERROR_ROUTING: Error routing: PIB slave: invalid read
47	RW			PIB_SLAVE_ADDR_PARITY_ERROR_ROUTING: Error routing: PIB slave: address parity error
48	RW			PIB_SLAVE_DATA_PARITY_ERROR_ROUTING: Error routing: PIB slave: data parity error
49	RW			REG_0X27_DATA_PARITY_ERROR_ROUTING: Error routing: TType control register(0x27): data parity error
50:52	RW			PIB_MASTER_RSP_INFO_ERROR_ROUTING: Error routing: PIB master: response infoerror
53	RW			RX_TTYPE_INVALID_ERROR_ROUTING: Error routing: received invalid TType via register 0x21
54	RW			RX_TTYPE_4_DATA_PARITY_ERROR_ROUTING: Error routing: data parity error on received TType-4 via register 0x21
55	RW			PIB_MASTER_REQUEST_ERROR_ROUTING: Error routing: PIB master; request while busy error
56	RW			PIB_RESET_DURING_PIB_ACCESS_ERROR_ROUTING: Error routing: PIB reset received during a PIB master or PIB slave operation
57	RW			EXTERNAL_XSTOP_ERROR_ROUTING: Error routing: TOD received an external checkstop
58	RW			SPARE_ERROR_ROUTING_58: Error routing: spare
59	RW			SPARE_ERROR_ROUTING_59: Error routing: spare
60	RW			SPARE_ERROR_ROUTING_60: Error routing: spare
61	RW			SPARE_ERROR_ROUTING_61: Error routing: spare
62	RW			OSCSWITCH_INTERRUPT_ROUTING: Error routing: Interrupt from the oscillator switch
63	RW			SPARE_ERROR_ROUTING_63: Error routing: spare

I2C Configuration Register (DeviceID) for Engine A
Addr:	0000000000050190 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.I2CDEVICEID_REGISTER
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPREG.I2C_DEVICEID_INST.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:17	RWX			I2C_DEVICEID_PORT_PROTECTION_A: Protected PORTs of I2C Engine A. Can only be updated when SUL=0
18:24	RWX			I2C_DEVICEID_SLV_ID_A: Protected SLAVE_IDs of I2C Engine A. Can only be updated when SUL=0
25:31	RWX			I2C_DEVICEID_MASK_ID_A: Protected MASK_IDs of I2C Engine A. Can only be updated when SUL=0

OCB_OCI GPE Timer Select Register
Addr:	0000000000060000 (SCOM) 00000000C0000000 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPETSEL
Constant(s):
Comments:	This register selects the rate of the Fixed Interval and Watchdog Timers The input to the PPE will pulse every 2^(23 - select) times the input timer period (which is the PAU cycle time/64), unless select is zero in which case the timer pulse is disabled. SUMMARY: the resultant timer rate is given by: 2^(29-select) / PAU_Frequency when select is non-zero.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.OCC.OCI.GPE0.PPEREG.GPETSEL_Q_0_INST.LATC.L2(0:7) [00000000]
Bit(s)	SCOM	OCI		Dial: Description
0:3	RW	RW		OCB_OCI_GPETSEL_WATCHDOG_SEL: Selects Watchdog Timer rate
4:7	RW	RW		OCB_OCI_GPETSEL_FIT_SEL: Selects Fixed Interval Timer rate
8:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000

OCB_OCI GPE Interrupt Vector Prefix Register
Addr:	0000000000060001 (SCOM) 00000000C0000008 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEIVPR
Constant(s):
Comments:	This register selects the top 23 bits of the Interrupt Address Vector.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:22	TP.TPCHIP.OCC.OCI.GPE0.PPEREG.GPEIVPR_Q_0_INST.LATC.L2(0:22) [00000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:22	RW	RW		OCB_OCI_GPEIVPR_IVPR: Interrupt Prefix Vector Register (Resets to 0xFFFFFE left justified)
23:63	RO	RO		constant=0b00000000000000000000000000000000000000000

OCB_OCI GPE Debug Mode Register
Addr:	0000000000060002 (SCOM) 00000000C0000010 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEDBG
Constant(s):
Comments:	This register contains mode bits controlling the debug bolt-on and PPE behavior on checkstop and trigger.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:23	TP.TPCHIP.OCC.OCI.GPE0.PPEREG.GPEDBG_Q_0_INST.LATC.L2(0:23) [000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	RW	RW		OCB_OCI_GPEDBG_EN_DBG: Enable Debug Trace. Master switch that enables clocks to the trace. Also causes RiscTrace to start on rising edge & stop on falling edge when RISCTRACE is enabled (TRACE_DATA_SEL(0)=0).
1	RW	RW		OCB_OCI_GPEDBG_HALT_ON_XSTOP: Enable Halt on Checkstop input
2	RW	RW		OCB_OCI_GPEDBG_HALT_ON_TRIG: Enable Halt on Trigger input
3	RW	RW		OCB_OCI_GPEDBG_EN_COVERAGE_MODE: Enables Code Coverage Trace Mode. When set, no longer traces every instruction executed, and adds SPRG0 and MARK data to the trace. Note: only supported when EN_INTR_ADDR and EN_TRACE_EXTRA are both set to 0.
4	RW	RW		OCB_OCI_GPEDBG_EN_INTR_ADDR: When RISCTRACE is enabled, trace the Full Interrupt Vector Address, otherwise only trace the lower byte of address.
5	RW	RW		OCB_OCI_GPEDBG_EN_TRACE_EXTRA: When RISCTRACE is enabled and this bit is set, records extra trace data not needed for 405 RISCTrace spec. When this bit is set, record MTMSR or MTSPRG0 data and new MSR value set by RFI.
6	RW	RW		OCB_OCI_GPEDBG_EN_TRACE_STALL: When RISCTRACE is enabled and this bit is set, stall cycles when the processor is not actively executing an instruction, that are not already included in the previous event, are recorded unless it is Halted or in Wait state. When this mode is not set, the RISTRACE is smaller but not time accurate.
7	RW	RW		OCB_OCI_GPEDBG_EN_WAIT_CYCLES: When RISCTRACE is enabled and this bit is set, Stall Events are used to record the number of cycles the PPE is in Wait state. Otherwise cycles in Wait state are ignored. When this bit is set, EN_TRACE_STALL must also be set.
8	RW	RW		OCB_OCI_GPEDBG_EN_FULL_SPEED: When set, the trace valid is pulsed at 1:1 (4x faster than the debug data, which changes at PPE clock speed). This is used for CHTM and NHTM (in memory trace). When this mode is NOT set, trace valid is held constant for a full PPE cycle (four 1:1 cycles). When connected to a trace array this bit should match the corresponding speed of the array.
9	RW	RW		OCB_OCI_GPEDBG_DIS_FLOW_CHANGE: When set, do not record code flow change and IAR trace events (taken & untaken branches, Interrupts/Exceptions, RFI, WRTEE, or Sync Events). Setting this mode is only supported when EN_COVERAGE_MODE=1.
10:11	RW	RW		OCB_OCI_GPEDBG_TRACE_MODE_SEL: Bit 0 chooses between 0: PPE Core Debug Mode A; 1: Mode B Bit 1 when set, ORs in the secondary valid corresponding to lower bits of the trace data when they are from a different source than bits 0:23 (NOTE: likely 0 for HTM tracing)
12	RW	RW		OCB_OCI_GPEDBG_EN_MARK_TRACE: Traces a unique record with an additional 16-bits to capture the (TG, TO, RA, and RB) fields on MARK type instructions.
13	RW	RW		OCB_OCI_GPEDBG_EN_EE_TRACE: Traces wrtee or wrteei instructions along with the new value of the EE bit with a unique record. If (EN_TRACE_EXTRA=0 or EN_COVERAGE_MODE=1), a unique record is also generated for RFI and MTMSR and exceptions to trace the value of the EE bit .
14:15	RW	RW		OCB_OCI_GPEDBG_RESERVED14_15: Implemented but not used.
16	RW	RW		OCB_OCI_GPEDBG_FIR_TRIGGER: NOT CONNECTED. GPE can write FIR directly if needed. Intended to Programmatically assert a FIR bit to inject checkstop or send Attention to the Service Element.
17:19	RW	RW		OCB_OCI_GPEDBG_SPARE: Spare (used for GPIO on other instances)
20:23	RW	RW		OCB_OCI_GPEDBG_TRACE_DATA_SEL: Mux select to choose debug data content on the trace bus. All 16 encodes are defined as per the table in the Debug Bolt-on chapter of the Power Management Spec. 0x0 chooses an 88-bit PPE-RISCtrace by default. b00XX enables Risctrace records to be generated in the upper 64-bits of trace data. bXX00 selects the remaining 24 bits to form 88-bit Trace Packets to be generated on the debug bus to be sent to the hardware trace array (otherwise PPE, MIB, or EXT data will be used) The other 12 encodes contain permutations of the PPE Core, Memory Interface, and External debug buses instead of RISCtrace records.
24:63	RO	RO		constant=0b0000000000000000000000000000000000000000

OCB_OCI GPE Memory Access Configuration Register
Addr:	0000000000060004 (SCOM) 00000000C0000020 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEMACR
Constant(s):
Comments:	This register controls Memory Access Priority on the OCI.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:12	TP.TPCHIP.OCC.OCI.GPE0.PPEREG.GPEMACR_Q_0_INST.LATC.L2(0:12) [0000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:1	RW	RW		OCB_OCI_GPEMACR_MEM_LOW_PRIORITY: OCI priority to use for accessing Main Memory when Address(0:1) = "10" and the PPE high priority output is 0
2:3	RW	RW		OCB_OCI_GPEMACR_MEM_HIGH_PRIORITY: OCI priority to use for accessing Main Memory when Address(0:1) = "10" and the PPE high priority output is 1
4:5	RW	RW		OCB_OCI_GPEMACR_LOCAL_LOW_PRIORITY: OCI priority to use for accessing Local Registers when Address(0:2) = "110" and the PPE high priority output is 0
6:7	RW	RW		OCB_OCI_GPEMACR_LOCAL_HIGH_PRIORITY: OCI priority to use for accessing Local Registers when Address(0:2) = "110" and the PPE high priority output is 1
8:9	RW	RW		OCB_OCI_GPEMACR_SRAM_LOW_PRIORITY: OCI priority to use for accessing SRAM tank when Address(0:2) = "111" and the PPE high priority output is 0
10:11	RW	RW		OCB_OCI_GPEMACR_SRAM_HIGH_PRIORITY: OCI priority to use for accessing SRAM tank when Address(0:2) = "111" and the PPE high priority output is 1
12	RW	RW		OCB_OCI_GPEMACR_WRITE_PROTECT_ENABLE: Enables PPE write protect regions. When 0, the contents of GPESWPR[n] have no effect. When 1, and GPEWPR[n] are non-zero, this GPE can only write the OCC SRAM in the configured regions.
13:63	RO	RO		constant=0b000000000000000000000000000000000000000000000000000

OCB_OCI GPE SRAM Write Protect Register 0
Addr:	0000000000060005 (SCOM) 00000000C0000028 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPESWPR0
Constant(s):
Comments:	When enabled, these registers control the regions of OCC SRAM the GPE is allowed to write.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.OCC.OCI.GPE0.PPEREG.GPESWPR0A_Q_0_INST.LATC.L2(0:26) [000000000000000000000000000]
	44:58	TP.TPCHIP.OCC.OCI.GPE0.PPEREG.GPESWPR0B_Q_44_INST.LATC.L2(44:58) [000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:26	RW	RW		OCB_OCI_GPESWPR0_WRITE_PROTECT_BAR: Base address of write protect region 0. Must be 32B aligned
27:43	RO	RO		constant=0b00000000000000000
44:58	RW	RW		OCB_OCI_GPESWPR0_WRITE_PROTECT_SIZE: Size of write protect region 0 in 32B units. Bit aligned so the size can be added to the BAR to compute the maximum address of this write protect region. Maximum address is bar+size*32-1.
59:63	RO	RO		constant=0b00000

OCB_OCI GPE SRAM Write Protect Register 1
Addr:	0000000000060006 (SCOM) 00000000C0000030 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPESWPR1
Constant(s):
Comments:	When enabled, these registers control the regions of OCC SRAM the GPE is allowed to write.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.OCC.OCI.GPE0.PPEREG.GPESWPR1A_Q_0_INST.LATC.L2(0:26) [000000000000000000000000000]
	44:58	TP.TPCHIP.OCC.OCI.GPE0.PPEREG.GPESWPR1B_Q_44_INST.LATC.L2(44:58) [000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:26	RW	RW		OCB_OCI_GPESWPR1_WRITE_PROTECT_BAR: Base address of write protect region 1. Must be 32B aligned
27:43	RO	RO		constant=0b00000000000000000
44:58	RW	RW		OCB_OCI_GPESWPR1_WRITE_PROTECT_SIZE: Size of write protect region 1 in 32B units. Bit aligned so the size can be added to the BAR to compute the maximum address of this write protect region. Maximum address is bar+size*32-1.
59:63	RO	RO		constant=0b00000

OCB_OCI GPE External Interface XCR
Addr:	0000000000060010 (SCOM) 00000000C0000080 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIXCR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR0 External Control Register (XCR) Note: CTR was added for P10
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.LT_XIR_XCR_CMND.LATC.L2(0:2) [000]
	32:63	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_CTR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	RO	RO		constant=0b0
1:3	WOX	WOX		OCB_OCI_GPEOXIXCR_XCR: PPE External Control Register See PPE Specification for bit definitions. Corresponds to XIR0 bits 1:3
4:31	RO	RO		constant=0b0000000000000000000000000000
32:63	ROX	ROX		OCB_OCI_GPEXICTR_CTR: Count Register. Added for P10. Potentially useful for Debug since can indicate loop iteration or a recent branch target address, depending on compiler optimization decisions. Corresponds to XIR0 bits 32:63

OCB_OCI GPE External Interface RAMRA
Addr:	0000000000060011 (SCOM) 00000000C0000088 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIRAMRA
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR1 Ram Restore Acceleration Register. Can be used to restore SPRG0 plus Resume (or Single Step) with one command.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.LT_XIR_XCR_CMND.LATC.L2(0:2) [000]
	32:63	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_SPRG0.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	RO	RO		constant=0b0
1:3	WOX	WOX		OCB_OCI_GPEOXIXCR_XCR: PPE External Control Register See PPE Specification for bit definitions. Corresponds to XIR0 bits 1:3
4:31	RO	RO		constant=0b0000000000000000000000000000
32:63	WOX	WOX		SPRG0

OCB_OCI GPE External Interface RAMGA
Addr:	0000000000060012 (SCOM) 00000000C0000090 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIRAMGA
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR2 Ram GPR Acceleration Register. Can be used to modify a GPR with one command (where IR = MFSPRG0 instruction 0xFC2082A6 .. 0xFFD082A6)
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_ISP.LT_IR.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_SPRG0.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	WOX	WOX		OCB_OCI_GPEXIRAMEDR_IR: PPE Instruction Register. Writes cause a RAM operation. Provides the requested PPE Instruction to execute.
32:63	WOX	WOX		SPRG0

OCB_OCI GPE External Interface RAMDBG
Addr:	0000000000060013 (SCOM) 00000000C0000098 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIRAMDBG
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR3 Ram & Debug Register. Read status and data. Allows write ability to modify only SPRG0 for a subsequent RAM operation.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.XSR_INT_SPR(0) [0]
	1:3	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_HC.LATC.L2(0:2) [000]
	4	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_HCP.LATC.L2(0) [0]
	5	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_RIP.LATC.L2(0) [0]
	6	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_SIP.LATC.L2(0) [0]
	7	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_TRAP.LATC.L2(0) [0]
	8	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_IAC.LATC.L2(0) [0]
	9:11	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(9:11) [000]
	12	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_RDAC.LATC.L2(0) [0]
	13	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_WDAC.LATC.L2(0) [0]
	14	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(13) [0]
	15	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_TRH.LATC.L2(0) [0]
	16:19	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_DECODER.FSM_STATE_LATCH.LATC.L2(0:3) [0000]
	20	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(12) [0]
	21	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_EP.LATC.L2(0) [0]
	24:25	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_ISR_24_25.LATC.L2(24:25) [00]
	28:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_ISR_28_31.LATC.L2(28:31) [0000]
	32:63	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_SPRG0.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		XSR_HS
1:3	RWX	RWX		XSR_HC
4	ROX	ROX		XSR_HCP
5	ROX	ROX		XSR_RIP
6	ROX	ROX		XSR_SIP
7	RWX	RWX		XSR_TRAP
8	RWX	RWX		XSR_IAC
9:11	ROX	ROX		XSR_SIB
12	RWX	RWX		XSR_RDAC
13	RWX	RWX		XSR_WDAC
14	ROX	ROX		XSR_WS
15	ROX	ROX		XSR_TRH
16:19	ROX	ROX		XSR_SMS
20	ROX	ROX		XSR_LP
21	ROX	ROX		XSR_EP
22:23	RO	RO		constant=0b00
24	ROX	ROX		XSR_PTR
25	ROX	ROX		XSR_ST
26:27	RO	RO		constant=0b00
28	ROX	ROX		XSR_MFE
29:31	ROX	ROX		XSR_MCS
32:63	RWX	RWX		SPRG0

OCB_OCI GPE External Interface RAMEDR
Addr:	0000000000060014 (SCOM) 00000000C00000A0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIRAMEDR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR4 Ram & Error Diagnosis Register. Can be used to read IR and EDR for debug. Also provides ability to RAM an instruction without modifying SPRG0.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_ISP.LT_IR.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_EDR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RWX	RWX		OCB_OCI_GPEXIRAMEDR_IR: PPE Instruction Register. Writes cause a RAM operation. Provides the requested PPE Instruction to execute.
32:63	ROX	ROX		OCB_OCI_GPEXIRAMEDR_EDR: Error Data Register, set on PPE interrupts caused by an error. See PPE Specification for definition.

OCB_OCI GPE External Interface DBGPRO
Addr:	0000000000060015 (SCOM) 00000000C00000A8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIDBGPRO
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR5 Debug & Runtime Profiling Read program location and status. Also used to write XSR & IAR.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.XSR_INT_SPR(0) [0]
	1:3	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_HC.LATC.L2(0:2) [000]
	4	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_HCP.LATC.L2(0) [0]
	5	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_RIP.LATC.L2(0) [0]
	6	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_SIP.LATC.L2(0) [0]
	7	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_TRAP.LATC.L2(0) [0]
	8	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_IAC.LATC.L2(0) [0]
	9:11	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(9:11) [000]
	12	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_RDAC.LATC.L2(0) [0]
	13	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_WDAC.LATC.L2(0) [0]
	14	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(13) [0]
	15	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_TRH.LATC.L2(0) [0]
	16:19	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_DECODER.FSM_STATE_LATCH.LATC.L2(0:3) [0000]
	20	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(12) [0]
	21	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_EP.LATC.L2(0) [0]
	24:25	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_ISR_24_25.LATC.L2(24:25) [00]
	28:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_ISR_28_31.LATC.L2(28:31) [0000]
	32:61	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_ISP.LT_IAR.LATC.L2(0:29) [000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		XSR_HS
1:3	RWX	RWX		XSR_HC
4	ROX	ROX		XSR_HCP
5	ROX	ROX		XSR_RIP
6	ROX	ROX		XSR_SIP
7	RWX	RWX		XSR_TRAP
8	RWX	RWX		XSR_IAC
9:11	ROX	ROX		XSR_SIB
12	RWX	RWX		XSR_RDAC
13	RWX	RWX		XSR_WDAC
14	ROX	ROX		XSR_WS
15	ROX	ROX		XSR_TRH
16:19	ROX	ROX		XSR_SMS
20	ROX	ROX		XSR_LP
21	ROX	ROX		XSR_EP
22:23	RO	RO		constant=0b00
24	ROX	ROX		XSR_PTR
25	ROX	ROX		XSR_ST
26:27	RO	RO		constant=0b00
28	ROX	ROX		XSR_MFE
29:31	ROX	ROX		XSR_MCS
32:61	RWX	RWX		OCB_OCI_GPEXIIAR_IAR: PPE Instruction Address Register See PPE Specification for bit definitions. Corresponds to XIR5 bits 32:63
62:63	RO	RO		constant=0b00

OCB_OCI GPE External Interface SIB Info
Addr:	0000000000060016 (SCOM) 00000000C00000B0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXISIB
Constant(s):
Comments:	XIR6 SIB Transaction buffer info for debug
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	32	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_R_NW_Q_INST.LATC.L2(0) [0]
	33	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_BUSY_Q_INST.LATC.L2(0) [0]
	34	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.PIB_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0]
	49:51	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_RSP_INFO_Q_0_INST.LATC.L2(0:2) [000]
	61	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_RESET_PENDING_Q_INST.LATC.L2(0) [0]
	62	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.IFETCH_PIB_PENDING_Q_INST.LATC.L2(0) [0]
	63	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.PIB_DATAOP_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXISIB_PIB_ADDR: PIB transaction buffer current or previous transaction byte address
32	ROX	ROX		OCB_OCI_GPEXISIB_PIB_R_NW: PIB transaction buffer current or previous transaction type, read if 1 and write if 0.
33	ROX	ROX		OCB_OCI_GPEXISIB_PIB_BUSY: Indicates if the transaction buffer is occupied with an ongoing transaction. Busy is cleared when the transaction is completed.
34	ROX	ROX		OCB_OCI_GPEXISIB_PIB_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the PIB interface can continue to service I-fetches (only in case of SBE instance).
35:48	RO	RO		constant=0b00000000000000
49:51	ROX	ROX		OCB_OCI_GPEXISIB_PIB_RSP_INFO: PIB transaction buffer response info. Current or previous transaction got an error on the PIB interface when non-zero.
52:60	RO	RO		constant=0b000000000
61	ROX	ROX		OCB_OCI_GPEXISIB_PIB_RESET_PENDING: Indicates if hard reset occurred during an ongoing transcation and transaction is still pending when set to 1.
62	ROX	ROX		OCB_OCI_GPEXISIB_PIB_IFETCH_PENDING: Indicates a instruction fetch is pending on the PIB interface when set to 1.
63	ROX	ROX		OCB_OCI_GPEXISIB_PIB_DATAOP_PENDING: Indicates a data transaction is pending on the PIB interface when set to 1.

OCB_OCI GPE External Interface MEM Info
Addr:	0000000000060017 (SCOM) 00000000C00000B8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIMEM
Constant(s):
Comments:	XIR7 Memory Interface transaction buffer info for debug
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.MEM_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	32	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.MEM_R_NW_Q_INST.LATC.L2(0) [0]
	33	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.MEM_BUSY_Q_INST.LATC.L2(0) [0]
	34	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.MEM_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0]
	35:42	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.MEM_BYTE_ENABLE_Q_0_INST.LATC.L2(0:7) [00000000]
	43	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.MEM_LINE_MODE_Q_INST.LATC.L2(0) [0]
	49:51	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.MEM_ERROR_Q_0_INST.LATC.L2(0:2) [000]
	62	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.IFETCH_MEM_PENDING_Q_INST.LATC.L2(0) [0]
	63	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.MEM_DATAOP_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_ADDR: MEM transaction buffer current or previous transaction byte address.
32	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_R_NW: MEM transaction buffer current or previous transaction type, read if 1 and write if 0.
33	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_BUSY: Indicates if the transaction buffer is occupied with an ongoing transaction. Busy is cleared when the transaction is completed.
34	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the memory interface can continue to service I-fetches.
35:42	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_BYTE_ENABLE: MEM transaction buffer current or previous transaction byte enables.
43	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_LINE_MODE: MEM transaction buffer current or previous transaction line mode. Indicates a 32B read request when set to 1.
44:48	RO	RO		constant=0b00000
49:51	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_ERROR: MEM transaction buffer error code. Current or previous transaction got an error on the memory interface when non-zero.
52:61	RO	RO		constant=0b0000000000
62	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IFETCH_PENDING: Indicates a instruction fetch is pending on the MEM interface when set to 1.
63	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_DATAOP_PENDING: Indicates a data transaction is pending on the MEM interface when set to 1.

OCB_OCI GPE External Interface Store Gather Buffer Info
Addr:	0000000000060018 (SCOM) 00000000C00000C0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXISGB
Constant(s):
Comments:	XIR8 Store Gather Buffer Info for debug
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.STR_GTHR_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	35	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.MEM_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0]
	36:39	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.STR_GTHR_VALID_Q_0_INST.LATC.L2(0:3) [0000]
	63	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.STR_GTHR_FLUSH_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		STORE_ADDRESS
32:34	RO	RO		constant=0b000
35	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the memory interface can continue to service I-fetches.
36:39	ROX	ROX		SGB_BYTE_VALID
40:62	RO	RO		constant=0b00000000000000000000000
63	ROX	ROX		SGB_FLUSH_PENDING

OCB_OCI GPE External Interface Icache Info
Addr:	0000000000060019 (SCOM) 00000000C00000C8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIICAC
Constant(s):
Comments:	XIR9 Instruction Cache Info for debug
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.ICACHE_COMP.ICACHE_TAG_ADDR_LATCH.LATC.L2(0:26) [000000000000000000000000000]
	32	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.ICACHE_COMP.ICACHE_ERR_LATCH.LATC.L2(0) [0]
	34	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.IFETCH_PIB_PENDING_Q_INST.LATC.L2(0) [0]
	35	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.IFETCH_MEM_PENDING_Q_INST.LATC.L2(0) [0]
	36:39	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.ICACHE_COMP.ICACHE_VALID_LATCH.LATC.L2(0:3) [0000]
	40:43	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.ICACHE_COMP.INCLUDE_ADDN_CACHE_LINE.ICACHE_LINE2_VALID_LATCH.LATC.L2(0:3) [0000]
	45	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.ICACHE_COMP.INCLUDE_ADDN_CACHE_LINE.ICACHE_LINE_PTR_LATCH.LATC.L2(0) [0]
	46	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.ICACHE_COMP.INCLUDE_ADDN_CACHE_LINE.ICACHE_LINE2_ERR_LATCH.LATC.L2(0) [0]
	47	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.INCLUDE_PREFETCH.ICACHE_PREFETCH_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0:26	ROX	ROX		ICACHE_TAG_ADDR
27:31	RO	RO		constant=0b00000
32	ROX	ROX		ICACHE_ERR
33	RO	RO		constant=0b0
34	ROX	ROX		OCB_OCI_GPEXISIB_PIB_IFETCH_PENDING: Indicates a instruction fetch is pending on the PIB interface when set to 1.
35	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IFETCH_PENDING: Indicates a instruction fetch is pending on the MEM interface when set to 1.
36:39	ROX	ROX		ICACHE_VALID
40:43	ROX	ROX		ICACHE_LINE2_VALID
44	RO	RO		constant=0b0
45	ROX	ROX		ICACHE_LINE_PTR
46	ROX	ROX		ICACHE_LINE2_ERR
47	ROX	ROX		ICACHE_PREFETCH_PENDING
48:63	RO	RO		constant=0b0000000000000000

OCB_OCI GPE External Interface Dcache Info
Addr:	000000000006001A (SCOM) 00000000C00000D0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIDCAC
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR10 Data Cache Info for debug
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_COMP.DCACHE_TAG_ADDR_LATCH.LATC.L2(0:26) [000000000000000000000000000]
	32	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_COMP.DCACHE_ERR.LATC.L2(0) [0]
	35	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_POPULATE_PENDING_Q_INST.LATC.L2(0) [0]
	36:39	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_COMP.DCACHE_VALID_LATCH.LATC.L2(0:3) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0:26	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_TAG_ADDR: 32B Data Address Tag for the current or previous cache content.
27:31	RO	RO		constant=0b00000
32	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_ERR: Indicates the current or previous content of the cache is bad due to an interface error during populate.
33:34	RO	RO		constant=0b00
35	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_POPULATE_PENDING: Data populate to D-Cache pending from MEM interface.
36:39	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_VALID: Double word valids indicating the corresponding double word in the cache is valid
40:63	RO	RO		constant=0b000000000000000000000000

OCB_OCI GPE External Interface DBGINF
Addr:	000000000006001F (SCOM) 00000000C00000F8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIDBGINF
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: Debug Information Read registers containing recent program address information. New for P10.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:29	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_SRR0.LATC.L2(0:29) [000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_LR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:29	ROX	ROX		OCB_OCI_GPEXIDBGINF_SRR0: PPE Save & Restore Register 0 Contains address of the most recent interrupt taken. Potentially useful during debug.
30:31	RO	RO		constant=0b00
32:63	ROX	ROX		OCB_OCI_GPEXIDBGINF_LR: PPE Link Register. Contains address of the instruction following the most recent Branch with Link instruction executed, to give an idea from whence the code recently came. Potentially useful during debug.

OCB_OCI GPE External Interface OCI-Word XCR
Addr:	0000000000060020 (SCOM) 00000000C0000100 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEOXIXCR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR0(0:31) External Control Register (XCR). Note this is the same as GPEXIXCR but included separately for consistency in 32-bit access OCI address mapping.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.LT_XIR_XCR_CMND.LATC.L2(0:2) [000]
Bit(s)	SCOM	OCI		Dial: Description
0	RO	RO		constant=0b0
1:3	WOX	WOX		OCB_OCI_GPEOXIXCR_XCR: PPE External Control Register See PPE Specification for bit definitions. Corresponds to XIR0 bits 1:3
4:63	RO	RO		constant=0b000000000000000000000000000000000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word XSR
Addr:	0000000000060021 (SCOM) 00000000C0000108 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIXSR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR3(0:31) External Status Register (XSR)
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.XSR_INT_SPR(0) [0]
	1:3	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_HC.LATC.L2(0:2) [000]
	4	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_HCP.LATC.L2(0) [0]
	5	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_RIP.LATC.L2(0) [0]
	6	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_SIP.LATC.L2(0) [0]
	7	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_TRAP.LATC.L2(0) [0]
	8	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_IAC.LATC.L2(0) [0]
	9:11	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(9:11) [000]
	12	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_RDAC.LATC.L2(0) [0]
	13	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_WDAC.LATC.L2(0) [0]
	14	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(13) [0]
	15	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_TRH.LATC.L2(0) [0]
	16:19	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_DECODER.FSM_STATE_LATCH.LATC.L2(0:3) [0000]
	20	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(12) [0]
	21	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_XSR_EP.LATC.L2(0) [0]
	24:25	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_ISR_24_25.LATC.L2(24:25) [00]
	28:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_ISR_28_31.LATC.L2(28:31) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		XSR_HS
1:3	ROX	ROX		XSR_HC
4	ROX	ROX		XSR_HCP
5	ROX	ROX		XSR_RIP
6	ROX	ROX		XSR_SIP
7	ROX	ROX		XSR_TRAP
8	ROX	ROX		XSR_IAC
9:11	ROX	ROX		XSR_SIB
12	ROX	ROX		XSR_RDAC
13	ROX	ROX		XSR_WDAC
14	ROX	ROX		XSR_WS
15	ROX	ROX		XSR_TRH
16:19	ROX	ROX		XSR_SMS
20	ROX	ROX		XSR_LP
21	ROX	ROX		XSR_EP
22:23	RO	RO		constant=0b00
24	ROX	ROX		XSR_PTR
25	ROX	ROX		XSR_ST
26:27	RO	RO		constant=0b00
28	ROX	ROX		XSR_MFE
29:31	ROX	ROX		XSR_MCS
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word SPRG0
Addr:	0000000000060022 (SCOM) 00000000C0000110 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXISPRG0
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR3(32:63) SPRG0 register
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_SPRG0.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RWX	RWX		SPRG0
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word EDR
Addr:	0000000000060023 (SCOM) 00000000C0000118 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIEDR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR4(32:63) Error Data Register (EDR)
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_EDR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIRAMEDR_EDR: Error Data Register, set on PPE interrupts caused by an error. See PPE Specification for definition.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word IR
Addr:	0000000000060024 (SCOM) 00000000C0000120 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIIR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR4(0:31) Instruction Register (IR)
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_ISP.LT_IR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RWX	RWX		OCB_OCI_GPEXIRAMEDR_IR: PPE Instruction Register. Writes cause a RAM operation. Provides the requested PPE Instruction to execute.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word IAR
Addr:	0000000000060025 (SCOM) 00000000C0000128 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIIAR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR5(32:63) Instruction Register (IAR)
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:29	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_ISP.LT_IAR.LATC.L2(0:29) [000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:29	RWX	RWX		OCB_OCI_GPEXIIAR_IAR: PPE Instruction Address Register See PPE Specification for bit definitions. Corresponds to XIR5 bits 32:63
30:63	RO	RO		constant=0b0000000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word SIB Info Upper
Addr:	0000000000060026 (SCOM) 00000000C0000130 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXISIBU
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR6(0:31) SIB Info Upper bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RO	RO		OCB_OCI_GPEXISIB_PIB_ADDR: PIB transaction buffer current or previous transaction byte address
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word SIB Info Lower
Addr:	0000000000060027 (SCOM) 00000000C0000138 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXISIBL
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR6(32:63) SIB Info Lower bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_R_NW_Q_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_BUSY_Q_INST.LATC.L2(0) [0]
	2	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.PIB_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0]
	17:19	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_RSP_INFO_Q_0_INST.LATC.L2(0:2) [000]
	30	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.IFETCH_PIB_PENDING_Q_INST.LATC.L2(0) [0]
	31	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.PIB_DATAOP_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		OCB_OCI_GPEXISIB_PIB_R_NW: PIB transaction buffer current or previous transaction type, read if 1 and write if 0.
1	ROX	ROX		OCB_OCI_GPEXISIB_PIB_BUSY: Indicates if the transaction buffer is occupied with an ongoing transaction. Busy is cleared when the transaction is completed.
2	ROX	ROX		OCB_OCI_GPEXISIB_PIB_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the PIB interface can continue to service I-fetches (only in case of SBE instance).
3:16	RO	RO		constant=0b00000000000000
17:19	ROX	ROX		OCB_OCI_GPEXISIB_PIB_RSP_INFO: PIB transaction buffer response info. Current or previous transaction got an error on the PIB interface when non-zero.
20:29	RO	RO		constant=0b0000000000
30	ROX	ROX		OCB_OCI_GPEXISIB_PIB_IFETCH_PENDING: Indicates a instruction fetch is pending on the PIB interface when set to 1.
31	ROX	ROX		OCB_OCI_GPEXISIB_PIB_DATAOP_PENDING: Indicates a data transaction is pending on the PIB interface when set to 1.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word MEM Info Upper
Addr:	0000000000060028 (SCOM) 00000000C0000140 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIMEMU
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR7(0:31) Memory Interface Info Upper bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.MEM_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_ADDR: MEM transaction buffer current or previous transaction byte address.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word MEM Info Lower
Addr:	0000000000060029 (SCOM) 00000000C0000148 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIMEML
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR7(32:63) Memory Interface Info Lower bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.MEM_BUSY_Q_INST.LATC.L2(0) [0]
	2	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.MEM_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0]
	3:10	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.MEM_BYTE_ENABLE_Q_0_INST.LATC.L2(0:7) [00000000]
	11	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.MEM_LINE_MODE_Q_INST.LATC.L2(0) [0]
	12	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.MIB_SCOM_REG_2_DATA(44) [0]
	17:19	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.MEM_ERROR_Q_0_INST.LATC.L2(0:2) [000]
	30	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.IFETCH_MEM_PENDING_Q_INST.LATC.L2(0) [0]
	31	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.MEM_DATAOP_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0	RO	RO		constant=0b0
1	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_BUSY: Indicates if the transaction buffer is occupied with an ongoing transaction. Busy is cleared when the transaction is completed.
2	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the memory interface can continue to service I-fetches.
3:10	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_BYTE_ENABLE: MEM transaction buffer current or previous transaction byte enables.
11	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_LINE_MODE: MEM transaction buffer current or previous transaction line mode. Indicates a 32B read request when set to 1.
12	ROX	ROX		Memory_Info_Lower_part1
13:16	RO	RO		constant=0b0000
17:19	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_ERROR: MEM transaction buffer error code. Current or previous transaction got an error on the memory interface when non-zero.
20:29	RO	RO		constant=0b0000000000
30	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IFETCH_PENDING: Indicates a instruction fetch is pending on the MEM interface when set to 1.
31	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_DATAOP_PENDING: Indicates a data transaction is pending on the MEM interface when set to 1.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word SGB Info Upper
Addr:	000000000006002A (SCOM) 00000000C0000150 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXISGBU
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR8(0:31) Store Gather Buffer Info Upper bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.STR_GTHR_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		SGB_Info_Upper
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word SGB Info Lower
Addr:	000000000006002B (SCOM) 00000000C0000158 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXISGBL
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR8(32:63) Store Gather Buffer Info Lower bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	3	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.MEM_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0]
	4:7	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.STR_GTHR_VALID_Q_0_INST.LATC.L2(0:3) [0000]
	31	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.STR_GTHR_FLUSH_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0:2	RO	RO		constant=0b000
3	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the memory interface can continue to service I-fetches.
4:7	ROX	ROX		SGB_Info_Lower_part1
8:30	RO	RO		constant=0b00000000000000000000000
31	ROX	ROX		SGB_Info_Lower_part2
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word Icache Info Upper
Addr:	000000000006002C (SCOM) 00000000C0000160 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIICACU
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR9(0:31) Instruction Cache Info Upper bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.ICACHE_COMP.ICACHE_TAG_ADDR_LATCH.LATC.L2(0:26) [000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:26	ROX	ROX		Icache_Info_Upper
27:63	RO	RO		constant=0b0000000000000000000000000000000000000

OCB_OCI GPE External Interface MEM Icache Info Lower
Addr:	000000000006002D (SCOM) 00000000C0000168 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIICACL
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR9(32:63) Instruction Cache Info Lower bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.ICACHE_COMP.ICACHE_ERR_LATCH.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.MIB_SCOM_REG_4_DATA(33) [0]
	2	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.IFETCH_PIB_PENDING_Q_INST.LATC.L2(0) [0]
	3	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.IFETCH_MEM_PENDING_Q_INST.LATC.L2(0) [0]
	4:7	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.ICACHE_COMP.ICACHE_VALID_LATCH.LATC.L2(0:3) [0000]
	8:11	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.ICACHE_COMP.INCLUDE_ADDN_CACHE_LINE.ICACHE_LINE2_VALID_LATCH.LATC.L2(0:3) [0000]
	13	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.ICACHE_COMP.INCLUDE_ADDN_CACHE_LINE.ICACHE_LINE_PTR_LATCH.LATC.L2(0) [0]
	14	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.ICACHE_COMP.INCLUDE_ADDN_CACHE_LINE.ICACHE_LINE2_ERR_LATCH.LATC.L2(0) [0]
	15	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.INCLUDE_PREFETCH.ICACHE_PREFETCH_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0:1	ROX	ROX		Icache_Info_Lower_part1
2	ROX	ROX		OCB_OCI_GPEXISIB_PIB_IFETCH_PENDING: Indicates a instruction fetch is pending on the PIB interface when set to 1.
3	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IFETCH_PENDING: Indicates a instruction fetch is pending on the MEM interface when set to 1.
4:11	ROX	ROX		Icache_Info_Lower_part1
12	RO	RO		constant=0b0
13:15	ROX	ROX		Icache_Info_Lower_part2
16:63	RO	RO		constant=0b000000000000000000000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word Dcache Info Upper
Addr:	000000000006002E (SCOM) 00000000C0000170 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIDCACU
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR10(0:31) Data Cache Info Upper bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_COMP.DCACHE_TAG_ADDR_LATCH.LATC.L2(0:26) [000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:26	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_TAG_ADDR: 32B Data Address Tag for the current or previous cache content.
27:31	RO	RO		constant=0b00000

OCB_OCI GPE External Interface MEM Dcache Info Lower
Addr:	000000000006002F (SCOM) 00000000C0000178 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIDCACL
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR10(32:63) Data Cache Info Lower bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_COMP.DCACHE_ERR.LATC.L2(0) [0]
	3	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_POPULATE_PENDING_Q_INST.LATC.L2(0) [0]
	4:7	TP.TPCHIP.OCC.OCI.GPE0.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_COMP.DCACHE_VALID_LATCH.LATC.L2(0:3) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_ERR: Indicates the current or previous content of the cache is bad due to an interface error during populate.
1:2	RO	RO		constant=0b00
3	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_POPULATE_PENDING: Data populate to D-Cache pending from MEM interface.
4:7	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_VALID: Double word valids indicating the corresponding double word in the cache is valid
8:31	RO	RO		constant=0b000000000000000000000000

OCB_OCI GPE External Interface OCI-Word SRR0
Addr:	0000000000060030 (SCOM) 00000000C0000180 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXISRR0
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR15(0:31) SRR0
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:29	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_SRR0.LATC.L2(0:29) [000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:29	ROX	ROX		OCB_OCI_GPEXIDBGINF_SRR0: PPE Save & Restore Register 0 Contains address of the most recent interrupt taken. Potentially useful during debug.
30:63	RO	RO		constant=0b0000000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word LR
Addr:	0000000000060031 (SCOM) 00000000C0000188 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXILR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR15(32:63) Link Register (LR)
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_LR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIDBGINF_LR: PPE Link Register. Contains address of the instruction following the most recent Branch with Link instruction executed, to give an idea from whence the code recently came. Potentially useful during debug.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word CTR
Addr:	0000000000060032 (SCOM) 00000000C0000190 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXICTR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR0(32:63) CTR
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_SPR.LT_CTR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXICTR_CTR: Count Register. Added for P10. Potentially useful for Debug since can indicate loop iteration or a recent branch target address, depending on compiler optimization decisions. Corresponds to XIR0 bits 32:63
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR0
Addr:	0000000000060040 (SCOM) 00000000C0000200 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR0
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR0
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR0.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR0_GPR0: General Purpose Register 0
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR1
Addr:	0000000000060041 (SCOM) 00000000C0000208 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR1
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR1
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR1.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR0_GPR1: General Purpose Register 1
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR2
Addr:	0000000000060042 (SCOM) 00000000C0000210 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR2
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR2
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR2.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR2_GPR2: General Purpose Register 2
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR3
Addr:	0000000000060043 (SCOM) 00000000C0000218 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR3
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR3
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR3.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR2_GPR3: General Purpose Register 3
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR4
Addr:	0000000000060044 (SCOM) 00000000C0000220 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR4
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR4
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR4.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR4_GPR4: General Purpose Register 4
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR5
Addr:	0000000000060045 (SCOM) 00000000C0000228 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR5
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR5
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR5.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR4_GPR5: General Purpose Register 5
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR6
Addr:	0000000000060046 (SCOM) 00000000C0000230 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR6
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR6
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR6.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR6_GPR6: General Purpose Register 6
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR7
Addr:	0000000000060047 (SCOM) 00000000C0000238 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR7
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR7
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR7.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR6_GPR7: General Purpose Register 7
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR8
Addr:	0000000000060048 (SCOM) 00000000C0000240 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR8
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR8
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR8.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR8_GPR8: General Purpose Register 8
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR9
Addr:	0000000000060049 (SCOM) 00000000C0000248 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR9
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR9
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR9.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR8_GPR9: General Purpose Register 9
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR10
Addr:	000000000006004A (SCOM) 00000000C0000250 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR10
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR10
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR10.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDRX_GPR10: General Purpose Register 10
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR13
Addr:	000000000006004B (SCOM) 00000000C0000258 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR13
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR13
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR13.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDRX_GPR13_11: DD1: General Purpose Register 13 DD2: General Purpose Register 11
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR28
Addr:	000000000006004C (SCOM) 00000000C0000260 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR28
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR28
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR28.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR28_GPR28: General Purpose Register 28
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR29
Addr:	000000000006004D (SCOM) 00000000C0000268 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR29
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR29
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR29.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR28_GPR29: General Purpose Register 29
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR30
Addr:	000000000006004E (SCOM) 00000000C0000270 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR30
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR30
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR30.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR30_GPR30: General Purpose Register 30
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR31
Addr:	000000000006004F (SCOM) 00000000C0000278 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR31
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR31
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR31.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RO	RO		OCB_OCI_GPEXIVDR30_GPR31: General Purpose Register 31
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface VDR0
Addr:	0000000000060080 (SCOM) 00000000C0000400 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIVDR0
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR0 & GPR1
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR0.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR1.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR0_GPR0: General Purpose Register 0
32:63	ROX	ROX		OCB_OCI_GPEXIVDR0_GPR1: General Purpose Register 1

OCB_OCI GPE External Interface VDR2
Addr:	0000000000060081 (SCOM) 00000000C0000408 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIVDR2
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR2 & GPR3
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR2.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR3.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR2_GPR2: General Purpose Register 2
32:63	ROX	ROX		OCB_OCI_GPEXIVDR2_GPR3: General Purpose Register 3

OCB_OCI GPE External Interface VDR4
Addr:	0000000000060082 (SCOM) 00000000C0000410 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIVDR4
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR4 & GPR5
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR4.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR5.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR4_GPR4: General Purpose Register 4
32:63	ROX	ROX		OCB_OCI_GPEXIVDR4_GPR5: General Purpose Register 5

OCB_OCI GPE External Interface VDR6
Addr:	0000000000060083 (SCOM) 00000000C0000418 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIVDR6
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR6 & GPR7
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR6.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR7.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR6_GPR6: General Purpose Register 6
32:63	ROX	ROX		OCB_OCI_GPEXIVDR6_GPR7: General Purpose Register 7

OCB_OCI GPE External Interface VDR8
Addr:	0000000000060084 (SCOM) 00000000C0000420 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIVDR8
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR8 & GPR9
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR8.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR9.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR8_GPR8: General Purpose Register 8
32:63	ROX	ROX		OCB_OCI_GPEXIVDR8_GPR9: General Purpose Register 9

OCB_OCI GPE External Interface VDRX
Addr:	0000000000060085 (SCOM) 00000000C0000428 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIVDRX
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: DD1: Virtual Doubleword X (GPR10 & GPR13) DD2: Virtual Doubleword 10 (GPR10 & GPR11) Note: unlike other 64-bit GPR XIRs, this is not a true VDR.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR10.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR13.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDRX_GPR10: General Purpose Register 10
32:63	ROX	ROX		OCB_OCI_GPEXIVDRX_GPR13_11: DD1: General Purpose Register 13 DD2: General Purpose Register 11

OCB_OCI GPE External Interface VDR28
Addr:	0000000000060086 (SCOM) 00000000C0000430 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIVDR28
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR28 & GPR29
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR28.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR29.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR28_GPR28: General Purpose Register 28
32:63	ROX	ROX		OCB_OCI_GPEXIVDR28_GPR29: General Purpose Register 29

OCB_OCI GPE External Interface VDR30
Addr:	0000000000060087 (SCOM) 00000000C0000438 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIVDR30
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR30 & GPR31
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR30.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE0.GPE.PPE.I_C_PPE42_GPR.LT_GPR31.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR30_GPR30: General Purpose Register 30
32:63	ROX	ROX		OCB_OCI_GPEXIVDR30_GPR31: General Purpose Register 31

OCB_OCI GPE Timer Select Register
Addr:	0000000000062000 (SCOM) 00000000C0010000 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPETSEL
Constant(s):
Comments:	This register selects the rate of the Fixed Interval and Watchdog Timers The input to the PPE will pulse every 2^(23 - select) times the input timer period (which is the PAU cycle time/64), unless select is zero in which case the timer pulse is disabled. SUMMARY: the resultant timer rate is given by: 2^(29-select) / PAU_Frequency when select is non-zero.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.OCC.OCI.GPE1.PPEREG.GPETSEL_Q_0_INST.LATC.L2(0:7) [00000000]
Bit(s)	SCOM	OCI		Dial: Description
0:3	RW	RW		OCB_OCI_GPETSEL_WATCHDOG_SEL: Selects Watchdog Timer rate
4:7	RW	RW		OCB_OCI_GPETSEL_FIT_SEL: Selects Fixed Interval Timer rate
8:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000

OCB_OCI GPE Interrupt Vector Prefix Register
Addr:	0000000000062001 (SCOM) 00000000C0010008 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEIVPR
Constant(s):
Comments:	This register selects the top 23 bits of the Interrupt Address Vector.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:22	TP.TPCHIP.OCC.OCI.GPE1.PPEREG.GPEIVPR_Q_0_INST.LATC.L2(0:22) [00000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:22	RW	RW		OCB_OCI_GPEIVPR_IVPR: Interrupt Prefix Vector Register (Resets to 0xFFFFFE left justified)
23:63	RO	RO		constant=0b00000000000000000000000000000000000000000

OCB_OCI GPE Debug Mode Register
Addr:	0000000000062002 (SCOM) 00000000C0010010 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEDBG
Constant(s):
Comments:	This register contains mode bits controlling the debug bolt-on and PPE behavior on checkstop and trigger.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:23	TP.TPCHIP.OCC.OCI.GPE1.PPEREG.GPEDBG_Q_0_INST.LATC.L2(0:23) [000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	RW	RW		OCB_OCI_GPEDBG_EN_DBG: Enable Debug Trace. Master switch that enables clocks to the trace. Also causes RiscTrace to start on rising edge & stop on falling edge when RISCTRACE is enabled (TRACE_DATA_SEL(0)=0).
1	RW	RW		OCB_OCI_GPEDBG_HALT_ON_XSTOP: Enable Halt on Checkstop input
2	RW	RW		OCB_OCI_GPEDBG_HALT_ON_TRIG: Enable Halt on Trigger input
3	RW	RW		OCB_OCI_GPEDBG_EN_COVERAGE_MODE: Enables Code Coverage Trace Mode. When set, no longer traces every instruction executed, and adds SPRG0 and MARK data to the trace. Note: only supported when EN_INTR_ADDR and EN_TRACE_EXTRA are both set to 0.
4	RW	RW		OCB_OCI_GPEDBG_EN_INTR_ADDR: When RISCTRACE is enabled, trace the Full Interrupt Vector Address, otherwise only trace the lower byte of address.
5	RW	RW		OCB_OCI_GPEDBG_EN_TRACE_EXTRA: When RISCTRACE is enabled and this bit is set, records extra trace data not needed for 405 RISCTrace spec. When this bit is set, record MTMSR or MTSPRG0 data and new MSR value set by RFI.
6	RW	RW		OCB_OCI_GPEDBG_EN_TRACE_STALL: When RISCTRACE is enabled and this bit is set, stall cycles when the processor is not actively executing an instruction, that are not already included in the previous event, are recorded unless it is Halted or in Wait state. When this mode is not set, the RISTRACE is smaller but not time accurate.
7	RW	RW		OCB_OCI_GPEDBG_EN_WAIT_CYCLES: When RISCTRACE is enabled and this bit is set, Stall Events are used to record the number of cycles the PPE is in Wait state. Otherwise cycles in Wait state are ignored. When this bit is set, EN_TRACE_STALL must also be set.
8	RW	RW		OCB_OCI_GPEDBG_EN_FULL_SPEED: When set, the trace valid is pulsed at 1:1 (4x faster than the debug data, which changes at PPE clock speed). This is used for CHTM and NHTM (in memory trace). When this mode is NOT set, trace valid is held constant for a full PPE cycle (four 1:1 cycles). When connected to a trace array this bit should match the corresponding speed of the array.
9	RW	RW		OCB_OCI_GPEDBG_DIS_FLOW_CHANGE: When set, do not record code flow change and IAR trace events (taken & untaken branches, Interrupts/Exceptions, RFI, WRTEE, or Sync Events). Setting this mode is only supported when EN_COVERAGE_MODE=1.
10:11	RW	RW		OCB_OCI_GPEDBG_TRACE_MODE_SEL: Bit 0 chooses between 0: PPE Core Debug Mode A; 1: Mode B Bit 1 when set, ORs in the secondary valid corresponding to lower bits of the trace data when they are from a different source than bits 0:23 (NOTE: likely 0 for HTM tracing)
12	RW	RW		OCB_OCI_GPEDBG_EN_MARK_TRACE: Traces a unique record with an additional 16-bits to capture the (TG, TO, RA, and RB) fields on MARK type instructions.
13	RW	RW		OCB_OCI_GPEDBG_EN_EE_TRACE: Traces wrtee or wrteei instructions along with the new value of the EE bit with a unique record. If (EN_TRACE_EXTRA=0 or EN_COVERAGE_MODE=1), a unique record is also generated for RFI and MTMSR and exceptions to trace the value of the EE bit .
14:15	RW	RW		OCB_OCI_GPEDBG_RESERVED14_15: Implemented but not used.
16	RW	RW		OCB_OCI_GPEDBG_FIR_TRIGGER: NOT CONNECTED. GPE can write FIR directly if needed. Intended to Programmatically assert a FIR bit to inject checkstop or send Attention to the Service Element.
17:19	RW	RW		OCB_OCI_GPEDBG_SPARE: Spare (used for GPIO on other instances)
20:23	RW	RW		OCB_OCI_GPEDBG_TRACE_DATA_SEL: Mux select to choose debug data content on the trace bus. All 16 encodes are defined as per the table in the Debug Bolt-on chapter of the Power Management Spec. 0x0 chooses an 88-bit PPE-RISCtrace by default. b00XX enables Risctrace records to be generated in the upper 64-bits of trace data. bXX00 selects the remaining 24 bits to form 88-bit Trace Packets to be generated on the debug bus to be sent to the hardware trace array (otherwise PPE, MIB, or EXT data will be used) The other 12 encodes contain permutations of the PPE Core, Memory Interface, and External debug buses instead of RISCtrace records.
24:63	RO	RO		constant=0b0000000000000000000000000000000000000000

OCB_OCI GPE Memory Access Configuration Register
Addr:	0000000000062004 (SCOM) 00000000C0010020 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEMACR
Constant(s):
Comments:	This register controls Memory Access Priority on the OCI.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:12	TP.TPCHIP.OCC.OCI.GPE1.PPEREG.GPEMACR_Q_0_INST.LATC.L2(0:12) [0000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:1	RW	RW		OCB_OCI_GPEMACR_MEM_LOW_PRIORITY: OCI priority to use for accessing Main Memory when Address(0:1) = "10" and the PPE high priority output is 0
2:3	RW	RW		OCB_OCI_GPEMACR_MEM_HIGH_PRIORITY: OCI priority to use for accessing Main Memory when Address(0:1) = "10" and the PPE high priority output is 1
4:5	RW	RW		OCB_OCI_GPEMACR_LOCAL_LOW_PRIORITY: OCI priority to use for accessing Local Registers when Address(0:2) = "110" and the PPE high priority output is 0
6:7	RW	RW		OCB_OCI_GPEMACR_LOCAL_HIGH_PRIORITY: OCI priority to use for accessing Local Registers when Address(0:2) = "110" and the PPE high priority output is 1
8:9	RW	RW		OCB_OCI_GPEMACR_SRAM_LOW_PRIORITY: OCI priority to use for accessing SRAM tank when Address(0:2) = "111" and the PPE high priority output is 0
10:11	RW	RW		OCB_OCI_GPEMACR_SRAM_HIGH_PRIORITY: OCI priority to use for accessing SRAM tank when Address(0:2) = "111" and the PPE high priority output is 1
12	RW	RW		OCB_OCI_GPEMACR_WRITE_PROTECT_ENABLE: Enables PPE write protect regions. When 0, the contents of GPESWPR[n] have no effect. When 1, and GPEWPR[n] are non-zero, this GPE can only write the OCC SRAM in the configured regions.
13:63	RO	RO		constant=0b000000000000000000000000000000000000000000000000000

OCB_OCI GPE SRAM Write Protect Register 0
Addr:	0000000000062005 (SCOM) 00000000C0010028 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPESWPR0
Constant(s):
Comments:	When enabled, these registers control the regions of OCC SRAM the GPE is allowed to write.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.OCC.OCI.GPE1.PPEREG.GPESWPR0A_Q_0_INST.LATC.L2(0:26) [000000000000000000000000000]
	44:58	TP.TPCHIP.OCC.OCI.GPE1.PPEREG.GPESWPR0B_Q_44_INST.LATC.L2(44:58) [000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:26	RW	RW		OCB_OCI_GPESWPR0_WRITE_PROTECT_BAR: Base address of write protect region 0. Must be 32B aligned
27:43	RO	RO		constant=0b00000000000000000
44:58	RW	RW		OCB_OCI_GPESWPR0_WRITE_PROTECT_SIZE: Size of write protect region 0 in 32B units. Bit aligned so the size can be added to the BAR to compute the maximum address of this write protect region. Maximum address is bar+size*32-1.
59:63	RO	RO		constant=0b00000

OCB_OCI GPE SRAM Write Protect Register 1
Addr:	0000000000062006 (SCOM) 00000000C0010030 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPESWPR1
Constant(s):
Comments:	When enabled, these registers control the regions of OCC SRAM the GPE is allowed to write.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.OCC.OCI.GPE1.PPEREG.GPESWPR1A_Q_0_INST.LATC.L2(0:26) [000000000000000000000000000]
	44:58	TP.TPCHIP.OCC.OCI.GPE1.PPEREG.GPESWPR1B_Q_44_INST.LATC.L2(44:58) [000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:26	RW	RW		OCB_OCI_GPESWPR1_WRITE_PROTECT_BAR: Base address of write protect region 1. Must be 32B aligned
27:43	RO	RO		constant=0b00000000000000000
44:58	RW	RW		OCB_OCI_GPESWPR1_WRITE_PROTECT_SIZE: Size of write protect region 1 in 32B units. Bit aligned so the size can be added to the BAR to compute the maximum address of this write protect region. Maximum address is bar+size*32-1.
59:63	RO	RO		constant=0b00000

OCB_OCI GPE External Interface XCR
Addr:	0000000000062010 (SCOM) 00000000C0010080 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIXCR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR0 External Control Register (XCR) Note: CTR was added for P10
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.LT_XIR_XCR_CMND.LATC.L2(0:2) [000]
	32:63	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_CTR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	RO	RO		constant=0b0
1:3	WOX	WOX		OCB_OCI_GPEOXIXCR_XCR: PPE External Control Register See PPE Specification for bit definitions. Corresponds to XIR0 bits 1:3
4:31	RO	RO		constant=0b0000000000000000000000000000
32:63	ROX	ROX		OCB_OCI_GPEXICTR_CTR: Count Register. Added for P10. Potentially useful for Debug since can indicate loop iteration or a recent branch target address, depending on compiler optimization decisions. Corresponds to XIR0 bits 32:63

OCB_OCI GPE External Interface RAMRA
Addr:	0000000000062011 (SCOM) 00000000C0010088 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIRAMRA
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR1 Ram Restore Acceleration Register. Can be used to restore SPRG0 plus Resume (or Single Step) with one command.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.LT_XIR_XCR_CMND.LATC.L2(0:2) [000]
	32:63	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_SPRG0.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	RO	RO		constant=0b0
1:3	WOX	WOX		OCB_OCI_GPEOXIXCR_XCR: PPE External Control Register See PPE Specification for bit definitions. Corresponds to XIR0 bits 1:3
4:31	RO	RO		constant=0b0000000000000000000000000000
32:63	WOX	WOX		SPRG0

OCB_OCI GPE External Interface RAMGA
Addr:	0000000000062012 (SCOM) 00000000C0010090 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIRAMGA
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR2 Ram GPR Acceleration Register. Can be used to modify a GPR with one command (where IR = MFSPRG0 instruction 0xFC2082A6 .. 0xFFD082A6)
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_ISP.LT_IR.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_SPRG0.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	WOX	WOX		OCB_OCI_GPEXIRAMEDR_IR: PPE Instruction Register. Writes cause a RAM operation. Provides the requested PPE Instruction to execute.
32:63	WOX	WOX		SPRG0

OCB_OCI GPE External Interface RAMDBG
Addr:	0000000000062013 (SCOM) 00000000C0010098 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIRAMDBG
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR3 Ram & Debug Register. Read status and data. Allows write ability to modify only SPRG0 for a subsequent RAM operation.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.XSR_INT_SPR(0) [0]
	1:3	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_HC.LATC.L2(0:2) [000]
	4	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_HCP.LATC.L2(0) [0]
	5	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_RIP.LATC.L2(0) [0]
	6	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_SIP.LATC.L2(0) [0]
	7	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_TRAP.LATC.L2(0) [0]
	8	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_IAC.LATC.L2(0) [0]
	9:11	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(9:11) [000]
	12	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_RDAC.LATC.L2(0) [0]
	13	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_WDAC.LATC.L2(0) [0]
	14	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(13) [0]
	15	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_TRH.LATC.L2(0) [0]
	16:19	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_DECODER.FSM_STATE_LATCH.LATC.L2(0:3) [0000]
	20	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(12) [0]
	21	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_EP.LATC.L2(0) [0]
	24:25	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_ISR_24_25.LATC.L2(24:25) [00]
	28:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_ISR_28_31.LATC.L2(28:31) [0000]
	32:63	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_SPRG0.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		XSR_HS
1:3	RWX	RWX		XSR_HC
4	ROX	ROX		XSR_HCP
5	ROX	ROX		XSR_RIP
6	ROX	ROX		XSR_SIP
7	RWX	RWX		XSR_TRAP
8	RWX	RWX		XSR_IAC
9:11	ROX	ROX		XSR_SIB
12	RWX	RWX		XSR_RDAC
13	RWX	RWX		XSR_WDAC
14	ROX	ROX		XSR_WS
15	ROX	ROX		XSR_TRH
16:19	ROX	ROX		XSR_SMS
20	ROX	ROX		XSR_LP
21	ROX	ROX		XSR_EP
22:23	RO	RO		constant=0b00
24	ROX	ROX		XSR_PTR
25	ROX	ROX		XSR_ST
26:27	RO	RO		constant=0b00
28	ROX	ROX		XSR_MFE
29:31	ROX	ROX		XSR_MCS
32:63	RWX	RWX		SPRG0

OCB_OCI GPE External Interface RAMEDR
Addr:	0000000000062014 (SCOM) 00000000C00100A0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIRAMEDR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR4 Ram & Error Diagnosis Register. Can be used to read IR and EDR for debug. Also provides ability to RAM an instruction without modifying SPRG0.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_ISP.LT_IR.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_EDR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RWX	RWX		OCB_OCI_GPEXIRAMEDR_IR: PPE Instruction Register. Writes cause a RAM operation. Provides the requested PPE Instruction to execute.
32:63	ROX	ROX		OCB_OCI_GPEXIRAMEDR_EDR: Error Data Register, set on PPE interrupts caused by an error. See PPE Specification for definition.

OCB_OCI GPE External Interface DBGPRO
Addr:	0000000000062015 (SCOM) 00000000C00100A8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIDBGPRO
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR5 Debug & Runtime Profiling Read program location and status. Also used to write XSR & IAR.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.XSR_INT_SPR(0) [0]
	1:3	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_HC.LATC.L2(0:2) [000]
	4	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_HCP.LATC.L2(0) [0]
	5	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_RIP.LATC.L2(0) [0]
	6	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_SIP.LATC.L2(0) [0]
	7	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_TRAP.LATC.L2(0) [0]
	8	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_IAC.LATC.L2(0) [0]
	9:11	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(9:11) [000]
	12	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_RDAC.LATC.L2(0) [0]
	13	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_WDAC.LATC.L2(0) [0]
	14	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(13) [0]
	15	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_TRH.LATC.L2(0) [0]
	16:19	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_DECODER.FSM_STATE_LATCH.LATC.L2(0:3) [0000]
	20	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(12) [0]
	21	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_EP.LATC.L2(0) [0]
	24:25	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_ISR_24_25.LATC.L2(24:25) [00]
	28:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_ISR_28_31.LATC.L2(28:31) [0000]
	32:61	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_ISP.LT_IAR.LATC.L2(0:29) [000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		XSR_HS
1:3	RWX	RWX		XSR_HC
4	ROX	ROX		XSR_HCP
5	ROX	ROX		XSR_RIP
6	ROX	ROX		XSR_SIP
7	RWX	RWX		XSR_TRAP
8	RWX	RWX		XSR_IAC
9:11	ROX	ROX		XSR_SIB
12	RWX	RWX		XSR_RDAC
13	RWX	RWX		XSR_WDAC
14	ROX	ROX		XSR_WS
15	ROX	ROX		XSR_TRH
16:19	ROX	ROX		XSR_SMS
20	ROX	ROX		XSR_LP
21	ROX	ROX		XSR_EP
22:23	RO	RO		constant=0b00
24	ROX	ROX		XSR_PTR
25	ROX	ROX		XSR_ST
26:27	RO	RO		constant=0b00
28	ROX	ROX		XSR_MFE
29:31	ROX	ROX		XSR_MCS
32:61	RWX	RWX		OCB_OCI_GPEXIIAR_IAR: PPE Instruction Address Register See PPE Specification for bit definitions. Corresponds to XIR5 bits 32:63
62:63	RO	RO		constant=0b00

OCB_OCI GPE External Interface SIB Info
Addr:	0000000000062016 (SCOM) 00000000C00100B0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXISIB
Constant(s):
Comments:	XIR6 SIB Transaction buffer info for debug
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	32	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_R_NW_Q_INST.LATC.L2(0) [0]
	33	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_BUSY_Q_INST.LATC.L2(0) [0]
	34	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.PIB_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0]
	49:51	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_RSP_INFO_Q_0_INST.LATC.L2(0:2) [000]
	61	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_RESET_PENDING_Q_INST.LATC.L2(0) [0]
	62	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.IFETCH_PIB_PENDING_Q_INST.LATC.L2(0) [0]
	63	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.PIB_DATAOP_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXISIB_PIB_ADDR: PIB transaction buffer current or previous transaction byte address
32	ROX	ROX		OCB_OCI_GPEXISIB_PIB_R_NW: PIB transaction buffer current or previous transaction type, read if 1 and write if 0.
33	ROX	ROX		OCB_OCI_GPEXISIB_PIB_BUSY: Indicates if the transaction buffer is occupied with an ongoing transaction. Busy is cleared when the transaction is completed.
34	ROX	ROX		OCB_OCI_GPEXISIB_PIB_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the PIB interface can continue to service I-fetches (only in case of SBE instance).
35:48	RO	RO		constant=0b00000000000000
49:51	ROX	ROX		OCB_OCI_GPEXISIB_PIB_RSP_INFO: PIB transaction buffer response info. Current or previous transaction got an error on the PIB interface when non-zero.
52:60	RO	RO		constant=0b000000000
61	ROX	ROX		OCB_OCI_GPEXISIB_PIB_RESET_PENDING: Indicates if hard reset occurred during an ongoing transcation and transaction is still pending when set to 1.
62	ROX	ROX		OCB_OCI_GPEXISIB_PIB_IFETCH_PENDING: Indicates a instruction fetch is pending on the PIB interface when set to 1.
63	ROX	ROX		OCB_OCI_GPEXISIB_PIB_DATAOP_PENDING: Indicates a data transaction is pending on the PIB interface when set to 1.

OCB_OCI GPE External Interface MEM Info
Addr:	0000000000062017 (SCOM) 00000000C00100B8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIMEM
Constant(s):
Comments:	XIR7 Memory Interface transaction buffer info for debug
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.MEM_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	32	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.MEM_R_NW_Q_INST.LATC.L2(0) [0]
	33	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.MEM_BUSY_Q_INST.LATC.L2(0) [0]
	34	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.MEM_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0]
	35:42	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.MEM_BYTE_ENABLE_Q_0_INST.LATC.L2(0:7) [00000000]
	43	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.MEM_LINE_MODE_Q_INST.LATC.L2(0) [0]
	49:51	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.MEM_ERROR_Q_0_INST.LATC.L2(0:2) [000]
	62	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.IFETCH_MEM_PENDING_Q_INST.LATC.L2(0) [0]
	63	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.MEM_DATAOP_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_ADDR: MEM transaction buffer current or previous transaction byte address.
32	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_R_NW: MEM transaction buffer current or previous transaction type, read if 1 and write if 0.
33	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_BUSY: Indicates if the transaction buffer is occupied with an ongoing transaction. Busy is cleared when the transaction is completed.
34	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the memory interface can continue to service I-fetches.
35:42	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_BYTE_ENABLE: MEM transaction buffer current or previous transaction byte enables.
43	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_LINE_MODE: MEM transaction buffer current or previous transaction line mode. Indicates a 32B read request when set to 1.
44:48	RO	RO		constant=0b00000
49:51	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_ERROR: MEM transaction buffer error code. Current or previous transaction got an error on the memory interface when non-zero.
52:61	RO	RO		constant=0b0000000000
62	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IFETCH_PENDING: Indicates a instruction fetch is pending on the MEM interface when set to 1.
63	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_DATAOP_PENDING: Indicates a data transaction is pending on the MEM interface when set to 1.

OCB_OCI GPE External Interface Store Gather Buffer Info
Addr:	0000000000062018 (SCOM) 00000000C00100C0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXISGB
Constant(s):
Comments:	XIR8 Store Gather Buffer Info for debug
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.STR_GTHR_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	35	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.MEM_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0]
	36:39	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.STR_GTHR_VALID_Q_0_INST.LATC.L2(0:3) [0000]
	63	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.STR_GTHR_FLUSH_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		STORE_ADDRESS
32:34	RO	RO		constant=0b000
35	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the memory interface can continue to service I-fetches.
36:39	ROX	ROX		SGB_BYTE_VALID
40:62	RO	RO		constant=0b00000000000000000000000
63	ROX	ROX		SGB_FLUSH_PENDING

OCB_OCI GPE External Interface Icache Info
Addr:	0000000000062019 (SCOM) 00000000C00100C8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIICAC
Constant(s):
Comments:	XIR9 Instruction Cache Info for debug
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.ICACHE_COMP.ICACHE_TAG_ADDR_LATCH.LATC.L2(0:26) [000000000000000000000000000]
	32	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.ICACHE_COMP.ICACHE_ERR_LATCH.LATC.L2(0) [0]
	34	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.IFETCH_PIB_PENDING_Q_INST.LATC.L2(0) [0]
	35	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.IFETCH_MEM_PENDING_Q_INST.LATC.L2(0) [0]
	36:39	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.ICACHE_COMP.ICACHE_VALID_LATCH.LATC.L2(0:3) [0000]
	40:43	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.ICACHE_COMP.INCLUDE_ADDN_CACHE_LINE.ICACHE_LINE2_VALID_LATCH.LATC.L2(0:3) [0000]
	45	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.ICACHE_COMP.INCLUDE_ADDN_CACHE_LINE.ICACHE_LINE_PTR_LATCH.LATC.L2(0) [0]
	46	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.ICACHE_COMP.INCLUDE_ADDN_CACHE_LINE.ICACHE_LINE2_ERR_LATCH.LATC.L2(0) [0]
	47	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.INCLUDE_PREFETCH.ICACHE_PREFETCH_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0:26	ROX	ROX		ICACHE_TAG_ADDR
27:31	RO	RO		constant=0b00000
32	ROX	ROX		ICACHE_ERR
33	RO	RO		constant=0b0
34	ROX	ROX		OCB_OCI_GPEXISIB_PIB_IFETCH_PENDING: Indicates a instruction fetch is pending on the PIB interface when set to 1.
35	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IFETCH_PENDING: Indicates a instruction fetch is pending on the MEM interface when set to 1.
36:39	ROX	ROX		ICACHE_VALID
40:43	ROX	ROX		ICACHE_LINE2_VALID
44	RO	RO		constant=0b0
45	ROX	ROX		ICACHE_LINE_PTR
46	ROX	ROX		ICACHE_LINE2_ERR
47	ROX	ROX		ICACHE_PREFETCH_PENDING
48:63	RO	RO		constant=0b0000000000000000

OCB_OCI GPE External Interface Dcache Info
Addr:	000000000006201A (SCOM) 00000000C00100D0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIDCAC
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR10 Data Cache Info for debug
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_COMP.DCACHE_TAG_ADDR_LATCH.LATC.L2(0:26) [000000000000000000000000000]
	32	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_COMP.DCACHE_ERR.LATC.L2(0) [0]
	35	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_POPULATE_PENDING_Q_INST.LATC.L2(0) [0]
	36:39	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_COMP.DCACHE_VALID_LATCH.LATC.L2(0:3) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0:26	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_TAG_ADDR: 32B Data Address Tag for the current or previous cache content.
27:31	RO	RO		constant=0b00000
32	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_ERR: Indicates the current or previous content of the cache is bad due to an interface error during populate.
33:34	RO	RO		constant=0b00
35	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_POPULATE_PENDING: Data populate to D-Cache pending from MEM interface.
36:39	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_VALID: Double word valids indicating the corresponding double word in the cache is valid
40:63	RO	RO		constant=0b000000000000000000000000

OCB_OCI GPE External Interface DBGINF
Addr:	000000000006201F (SCOM) 00000000C00100F8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIDBGINF
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: Debug Information Read registers containing recent program address information. New for P10.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:29	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_SRR0.LATC.L2(0:29) [000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_LR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:29	ROX	ROX		OCB_OCI_GPEXIDBGINF_SRR0: PPE Save & Restore Register 0 Contains address of the most recent interrupt taken. Potentially useful during debug.
30:31	RO	RO		constant=0b00
32:63	ROX	ROX		OCB_OCI_GPEXIDBGINF_LR: PPE Link Register. Contains address of the instruction following the most recent Branch with Link instruction executed, to give an idea from whence the code recently came. Potentially useful during debug.

OCB_OCI GPE External Interface OCI-Word XCR
Addr:	0000000000062020 (SCOM) 00000000C0010100 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEOXIXCR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR0(0:31) External Control Register (XCR). Note this is the same as GPEXIXCR but included separately for consistency in 32-bit access OCI address mapping.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.LT_XIR_XCR_CMND.LATC.L2(0:2) [000]
Bit(s)	SCOM	OCI		Dial: Description
0	RO	RO		constant=0b0
1:3	WOX	WOX		OCB_OCI_GPEOXIXCR_XCR: PPE External Control Register See PPE Specification for bit definitions. Corresponds to XIR0 bits 1:3
4:63	RO	RO		constant=0b000000000000000000000000000000000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word XSR
Addr:	0000000000062021 (SCOM) 00000000C0010108 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIXSR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR3(0:31) External Status Register (XSR)
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.XSR_INT_SPR(0) [0]
	1:3	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_HC.LATC.L2(0:2) [000]
	4	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_HCP.LATC.L2(0) [0]
	5	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_RIP.LATC.L2(0) [0]
	6	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_SIP.LATC.L2(0) [0]
	7	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_TRAP.LATC.L2(0) [0]
	8	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_IAC.LATC.L2(0) [0]
	9:11	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(9:11) [000]
	12	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_RDAC.LATC.L2(0) [0]
	13	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_WDAC.LATC.L2(0) [0]
	14	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(13) [0]
	15	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_TRH.LATC.L2(0) [0]
	16:19	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_DECODER.FSM_STATE_LATCH.LATC.L2(0:3) [0000]
	20	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(12) [0]
	21	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_XSR_EP.LATC.L2(0) [0]
	24:25	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_ISR_24_25.LATC.L2(24:25) [00]
	28:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_ISR_28_31.LATC.L2(28:31) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		XSR_HS
1:3	ROX	ROX		XSR_HC
4	ROX	ROX		XSR_HCP
5	ROX	ROX		XSR_RIP
6	ROX	ROX		XSR_SIP
7	ROX	ROX		XSR_TRAP
8	ROX	ROX		XSR_IAC
9:11	ROX	ROX		XSR_SIB
12	ROX	ROX		XSR_RDAC
13	ROX	ROX		XSR_WDAC
14	ROX	ROX		XSR_WS
15	ROX	ROX		XSR_TRH
16:19	ROX	ROX		XSR_SMS
20	ROX	ROX		XSR_LP
21	ROX	ROX		XSR_EP
22:23	RO	RO		constant=0b00
24	ROX	ROX		XSR_PTR
25	ROX	ROX		XSR_ST
26:27	RO	RO		constant=0b00
28	ROX	ROX		XSR_MFE
29:31	ROX	ROX		XSR_MCS
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word SPRG0
Addr:	0000000000062022 (SCOM) 00000000C0010110 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXISPRG0
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR3(32:63) SPRG0 register
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_SPRG0.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RWX	RWX		SPRG0
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word EDR
Addr:	0000000000062023 (SCOM) 00000000C0010118 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIEDR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR4(32:63) Error Data Register (EDR)
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_EDR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIRAMEDR_EDR: Error Data Register, set on PPE interrupts caused by an error. See PPE Specification for definition.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word IR
Addr:	0000000000062024 (SCOM) 00000000C0010120 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIIR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR4(0:31) Instruction Register (IR)
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_ISP.LT_IR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RWX	RWX		OCB_OCI_GPEXIRAMEDR_IR: PPE Instruction Register. Writes cause a RAM operation. Provides the requested PPE Instruction to execute.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word IAR
Addr:	0000000000062025 (SCOM) 00000000C0010128 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIIAR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR5(32:63) Instruction Register (IAR)
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:29	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_ISP.LT_IAR.LATC.L2(0:29) [000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:29	RWX	RWX		OCB_OCI_GPEXIIAR_IAR: PPE Instruction Address Register See PPE Specification for bit definitions. Corresponds to XIR5 bits 32:63
30:63	RO	RO		constant=0b0000000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word SIB Info Upper
Addr:	0000000000062026 (SCOM) 00000000C0010130 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXISIBU
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR6(0:31) SIB Info Upper bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RO	RO		OCB_OCI_GPEXISIB_PIB_ADDR: PIB transaction buffer current or previous transaction byte address
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word SIB Info Lower
Addr:	0000000000062027 (SCOM) 00000000C0010138 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXISIBL
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR6(32:63) SIB Info Lower bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_R_NW_Q_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_BUSY_Q_INST.LATC.L2(0) [0]
	2	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.PIB_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0]
	17:19	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_RSP_INFO_Q_0_INST.LATC.L2(0:2) [000]
	30	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.IFETCH_PIB_PENDING_Q_INST.LATC.L2(0) [0]
	31	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.PIB_DATAOP_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		OCB_OCI_GPEXISIB_PIB_R_NW: PIB transaction buffer current or previous transaction type, read if 1 and write if 0.
1	ROX	ROX		OCB_OCI_GPEXISIB_PIB_BUSY: Indicates if the transaction buffer is occupied with an ongoing transaction. Busy is cleared when the transaction is completed.
2	ROX	ROX		OCB_OCI_GPEXISIB_PIB_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the PIB interface can continue to service I-fetches (only in case of SBE instance).
3:16	RO	RO		constant=0b00000000000000
17:19	ROX	ROX		OCB_OCI_GPEXISIB_PIB_RSP_INFO: PIB transaction buffer response info. Current or previous transaction got an error on the PIB interface when non-zero.
20:29	RO	RO		constant=0b0000000000
30	ROX	ROX		OCB_OCI_GPEXISIB_PIB_IFETCH_PENDING: Indicates a instruction fetch is pending on the PIB interface when set to 1.
31	ROX	ROX		OCB_OCI_GPEXISIB_PIB_DATAOP_PENDING: Indicates a data transaction is pending on the PIB interface when set to 1.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word MEM Info Upper
Addr:	0000000000062028 (SCOM) 00000000C0010140 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIMEMU
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR7(0:31) Memory Interface Info Upper bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.MEM_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_ADDR: MEM transaction buffer current or previous transaction byte address.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word MEM Info Lower
Addr:	0000000000062029 (SCOM) 00000000C0010148 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIMEML
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR7(32:63) Memory Interface Info Lower bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.MEM_BUSY_Q_INST.LATC.L2(0) [0]
	2	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.MEM_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0]
	3:10	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.MEM_BYTE_ENABLE_Q_0_INST.LATC.L2(0:7) [00000000]
	11	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.MEM_LINE_MODE_Q_INST.LATC.L2(0) [0]
	12	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.MIB_SCOM_REG_2_DATA(44) [0]
	17:19	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.MEM_ERROR_Q_0_INST.LATC.L2(0:2) [000]
	30	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.IFETCH_MEM_PENDING_Q_INST.LATC.L2(0) [0]
	31	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.MEM_DATAOP_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0	RO	RO		constant=0b0
1	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_BUSY: Indicates if the transaction buffer is occupied with an ongoing transaction. Busy is cleared when the transaction is completed.
2	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the memory interface can continue to service I-fetches.
3:10	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_BYTE_ENABLE: MEM transaction buffer current or previous transaction byte enables.
11	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_LINE_MODE: MEM transaction buffer current or previous transaction line mode. Indicates a 32B read request when set to 1.
12	ROX	ROX		Memory_Info_Lower_part1
13:16	RO	RO		constant=0b0000
17:19	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_ERROR: MEM transaction buffer error code. Current or previous transaction got an error on the memory interface when non-zero.
20:29	RO	RO		constant=0b0000000000
30	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IFETCH_PENDING: Indicates a instruction fetch is pending on the MEM interface when set to 1.
31	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_DATAOP_PENDING: Indicates a data transaction is pending on the MEM interface when set to 1.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word SGB Info Upper
Addr:	000000000006202A (SCOM) 00000000C0010150 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXISGBU
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR8(0:31) Store Gather Buffer Info Upper bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.STR_GTHR_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		SGB_Info_Upper
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word SGB Info Lower
Addr:	000000000006202B (SCOM) 00000000C0010158 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXISGBL
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR8(32:63) Store Gather Buffer Info Lower bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	3	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.MEM_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0]
	4:7	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.STR_GTHR_VALID_Q_0_INST.LATC.L2(0:3) [0000]
	31	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.STR_GTHR_FLUSH_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0:2	RO	RO		constant=0b000
3	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the memory interface can continue to service I-fetches.
4:7	ROX	ROX		SGB_Info_Lower_part1
8:30	RO	RO		constant=0b00000000000000000000000
31	ROX	ROX		SGB_Info_Lower_part2
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word Icache Info Upper
Addr:	000000000006202C (SCOM) 00000000C0010160 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIICACU
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR9(0:31) Instruction Cache Info Upper bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.ICACHE_COMP.ICACHE_TAG_ADDR_LATCH.LATC.L2(0:26) [000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:26	ROX	ROX		Icache_Info_Upper
27:63	RO	RO		constant=0b0000000000000000000000000000000000000

OCB_OCI GPE External Interface MEM Icache Info Lower
Addr:	000000000006202D (SCOM) 00000000C0010168 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIICACL
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR9(32:63) Instruction Cache Info Lower bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.ICACHE_COMP.ICACHE_ERR_LATCH.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.MIB_SCOM_REG_4_DATA(33) [0]
	2	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.IFETCH_PIB_PENDING_Q_INST.LATC.L2(0) [0]
	3	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.IFETCH_MEM_PENDING_Q_INST.LATC.L2(0) [0]
	4:7	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.ICACHE_COMP.ICACHE_VALID_LATCH.LATC.L2(0:3) [0000]
	8:11	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.ICACHE_COMP.INCLUDE_ADDN_CACHE_LINE.ICACHE_LINE2_VALID_LATCH.LATC.L2(0:3) [0000]
	13	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.ICACHE_COMP.INCLUDE_ADDN_CACHE_LINE.ICACHE_LINE_PTR_LATCH.LATC.L2(0) [0]
	14	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.ICACHE_COMP.INCLUDE_ADDN_CACHE_LINE.ICACHE_LINE2_ERR_LATCH.LATC.L2(0) [0]
	15	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.INCLUDE_PREFETCH.ICACHE_PREFETCH_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0:1	ROX	ROX		Icache_Info_Lower_part1
2	ROX	ROX		OCB_OCI_GPEXISIB_PIB_IFETCH_PENDING: Indicates a instruction fetch is pending on the PIB interface when set to 1.
3	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IFETCH_PENDING: Indicates a instruction fetch is pending on the MEM interface when set to 1.
4:11	ROX	ROX		Icache_Info_Lower_part1
12	RO	RO		constant=0b0
13:15	ROX	ROX		Icache_Info_Lower_part2
16:63	RO	RO		constant=0b000000000000000000000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word Dcache Info Upper
Addr:	000000000006202E (SCOM) 00000000C0010170 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIDCACU
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR10(0:31) Data Cache Info Upper bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_COMP.DCACHE_TAG_ADDR_LATCH.LATC.L2(0:26) [000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:26	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_TAG_ADDR: 32B Data Address Tag for the current or previous cache content.
27:31	RO	RO		constant=0b00000

OCB_OCI GPE External Interface MEM Dcache Info Lower
Addr:	000000000006202F (SCOM) 00000000C0010178 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIDCACL
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR10(32:63) Data Cache Info Lower bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_COMP.DCACHE_ERR.LATC.L2(0) [0]
	3	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_POPULATE_PENDING_Q_INST.LATC.L2(0) [0]
	4:7	TP.TPCHIP.OCC.OCI.GPE1.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_COMP.DCACHE_VALID_LATCH.LATC.L2(0:3) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_ERR: Indicates the current or previous content of the cache is bad due to an interface error during populate.
1:2	RO	RO		constant=0b00
3	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_POPULATE_PENDING: Data populate to D-Cache pending from MEM interface.
4:7	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_VALID: Double word valids indicating the corresponding double word in the cache is valid
8:31	RO	RO		constant=0b000000000000000000000000

OCB_OCI GPE External Interface OCI-Word SRR0
Addr:	0000000000062030 (SCOM) 00000000C0010180 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXISRR0
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR15(0:31) SRR0
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:29	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_SRR0.LATC.L2(0:29) [000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:29	ROX	ROX		OCB_OCI_GPEXIDBGINF_SRR0: PPE Save & Restore Register 0 Contains address of the most recent interrupt taken. Potentially useful during debug.
30:63	RO	RO		constant=0b0000000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word LR
Addr:	0000000000062031 (SCOM) 00000000C0010188 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXILR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR15(32:63) Link Register (LR)
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_LR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIDBGINF_LR: PPE Link Register. Contains address of the instruction following the most recent Branch with Link instruction executed, to give an idea from whence the code recently came. Potentially useful during debug.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word CTR
Addr:	0000000000062032 (SCOM) 00000000C0010190 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXICTR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR0(32:63) CTR
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_SPR.LT_CTR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXICTR_CTR: Count Register. Added for P10. Potentially useful for Debug since can indicate loop iteration or a recent branch target address, depending on compiler optimization decisions. Corresponds to XIR0 bits 32:63
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR0
Addr:	0000000000062040 (SCOM) 00000000C0010200 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR0
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR0
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR0.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR0_GPR0: General Purpose Register 0
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR1
Addr:	0000000000062041 (SCOM) 00000000C0010208 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR1
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR1
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR1.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR0_GPR1: General Purpose Register 1
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR2
Addr:	0000000000062042 (SCOM) 00000000C0010210 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR2
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR2
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR2.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR2_GPR2: General Purpose Register 2
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR3
Addr:	0000000000062043 (SCOM) 00000000C0010218 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR3
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR3
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR3.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR2_GPR3: General Purpose Register 3
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR4
Addr:	0000000000062044 (SCOM) 00000000C0010220 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR4
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR4
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR4.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR4_GPR4: General Purpose Register 4
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR5
Addr:	0000000000062045 (SCOM) 00000000C0010228 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR5
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR5
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR5.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR4_GPR5: General Purpose Register 5
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR6
Addr:	0000000000062046 (SCOM) 00000000C0010230 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR6
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR6
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR6.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR6_GPR6: General Purpose Register 6
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR7
Addr:	0000000000062047 (SCOM) 00000000C0010238 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR7
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR7
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR7.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR6_GPR7: General Purpose Register 7
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR8
Addr:	0000000000062048 (SCOM) 00000000C0010240 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR8
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR8
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR8.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR8_GPR8: General Purpose Register 8
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR9
Addr:	0000000000062049 (SCOM) 00000000C0010248 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR9
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR9
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR9.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR8_GPR9: General Purpose Register 9
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR10
Addr:	000000000006204A (SCOM) 00000000C0010250 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR10
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR10
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR10.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDRX_GPR10: General Purpose Register 10
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR13
Addr:	000000000006204B (SCOM) 00000000C0010258 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR13
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR13
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR13.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDRX_GPR13_11: DD1: General Purpose Register 13 DD2: General Purpose Register 11
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR28
Addr:	000000000006204C (SCOM) 00000000C0010260 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR28
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR28
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR28.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR28_GPR28: General Purpose Register 28
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR29
Addr:	000000000006204D (SCOM) 00000000C0010268 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR29
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR29
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR29.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR28_GPR29: General Purpose Register 29
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR30
Addr:	000000000006204E (SCOM) 00000000C0010270 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR30
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR30
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR30.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR30_GPR30: General Purpose Register 30
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR31
Addr:	000000000006204F (SCOM) 00000000C0010278 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR31
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR31
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR31.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RO	RO		OCB_OCI_GPEXIVDR30_GPR31: General Purpose Register 31
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface VDR0
Addr:	0000000000062080 (SCOM) 00000000C0010400 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIVDR0
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR0 & GPR1
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR0.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR1.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR0_GPR0: General Purpose Register 0
32:63	ROX	ROX		OCB_OCI_GPEXIVDR0_GPR1: General Purpose Register 1

OCB_OCI GPE External Interface VDR2
Addr:	0000000000062081 (SCOM) 00000000C0010408 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIVDR2
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR2 & GPR3
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR2.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR3.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR2_GPR2: General Purpose Register 2
32:63	ROX	ROX		OCB_OCI_GPEXIVDR2_GPR3: General Purpose Register 3

OCB_OCI GPE External Interface VDR4
Addr:	0000000000062082 (SCOM) 00000000C0010410 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIVDR4
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR4 & GPR5
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR4.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR5.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR4_GPR4: General Purpose Register 4
32:63	ROX	ROX		OCB_OCI_GPEXIVDR4_GPR5: General Purpose Register 5

OCB_OCI GPE External Interface VDR6
Addr:	0000000000062083 (SCOM) 00000000C0010418 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIVDR6
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR6 & GPR7
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR6.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR7.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR6_GPR6: General Purpose Register 6
32:63	ROX	ROX		OCB_OCI_GPEXIVDR6_GPR7: General Purpose Register 7

OCB_OCI GPE External Interface VDR8
Addr:	0000000000062084 (SCOM) 00000000C0010420 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIVDR8
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR8 & GPR9
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR8.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR9.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR8_GPR8: General Purpose Register 8
32:63	ROX	ROX		OCB_OCI_GPEXIVDR8_GPR9: General Purpose Register 9

OCB_OCI GPE External Interface VDRX
Addr:	0000000000062085 (SCOM) 00000000C0010428 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIVDRX
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: DD1: Virtual Doubleword X (GPR10 & GPR13) DD2: Virtual Doubleword 10 (GPR10 & GPR11) Note: unlike other 64-bit GPR XIRs, this is not a true VDR.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR10.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR13.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDRX_GPR10: General Purpose Register 10
32:63	ROX	ROX		OCB_OCI_GPEXIVDRX_GPR13_11: DD1: General Purpose Register 13 DD2: General Purpose Register 11

OCB_OCI GPE External Interface VDR28
Addr:	0000000000062086 (SCOM) 00000000C0010430 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIVDR28
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR28 & GPR29
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR28.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR29.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR28_GPR28: General Purpose Register 28
32:63	ROX	ROX		OCB_OCI_GPEXIVDR28_GPR29: General Purpose Register 29

OCB_OCI GPE External Interface VDR30
Addr:	0000000000062087 (SCOM) 00000000C0010438 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIVDR30
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR30 & GPR31
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR30.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE1.GPE.PPE.I_C_PPE42_GPR.LT_GPR31.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR30_GPR30: General Purpose Register 30
32:63	ROX	ROX		OCB_OCI_GPEXIVDR30_GPR31: General Purpose Register 31

OCB_OCI GPE Timer Select Register
Addr:	0000000000064000 (SCOM) 00000000C0020000 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPETSEL
Constant(s):
Comments:	This register selects the rate of the Fixed Interval and Watchdog Timers The input to the PPE will pulse every 2^(23 - select) times the input timer period (which is the PAU cycle time/64), unless select is zero in which case the timer pulse is disabled. SUMMARY: the resultant timer rate is given by: 2^(29-select) / PAU_Frequency when select is non-zero.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.OCC.OCI.GPE2.PPEREG.GPETSEL_Q_0_INST.LATC.L2(0:7) [00000000]
Bit(s)	SCOM	OCI		Dial: Description
0:3	RW	RW		OCB_OCI_GPETSEL_WATCHDOG_SEL: Selects Watchdog Timer rate
4:7	RW	RW		OCB_OCI_GPETSEL_FIT_SEL: Selects Fixed Interval Timer rate
8:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000

OCB_OCI GPE Interrupt Vector Prefix Register
Addr:	0000000000064001 (SCOM) 00000000C0020008 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEIVPR
Constant(s):
Comments:	This register selects the top 23 bits of the Interrupt Address Vector.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:22	TP.TPCHIP.OCC.OCI.GPE2.PPEREG.GPEIVPR_Q_0_INST.LATC.L2(0:22) [00000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:22	RW	RW		OCB_OCI_GPEIVPR_IVPR: Interrupt Prefix Vector Register (Resets to 0xFFFFFE left justified)
23:63	RO	RO		constant=0b00000000000000000000000000000000000000000

OCB_OCI GPE Debug Mode Register
Addr:	0000000000064002 (SCOM) 00000000C0020010 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEDBG
Constant(s):
Comments:	This register contains mode bits controlling the debug bolt-on and PPE behavior on checkstop and trigger.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:23	TP.TPCHIP.OCC.OCI.GPE2.PPEREG.GPEDBG_Q_0_INST.LATC.L2(0:23) [000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	RW	RW		OCB_OCI_GPEDBG_EN_DBG: Enable Debug Trace. Master switch that enables clocks to the trace. Also causes RiscTrace to start on rising edge & stop on falling edge when RISCTRACE is enabled (TRACE_DATA_SEL(0)=0).
1	RW	RW		OCB_OCI_GPEDBG_HALT_ON_XSTOP: Enable Halt on Checkstop input
2	RW	RW		OCB_OCI_GPEDBG_HALT_ON_TRIG: Enable Halt on Trigger input
3	RW	RW		OCB_OCI_GPEDBG_EN_COVERAGE_MODE: Enables Code Coverage Trace Mode. When set, no longer traces every instruction executed, and adds SPRG0 and MARK data to the trace. Note: only supported when EN_INTR_ADDR and EN_TRACE_EXTRA are both set to 0.
4	RW	RW		OCB_OCI_GPEDBG_EN_INTR_ADDR: When RISCTRACE is enabled, trace the Full Interrupt Vector Address, otherwise only trace the lower byte of address.
5	RW	RW		OCB_OCI_GPEDBG_EN_TRACE_EXTRA: When RISCTRACE is enabled and this bit is set, records extra trace data not needed for 405 RISCTrace spec. When this bit is set, record MTMSR or MTSPRG0 data and new MSR value set by RFI.
6	RW	RW		OCB_OCI_GPEDBG_EN_TRACE_STALL: When RISCTRACE is enabled and this bit is set, stall cycles when the processor is not actively executing an instruction, that are not already included in the previous event, are recorded unless it is Halted or in Wait state. When this mode is not set, the RISTRACE is smaller but not time accurate.
7	RW	RW		OCB_OCI_GPEDBG_EN_WAIT_CYCLES: When RISCTRACE is enabled and this bit is set, Stall Events are used to record the number of cycles the PPE is in Wait state. Otherwise cycles in Wait state are ignored. When this bit is set, EN_TRACE_STALL must also be set.
8	RW	RW		OCB_OCI_GPEDBG_EN_FULL_SPEED: When set, the trace valid is pulsed at 1:1 (4x faster than the debug data, which changes at PPE clock speed). This is used for CHTM and NHTM (in memory trace). When this mode is NOT set, trace valid is held constant for a full PPE cycle (four 1:1 cycles). When connected to a trace array this bit should match the corresponding speed of the array.
9	RW	RW		OCB_OCI_GPEDBG_DIS_FLOW_CHANGE: When set, do not record code flow change and IAR trace events (taken & untaken branches, Interrupts/Exceptions, RFI, WRTEE, or Sync Events). Setting this mode is only supported when EN_COVERAGE_MODE=1.
10:11	RW	RW		OCB_OCI_GPEDBG_TRACE_MODE_SEL: Bit 0 chooses between 0: PPE Core Debug Mode A; 1: Mode B Bit 1 when set, ORs in the secondary valid corresponding to lower bits of the trace data when they are from a different source than bits 0:23 (NOTE: likely 0 for HTM tracing)
12	RW	RW		OCB_OCI_GPEDBG_EN_MARK_TRACE: Traces a unique record with an additional 16-bits to capture the (TG, TO, RA, and RB) fields on MARK type instructions.
13	RW	RW		OCB_OCI_GPEDBG_EN_EE_TRACE: Traces wrtee or wrteei instructions along with the new value of the EE bit with a unique record. If (EN_TRACE_EXTRA=0 or EN_COVERAGE_MODE=1), a unique record is also generated for RFI and MTMSR and exceptions to trace the value of the EE bit .
14:15	RW	RW		OCB_OCI_GPEDBG_RESERVED14_15: Implemented but not used.
16	RW	RW		OCB_OCI_GPEDBG_FIR_TRIGGER: NOT CONNECTED. GPE can write FIR directly if needed. Intended to Programmatically assert a FIR bit to inject checkstop or send Attention to the Service Element.
17:19	RW	RW		OCB_OCI_GPEDBG_SPARE: Spare (used for GPIO on other instances)
20:23	RW	RW		OCB_OCI_GPEDBG_TRACE_DATA_SEL: Mux select to choose debug data content on the trace bus. All 16 encodes are defined as per the table in the Debug Bolt-on chapter of the Power Management Spec. 0x0 chooses an 88-bit PPE-RISCtrace by default. b00XX enables Risctrace records to be generated in the upper 64-bits of trace data. bXX00 selects the remaining 24 bits to form 88-bit Trace Packets to be generated on the debug bus to be sent to the hardware trace array (otherwise PPE, MIB, or EXT data will be used) The other 12 encodes contain permutations of the PPE Core, Memory Interface, and External debug buses instead of RISCtrace records.
24:63	RO	RO		constant=0b0000000000000000000000000000000000000000

OCB_OCI GPE Memory Access Configuration Register
Addr:	0000000000064004 (SCOM) 00000000C0020020 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEMACR
Constant(s):
Comments:	This register controls Memory Access Priority on the OCI.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:12	TP.TPCHIP.OCC.OCI.GPE2.PPEREG.GPEMACR_Q_0_INST.LATC.L2(0:12) [0000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:1	RW	RW		OCB_OCI_GPEMACR_MEM_LOW_PRIORITY: OCI priority to use for accessing Main Memory when Address(0:1) = "10" and the PPE high priority output is 0
2:3	RW	RW		OCB_OCI_GPEMACR_MEM_HIGH_PRIORITY: OCI priority to use for accessing Main Memory when Address(0:1) = "10" and the PPE high priority output is 1
4:5	RW	RW		OCB_OCI_GPEMACR_LOCAL_LOW_PRIORITY: OCI priority to use for accessing Local Registers when Address(0:2) = "110" and the PPE high priority output is 0
6:7	RW	RW		OCB_OCI_GPEMACR_LOCAL_HIGH_PRIORITY: OCI priority to use for accessing Local Registers when Address(0:2) = "110" and the PPE high priority output is 1
8:9	RW	RW		OCB_OCI_GPEMACR_SRAM_LOW_PRIORITY: OCI priority to use for accessing SRAM tank when Address(0:2) = "111" and the PPE high priority output is 0
10:11	RW	RW		OCB_OCI_GPEMACR_SRAM_HIGH_PRIORITY: OCI priority to use for accessing SRAM tank when Address(0:2) = "111" and the PPE high priority output is 1
12	RW	RW		OCB_OCI_GPEMACR_WRITE_PROTECT_ENABLE: Enables PPE write protect regions. When 0, the contents of GPESWPR[n] have no effect. When 1, and GPEWPR[n] are non-zero, this GPE can only write the OCC SRAM in the configured regions.
13:63	RO	RO		constant=0b000000000000000000000000000000000000000000000000000

OCB_OCI GPE SRAM Write Protect Register 0
Addr:	0000000000064005 (SCOM) 00000000C0020028 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPESWPR0
Constant(s):
Comments:	When enabled, these registers control the regions of OCC SRAM the GPE is allowed to write.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.OCC.OCI.GPE2.PPEREG.GPESWPR0A_Q_0_INST.LATC.L2(0:26) [000000000000000000000000000]
	44:58	TP.TPCHIP.OCC.OCI.GPE2.PPEREG.GPESWPR0B_Q_44_INST.LATC.L2(44:58) [000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:26	RW	RW		OCB_OCI_GPESWPR0_WRITE_PROTECT_BAR: Base address of write protect region 0. Must be 32B aligned
27:43	RO	RO		constant=0b00000000000000000
44:58	RW	RW		OCB_OCI_GPESWPR0_WRITE_PROTECT_SIZE: Size of write protect region 0 in 32B units. Bit aligned so the size can be added to the BAR to compute the maximum address of this write protect region. Maximum address is bar+size*32-1.
59:63	RO	RO		constant=0b00000

OCB_OCI GPE SRAM Write Protect Register 1
Addr:	0000000000064006 (SCOM) 00000000C0020030 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPESWPR1
Constant(s):
Comments:	When enabled, these registers control the regions of OCC SRAM the GPE is allowed to write.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.OCC.OCI.GPE2.PPEREG.GPESWPR1A_Q_0_INST.LATC.L2(0:26) [000000000000000000000000000]
	44:58	TP.TPCHIP.OCC.OCI.GPE2.PPEREG.GPESWPR1B_Q_44_INST.LATC.L2(44:58) [000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:26	RW	RW		OCB_OCI_GPESWPR1_WRITE_PROTECT_BAR: Base address of write protect region 1. Must be 32B aligned
27:43	RO	RO		constant=0b00000000000000000
44:58	RW	RW		OCB_OCI_GPESWPR1_WRITE_PROTECT_SIZE: Size of write protect region 1 in 32B units. Bit aligned so the size can be added to the BAR to compute the maximum address of this write protect region. Maximum address is bar+size*32-1.
59:63	RO	RO		constant=0b00000

OCB_OCI GPE External Interface XCR
Addr:	0000000000064010 (SCOM) 00000000C0020080 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIXCR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR0 External Control Register (XCR) Note: CTR was added for P10
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.LT_XIR_XCR_CMND.LATC.L2(0:2) [000]
	32:63	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_CTR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	RO	RO		constant=0b0
1:3	WOX	WOX		OCB_OCI_GPEOXIXCR_XCR: PPE External Control Register See PPE Specification for bit definitions. Corresponds to XIR0 bits 1:3
4:31	RO	RO		constant=0b0000000000000000000000000000
32:63	ROX	ROX		OCB_OCI_GPEXICTR_CTR: Count Register. Added for P10. Potentially useful for Debug since can indicate loop iteration or a recent branch target address, depending on compiler optimization decisions. Corresponds to XIR0 bits 32:63

OCB_OCI GPE External Interface RAMRA
Addr:	0000000000064011 (SCOM) 00000000C0020088 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIRAMRA
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR1 Ram Restore Acceleration Register. Can be used to restore SPRG0 plus Resume (or Single Step) with one command.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.LT_XIR_XCR_CMND.LATC.L2(0:2) [000]
	32:63	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_SPRG0.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	RO	RO		constant=0b0
1:3	WOX	WOX		OCB_OCI_GPEOXIXCR_XCR: PPE External Control Register See PPE Specification for bit definitions. Corresponds to XIR0 bits 1:3
4:31	RO	RO		constant=0b0000000000000000000000000000
32:63	WOX	WOX		SPRG0

OCB_OCI GPE External Interface RAMGA
Addr:	0000000000064012 (SCOM) 00000000C0020090 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIRAMGA
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR2 Ram GPR Acceleration Register. Can be used to modify a GPR with one command (where IR = MFSPRG0 instruction 0xFC2082A6 .. 0xFFD082A6)
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_ISP.LT_IR.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_SPRG0.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	WOX	WOX		OCB_OCI_GPEXIRAMEDR_IR: PPE Instruction Register. Writes cause a RAM operation. Provides the requested PPE Instruction to execute.
32:63	WOX	WOX		SPRG0

OCB_OCI GPE External Interface RAMDBG
Addr:	0000000000064013 (SCOM) 00000000C0020098 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIRAMDBG
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR3 Ram & Debug Register. Read status and data. Allows write ability to modify only SPRG0 for a subsequent RAM operation.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.XSR_INT_SPR(0) [0]
	1:3	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_HC.LATC.L2(0:2) [000]
	4	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_HCP.LATC.L2(0) [0]
	5	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_RIP.LATC.L2(0) [0]
	6	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_SIP.LATC.L2(0) [0]
	7	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_TRAP.LATC.L2(0) [0]
	8	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_IAC.LATC.L2(0) [0]
	9:11	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(9:11) [000]
	12	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_RDAC.LATC.L2(0) [0]
	13	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_WDAC.LATC.L2(0) [0]
	14	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(13) [0]
	15	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_TRH.LATC.L2(0) [0]
	16:19	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_DECODER.FSM_STATE_LATCH.LATC.L2(0:3) [0000]
	20	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(12) [0]
	21	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_EP.LATC.L2(0) [0]
	24:25	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_ISR_24_25.LATC.L2(24:25) [00]
	28:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_ISR_28_31.LATC.L2(28:31) [0000]
	32:63	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_SPRG0.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		XSR_HS
1:3	RWX	RWX		XSR_HC
4	ROX	ROX		XSR_HCP
5	ROX	ROX		XSR_RIP
6	ROX	ROX		XSR_SIP
7	RWX	RWX		XSR_TRAP
8	RWX	RWX		XSR_IAC
9:11	ROX	ROX		XSR_SIB
12	RWX	RWX		XSR_RDAC
13	RWX	RWX		XSR_WDAC
14	ROX	ROX		XSR_WS
15	ROX	ROX		XSR_TRH
16:19	ROX	ROX		XSR_SMS
20	ROX	ROX		XSR_LP
21	ROX	ROX		XSR_EP
22:23	RO	RO		constant=0b00
24	ROX	ROX		XSR_PTR
25	ROX	ROX		XSR_ST
26:27	RO	RO		constant=0b00
28	ROX	ROX		XSR_MFE
29:31	ROX	ROX		XSR_MCS
32:63	RWX	RWX		SPRG0

OCB_OCI GPE External Interface RAMEDR
Addr:	0000000000064014 (SCOM) 00000000C00200A0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIRAMEDR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR4 Ram & Error Diagnosis Register. Can be used to read IR and EDR for debug. Also provides ability to RAM an instruction without modifying SPRG0.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_ISP.LT_IR.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_EDR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RWX	RWX		OCB_OCI_GPEXIRAMEDR_IR: PPE Instruction Register. Writes cause a RAM operation. Provides the requested PPE Instruction to execute.
32:63	ROX	ROX		OCB_OCI_GPEXIRAMEDR_EDR: Error Data Register, set on PPE interrupts caused by an error. See PPE Specification for definition.

OCB_OCI GPE External Interface DBGPRO
Addr:	0000000000064015 (SCOM) 00000000C00200A8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIDBGPRO
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR5 Debug & Runtime Profiling Read program location and status. Also used to write XSR & IAR.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.XSR_INT_SPR(0) [0]
	1:3	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_HC.LATC.L2(0:2) [000]
	4	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_HCP.LATC.L2(0) [0]
	5	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_RIP.LATC.L2(0) [0]
	6	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_SIP.LATC.L2(0) [0]
	7	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_TRAP.LATC.L2(0) [0]
	8	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_IAC.LATC.L2(0) [0]
	9:11	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(9:11) [000]
	12	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_RDAC.LATC.L2(0) [0]
	13	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_WDAC.LATC.L2(0) [0]
	14	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(13) [0]
	15	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_TRH.LATC.L2(0) [0]
	16:19	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_DECODER.FSM_STATE_LATCH.LATC.L2(0:3) [0000]
	20	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(12) [0]
	21	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_EP.LATC.L2(0) [0]
	24:25	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_ISR_24_25.LATC.L2(24:25) [00]
	28:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_ISR_28_31.LATC.L2(28:31) [0000]
	32:61	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_ISP.LT_IAR.LATC.L2(0:29) [000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		XSR_HS
1:3	RWX	RWX		XSR_HC
4	ROX	ROX		XSR_HCP
5	ROX	ROX		XSR_RIP
6	ROX	ROX		XSR_SIP
7	RWX	RWX		XSR_TRAP
8	RWX	RWX		XSR_IAC
9:11	ROX	ROX		XSR_SIB
12	RWX	RWX		XSR_RDAC
13	RWX	RWX		XSR_WDAC
14	ROX	ROX		XSR_WS
15	ROX	ROX		XSR_TRH
16:19	ROX	ROX		XSR_SMS
20	ROX	ROX		XSR_LP
21	ROX	ROX		XSR_EP
22:23	RO	RO		constant=0b00
24	ROX	ROX		XSR_PTR
25	ROX	ROX		XSR_ST
26:27	RO	RO		constant=0b00
28	ROX	ROX		XSR_MFE
29:31	ROX	ROX		XSR_MCS
32:61	RWX	RWX		OCB_OCI_GPEXIIAR_IAR: PPE Instruction Address Register See PPE Specification for bit definitions. Corresponds to XIR5 bits 32:63
62:63	RO	RO		constant=0b00

OCB_OCI GPE External Interface SIB Info
Addr:	0000000000064016 (SCOM) 00000000C00200B0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXISIB
Constant(s):
Comments:	XIR6 SIB Transaction buffer info for debug
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	32	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_R_NW_Q_INST.LATC.L2(0) [0]
	33	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_BUSY_Q_INST.LATC.L2(0) [0]
	34	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.PIB_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0]
	49:51	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_RSP_INFO_Q_0_INST.LATC.L2(0:2) [000]
	61	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_RESET_PENDING_Q_INST.LATC.L2(0) [0]
	62	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.IFETCH_PIB_PENDING_Q_INST.LATC.L2(0) [0]
	63	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.PIB_DATAOP_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXISIB_PIB_ADDR: PIB transaction buffer current or previous transaction byte address
32	ROX	ROX		OCB_OCI_GPEXISIB_PIB_R_NW: PIB transaction buffer current or previous transaction type, read if 1 and write if 0.
33	ROX	ROX		OCB_OCI_GPEXISIB_PIB_BUSY: Indicates if the transaction buffer is occupied with an ongoing transaction. Busy is cleared when the transaction is completed.
34	ROX	ROX		OCB_OCI_GPEXISIB_PIB_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the PIB interface can continue to service I-fetches (only in case of SBE instance).
35:48	RO	RO		constant=0b00000000000000
49:51	ROX	ROX		OCB_OCI_GPEXISIB_PIB_RSP_INFO: PIB transaction buffer response info. Current or previous transaction got an error on the PIB interface when non-zero.
52:60	RO	RO		constant=0b000000000
61	ROX	ROX		OCB_OCI_GPEXISIB_PIB_RESET_PENDING: Indicates if hard reset occurred during an ongoing transcation and transaction is still pending when set to 1.
62	ROX	ROX		OCB_OCI_GPEXISIB_PIB_IFETCH_PENDING: Indicates a instruction fetch is pending on the PIB interface when set to 1.
63	ROX	ROX		OCB_OCI_GPEXISIB_PIB_DATAOP_PENDING: Indicates a data transaction is pending on the PIB interface when set to 1.

OCB_OCI GPE External Interface MEM Info
Addr:	0000000000064017 (SCOM) 00000000C00200B8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIMEM
Constant(s):
Comments:	XIR7 Memory Interface transaction buffer info for debug
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.MEM_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	32	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.MEM_R_NW_Q_INST.LATC.L2(0) [0]
	33	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.MEM_BUSY_Q_INST.LATC.L2(0) [0]
	34	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.MEM_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0]
	35:42	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.MEM_BYTE_ENABLE_Q_0_INST.LATC.L2(0:7) [00000000]
	43	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.MEM_LINE_MODE_Q_INST.LATC.L2(0) [0]
	49:51	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.MEM_ERROR_Q_0_INST.LATC.L2(0:2) [000]
	62	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.IFETCH_MEM_PENDING_Q_INST.LATC.L2(0) [0]
	63	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.MEM_DATAOP_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_ADDR: MEM transaction buffer current or previous transaction byte address.
32	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_R_NW: MEM transaction buffer current or previous transaction type, read if 1 and write if 0.
33	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_BUSY: Indicates if the transaction buffer is occupied with an ongoing transaction. Busy is cleared when the transaction is completed.
34	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the memory interface can continue to service I-fetches.
35:42	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_BYTE_ENABLE: MEM transaction buffer current or previous transaction byte enables.
43	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_LINE_MODE: MEM transaction buffer current or previous transaction line mode. Indicates a 32B read request when set to 1.
44:48	RO	RO		constant=0b00000
49:51	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_ERROR: MEM transaction buffer error code. Current or previous transaction got an error on the memory interface when non-zero.
52:61	RO	RO		constant=0b0000000000
62	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IFETCH_PENDING: Indicates a instruction fetch is pending on the MEM interface when set to 1.
63	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_DATAOP_PENDING: Indicates a data transaction is pending on the MEM interface when set to 1.

OCB_OCI GPE External Interface Store Gather Buffer Info
Addr:	0000000000064018 (SCOM) 00000000C00200C0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXISGB
Constant(s):
Comments:	XIR8 Store Gather Buffer Info for debug
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.STR_GTHR_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	35	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.MEM_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0]
	36:39	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.STR_GTHR_VALID_Q_0_INST.LATC.L2(0:3) [0000]
	63	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.STR_GTHR_FLUSH_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		STORE_ADDRESS
32:34	RO	RO		constant=0b000
35	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the memory interface can continue to service I-fetches.
36:39	ROX	ROX		SGB_BYTE_VALID
40:62	RO	RO		constant=0b00000000000000000000000
63	ROX	ROX		SGB_FLUSH_PENDING

OCB_OCI GPE External Interface Icache Info
Addr:	0000000000064019 (SCOM) 00000000C00200C8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIICAC
Constant(s):
Comments:	XIR9 Instruction Cache Info for debug
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.ICACHE_COMP.ICACHE_TAG_ADDR_LATCH.LATC.L2(0:26) [000000000000000000000000000]
	32	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.ICACHE_COMP.ICACHE_ERR_LATCH.LATC.L2(0) [0]
	34	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.IFETCH_PIB_PENDING_Q_INST.LATC.L2(0) [0]
	35	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.IFETCH_MEM_PENDING_Q_INST.LATC.L2(0) [0]
	36:39	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.ICACHE_COMP.ICACHE_VALID_LATCH.LATC.L2(0:3) [0000]
	40:43	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.ICACHE_COMP.INCLUDE_ADDN_CACHE_LINE.ICACHE_LINE2_VALID_LATCH.LATC.L2(0:3) [0000]
	45	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.ICACHE_COMP.INCLUDE_ADDN_CACHE_LINE.ICACHE_LINE_PTR_LATCH.LATC.L2(0) [0]
	46	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.ICACHE_COMP.INCLUDE_ADDN_CACHE_LINE.ICACHE_LINE2_ERR_LATCH.LATC.L2(0) [0]
	47	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.INCLUDE_PREFETCH.ICACHE_PREFETCH_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0:26	ROX	ROX		ICACHE_TAG_ADDR
27:31	RO	RO		constant=0b00000
32	ROX	ROX		ICACHE_ERR
33	RO	RO		constant=0b0
34	ROX	ROX		OCB_OCI_GPEXISIB_PIB_IFETCH_PENDING: Indicates a instruction fetch is pending on the PIB interface when set to 1.
35	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IFETCH_PENDING: Indicates a instruction fetch is pending on the MEM interface when set to 1.
36:39	ROX	ROX		ICACHE_VALID
40:43	ROX	ROX		ICACHE_LINE2_VALID
44	RO	RO		constant=0b0
45	ROX	ROX		ICACHE_LINE_PTR
46	ROX	ROX		ICACHE_LINE2_ERR
47	ROX	ROX		ICACHE_PREFETCH_PENDING
48:63	RO	RO		constant=0b0000000000000000

OCB_OCI GPE External Interface Dcache Info
Addr:	000000000006401A (SCOM) 00000000C00200D0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIDCAC
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR10 Data Cache Info for debug
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_COMP.DCACHE_TAG_ADDR_LATCH.LATC.L2(0:26) [000000000000000000000000000]
	32	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_COMP.DCACHE_ERR.LATC.L2(0) [0]
	35	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_POPULATE_PENDING_Q_INST.LATC.L2(0) [0]
	36:39	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_COMP.DCACHE_VALID_LATCH.LATC.L2(0:3) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0:26	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_TAG_ADDR: 32B Data Address Tag for the current or previous cache content.
27:31	RO	RO		constant=0b00000
32	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_ERR: Indicates the current or previous content of the cache is bad due to an interface error during populate.
33:34	RO	RO		constant=0b00
35	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_POPULATE_PENDING: Data populate to D-Cache pending from MEM interface.
36:39	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_VALID: Double word valids indicating the corresponding double word in the cache is valid
40:63	RO	RO		constant=0b000000000000000000000000

OCB_OCI GPE External Interface DBGINF
Addr:	000000000006401F (SCOM) 00000000C00200F8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIDBGINF
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: Debug Information Read registers containing recent program address information. New for P10.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:29	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_SRR0.LATC.L2(0:29) [000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_LR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:29	ROX	ROX		OCB_OCI_GPEXIDBGINF_SRR0: PPE Save & Restore Register 0 Contains address of the most recent interrupt taken. Potentially useful during debug.
30:31	RO	RO		constant=0b00
32:63	ROX	ROX		OCB_OCI_GPEXIDBGINF_LR: PPE Link Register. Contains address of the instruction following the most recent Branch with Link instruction executed, to give an idea from whence the code recently came. Potentially useful during debug.

OCB_OCI GPE External Interface OCI-Word XCR
Addr:	0000000000064020 (SCOM) 00000000C0020100 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEOXIXCR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR0(0:31) External Control Register (XCR). Note this is the same as GPEXIXCR but included separately for consistency in 32-bit access OCI address mapping.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.LT_XIR_XCR_CMND.LATC.L2(0:2) [000]
Bit(s)	SCOM	OCI		Dial: Description
0	RO	RO		constant=0b0
1:3	WOX	WOX		OCB_OCI_GPEOXIXCR_XCR: PPE External Control Register See PPE Specification for bit definitions. Corresponds to XIR0 bits 1:3
4:63	RO	RO		constant=0b000000000000000000000000000000000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word XSR
Addr:	0000000000064021 (SCOM) 00000000C0020108 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIXSR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR3(0:31) External Status Register (XSR)
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.XSR_INT_SPR(0) [0]
	1:3	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_HC.LATC.L2(0:2) [000]
	4	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_HCP.LATC.L2(0) [0]
	5	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_RIP.LATC.L2(0) [0]
	6	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_SIP.LATC.L2(0) [0]
	7	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_TRAP.LATC.L2(0) [0]
	8	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_IAC.LATC.L2(0) [0]
	9:11	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(9:11) [000]
	12	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_RDAC.LATC.L2(0) [0]
	13	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_WDAC.LATC.L2(0) [0]
	14	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(13) [0]
	15	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_TRH.LATC.L2(0) [0]
	16:19	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_DECODER.FSM_STATE_LATCH.LATC.L2(0:3) [0000]
	20	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(12) [0]
	21	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_XSR_EP.LATC.L2(0) [0]
	24:25	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_ISR_24_25.LATC.L2(24:25) [00]
	28:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_ISR_28_31.LATC.L2(28:31) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		XSR_HS
1:3	ROX	ROX		XSR_HC
4	ROX	ROX		XSR_HCP
5	ROX	ROX		XSR_RIP
6	ROX	ROX		XSR_SIP
7	ROX	ROX		XSR_TRAP
8	ROX	ROX		XSR_IAC
9:11	ROX	ROX		XSR_SIB
12	ROX	ROX		XSR_RDAC
13	ROX	ROX		XSR_WDAC
14	ROX	ROX		XSR_WS
15	ROX	ROX		XSR_TRH
16:19	ROX	ROX		XSR_SMS
20	ROX	ROX		XSR_LP
21	ROX	ROX		XSR_EP
22:23	RO	RO		constant=0b00
24	ROX	ROX		XSR_PTR
25	ROX	ROX		XSR_ST
26:27	RO	RO		constant=0b00
28	ROX	ROX		XSR_MFE
29:31	ROX	ROX		XSR_MCS
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word SPRG0
Addr:	0000000000064022 (SCOM) 00000000C0020110 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXISPRG0
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR3(32:63) SPRG0 register
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_SPRG0.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RWX	RWX		SPRG0
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word EDR
Addr:	0000000000064023 (SCOM) 00000000C0020118 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIEDR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR4(32:63) Error Data Register (EDR)
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_EDR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIRAMEDR_EDR: Error Data Register, set on PPE interrupts caused by an error. See PPE Specification for definition.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word IR
Addr:	0000000000064024 (SCOM) 00000000C0020120 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIIR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR4(0:31) Instruction Register (IR)
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_ISP.LT_IR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RWX	RWX		OCB_OCI_GPEXIRAMEDR_IR: PPE Instruction Register. Writes cause a RAM operation. Provides the requested PPE Instruction to execute.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word IAR
Addr:	0000000000064025 (SCOM) 00000000C0020128 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIIAR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR5(32:63) Instruction Register (IAR)
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:29	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_ISP.LT_IAR.LATC.L2(0:29) [000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:29	RWX	RWX		OCB_OCI_GPEXIIAR_IAR: PPE Instruction Address Register See PPE Specification for bit definitions. Corresponds to XIR5 bits 32:63
30:63	RO	RO		constant=0b0000000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word SIB Info Upper
Addr:	0000000000064026 (SCOM) 00000000C0020130 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXISIBU
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR6(0:31) SIB Info Upper bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RO	RO		OCB_OCI_GPEXISIB_PIB_ADDR: PIB transaction buffer current or previous transaction byte address
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word SIB Info Lower
Addr:	0000000000064027 (SCOM) 00000000C0020138 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXISIBL
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR6(32:63) SIB Info Lower bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_R_NW_Q_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_BUSY_Q_INST.LATC.L2(0) [0]
	2	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.PIB_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0]
	17:19	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_RSP_INFO_Q_0_INST.LATC.L2(0:2) [000]
	30	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.IFETCH_PIB_PENDING_Q_INST.LATC.L2(0) [0]
	31	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.PIB_DATAOP_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		OCB_OCI_GPEXISIB_PIB_R_NW: PIB transaction buffer current or previous transaction type, read if 1 and write if 0.
1	ROX	ROX		OCB_OCI_GPEXISIB_PIB_BUSY: Indicates if the transaction buffer is occupied with an ongoing transaction. Busy is cleared when the transaction is completed.
2	ROX	ROX		OCB_OCI_GPEXISIB_PIB_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the PIB interface can continue to service I-fetches (only in case of SBE instance).
3:16	RO	RO		constant=0b00000000000000
17:19	ROX	ROX		OCB_OCI_GPEXISIB_PIB_RSP_INFO: PIB transaction buffer response info. Current or previous transaction got an error on the PIB interface when non-zero.
20:29	RO	RO		constant=0b0000000000
30	ROX	ROX		OCB_OCI_GPEXISIB_PIB_IFETCH_PENDING: Indicates a instruction fetch is pending on the PIB interface when set to 1.
31	ROX	ROX		OCB_OCI_GPEXISIB_PIB_DATAOP_PENDING: Indicates a data transaction is pending on the PIB interface when set to 1.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word MEM Info Upper
Addr:	0000000000064028 (SCOM) 00000000C0020140 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIMEMU
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR7(0:31) Memory Interface Info Upper bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.MEM_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_ADDR: MEM transaction buffer current or previous transaction byte address.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word MEM Info Lower
Addr:	0000000000064029 (SCOM) 00000000C0020148 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIMEML
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR7(32:63) Memory Interface Info Lower bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.MEM_BUSY_Q_INST.LATC.L2(0) [0]
	2	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.MEM_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0]
	3:10	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.MEM_BYTE_ENABLE_Q_0_INST.LATC.L2(0:7) [00000000]
	11	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.MEM_LINE_MODE_Q_INST.LATC.L2(0) [0]
	12	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.MIB_SCOM_REG_2_DATA(44) [0]
	17:19	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.MEM_ERROR_Q_0_INST.LATC.L2(0:2) [000]
	30	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.IFETCH_MEM_PENDING_Q_INST.LATC.L2(0) [0]
	31	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.MEM_DATAOP_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0	RO	RO		constant=0b0
1	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_BUSY: Indicates if the transaction buffer is occupied with an ongoing transaction. Busy is cleared when the transaction is completed.
2	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the memory interface can continue to service I-fetches.
3:10	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_BYTE_ENABLE: MEM transaction buffer current or previous transaction byte enables.
11	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_LINE_MODE: MEM transaction buffer current or previous transaction line mode. Indicates a 32B read request when set to 1.
12	ROX	ROX		Memory_Info_Lower_part1
13:16	RO	RO		constant=0b0000
17:19	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_ERROR: MEM transaction buffer error code. Current or previous transaction got an error on the memory interface when non-zero.
20:29	RO	RO		constant=0b0000000000
30	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IFETCH_PENDING: Indicates a instruction fetch is pending on the MEM interface when set to 1.
31	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_DATAOP_PENDING: Indicates a data transaction is pending on the MEM interface when set to 1.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word SGB Info Upper
Addr:	000000000006402A (SCOM) 00000000C0020150 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXISGBU
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR8(0:31) Store Gather Buffer Info Upper bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.STR_GTHR_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		SGB_Info_Upper
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word SGB Info Lower
Addr:	000000000006402B (SCOM) 00000000C0020158 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXISGBL
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR8(32:63) Store Gather Buffer Info Lower bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	3	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.MEM_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0]
	4:7	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.STR_GTHR_VALID_Q_0_INST.LATC.L2(0:3) [0000]
	31	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.STR_GTHR_FLUSH_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0:2	RO	RO		constant=0b000
3	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the memory interface can continue to service I-fetches.
4:7	ROX	ROX		SGB_Info_Lower_part1
8:30	RO	RO		constant=0b00000000000000000000000
31	ROX	ROX		SGB_Info_Lower_part2
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word Icache Info Upper
Addr:	000000000006402C (SCOM) 00000000C0020160 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIICACU
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR9(0:31) Instruction Cache Info Upper bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.ICACHE_COMP.ICACHE_TAG_ADDR_LATCH.LATC.L2(0:26) [000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:26	ROX	ROX		Icache_Info_Upper
27:63	RO	RO		constant=0b0000000000000000000000000000000000000

OCB_OCI GPE External Interface MEM Icache Info Lower
Addr:	000000000006402D (SCOM) 00000000C0020168 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIICACL
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR9(32:63) Instruction Cache Info Lower bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.ICACHE_COMP.ICACHE_ERR_LATCH.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.MIB_SCOM_REG_4_DATA(33) [0]
	2	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.IFETCH_PIB_PENDING_Q_INST.LATC.L2(0) [0]
	3	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.IFETCH_MEM_PENDING_Q_INST.LATC.L2(0) [0]
	4:7	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.ICACHE_COMP.ICACHE_VALID_LATCH.LATC.L2(0:3) [0000]
	8:11	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.ICACHE_COMP.INCLUDE_ADDN_CACHE_LINE.ICACHE_LINE2_VALID_LATCH.LATC.L2(0:3) [0000]
	13	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.ICACHE_COMP.INCLUDE_ADDN_CACHE_LINE.ICACHE_LINE_PTR_LATCH.LATC.L2(0) [0]
	14	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.ICACHE_COMP.INCLUDE_ADDN_CACHE_LINE.ICACHE_LINE2_ERR_LATCH.LATC.L2(0) [0]
	15	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.INCLUDE_PREFETCH.ICACHE_PREFETCH_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0:1	ROX	ROX		Icache_Info_Lower_part1
2	ROX	ROX		OCB_OCI_GPEXISIB_PIB_IFETCH_PENDING: Indicates a instruction fetch is pending on the PIB interface when set to 1.
3	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IFETCH_PENDING: Indicates a instruction fetch is pending on the MEM interface when set to 1.
4:11	ROX	ROX		Icache_Info_Lower_part1
12	RO	RO		constant=0b0
13:15	ROX	ROX		Icache_Info_Lower_part2
16:63	RO	RO		constant=0b000000000000000000000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word Dcache Info Upper
Addr:	000000000006402E (SCOM) 00000000C0020170 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIDCACU
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR10(0:31) Data Cache Info Upper bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_COMP.DCACHE_TAG_ADDR_LATCH.LATC.L2(0:26) [000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:26	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_TAG_ADDR: 32B Data Address Tag for the current or previous cache content.
27:31	RO	RO		constant=0b00000

OCB_OCI GPE External Interface MEM Dcache Info Lower
Addr:	000000000006402F (SCOM) 00000000C0020178 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIDCACL
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR10(32:63) Data Cache Info Lower bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_COMP.DCACHE_ERR.LATC.L2(0) [0]
	3	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_POPULATE_PENDING_Q_INST.LATC.L2(0) [0]
	4:7	TP.TPCHIP.OCC.OCI.GPE2.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_COMP.DCACHE_VALID_LATCH.LATC.L2(0:3) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_ERR: Indicates the current or previous content of the cache is bad due to an interface error during populate.
1:2	RO	RO		constant=0b00
3	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_POPULATE_PENDING: Data populate to D-Cache pending from MEM interface.
4:7	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_VALID: Double word valids indicating the corresponding double word in the cache is valid
8:31	RO	RO		constant=0b000000000000000000000000

OCB_OCI GPE External Interface OCI-Word SRR0
Addr:	0000000000064030 (SCOM) 00000000C0020180 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXISRR0
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR15(0:31) SRR0
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:29	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_SRR0.LATC.L2(0:29) [000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:29	ROX	ROX		OCB_OCI_GPEXIDBGINF_SRR0: PPE Save & Restore Register 0 Contains address of the most recent interrupt taken. Potentially useful during debug.
30:63	RO	RO		constant=0b0000000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word LR
Addr:	0000000000064031 (SCOM) 00000000C0020188 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXILR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR15(32:63) Link Register (LR)
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_LR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIDBGINF_LR: PPE Link Register. Contains address of the instruction following the most recent Branch with Link instruction executed, to give an idea from whence the code recently came. Potentially useful during debug.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word CTR
Addr:	0000000000064032 (SCOM) 00000000C0020190 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXICTR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR0(32:63) CTR
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_SPR.LT_CTR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXICTR_CTR: Count Register. Added for P10. Potentially useful for Debug since can indicate loop iteration or a recent branch target address, depending on compiler optimization decisions. Corresponds to XIR0 bits 32:63
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR0
Addr:	0000000000064040 (SCOM) 00000000C0020200 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR0
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR0
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR0.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR0_GPR0: General Purpose Register 0
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR1
Addr:	0000000000064041 (SCOM) 00000000C0020208 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR1
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR1
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR1.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR0_GPR1: General Purpose Register 1
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR2
Addr:	0000000000064042 (SCOM) 00000000C0020210 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR2
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR2
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR2.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR2_GPR2: General Purpose Register 2
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR3
Addr:	0000000000064043 (SCOM) 00000000C0020218 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR3
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR3
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR3.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR2_GPR3: General Purpose Register 3
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR4
Addr:	0000000000064044 (SCOM) 00000000C0020220 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR4
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR4
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR4.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR4_GPR4: General Purpose Register 4
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR5
Addr:	0000000000064045 (SCOM) 00000000C0020228 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR5
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR5
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR5.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR4_GPR5: General Purpose Register 5
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR6
Addr:	0000000000064046 (SCOM) 00000000C0020230 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR6
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR6
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR6.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR6_GPR6: General Purpose Register 6
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR7
Addr:	0000000000064047 (SCOM) 00000000C0020238 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR7
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR7
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR7.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR6_GPR7: General Purpose Register 7
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR8
Addr:	0000000000064048 (SCOM) 00000000C0020240 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR8
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR8
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR8.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR8_GPR8: General Purpose Register 8
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR9
Addr:	0000000000064049 (SCOM) 00000000C0020248 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR9
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR9
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR9.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR8_GPR9: General Purpose Register 9
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR10
Addr:	000000000006404A (SCOM) 00000000C0020250 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR10
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR10
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR10.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDRX_GPR10: General Purpose Register 10
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR13
Addr:	000000000006404B (SCOM) 00000000C0020258 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR13
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR13
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR13.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDRX_GPR13_11: DD1: General Purpose Register 13 DD2: General Purpose Register 11
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR28
Addr:	000000000006404C (SCOM) 00000000C0020260 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR28
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR28
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR28.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR28_GPR28: General Purpose Register 28
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR29
Addr:	000000000006404D (SCOM) 00000000C0020268 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR29
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR29
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR29.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR28_GPR29: General Purpose Register 29
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR30
Addr:	000000000006404E (SCOM) 00000000C0020270 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR30
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR30
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR30.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR30_GPR30: General Purpose Register 30
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR31
Addr:	000000000006404F (SCOM) 00000000C0020278 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR31
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR31
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR31.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RO	RO		OCB_OCI_GPEXIVDR30_GPR31: General Purpose Register 31
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface VDR0
Addr:	0000000000064080 (SCOM) 00000000C0020400 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIVDR0
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR0 & GPR1
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR0.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR1.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR0_GPR0: General Purpose Register 0
32:63	ROX	ROX		OCB_OCI_GPEXIVDR0_GPR1: General Purpose Register 1

OCB_OCI GPE External Interface VDR2
Addr:	0000000000064081 (SCOM) 00000000C0020408 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIVDR2
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR2 & GPR3
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR2.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR3.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR2_GPR2: General Purpose Register 2
32:63	ROX	ROX		OCB_OCI_GPEXIVDR2_GPR3: General Purpose Register 3

OCB_OCI GPE External Interface VDR4
Addr:	0000000000064082 (SCOM) 00000000C0020410 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIVDR4
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR4 & GPR5
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR4.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR5.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR4_GPR4: General Purpose Register 4
32:63	ROX	ROX		OCB_OCI_GPEXIVDR4_GPR5: General Purpose Register 5

OCB_OCI GPE External Interface VDR6
Addr:	0000000000064083 (SCOM) 00000000C0020418 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIVDR6
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR6 & GPR7
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR6.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR7.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR6_GPR6: General Purpose Register 6
32:63	ROX	ROX		OCB_OCI_GPEXIVDR6_GPR7: General Purpose Register 7

OCB_OCI GPE External Interface VDR8
Addr:	0000000000064084 (SCOM) 00000000C0020420 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIVDR8
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR8 & GPR9
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR8.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR9.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR8_GPR8: General Purpose Register 8
32:63	ROX	ROX		OCB_OCI_GPEXIVDR8_GPR9: General Purpose Register 9

OCB_OCI GPE External Interface VDRX
Addr:	0000000000064085 (SCOM) 00000000C0020428 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIVDRX
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: DD1: Virtual Doubleword X (GPR10 & GPR13) DD2: Virtual Doubleword 10 (GPR10 & GPR11) Note: unlike other 64-bit GPR XIRs, this is not a true VDR.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR10.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR13.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDRX_GPR10: General Purpose Register 10
32:63	ROX	ROX		OCB_OCI_GPEXIVDRX_GPR13_11: DD1: General Purpose Register 13 DD2: General Purpose Register 11

OCB_OCI GPE External Interface VDR28
Addr:	0000000000064086 (SCOM) 00000000C0020430 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIVDR28
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR28 & GPR29
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR28.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR29.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR28_GPR28: General Purpose Register 28
32:63	ROX	ROX		OCB_OCI_GPEXIVDR28_GPR29: General Purpose Register 29

OCB_OCI GPE External Interface VDR30
Addr:	0000000000064087 (SCOM) 00000000C0020438 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIVDR30
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR30 & GPR31
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR30.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE2.GPE.PPE.I_C_PPE42_GPR.LT_GPR31.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR30_GPR30: General Purpose Register 30
32:63	ROX	ROX		OCB_OCI_GPEXIVDR30_GPR31: General Purpose Register 31

OCB_OCI GPE Timer Select Register
Addr:	0000000000066000 (SCOM) 00000000C0030000 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPETSEL
Constant(s):
Comments:	This register selects the rate of the Fixed Interval and Watchdog Timers The input to the PPE will pulse every 2^(23 - select) times the input timer period (which is the PAU cycle time/64), unless select is zero in which case the timer pulse is disabled. SUMMARY: the resultant timer rate is given by: 2^(29-select) / PAU_Frequency when select is non-zero.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.OCC.OCI.GPE3.PPEREG.GPETSEL_Q_0_INST.LATC.L2(0:7) [00000000]
Bit(s)	SCOM	OCI		Dial: Description
0:3	RW	RW		OCB_OCI_GPETSEL_WATCHDOG_SEL: Selects Watchdog Timer rate
4:7	RW	RW		OCB_OCI_GPETSEL_FIT_SEL: Selects Fixed Interval Timer rate
8:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000

OCB_OCI GPE Interrupt Vector Prefix Register
Addr:	0000000000066001 (SCOM) 00000000C0030008 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEIVPR
Constant(s):
Comments:	This register selects the top 23 bits of the Interrupt Address Vector.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:22	TP.TPCHIP.OCC.OCI.GPE3.PPEREG.GPEIVPR_Q_0_INST.LATC.L2(0:22) [00000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:22	RW	RW		OCB_OCI_GPEIVPR_IVPR: Interrupt Prefix Vector Register (Resets to 0xFFFFFE left justified)
23:63	RO	RO		constant=0b00000000000000000000000000000000000000000

OCB_OCI GPE Debug Mode Register
Addr:	0000000000066002 (SCOM) 00000000C0030010 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEDBG
Constant(s):
Comments:	This register contains mode bits controlling the debug bolt-on and PPE behavior on checkstop and trigger.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:23	TP.TPCHIP.OCC.OCI.GPE3.PPEREG.GPEDBG_Q_0_INST.LATC.L2(0:23) [000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	RW	RW		OCB_OCI_GPEDBG_EN_DBG: Enable Debug Trace. Master switch that enables clocks to the trace. Also causes RiscTrace to start on rising edge & stop on falling edge when RISCTRACE is enabled (TRACE_DATA_SEL(0)=0).
1	RW	RW		OCB_OCI_GPEDBG_HALT_ON_XSTOP: Enable Halt on Checkstop input
2	RW	RW		OCB_OCI_GPEDBG_HALT_ON_TRIG: Enable Halt on Trigger input
3	RW	RW		OCB_OCI_GPEDBG_EN_COVERAGE_MODE: Enables Code Coverage Trace Mode. When set, no longer traces every instruction executed, and adds SPRG0 and MARK data to the trace. Note: only supported when EN_INTR_ADDR and EN_TRACE_EXTRA are both set to 0.
4	RW	RW		OCB_OCI_GPEDBG_EN_INTR_ADDR: When RISCTRACE is enabled, trace the Full Interrupt Vector Address, otherwise only trace the lower byte of address.
5	RW	RW		OCB_OCI_GPEDBG_EN_TRACE_EXTRA: When RISCTRACE is enabled and this bit is set, records extra trace data not needed for 405 RISCTrace spec. When this bit is set, record MTMSR or MTSPRG0 data and new MSR value set by RFI.
6	RW	RW		OCB_OCI_GPEDBG_EN_TRACE_STALL: When RISCTRACE is enabled and this bit is set, stall cycles when the processor is not actively executing an instruction, that are not already included in the previous event, are recorded unless it is Halted or in Wait state. When this mode is not set, the RISTRACE is smaller but not time accurate.
7	RW	RW		OCB_OCI_GPEDBG_EN_WAIT_CYCLES: When RISCTRACE is enabled and this bit is set, Stall Events are used to record the number of cycles the PPE is in Wait state. Otherwise cycles in Wait state are ignored. When this bit is set, EN_TRACE_STALL must also be set.
8	RW	RW		OCB_OCI_GPEDBG_EN_FULL_SPEED: When set, the trace valid is pulsed at 1:1 (4x faster than the debug data, which changes at PPE clock speed). This is used for CHTM and NHTM (in memory trace). When this mode is NOT set, trace valid is held constant for a full PPE cycle (four 1:1 cycles). When connected to a trace array this bit should match the corresponding speed of the array.
9	RW	RW		OCB_OCI_GPEDBG_DIS_FLOW_CHANGE: When set, do not record code flow change and IAR trace events (taken & untaken branches, Interrupts/Exceptions, RFI, WRTEE, or Sync Events). Setting this mode is only supported when EN_COVERAGE_MODE=1.
10:11	RW	RW		OCB_OCI_GPEDBG_TRACE_MODE_SEL: Bit 0 chooses between 0: PPE Core Debug Mode A; 1: Mode B Bit 1 when set, ORs in the secondary valid corresponding to lower bits of the trace data when they are from a different source than bits 0:23 (NOTE: likely 0 for HTM tracing)
12	RW	RW		OCB_OCI_GPEDBG_EN_MARK_TRACE: Traces a unique record with an additional 16-bits to capture the (TG, TO, RA, and RB) fields on MARK type instructions.
13	RW	RW		OCB_OCI_GPEDBG_EN_EE_TRACE: Traces wrtee or wrteei instructions along with the new value of the EE bit with a unique record. If (EN_TRACE_EXTRA=0 or EN_COVERAGE_MODE=1), a unique record is also generated for RFI and MTMSR and exceptions to trace the value of the EE bit .
14:15	RW	RW		OCB_OCI_GPEDBG_RESERVED14_15: Implemented but not used.
16	RW	RW		OCB_OCI_GPEDBG_FIR_TRIGGER: NOT CONNECTED. GPE can write FIR directly if needed. Intended to Programmatically assert a FIR bit to inject checkstop or send Attention to the Service Element.
17:19	RW	RW		OCB_OCI_GPEDBG_SPARE: Spare (used for GPIO on other instances)
20:23	RW	RW		OCB_OCI_GPEDBG_TRACE_DATA_SEL: Mux select to choose debug data content on the trace bus. All 16 encodes are defined as per the table in the Debug Bolt-on chapter of the Power Management Spec. 0x0 chooses an 88-bit PPE-RISCtrace by default. b00XX enables Risctrace records to be generated in the upper 64-bits of trace data. bXX00 selects the remaining 24 bits to form 88-bit Trace Packets to be generated on the debug bus to be sent to the hardware trace array (otherwise PPE, MIB, or EXT data will be used) The other 12 encodes contain permutations of the PPE Core, Memory Interface, and External debug buses instead of RISCtrace records.
24:63	RO	RO		constant=0b0000000000000000000000000000000000000000

OCB_OCI GPE Memory Access Configuration Register
Addr:	0000000000066004 (SCOM) 00000000C0030020 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEMACR
Constant(s):
Comments:	This register controls Memory Access Priority on the OCI.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:12	TP.TPCHIP.OCC.OCI.GPE3.PPEREG.GPEMACR_Q_0_INST.LATC.L2(0:12) [0000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:1	RW	RW		OCB_OCI_GPEMACR_MEM_LOW_PRIORITY: OCI priority to use for accessing Main Memory when Address(0:1) = "10" and the PPE high priority output is 0
2:3	RW	RW		OCB_OCI_GPEMACR_MEM_HIGH_PRIORITY: OCI priority to use for accessing Main Memory when Address(0:1) = "10" and the PPE high priority output is 1
4:5	RW	RW		OCB_OCI_GPEMACR_LOCAL_LOW_PRIORITY: OCI priority to use for accessing Local Registers when Address(0:2) = "110" and the PPE high priority output is 0
6:7	RW	RW		OCB_OCI_GPEMACR_LOCAL_HIGH_PRIORITY: OCI priority to use for accessing Local Registers when Address(0:2) = "110" and the PPE high priority output is 1
8:9	RW	RW		OCB_OCI_GPEMACR_SRAM_LOW_PRIORITY: OCI priority to use for accessing SRAM tank when Address(0:2) = "111" and the PPE high priority output is 0
10:11	RW	RW		OCB_OCI_GPEMACR_SRAM_HIGH_PRIORITY: OCI priority to use for accessing SRAM tank when Address(0:2) = "111" and the PPE high priority output is 1
12	RW	RW		OCB_OCI_GPEMACR_WRITE_PROTECT_ENABLE: Enables PPE write protect regions. When 0, the contents of GPESWPR[n] have no effect. When 1, and GPEWPR[n] are non-zero, this GPE can only write the OCC SRAM in the configured regions.
13:63	RO	RO		constant=0b000000000000000000000000000000000000000000000000000

OCB_OCI GPE SRAM Write Protect Register 0
Addr:	0000000000066005 (SCOM) 00000000C0030028 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPESWPR0
Constant(s):
Comments:	When enabled, these registers control the regions of OCC SRAM the GPE is allowed to write.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.OCC.OCI.GPE3.PPEREG.GPESWPR0A_Q_0_INST.LATC.L2(0:26) [000000000000000000000000000]
	44:58	TP.TPCHIP.OCC.OCI.GPE3.PPEREG.GPESWPR0B_Q_44_INST.LATC.L2(44:58) [000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:26	RW	RW		OCB_OCI_GPESWPR0_WRITE_PROTECT_BAR: Base address of write protect region 0. Must be 32B aligned
27:43	RO	RO		constant=0b00000000000000000
44:58	RW	RW		OCB_OCI_GPESWPR0_WRITE_PROTECT_SIZE: Size of write protect region 0 in 32B units. Bit aligned so the size can be added to the BAR to compute the maximum address of this write protect region. Maximum address is bar+size*32-1.
59:63	RO	RO		constant=0b00000

OCB_OCI GPE SRAM Write Protect Register 1
Addr:	0000000000066006 (SCOM) 00000000C0030030 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPESWPR1
Constant(s):
Comments:	When enabled, these registers control the regions of OCC SRAM the GPE is allowed to write.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.OCC.OCI.GPE3.PPEREG.GPESWPR1A_Q_0_INST.LATC.L2(0:26) [000000000000000000000000000]
	44:58	TP.TPCHIP.OCC.OCI.GPE3.PPEREG.GPESWPR1B_Q_44_INST.LATC.L2(44:58) [000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:26	RW	RW		OCB_OCI_GPESWPR1_WRITE_PROTECT_BAR: Base address of write protect region 1. Must be 32B aligned
27:43	RO	RO		constant=0b00000000000000000
44:58	RW	RW		OCB_OCI_GPESWPR1_WRITE_PROTECT_SIZE: Size of write protect region 1 in 32B units. Bit aligned so the size can be added to the BAR to compute the maximum address of this write protect region. Maximum address is bar+size*32-1.
59:63	RO	RO		constant=0b00000

OCB_OCI GPE External Interface XCR
Addr:	0000000000066010 (SCOM) 00000000C0030080 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIXCR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR0 External Control Register (XCR) Note: CTR was added for P10
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.LT_XIR_XCR_CMND.LATC.L2(0:2) [000]
	32:63	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_CTR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	RO	RO		constant=0b0
1:3	WOX	WOX		OCB_OCI_GPEOXIXCR_XCR: PPE External Control Register See PPE Specification for bit definitions. Corresponds to XIR0 bits 1:3
4:31	RO	RO		constant=0b0000000000000000000000000000
32:63	ROX	ROX		OCB_OCI_GPEXICTR_CTR: Count Register. Added for P10. Potentially useful for Debug since can indicate loop iteration or a recent branch target address, depending on compiler optimization decisions. Corresponds to XIR0 bits 32:63

OCB_OCI GPE External Interface RAMRA
Addr:	0000000000066011 (SCOM) 00000000C0030088 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIRAMRA
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR1 Ram Restore Acceleration Register. Can be used to restore SPRG0 plus Resume (or Single Step) with one command.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.LT_XIR_XCR_CMND.LATC.L2(0:2) [000]
	32:63	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_SPRG0.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	RO	RO		constant=0b0
1:3	WOX	WOX		OCB_OCI_GPEOXIXCR_XCR: PPE External Control Register See PPE Specification for bit definitions. Corresponds to XIR0 bits 1:3
4:31	RO	RO		constant=0b0000000000000000000000000000
32:63	WOX	WOX		SPRG0

OCB_OCI GPE External Interface RAMGA
Addr:	0000000000066012 (SCOM) 00000000C0030090 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIRAMGA
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR2 Ram GPR Acceleration Register. Can be used to modify a GPR with one command (where IR = MFSPRG0 instruction 0xFC2082A6 .. 0xFFD082A6)
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_ISP.LT_IR.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_SPRG0.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	WOX	WOX		OCB_OCI_GPEXIRAMEDR_IR: PPE Instruction Register. Writes cause a RAM operation. Provides the requested PPE Instruction to execute.
32:63	WOX	WOX		SPRG0

OCB_OCI GPE External Interface RAMDBG
Addr:	0000000000066013 (SCOM) 00000000C0030098 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIRAMDBG
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR3 Ram & Debug Register. Read status and data. Allows write ability to modify only SPRG0 for a subsequent RAM operation.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.XSR_INT_SPR(0) [0]
	1:3	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_HC.LATC.L2(0:2) [000]
	4	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_HCP.LATC.L2(0) [0]
	5	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_RIP.LATC.L2(0) [0]
	6	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_SIP.LATC.L2(0) [0]
	7	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_TRAP.LATC.L2(0) [0]
	8	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_IAC.LATC.L2(0) [0]
	9:11	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(9:11) [000]
	12	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_RDAC.LATC.L2(0) [0]
	13	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_WDAC.LATC.L2(0) [0]
	14	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(13) [0]
	15	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_TRH.LATC.L2(0) [0]
	16:19	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_DECODER.FSM_STATE_LATCH.LATC.L2(0:3) [0000]
	20	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(12) [0]
	21	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_EP.LATC.L2(0) [0]
	24:25	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_ISR_24_25.LATC.L2(24:25) [00]
	28:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_ISR_28_31.LATC.L2(28:31) [0000]
	32:63	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_SPRG0.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		XSR_HS
1:3	RWX	RWX		XSR_HC
4	ROX	ROX		XSR_HCP
5	ROX	ROX		XSR_RIP
6	ROX	ROX		XSR_SIP
7	RWX	RWX		XSR_TRAP
8	RWX	RWX		XSR_IAC
9:11	ROX	ROX		XSR_SIB
12	RWX	RWX		XSR_RDAC
13	RWX	RWX		XSR_WDAC
14	ROX	ROX		XSR_WS
15	ROX	ROX		XSR_TRH
16:19	ROX	ROX		XSR_SMS
20	ROX	ROX		XSR_LP
21	ROX	ROX		XSR_EP
22:23	RO	RO		constant=0b00
24	ROX	ROX		XSR_PTR
25	ROX	ROX		XSR_ST
26:27	RO	RO		constant=0b00
28	ROX	ROX		XSR_MFE
29:31	ROX	ROX		XSR_MCS
32:63	RWX	RWX		SPRG0

OCB_OCI GPE External Interface RAMEDR
Addr:	0000000000066014 (SCOM) 00000000C00300A0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIRAMEDR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR4 Ram & Error Diagnosis Register. Can be used to read IR and EDR for debug. Also provides ability to RAM an instruction without modifying SPRG0.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_ISP.LT_IR.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_EDR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RWX	RWX		OCB_OCI_GPEXIRAMEDR_IR: PPE Instruction Register. Writes cause a RAM operation. Provides the requested PPE Instruction to execute.
32:63	ROX	ROX		OCB_OCI_GPEXIRAMEDR_EDR: Error Data Register, set on PPE interrupts caused by an error. See PPE Specification for definition.

OCB_OCI GPE External Interface DBGPRO
Addr:	0000000000066015 (SCOM) 00000000C00300A8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIDBGPRO
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR5 Debug & Runtime Profiling Read program location and status. Also used to write XSR & IAR.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.XSR_INT_SPR(0) [0]
	1:3	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_HC.LATC.L2(0:2) [000]
	4	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_HCP.LATC.L2(0) [0]
	5	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_RIP.LATC.L2(0) [0]
	6	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_SIP.LATC.L2(0) [0]
	7	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_TRAP.LATC.L2(0) [0]
	8	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_IAC.LATC.L2(0) [0]
	9:11	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(9:11) [000]
	12	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_RDAC.LATC.L2(0) [0]
	13	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_WDAC.LATC.L2(0) [0]
	14	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(13) [0]
	15	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_TRH.LATC.L2(0) [0]
	16:19	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_DECODER.FSM_STATE_LATCH.LATC.L2(0:3) [0000]
	20	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(12) [0]
	21	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_EP.LATC.L2(0) [0]
	24:25	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_ISR_24_25.LATC.L2(24:25) [00]
	28:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_ISR_28_31.LATC.L2(28:31) [0000]
	32:61	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_ISP.LT_IAR.LATC.L2(0:29) [000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		XSR_HS
1:3	RWX	RWX		XSR_HC
4	ROX	ROX		XSR_HCP
5	ROX	ROX		XSR_RIP
6	ROX	ROX		XSR_SIP
7	RWX	RWX		XSR_TRAP
8	RWX	RWX		XSR_IAC
9:11	ROX	ROX		XSR_SIB
12	RWX	RWX		XSR_RDAC
13	RWX	RWX		XSR_WDAC
14	ROX	ROX		XSR_WS
15	ROX	ROX		XSR_TRH
16:19	ROX	ROX		XSR_SMS
20	ROX	ROX		XSR_LP
21	ROX	ROX		XSR_EP
22:23	RO	RO		constant=0b00
24	ROX	ROX		XSR_PTR
25	ROX	ROX		XSR_ST
26:27	RO	RO		constant=0b00
28	ROX	ROX		XSR_MFE
29:31	ROX	ROX		XSR_MCS
32:61	RWX	RWX		OCB_OCI_GPEXIIAR_IAR: PPE Instruction Address Register See PPE Specification for bit definitions. Corresponds to XIR5 bits 32:63
62:63	RO	RO		constant=0b00

OCB_OCI GPE External Interface SIB Info
Addr:	0000000000066016 (SCOM) 00000000C00300B0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXISIB
Constant(s):
Comments:	XIR6 SIB Transaction buffer info for debug
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	32	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_R_NW_Q_INST.LATC.L2(0) [0]
	33	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_BUSY_Q_INST.LATC.L2(0) [0]
	34	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.PIB_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0]
	49:51	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_RSP_INFO_Q_0_INST.LATC.L2(0:2) [000]
	61	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_RESET_PENDING_Q_INST.LATC.L2(0) [0]
	62	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.IFETCH_PIB_PENDING_Q_INST.LATC.L2(0) [0]
	63	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.PIB_DATAOP_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXISIB_PIB_ADDR: PIB transaction buffer current or previous transaction byte address
32	ROX	ROX		OCB_OCI_GPEXISIB_PIB_R_NW: PIB transaction buffer current or previous transaction type, read if 1 and write if 0.
33	ROX	ROX		OCB_OCI_GPEXISIB_PIB_BUSY: Indicates if the transaction buffer is occupied with an ongoing transaction. Busy is cleared when the transaction is completed.
34	ROX	ROX		OCB_OCI_GPEXISIB_PIB_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the PIB interface can continue to service I-fetches (only in case of SBE instance).
35:48	RO	RO		constant=0b00000000000000
49:51	ROX	ROX		OCB_OCI_GPEXISIB_PIB_RSP_INFO: PIB transaction buffer response info. Current or previous transaction got an error on the PIB interface when non-zero.
52:60	RO	RO		constant=0b000000000
61	ROX	ROX		OCB_OCI_GPEXISIB_PIB_RESET_PENDING: Indicates if hard reset occurred during an ongoing transcation and transaction is still pending when set to 1.
62	ROX	ROX		OCB_OCI_GPEXISIB_PIB_IFETCH_PENDING: Indicates a instruction fetch is pending on the PIB interface when set to 1.
63	ROX	ROX		OCB_OCI_GPEXISIB_PIB_DATAOP_PENDING: Indicates a data transaction is pending on the PIB interface when set to 1.

OCB_OCI GPE External Interface MEM Info
Addr:	0000000000066017 (SCOM) 00000000C00300B8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIMEM
Constant(s):
Comments:	XIR7 Memory Interface transaction buffer info for debug
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.MEM_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	32	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.MEM_R_NW_Q_INST.LATC.L2(0) [0]
	33	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.MEM_BUSY_Q_INST.LATC.L2(0) [0]
	34	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.MEM_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0]
	35:42	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.MEM_BYTE_ENABLE_Q_0_INST.LATC.L2(0:7) [00000000]
	43	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.MEM_LINE_MODE_Q_INST.LATC.L2(0) [0]
	49:51	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.MEM_ERROR_Q_0_INST.LATC.L2(0:2) [000]
	62	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.IFETCH_MEM_PENDING_Q_INST.LATC.L2(0) [0]
	63	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.MEM_DATAOP_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_ADDR: MEM transaction buffer current or previous transaction byte address.
32	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_R_NW: MEM transaction buffer current or previous transaction type, read if 1 and write if 0.
33	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_BUSY: Indicates if the transaction buffer is occupied with an ongoing transaction. Busy is cleared when the transaction is completed.
34	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the memory interface can continue to service I-fetches.
35:42	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_BYTE_ENABLE: MEM transaction buffer current or previous transaction byte enables.
43	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_LINE_MODE: MEM transaction buffer current or previous transaction line mode. Indicates a 32B read request when set to 1.
44:48	RO	RO		constant=0b00000
49:51	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_ERROR: MEM transaction buffer error code. Current or previous transaction got an error on the memory interface when non-zero.
52:61	RO	RO		constant=0b0000000000
62	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IFETCH_PENDING: Indicates a instruction fetch is pending on the MEM interface when set to 1.
63	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_DATAOP_PENDING: Indicates a data transaction is pending on the MEM interface when set to 1.

OCB_OCI GPE External Interface Store Gather Buffer Info
Addr:	0000000000066018 (SCOM) 00000000C00300C0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXISGB
Constant(s):
Comments:	XIR8 Store Gather Buffer Info for debug
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.STR_GTHR_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	35	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.MEM_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0]
	36:39	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.STR_GTHR_VALID_Q_0_INST.LATC.L2(0:3) [0000]
	63	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.STR_GTHR_FLUSH_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		STORE_ADDRESS
32:34	RO	RO		constant=0b000
35	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the memory interface can continue to service I-fetches.
36:39	ROX	ROX		SGB_BYTE_VALID
40:62	RO	RO		constant=0b00000000000000000000000
63	ROX	ROX		SGB_FLUSH_PENDING

OCB_OCI GPE External Interface Icache Info
Addr:	0000000000066019 (SCOM) 00000000C00300C8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIICAC
Constant(s):
Comments:	XIR9 Instruction Cache Info for debug
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.ICACHE_COMP.ICACHE_TAG_ADDR_LATCH.LATC.L2(0:26) [000000000000000000000000000]
	32	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.ICACHE_COMP.ICACHE_ERR_LATCH.LATC.L2(0) [0]
	34	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.IFETCH_PIB_PENDING_Q_INST.LATC.L2(0) [0]
	35	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.IFETCH_MEM_PENDING_Q_INST.LATC.L2(0) [0]
	36:39	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.ICACHE_COMP.ICACHE_VALID_LATCH.LATC.L2(0:3) [0000]
	40:43	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.ICACHE_COMP.INCLUDE_ADDN_CACHE_LINE.ICACHE_LINE2_VALID_LATCH.LATC.L2(0:3) [0000]
	45	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.ICACHE_COMP.INCLUDE_ADDN_CACHE_LINE.ICACHE_LINE_PTR_LATCH.LATC.L2(0) [0]
	46	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.ICACHE_COMP.INCLUDE_ADDN_CACHE_LINE.ICACHE_LINE2_ERR_LATCH.LATC.L2(0) [0]
	47	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.INCLUDE_PREFETCH.ICACHE_PREFETCH_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0:26	ROX	ROX		ICACHE_TAG_ADDR
27:31	RO	RO		constant=0b00000
32	ROX	ROX		ICACHE_ERR
33	RO	RO		constant=0b0
34	ROX	ROX		OCB_OCI_GPEXISIB_PIB_IFETCH_PENDING: Indicates a instruction fetch is pending on the PIB interface when set to 1.
35	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IFETCH_PENDING: Indicates a instruction fetch is pending on the MEM interface when set to 1.
36:39	ROX	ROX		ICACHE_VALID
40:43	ROX	ROX		ICACHE_LINE2_VALID
44	RO	RO		constant=0b0
45	ROX	ROX		ICACHE_LINE_PTR
46	ROX	ROX		ICACHE_LINE2_ERR
47	ROX	ROX		ICACHE_PREFETCH_PENDING
48:63	RO	RO		constant=0b0000000000000000

OCB_OCI GPE External Interface Dcache Info
Addr:	000000000006601A (SCOM) 00000000C00300D0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIDCAC
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR10 Data Cache Info for debug
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_COMP.DCACHE_TAG_ADDR_LATCH.LATC.L2(0:26) [000000000000000000000000000]
	32	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_COMP.DCACHE_ERR.LATC.L2(0) [0]
	35	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_POPULATE_PENDING_Q_INST.LATC.L2(0) [0]
	36:39	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_COMP.DCACHE_VALID_LATCH.LATC.L2(0:3) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0:26	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_TAG_ADDR: 32B Data Address Tag for the current or previous cache content.
27:31	RO	RO		constant=0b00000
32	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_ERR: Indicates the current or previous content of the cache is bad due to an interface error during populate.
33:34	RO	RO		constant=0b00
35	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_POPULATE_PENDING: Data populate to D-Cache pending from MEM interface.
36:39	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_VALID: Double word valids indicating the corresponding double word in the cache is valid
40:63	RO	RO		constant=0b000000000000000000000000

OCB_OCI GPE External Interface DBGINF
Addr:	000000000006601F (SCOM) 00000000C00300F8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIDBGINF
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: Debug Information Read registers containing recent program address information. New for P10.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:29	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_SRR0.LATC.L2(0:29) [000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_LR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:29	ROX	ROX		OCB_OCI_GPEXIDBGINF_SRR0: PPE Save & Restore Register 0 Contains address of the most recent interrupt taken. Potentially useful during debug.
30:31	RO	RO		constant=0b00
32:63	ROX	ROX		OCB_OCI_GPEXIDBGINF_LR: PPE Link Register. Contains address of the instruction following the most recent Branch with Link instruction executed, to give an idea from whence the code recently came. Potentially useful during debug.

OCB_OCI GPE External Interface OCI-Word XCR
Addr:	0000000000066020 (SCOM) 00000000C0030100 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEOXIXCR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR0(0:31) External Control Register (XCR). Note this is the same as GPEXIXCR but included separately for consistency in 32-bit access OCI address mapping.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.LT_XIR_XCR_CMND.LATC.L2(0:2) [000]
Bit(s)	SCOM	OCI		Dial: Description
0	RO	RO		constant=0b0
1:3	WOX	WOX		OCB_OCI_GPEOXIXCR_XCR: PPE External Control Register See PPE Specification for bit definitions. Corresponds to XIR0 bits 1:3
4:63	RO	RO		constant=0b000000000000000000000000000000000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word XSR
Addr:	0000000000066021 (SCOM) 00000000C0030108 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIXSR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR3(0:31) External Status Register (XSR)
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.XSR_INT_SPR(0) [0]
	1:3	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_HC.LATC.L2(0:2) [000]
	4	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_HCP.LATC.L2(0) [0]
	5	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_RIP.LATC.L2(0) [0]
	6	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_SIP.LATC.L2(0) [0]
	7	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_TRAP.LATC.L2(0) [0]
	8	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_IAC.LATC.L2(0) [0]
	9:11	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(9:11) [000]
	12	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_RDAC.LATC.L2(0) [0]
	13	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_WDAC.LATC.L2(0) [0]
	14	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(13) [0]
	15	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_TRH.LATC.L2(0) [0]
	16:19	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_DECODER.FSM_STATE_LATCH.LATC.L2(0:3) [0000]
	20	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(12) [0]
	21	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_XSR_EP.LATC.L2(0) [0]
	24:25	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_ISR_24_25.LATC.L2(24:25) [00]
	28:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_ISR_28_31.LATC.L2(28:31) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		XSR_HS
1:3	ROX	ROX		XSR_HC
4	ROX	ROX		XSR_HCP
5	ROX	ROX		XSR_RIP
6	ROX	ROX		XSR_SIP
7	ROX	ROX		XSR_TRAP
8	ROX	ROX		XSR_IAC
9:11	ROX	ROX		XSR_SIB
12	ROX	ROX		XSR_RDAC
13	ROX	ROX		XSR_WDAC
14	ROX	ROX		XSR_WS
15	ROX	ROX		XSR_TRH
16:19	ROX	ROX		XSR_SMS
20	ROX	ROX		XSR_LP
21	ROX	ROX		XSR_EP
22:23	RO	RO		constant=0b00
24	ROX	ROX		XSR_PTR
25	ROX	ROX		XSR_ST
26:27	RO	RO		constant=0b00
28	ROX	ROX		XSR_MFE
29:31	ROX	ROX		XSR_MCS
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word SPRG0
Addr:	0000000000066022 (SCOM) 00000000C0030110 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXISPRG0
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR3(32:63) SPRG0 register
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_SPRG0.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RWX	RWX		SPRG0
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word EDR
Addr:	0000000000066023 (SCOM) 00000000C0030118 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIEDR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR4(32:63) Error Data Register (EDR)
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_EDR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIRAMEDR_EDR: Error Data Register, set on PPE interrupts caused by an error. See PPE Specification for definition.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word IR
Addr:	0000000000066024 (SCOM) 00000000C0030120 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIIR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR4(0:31) Instruction Register (IR)
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_ISP.LT_IR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RWX	RWX		OCB_OCI_GPEXIRAMEDR_IR: PPE Instruction Register. Writes cause a RAM operation. Provides the requested PPE Instruction to execute.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word IAR
Addr:	0000000000066025 (SCOM) 00000000C0030128 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIIAR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR5(32:63) Instruction Register (IAR)
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:29	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_ISP.LT_IAR.LATC.L2(0:29) [000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:29	RWX	RWX		OCB_OCI_GPEXIIAR_IAR: PPE Instruction Address Register See PPE Specification for bit definitions. Corresponds to XIR5 bits 32:63
30:63	RO	RO		constant=0b0000000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word SIB Info Upper
Addr:	0000000000066026 (SCOM) 00000000C0030130 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXISIBU
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR6(0:31) SIB Info Upper bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RO	RO		OCB_OCI_GPEXISIB_PIB_ADDR: PIB transaction buffer current or previous transaction byte address
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word SIB Info Lower
Addr:	0000000000066027 (SCOM) 00000000C0030138 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXISIBL
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR6(32:63) SIB Info Lower bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_R_NW_Q_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_BUSY_Q_INST.LATC.L2(0) [0]
	2	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.PIB_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0]
	17:19	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_RSP_INFO_Q_0_INST.LATC.L2(0:2) [000]
	30	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.IFETCH_PIB_PENDING_Q_INST.LATC.L2(0) [0]
	31	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.PIB_DATAOP_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		OCB_OCI_GPEXISIB_PIB_R_NW: PIB transaction buffer current or previous transaction type, read if 1 and write if 0.
1	ROX	ROX		OCB_OCI_GPEXISIB_PIB_BUSY: Indicates if the transaction buffer is occupied with an ongoing transaction. Busy is cleared when the transaction is completed.
2	ROX	ROX		OCB_OCI_GPEXISIB_PIB_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the PIB interface can continue to service I-fetches (only in case of SBE instance).
3:16	RO	RO		constant=0b00000000000000
17:19	ROX	ROX		OCB_OCI_GPEXISIB_PIB_RSP_INFO: PIB transaction buffer response info. Current or previous transaction got an error on the PIB interface when non-zero.
20:29	RO	RO		constant=0b0000000000
30	ROX	ROX		OCB_OCI_GPEXISIB_PIB_IFETCH_PENDING: Indicates a instruction fetch is pending on the PIB interface when set to 1.
31	ROX	ROX		OCB_OCI_GPEXISIB_PIB_DATAOP_PENDING: Indicates a data transaction is pending on the PIB interface when set to 1.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word MEM Info Upper
Addr:	0000000000066028 (SCOM) 00000000C0030140 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIMEMU
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR7(0:31) Memory Interface Info Upper bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.MEM_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_ADDR: MEM transaction buffer current or previous transaction byte address.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word MEM Info Lower
Addr:	0000000000066029 (SCOM) 00000000C0030148 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIMEML
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR7(32:63) Memory Interface Info Lower bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.MEM_BUSY_Q_INST.LATC.L2(0) [0]
	2	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.MEM_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0]
	3:10	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.MEM_BYTE_ENABLE_Q_0_INST.LATC.L2(0:7) [00000000]
	11	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.MEM_LINE_MODE_Q_INST.LATC.L2(0) [0]
	12	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.MIB_SCOM_REG_2_DATA(44) [0]
	17:19	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.MEM_ERROR_Q_0_INST.LATC.L2(0:2) [000]
	30	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.IFETCH_MEM_PENDING_Q_INST.LATC.L2(0) [0]
	31	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.MEM_DATAOP_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0	RO	RO		constant=0b0
1	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_BUSY: Indicates if the transaction buffer is occupied with an ongoing transaction. Busy is cleared when the transaction is completed.
2	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the memory interface can continue to service I-fetches.
3:10	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_BYTE_ENABLE: MEM transaction buffer current or previous transaction byte enables.
11	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_LINE_MODE: MEM transaction buffer current or previous transaction line mode. Indicates a 32B read request when set to 1.
12	ROX	ROX		Memory_Info_Lower_part1
13:16	RO	RO		constant=0b0000
17:19	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_ERROR: MEM transaction buffer error code. Current or previous transaction got an error on the memory interface when non-zero.
20:29	RO	RO		constant=0b0000000000
30	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IFETCH_PENDING: Indicates a instruction fetch is pending on the MEM interface when set to 1.
31	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_DATAOP_PENDING: Indicates a data transaction is pending on the MEM interface when set to 1.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word SGB Info Upper
Addr:	000000000006602A (SCOM) 00000000C0030150 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXISGBU
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR8(0:31) Store Gather Buffer Info Upper bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.STR_GTHR_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		SGB_Info_Upper
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word SGB Info Lower
Addr:	000000000006602B (SCOM) 00000000C0030158 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXISGBL
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR8(32:63) Store Gather Buffer Info Lower bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	3	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.MEM_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0]
	4:7	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.STR_GTHR_VALID_Q_0_INST.LATC.L2(0:3) [0000]
	31	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.STR_GTHR_FLUSH_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0:2	RO	RO		constant=0b000
3	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the memory interface can continue to service I-fetches.
4:7	ROX	ROX		SGB_Info_Lower_part1
8:30	RO	RO		constant=0b00000000000000000000000
31	ROX	ROX		SGB_Info_Lower_part2
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word Icache Info Upper
Addr:	000000000006602C (SCOM) 00000000C0030160 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIICACU
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR9(0:31) Instruction Cache Info Upper bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.ICACHE_COMP.ICACHE_TAG_ADDR_LATCH.LATC.L2(0:26) [000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:26	ROX	ROX		Icache_Info_Upper
27:63	RO	RO		constant=0b0000000000000000000000000000000000000

OCB_OCI GPE External Interface MEM Icache Info Lower
Addr:	000000000006602D (SCOM) 00000000C0030168 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIICACL
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR9(32:63) Instruction Cache Info Lower bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.ICACHE_COMP.ICACHE_ERR_LATCH.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.MIB_SCOM_REG_4_DATA(33) [0]
	2	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.IFETCH_PIB_PENDING_Q_INST.LATC.L2(0) [0]
	3	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.IFETCH_MEM_PENDING_Q_INST.LATC.L2(0) [0]
	4:7	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.ICACHE_COMP.ICACHE_VALID_LATCH.LATC.L2(0:3) [0000]
	8:11	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.ICACHE_COMP.INCLUDE_ADDN_CACHE_LINE.ICACHE_LINE2_VALID_LATCH.LATC.L2(0:3) [0000]
	13	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.ICACHE_COMP.INCLUDE_ADDN_CACHE_LINE.ICACHE_LINE_PTR_LATCH.LATC.L2(0) [0]
	14	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.ICACHE_COMP.INCLUDE_ADDN_CACHE_LINE.ICACHE_LINE2_ERR_LATCH.LATC.L2(0) [0]
	15	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.INCLUDE_PREFETCH.ICACHE_PREFETCH_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0:1	ROX	ROX		Icache_Info_Lower_part1
2	ROX	ROX		OCB_OCI_GPEXISIB_PIB_IFETCH_PENDING: Indicates a instruction fetch is pending on the PIB interface when set to 1.
3	ROX	ROX		OCB_OCI_GPEXIMEM_MEM_IFETCH_PENDING: Indicates a instruction fetch is pending on the MEM interface when set to 1.
4:11	ROX	ROX		Icache_Info_Lower_part1
12	RO	RO		constant=0b0
13:15	ROX	ROX		Icache_Info_Lower_part2
16:63	RO	RO		constant=0b000000000000000000000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word Dcache Info Upper
Addr:	000000000006602E (SCOM) 00000000C0030170 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIDCACU
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR10(0:31) Data Cache Info Upper bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_COMP.DCACHE_TAG_ADDR_LATCH.LATC.L2(0:26) [000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:26	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_TAG_ADDR: 32B Data Address Tag for the current or previous cache content.
27:31	RO	RO		constant=0b00000

OCB_OCI GPE External Interface MEM Dcache Info Lower
Addr:	000000000006602F (SCOM) 00000000C0030178 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIDCACL
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: XIR10(32:63) Data Cache Info Lower bits
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_COMP.DCACHE_ERR.LATC.L2(0) [0]
	3	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_POPULATE_PENDING_Q_INST.LATC.L2(0) [0]
	4:7	TP.TPCHIP.OCC.OCI.GPE3.GPE.MIB.INCLUDE_DCACHE_INST.DCACHE_COMP.DCACHE_VALID_LATCH.LATC.L2(0:3) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_ERR: Indicates the current or previous content of the cache is bad due to an interface error during populate.
1:2	RO	RO		constant=0b00
3	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_POPULATE_PENDING: Data populate to D-Cache pending from MEM interface.
4:7	ROX	ROX		OCB_OCI_GPEXIDCAC_DCACHE_VALID: Double word valids indicating the corresponding double word in the cache is valid
8:31	RO	RO		constant=0b000000000000000000000000

OCB_OCI GPE External Interface OCI-Word SRR0
Addr:	0000000000066030 (SCOM) 00000000C0030180 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXISRR0
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR15(0:31) SRR0
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:29	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_SRR0.LATC.L2(0:29) [000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:29	ROX	ROX		OCB_OCI_GPEXIDBGINF_SRR0: PPE Save & Restore Register 0 Contains address of the most recent interrupt taken. Potentially useful during debug.
30:63	RO	RO		constant=0b0000000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word LR
Addr:	0000000000066031 (SCOM) 00000000C0030188 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXILR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR15(32:63) Link Register (LR)
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_LR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIDBGINF_LR: PPE Link Register. Contains address of the instruction following the most recent Branch with Link instruction executed, to give an idea from whence the code recently came. Potentially useful during debug.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word CTR
Addr:	0000000000066032 (SCOM) 00000000C0030190 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXICTR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: XIR0(32:63) CTR
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_SPR.LT_CTR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXICTR_CTR: Count Register. Added for P10. Potentially useful for Debug since can indicate loop iteration or a recent branch target address, depending on compiler optimization decisions. Corresponds to XIR0 bits 32:63
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR0
Addr:	0000000000066040 (SCOM) 00000000C0030200 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR0
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR0
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR0.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR0_GPR0: General Purpose Register 0
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR1
Addr:	0000000000066041 (SCOM) 00000000C0030208 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR1
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR1
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR1.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR0_GPR1: General Purpose Register 1
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR2
Addr:	0000000000066042 (SCOM) 00000000C0030210 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR2
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR2
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR2.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR2_GPR2: General Purpose Register 2
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR3
Addr:	0000000000066043 (SCOM) 00000000C0030218 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR3
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR3
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR3.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR2_GPR3: General Purpose Register 3
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR4
Addr:	0000000000066044 (SCOM) 00000000C0030220 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR4
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR4
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR4.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR4_GPR4: General Purpose Register 4
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR5
Addr:	0000000000066045 (SCOM) 00000000C0030228 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR5
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR5
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR5.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR4_GPR5: General Purpose Register 5
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR6
Addr:	0000000000066046 (SCOM) 00000000C0030230 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR6
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR6
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR6.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR6_GPR6: General Purpose Register 6
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR7
Addr:	0000000000066047 (SCOM) 00000000C0030238 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR7
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR7
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR7.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR6_GPR7: General Purpose Register 7
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR8
Addr:	0000000000066048 (SCOM) 00000000C0030240 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR8
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR8
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR8.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR8_GPR8: General Purpose Register 8
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR9
Addr:	0000000000066049 (SCOM) 00000000C0030248 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR9
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR9
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR9.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR8_GPR9: General Purpose Register 9
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR10
Addr:	000000000006604A (SCOM) 00000000C0030250 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR10
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR10
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR10.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDRX_GPR10: General Purpose Register 10
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR13
Addr:	000000000006604B (SCOM) 00000000C0030258 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR13
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR13
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR13.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDRX_GPR13_11: DD1: General Purpose Register 13 DD2: General Purpose Register 11
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR28
Addr:	000000000006604C (SCOM) 00000000C0030260 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR28
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR28
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR28.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR28_GPR28: General Purpose Register 28
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR29
Addr:	000000000006604D (SCOM) 00000000C0030268 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR29
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR29
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR29.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR28_GPR29: General Purpose Register 29
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR30
Addr:	000000000006604E (SCOM) 00000000C0030270 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR30
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR30
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR30.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR30_GPR30: General Purpose Register 30
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface OCI-Word GPR31
Addr:	000000000006604F (SCOM) 00000000C0030278 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR31
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR31
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR31.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RO	RO		OCB_OCI_GPEXIVDR30_GPR31: General Purpose Register 31
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE External Interface VDR0
Addr:	0000000000066080 (SCOM) 00000000C0030400 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIVDR0
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR0 & GPR1
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR0.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR1.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR0_GPR0: General Purpose Register 0
32:63	ROX	ROX		OCB_OCI_GPEXIVDR0_GPR1: General Purpose Register 1

OCB_OCI GPE External Interface VDR2
Addr:	0000000000066081 (SCOM) 00000000C0030408 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIVDR2
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR2 & GPR3
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR2.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR3.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR2_GPR2: General Purpose Register 2
32:63	ROX	ROX		OCB_OCI_GPEXIVDR2_GPR3: General Purpose Register 3

OCB_OCI GPE External Interface VDR4
Addr:	0000000000066082 (SCOM) 00000000C0030410 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIVDR4
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR4 & GPR5
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR4.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR5.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR4_GPR4: General Purpose Register 4
32:63	ROX	ROX		OCB_OCI_GPEXIVDR4_GPR5: General Purpose Register 5

OCB_OCI GPE External Interface VDR6
Addr:	0000000000066083 (SCOM) 00000000C0030418 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIVDR6
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR6 & GPR7
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR6.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR7.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR6_GPR6: General Purpose Register 6
32:63	ROX	ROX		OCB_OCI_GPEXIVDR6_GPR7: General Purpose Register 7

OCB_OCI GPE External Interface VDR8
Addr:	0000000000066084 (SCOM) 00000000C0030420 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIVDR8
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR8 & GPR9
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR8.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR9.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR8_GPR8: General Purpose Register 8
32:63	ROX	ROX		OCB_OCI_GPEXIVDR8_GPR9: General Purpose Register 9

OCB_OCI GPE External Interface VDRX
Addr:	0000000000066085 (SCOM) 00000000C0030428 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIVDRX
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: DD1: Virtual Doubleword X (GPR10 & GPR13) DD2: Virtual Doubleword 10 (GPR10 & GPR11) Note: unlike other 64-bit GPR XIRs, this is not a true VDR.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR10.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR13.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDRX_GPR10: General Purpose Register 10
32:63	ROX	ROX		OCB_OCI_GPEXIVDRX_GPR13_11: DD1: General Purpose Register 13 DD2: General Purpose Register 11

OCB_OCI GPE External Interface VDR28
Addr:	0000000000066086 (SCOM) 00000000C0030430 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIVDR28
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR28 & GPR29
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR28.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR29.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR28_GPR28: General Purpose Register 28
32:63	ROX	ROX		OCB_OCI_GPEXIVDR28_GPR29: General Purpose Register 29

OCB_OCI GPE External Interface VDR30
Addr:	0000000000066087 (SCOM) 00000000C0030438 (OCI)
Name:	TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIVDR30
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: GPR30 & GPR31
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR30.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.GPE3.GPE.PPE.I_C_PPE42_GPR.LT_GPR31.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_GPEXIVDR30_GPR30: General Purpose Register 30
32:63	ROX	ROX		OCB_OCI_GPEXIVDR30_GPR31: General Purpose Register 31

PBA Mode and Control Register
Addr:	0000000000068000 (PIB) 00000000C0040000 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBAMODE
Constant(s):
Comments:	This register controls the modes that affect all the PBA, regardless of the master_id driving the transactions. The mode bits that control the PBA OCI Slave may not be changed unless the SLVRST[Busy SLV Status] = 0000. Mode bits that control the PBA OCI Master may not be changed unless the Block Copy Engines are Not running.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPBR.PBA.PBAO.OCIREG.PBA_MODE_Q_0_INST.LATC.L2(0:15) [0000000000000000]
	16:17	TP.TPBR.PBA.PBAO.OCIREG.PBAMODE_SCANONLY_Q_16_INST.LATC.L2(16:17) [00]
	18:63	TP.TPBR.PBA.PBAO.OCIREG.PBA_MODE_Q_0_INST.LATC.L2(18:63) [0000000000000000000000000000000000000000000000]
Bit(s)	PIB	OCI		Dial: Description
0:3	RW	RW		PBAMODE_RESERVED_0_3: These bits are spare
4	RW	RW		PBAMODE_DIS_REARB: Disable OCI Rearbitration This debug bit controls whether the PBA OCI slave supports delayed read mode. If this bit is set, the PBA will still assert pba_oci_s_rearbitrate for a write request if a write buffer is unavailable. OFF - Assert pba_oci_s_rearbitrate when requested read data is not valid in Buffer. This will free the bus for other operations while the data is fetched from system memory and is the expected default mode. ON - Assert pba_oci_s_wait when requested read data is not valid in the buffer. The arbiter will continue to assert oci_pba_s_pavalid and no other operations can proceed until the PBA responds. The PBA will assert pba_oci_s_addrAck for one cycle and deassert pba_oci_s_wait when the data has been fetched into the buffer. NOTE, IF THIS MODE IS ENABLED, PBASLVCTLn[Read Prefetch Control] must be set to No Prefetch. Additionally, Secondary read operations (SAVALID) are ignored so Pipeline support MUST BE DISABLED in the OCI Arbiter. Note: this mode has a known errata and should not be enabled.
5	RW	RW		PBAMODE_DIS_MSTID_MATCH_PREF_INV: Disable Master ID Match for Prefetch Invalidate Controls if a buffer can be invalidated when it contains valid data prefetched by another master. This bit MUST be set if prefetching is enabled for buffers shared with multiple masters. OFF - (default) Only the original Master can cause its prefetch to be invalidated when a buffer is needed. ON - Any master can cause a prefetched buffer to be invalidated when a buffer is needed.
6	RW	RW		PBAMODE_DIS_SLAVE_RDPIPE: Disable PBA Slave Read pipeline support This debug bit controls whether pipelined read requests are supported by the PBA OCI Slave for operations that target the powerbus. OFF - Monitor oci_pba_s_savlid for secondary read requests (2-level Pipelined support) ON - Do not respond (no AddrAck or ReArbitrate) for oci_pba_s_savalid for read requests. Requests will be qualified with oci_pba_s_pavalid only. (no pipeline support)
7	RW	RW		PBAMODE_DIS_SLAVE_WRPIPE: Disable PBA Slave Write pipeline support This debug bit controlls whether pipelined write requests are supported by the PBA OCI Slave for operations that target the powerbus. OFF - Monitor oci_pba_s_savlid for secondary write requests (2-level Pipelined support) ON - Do not respond (no AddrAck or ReArbitrate) for oci_pba_s_savalid for write requests. Requests will be qualified with oci_pba_s_pavalid only. (no pipeline support)
8	RW	RW		PBAMODE_EN_MARKER_ACK: Enable PBA Slave Acknowledge of OCC HTM Marker Operations This bit controls whether the PBA OCI Slave will AACK and then WRDACK the OCI transactions that target the OCC HTM Marker space. The PBAMODE [ OCI Marker Space] bits must be intialized before setting this bit. Read operations to the Marker space are not recommended.. OFF - Ignore OCC HTM Marker writes <ON - Acknowledge OCC HTM Marker writes.
9	RW	RW		PBAMODE_RESERVED_9: Spare
10	RW	RW		PBAMODE_EN_SECOND_WRBUF: Enable Second Write Buffer This bit controls whether the allocated write buffers for the PBA OCI Slave are treated as a pair or if just one is used. ON - Write buffers are used as a ping/pong pair. One buffer can be writing the forwarded data to the PowerBus while the other is receiving more data from the OCI OFF - Only one write buffer is used. (Default Mode and expected mode to use during IPL.)
11	RW	RW		PBAMODE_DIS_REREQUEST_TO: Disable ReRequest Timeout This debug bit disables the time that controls how long a the Read machine will wait for a re-presentation of the read request after the read from the powerbus has completed. This must not be set if the 405 is doing reads from the PBA for its ICACHE since it WILL abort requests. OFF - The length of the ReRequest timeout is controlled in PBACFG[ocislv_rereq_hang_div]. (expected default) ON - ReRequest Timeout is disabled.
12:13	RW	RW		PBAMODE_RESERVED_12_13: Reserved Was P9 inject_type. Functionality moved to PBAFCFG
14:15	RW	RW		PBAMODE_RESERVED_14_15: Reserved Was P9 inject_mode. Functionality moved to PBAFCFG
16:17	RO	RO		PBAMODE_PBA_REGION: PBA Region These bits define the PBA region decoded by the PBA OCI Slave in the upper two bits of the OCI Address and are SCAN ONLY. They are also visible through this register. They are initialized to 00.
18:20	RW	RW		PBAMODE_OCI_MARKER_SPACE: OCI Marker Space These bits define the Register region used for OCC Markers and correspond to address(13:15) when address(0:2) = 110. The PBA OCI Slave will always acknowledge writes to this register space and acknowledge and drop the data on the floor ifPBAMODE[Enable PBA Acknowledge of OCC HTM Marker Operations] = 1. This must not conflict with the defined register space of other OCI Slaves including PBAs own register space. Only 111 will avoid conflict.
21:22	RW	RW		PBAMODE_BCDE_OCITRANS: BCDE OCI Transaction Control These bits define how efficiently the data is written to the SRAM by the Block Copy Download Engine. These bits should be changed only when the BCDE is Not Running. 00 -- Data is written to the SRAM in 32-Byte transactions. (4 beats) 01 - Data is written to the SRAM in 64-byte transactions (8 beats) 10 - Data is written to the SRAM in 8-Byte transactions (1 beat) 11 - Not Defined
23:24	RW	RW		PBAMODE_BCUE_OCITRANS: BCUE OCI Transaction Control These bits define how efficiently the data is read from the SRAM by the Block Copy Upload Engine. These bits should be changed only when the BCUE is Not Running. 00 -- Data is read from the SRAM in 32-Byte transactions. (4 beats) 01 - Data is read from the SRAM in 64-byte transactions (8 beats) 10 - Data is read from the SRAM in 8-Byte transactions (1 beat) 11 - Not Defined
25	RW	RW		PBAMODE_DIS_MASTER_RD_PIPE: Disable PBA Master Read pipeline support This bit controls whether pipelined Read requests are supported by the PBA Block Copy Upload Engine. OFF - Assert pba_oci_m_request for a pending read request immediately after oci_pba_m_addrAck is received to allow for read pipelining on the OCI. (Expected default) ON - Do not assert pba_oci_m_request for a pending read request until all expected oci_pba_m_rddack have been received for the previous request.
26	RW	RW		PBAMODE_DIS_MASTER_WR_PIPE: Disable PBA Master Write pipeline support This bit controls whether pipelined Write requests are supported by the PBA Block Copy Download Engine and should be changed only when the BCDE is Stopped OFF - Assert pba_oci_m_request for a pending write request immediately after oci_pba_m_addrAck is received to allow for write pipelining on the OCI. ON - Do not assert pba_oci_m_request for a pending write request until all expected oci_pba_m_wrdack have been received for the previous request.
27	RW	RW		PBAMODE_EN_SLV_FAIRNESS: Enable PBA Slave Fairness support This bit controls whether the fairness protocol is engaged for the PBA Slave. It should be set if multiple OCI Masters are often sharing the same read and write buffers in the PBA. Mask bits can be configured in the PBACFG [ocislv_fairness_mask] to increase the probability that the PBA will engage the fairness. OFF - Do not engage Fairness protocol ON - Engage the PBA Slave Fairness protocol based on the probability of the Fairness Mask.
28	RW	RW		PBAMODE_EN_EVENT_COUNT: Enable Event count This bit enables the 4 PBAOCRn counters to be used as Event counters.
29	RW	RW		PBAMODE_RESERVED_29: Reserved (P9 was pb_noci_event_sel)
30:31	RW	RW		PBAMODE_SLV_EVENT_MUX: OCI Event Select These bits control which PBA Slave Buffer OCI events are muxed to the event counters. 00 - Buffer A ( Busy Rearb, Accept Rearb, Clr Prefetch, Drop Prefetch) 01 - Buffer B 10 - Buffer C 11 - not defined.
32	RW	RW		PBAMODE_ENABLE_DEBUG_BUS: Enable PBA Debug Outputs This bit enables the clock gating and allows PBA to drive the Debug Outputs to the trace array.
33	RW	RW		PBAMODE_DEBUG_PB_NOT_OCI: Debug Powerbus or OCI Logic This bit controls the muxing of the OCI logic or PowerBus logic to the Debug Outputs. OFF - OCI logic debug ON - PowerBus logic debug
34:38	RW	RW		PBAMODE_DEBUG_OCI_MODE: Debug Mux selects for OCI Logic These bit controll the muxing of trace information for the OCI logic debug. See the tp/misc/pba.template for detailed info.
39	RW	RW		PBAMODE_RESERVED_39: Spare
40:44	RW	RW		PBAMODE_OCISLV_FAIRNESS_MASK: PBA Slave Fairness Mask Mask to control Probability that the PBA Slave randomly ReArbs a Write or takes no action on a Read that it could otherwise handle. All 1s provides a 2:1 probability, All 0s provides 64:1 probability.
45:49	RW	RW		PBAMODE_OCISLV_REREQ_HANG_DIV: OCI ReRequest Hang Timeout Divider. Initializes when clocks are started. Divides a pulse that asserts every 64 cycles. Used to control the Rerequest Timeout for read requests that have been aborted without PBA seeing the abort.
50:63	RW	RW		PBAMODE_RESERVED_50_63: Spare

PBA Slave Reset Register
Addr:	0000000000068001 (PIB) 00000000C0040008 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBASLVRST
Constant(s):
Comments:	This register allows the Read and write buffers associated with the PBA slave logic to be reset. This is necessary to recover when an error has occured that hangs the buffers or if the PBASLVCTL address bits need to be updated.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPBR.PBA.PBAO.OCIREG.PBA_SLVRST_CTL_Q_0_INST.LATC.L2(0:2) [000]
	4:7	TP.TPBR.PBA.PBAO.OCIREG.PBA_SLVRST_Q_0_INST.LATC.L2(0:3) [0000]
	8:11	TP.TPBR.PBA.PBAO.OCIREG.BUSY_SLV_STATUS_Q_0_INST.LATC.L2(0:3) [0000]
	12:13	TP.TPBR.PBA.PBAO.OCIREG.SCOPE_ATTN_BAR_Q_0_INST.LATC.L2(0:1) [00]
Bit(s)	PIB	OCI		Dial: Description
0:2	WOX	WOX		PBASLVRST_SET: SLV Reset These bits are written to force the allocated buffers currently being used by the selected PBASLVCTL to be reset to the Empty State. Read buffers are invalidated and Write Buffers are flushed to memory. If the buffer is hung in an error state it is forced to the Empty state. When all allocated buffers are reset, the Busy SLV Status bits for that PBASLVCTL are cleared. (should be WO_2P) Note: If write gathering is enabled and the slave is reset while OCI data is still pending, the slave reset will be ignored. Reset is intended to be used when switching OCI masters, or to recover from a hung state. Dial enums: PBASLVCTL0=>0b100 PBASLVCTL1=>0b101 PBASLVCTL2=>0b110 PBASLVCTL3=>0b111
3	RO	RO		constant=0b0 Dial enums: PBASLVCTL0=>0b100 PBASLVCTL1=>0b101 PBASLVCTL2=>0b110 PBASLVCTL3=>0b111
4:7	ROX	ROX		PBASLVRST_IN_PROG: SLV Reset in Progress These bits indicate which PBASLVCTL s have a reset in progress. The bit is set when the SLV Reset for the PBASLVCTL is written to 1. It is reset when the Busy SLV Status goes to zero. 1xxx - PBASLVCTL0 has reset in progress x1xx - PBASLVCTL1 has reset in progress xx1x - PBASLVCTL2 has reset in progress xxx1 - PBASLVCTL3 has reset in progress
8:11	ROX	ROX		PBASLVRST_BUSY_STATUS: Busy SLV Status These bits indicate the Not Empty buffer state of all allocated buffers to a PBASLVCTL. When a bit is set, it indicates that a Read buffer allocated to a PBASLVCTL contains valid data or may be in the middle of a prefetch. A Write buffer allocated to a PBASLVCTL may be in the middle of a write to the PowerBus. 1xxx - Buffers allocated to PBASLVCTL0 are Busy x1xx - Buffers allocated to PBASLVCTL1 are Busy xx1x - Buffers allocated to PBASLVCTL2 are Busy xxx1 - Buffers allocated to PBASLVCTL3 are Busy 0000 - All Allocated Buffers are in Empty State
12:13	ROX	ROX		PBASLVRST_SCOPE_ATTN_BAR: Scope Attn Bar The BAR used to select the initial scope of the operation when the powerbus signaled a scope increase. This register is updated whenever the powerbus signals a cresp=rty_inc.
14:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000

PBA Slave Control 0 Register
Addr:	0000000000068004 (PIB) 00000000C0040020 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBASLVCTL0
Constant(s):
Comments:	This register must be initialized by the OCC Firmware to allow PBA to forward requests to the PowerBus.. PBASLVCTL0, 1, 2 initialize to zero. PBASLVCTL3 initializes to allow access by FSI through OCB with LCO_M write ttype for a fast IPL. (0xD720_5400_0000_0000)
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0:50	TP.TPBR.PBA.PBAO.OCIREG.PBA_SLVCTL0_Q_0_INST.LATC.L2(0:50) [000000000000000000000000000000000000000000000000000]
Bit(s)	PIB	OCI		Dial: Description
0	RW	RW		PBASLVCTL0_ENABLE: OCI_Base_Address_Range_Enabled This bit must be set by software for the PBA to respond to an OCI request that targets Power Bus and matches the OCI MasterID Match Value. OFF - Ignore OCI operations ON - Accept OCI operations
1:3	RW	RW		PBASLVCTL0_MID_MATCH_VALUE: OCI Masterid Match Value These bits must be initialzed by software to indicate the OCI master id that will use this set of Base Address Registers when the OCI request targets the PowerBus region. Only ONE PBASLVCTLn may match any Master ID.
4	RW	RW		PBASLVCTL0_RESERVED_4: Spare
5:7	RW	RW		PBASLVCTL0_MID_CARE_MASK: OCI Masterid Care Mask These bits must be intialized by software to indicate which OCI Masterid bits must match the OCI Master ID Match Value. If only one OCI Master is using this PBASLVCTL , these bits must be set to 111.
8:10	RW	RW		PBASLVCTL0_WRITE_TTYPE: Write Ttype Forwarded write requests that target this PBASLVCTL register will use the specified write ttype on the PowerBus. DMA will use a DMA_PR_W to write 1 to 127 bytes or a CL_DMA_W_I to write the gathered 128 bytes. LCO_M is a Lateral Castout M that is used only at IPL time. Cache_Inj is a Cache Line DMA Cache Inject ttype that is used only at IPL time to write an L3 line that has already been initialized. CI_PR_WR is a Cache Inhibited Partial Write ttype implemented to write to Centaur register space. It will forward the write exactly as it was asked for in the OCI operation. Atomic is an Atomic RMW operation that should only be done as an 8-byte write. Dial enums: DMA=>0b000 LCO_M=>0b001 ATOMIC=>0b010 CACHE_INJ=>0b011 CI_PR_W=>0b100
11:14	RW	RW		PBASLVCTL0_RESERVED_11_14: Spare
15	RW	RW		PBASLVCTL0_READ_TTYPE: Read Ttype Forwarded read requesta that target this PBASLVCTL register will use the specified ttype on the PowerBus. CL_RD_NC is a Cache Line DMA Read with no intent to cache. It will always read 128 bytes from system memory. CI_PR_RD is a Cache Inhibited Partial Read. It will forward the read exactly as it was asked for in the OCI operation. This mode is required when accessing Centaur register space. Dial enums: CL_RD_NC=>0b0 CI_PR_RD=>0b1
16:17	RW	RW		PBASLVCTL0_READ_PREFETCH_CTL: Read Prefech Control No Prefetch Ahead - Fetch only current requested 128-byte cacheline. This is also the default. Auto Late Prefetch Ahead - Prefetch next cacheline after last read data returned for current cacheline. This mode may also be used if two masters need to share a buffer pair but the PBAMODE [dis_mstid_match_pref_inv] mode bit must be set to avoid a hang condition. Dial enums: DEFAULT=>0b00 NO_PREFETCH=>0b01 AUTO_LATE_PREFETCH=>0b10
18	RW	RW		PBASLVCTL0_BUF_INVALIDATE_CTL: Read Buffer Invalidate Control 0 : Do not invalidate read buffer data automatically <1 : Invalidate read buffer after 1st read data returned. This Mode is NOT VALID with any prefetch modes enabled. This mode must be enabled if Read Ttype = Cache Inhibited Partial Read.
19	RW	RW		PBASLVCTL0_BUF_ALLOC_W: Write Buffer Pair Allocation The Master ID that uses this PBASLVCTL may use only the allocated buffers. Buffer allocation is for a buffer pair. Multiple buffer pairs may be assigned. This bit must be set for the PBA to respond to Write operations through this PBASLVCTL register.
20	RW	RW		PBASLVCTL0_BUF_ALLOC_A: Read Buffer Pair A Allocation The Master ID that uses this PBASLVCTL may use only the allocated buffers. Buffer allocation is for a buffer pair. Multiple buffer pairs may be assigned. At least one read buffer must be allocated for teh PBA to respond to Read operations through this PBASLVCTL register.
21	RW	RW		PBASLVCTL0_BUF_ALLOC_B: Read Buffer Pair B Allocation The Master ID that uses this PBASLVCTL may use only the allocated buffers. Buffer allocation is for a buffer pair. Multiple buffer pairs may be assigned.
22	RW	RW		PBASLVCTL0_BUF_ALLOC_C: Read Buffer Pair C Allocation The Master ID that uses this PBASLVCTL may use only the allocated buffers. Buffer allocation is for a buffer pair. Multiple buffer pairs may be assigned.
23	RW	RW		PBASLVCTL0_RESERVED_23: Spare buffer allocation bit.
24	RW	RW		PBASLVCTL0_DIS_WRITE_GATHER: Disable Write Gather This bit disables gathering of write data in the buffer. This mode bit used only when PBASLVCTL[Write ttype] = DMA_PR_W. Otherwise it is ignored. OFF - Gather writes into the write buffer ON - Do not gather. Writes forwarded to Powerbus as written from OCI.
25:27	RW	RW		PBASLVCTL0_WR_GATHER_TIMEOUT: Write Gather Timeout Control These bits control how long the PBA should wait to gather write operations. This mode bit used only when PBASLVCTL[Write ttype] = DMA_PR_W. Otherwise it is ignored. When a write buffer is active, the PBA counts Write Gather Timeout Pulses that arrive every 64 OCI cycles, and uses the value in this register to divide the write gather timeout pulse frequency, and generate an internal hang pulse. If two hang pulses occur without a new write to the buffer, a write gather timeout occurs and the buffer is flushed to the Powerbus. Write gather timeouts must NOT be disabled if multiple masters are enabled to write through the PBA. 000 - Disable Write Gather Timeout. Write will be flushed under the following conditions: Need another write by the same master to a non-sequential address, Gathered data to cacheline boundary, Read by a master that uses this same SLVCTL register to the same address, or a PBASLVRST[SLV Reset(n)] for this PBASLVCTL. 100 - 2 Write Gather Pulses (64 to 128 OCI cycles, 64 cycles with no write) 101 - 4 Write Gather Pulses (192 to 256 OCI cycles, 128 cycles with no write) 110 - 8 Write Gather Pulses (448 to 512 OCI cycles, 256 cycles with no write) 111 - 16 Write Gather Pulses (960 to 1024 OCI cycles, 512 cycles with no write)
28:35	RW	RW		PBASLVCTL0_WRITE_TSIZE: Write Tsize These bits are valid when the PBASLVCTL[Write Ttype] = LCO_M or ATOMIC. They are used to specify the tsize bits for the powerbus operation. When PBASLVCTL[Write Ttype] = LCO_M, these bits provide a secondary encoding for the write defined as 00cc_ccc0. c_cccc is the chiplet ID of the L3 cache. When PBASLVCTL[Write Ttype] = Atomic RNW no fetch, these bits provide a secondary encoding for the atomic operation defined as fff00010. The fff specify the function to be applied to the operand. Only 8-byte operations are supported in Big Endian. Supported fff values: 000 - armw_add 001 - armw_and 010 - armw_or 011 - armw_xor
36:49	RW	RW		PBASLVCTL0_EXTADDR: PB Extaddr This bits are the PowerBus address bits (23:36) that may be used when forwarding the operation if the selected PBABARMSK bits are one.
50	RW	RW		PBASLVCTL0_RESERVED_50: Spare
51:63	RO	RO		constant=0b0000000000000

PBA Slave Control 1 Register
Addr:	0000000000068005 (PIB) 00000000C0040028 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBASLVCTL1
Constant(s):
Comments:	This register must be initialized by the OCC Firmware to allow PBA to forward requests to the PowerBus.. PBASLVCTL0, 1, 2 initialize to zero. PBASLVCTL3 initializes to allow access by FSI through OCB with LCO_M write ttype for a fast IPL. (0xD720_5400_0000_0000)
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0:50	TP.TPBR.PBA.PBAO.OCIREG.PBA_SLVCTL1_Q_0_INST.LATC.L2(0:50) [000000000000000000000000000000000000000000000000000]
Bit(s)	PIB	OCI		Dial: Description
0	RW	RW		PBASLVCTL1_ENABLE: OCI_Base_Address_Range_Enabled This bit must be set by software for the PBA to respond to an OCI request that targets Power Bus and matches the OCI MasterID Match Value. OFF - Ignore OCI operations ON - Accept OCI operations
1:3	RW	RW		PBASLVCTL1_MID_MATCH_VALUE: OCI Masterid Match Value These bits must be initialzed by software to indicate the OCI master id that will use this set of Base Address Registers when the OCI request targets the PowerBus region. Only ONE PBASLVCTLn may match any Master ID.
4	RW	RW		PBASLVCTL1_RESERVED_4: Spare
5:7	RW	RW		PBASLVCTL1_MID_CARE_MASK: OCI Masterid Care Mask These bits must be intialized by software to indicate which OCI Masterid bits must match the OCI Master ID Match Value. If only one OCI Master is using this PBASLVCTL , these bits must be set to 111.
8:10	RW	RW		PBASLVCTL1_WRITE_TTYPE: Write Ttype Forwarded write requests that target this PBASLVCTL register will use the specified write ttype on the PowerBus. DMA will use a DMA_PR_W to write 1 to 127 bytes or a CL_DMA_W_I to write the gathered 128 bytes. LCO_M is a Lateral Castout M that is used only at IPL time. Cache_Inj is a Cache Line DMA Cache Inject ttype that is used only at IPL time to write an L3 line that has already been initialized. CI_PR_WR is a Cache Inhibited Partial Write ttype implemented to write to Centaur register space. It will forward the write exactly as it was asked for in the OCI operation. Atomic is an Atomic RMW operation that should only be done as an 8-byte write. Dial enums: DMA=>0b000 LCO_M=>0b001 ATOMIC=>0b010 CACHE_INJ=>0b011 CI_PR_W=>0b100
11:14	RW	RW		PBASLVCTL1_RESERVED_11_14: Spare
15	RW	RW		PBASLVCTL1_READ_TTYPE: Read Ttype Forwarded read requesta that target this PBASLVCTL register will use the specified ttype on the PowerBus. CL_RD_NC is a Cache Line DMA Read with no intent to cache. It will always read 128 bytes from system memory. CI_PR_RD is a Cache Inhibited Partial Read. It will forward the read exactly as it was asked for in the OCI operation. This mode is required when accessing Centaur register space. Dial enums: CL_RD_NC=>0b0 CI_PR_RD=>0b1
16:17	RW	RW		PBASLVCTL1_READ_PREFETCH_CTL: Read Prefech Control No Prefetch Ahead - Fetch only current requested 128-byte cacheline. This is also the default. Auto Late Prefetch Ahead - Prefetch next cacheline after last read data returned for current cacheline. This mode may also be used if two masters need to share a buffer pair but the PBAMODE [dis_mstid_match_pref_inv] mode bit must be set to avoid a hang condition. Dial enums: DEFAULT=>0b00 NO_PREFETCH=>0b01 AUTO_LATE_PREFETCH=>0b10
18	RW	RW		PBASLVCTL1_BUF_INVALIDATE_CTL: Read Buffer Invalidate Control 0 : Do not invalidate read buffer data automatically <1 : Invalidate read buffer after 1st read data returned. This Mode is NOT VALID with any prefetch modes enabled. This mode must be enabled if Read Ttype = Cache Inhibited Partial Read.
19	RW	RW		PBASLVCTL1_BUF_ALLOC_W: Write Buffer Pair Allocation The Master ID that uses this PBASLVCTL may use only the allocated buffers. Buffer allocation is for a buffer pair. Multiple buffer pairs may be assigned. This bit must be set for the PBA to respond to Write operations through this PBASLVCTL register.
20	RW	RW		PBASLVCTL1_BUF_ALLOC_A: Read Buffer Pair A Allocation The Master ID that uses this PBASLVCTL may use only the allocated buffers. Buffer allocation is for a buffer pair. Multiple buffer pairs may be assigned. At least one read buffer must be allocated for teh PBA to respond to Read operations through this PBASLVCTL register.
21	RW	RW		PBASLVCTL1_BUF_ALLOC_B: Read Buffer Pair B Allocation The Master ID that uses this PBASLVCTL may use only the allocated buffers. Buffer allocation is for a buffer pair. Multiple buffer pairs may be assigned.
22	RW	RW		PBASLVCTL1_BUF_ALLOC_C: Read Buffer Pair C Allocation The Master ID that uses this PBASLVCTL may use only the allocated buffers. Buffer allocation is for a buffer pair. Multiple buffer pairs may be assigned.
23	RW	RW		PBASLVCTL1_RESERVED_23: Spare buffer allocation bit.
24	RW	RW		PBASLVCTL1_DIS_WRITE_GATHER: Disable Write Gather This bit disables gathering of write data in the buffer. This mode bit used only when PBASLVCTL[Write ttype] = DMA_PR_W. Otherwise it is ignored. OFF - Gather writes into the write buffer ON - Do not gather. Writes forwarded to Powerbus as written from OCI.
25:27	RW	RW		PBASLVCTL1_WR_GATHER_TIMEOUT: Write Gather Timeout Control These bits control how long the PBA should wait to gather write operations. This mode bit used only when PBASLVCTL[Write ttype] = DMA_PR_W. Otherwise it is ignored. When a write buffer is active, the PBA counts Write Gather Timeout Pulses that arrive every 64 OCI cycles, and uses the value in this register to divide the write gather timeout pulse frequency, and generate an internal hang pulse. If two hang pulses occur without a new write to the buffer, a write gather timeout occurs and the buffer is flushed to the Powerbus. Write gather timeouts must NOT be disabled if multiple masters are enabled to write through the PBA. 000 - Disable Write Gather Timeout. Write will be flushed under the following conditions: Need another write by the same master to a non-sequential address, Gathered data to cacheline boundary, Read by a master that uses this same SLVCTL register to the same address, or a PBASLVRST[SLV Reset(n)] for this PBASLVCTL. 100 - 2 Write Gather Pulses (64 to 128 OCI cycles, 64 cycles with no write) 101 - 4 Write Gather Pulses (192 to 256 OCI cycles, 128 cycles with no write) 110 - 8 Write Gather Pulses (448 to 512 OCI cycles, 256 cycles with no write) 111 - 16 Write Gather Pulses (960 to 1024 OCI cycles, 512 cycles with no write)
28:35	RW	RW		PBASLVCTL1_WRITE_TSIZE: Write Tsize These bits are valid when the PBASLVCTL[Write Ttype] = LCO_M or ATOMIC. They are used to specify the tsize bits for the powerbus operation. When PBASLVCTL[Write Ttype] = LCO_M, these bits provide a secondary encoding for the write defined as 00cc_ccc0. c_cccc is the chiplet ID of the L3 cache. When PBASLVCTL[Write Ttype] = Atomic RNW no fetch, these bits provide a secondary encoding for the atomic operation defined as fff00010. The fff specify the function to be applied to the operand. Only 8-byte operations are supported in Big Endian. Supported fff values: 000 - armw_add 001 - armw_and 010 - armw_or 011 - armw_xor
36:49	RW	RW		PBASLVCTL1_EXTADDR: PB Extaddr This bits are the PowerBus address bits (23:36) that may be used when forwarding the operation if the selected PBABARMSK bits are one.
50	RW	RW		PBASLVCTL1_RESERVED_50: Spare
51:63	RO	RO		constant=0b0000000000000

PBA Slave Control 2 Register
Addr:	0000000000068006 (PIB) 00000000C0040030 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBASLVCTL2
Constant(s):
Comments:	This register must be initialized by the OCC Firmware to allow PBA to forward requests to the PowerBus.. PBASLVCTL0, 1, 2 initialize to zero. PBASLVCTL3 initializes to allow access by FSI through OCB with LCO_M write ttype for a fast IPL. (0xD720_5400_0000_0000)
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0:50	TP.TPBR.PBA.PBAO.OCIREG.PBA_SLVCTL2_Q_0_INST.LATC.L2(0:50) [000000000000000000000000000000000000000000000000000]
Bit(s)	PIB	OCI		Dial: Description
0	RW	RW		PBASLVCTL2_ENABLE: OCI_Base_Address_Range_Enabled This bit must be set by software for the PBA to respond to an OCI request that targets Power Bus and matches the OCI MasterID Match Value. OFF - Ignore OCI operations ON - Accept OCI operations
1:3	RW	RW		PBASLVCTL2_MID_MATCH_VALUE: OCI Masterid Match Value These bits must be initialzed by software to indicate the OCI master id that will use this set of Base Address Registers when the OCI request targets the PowerBus region. Only ONE PBASLVCTLn may match any Master ID.
4	RW	RW		PBASLVCTL2_RESERVED_4: Spare
5:7	RW	RW		PBASLVCTL2_MID_CARE_MASK: OCI Masterid Care Mask These bits must be intialized by software to indicate which OCI Masterid bits must match the OCI Master ID Match Value. If only one OCI Master is using this PBASLVCTL , these bits must be set to 111.
8:10	RW	RW		PBASLVCTL2_WRITE_TTYPE: Write Ttype Forwarded write requests that target this PBASLVCTL register will use the specified write ttype on the PowerBus. DMA will use a DMA_PR_W to write 1 to 127 bytes or a CL_DMA_W_I to write the gathered 128 bytes. LCO_M is a Lateral Castout M that is used only at IPL time. Cache_Inj is a Cache Line DMA Cache Inject ttype that is used only at IPL time to write an L3 line that has already been initialized. CI_PR_WR is a Cache Inhibited Partial Write ttype implemented to write to Centaur register space. It will forward the write exactly as it was asked for in the OCI operation. Atomic is an Atomic RMW operation that should only be done as an 8-byte write. Dial enums: DMA=>0b000 LCO_M=>0b001 ATOMIC=>0b010 CACHE_INJ=>0b011 CI_PR_W=>0b100
11:14	RW	RW		PBASLVCTL2_RESERVED_11_14: Spare
15	RW	RW		PBASLVCTL2_READ_TTYPE: Read Ttype Forwarded read requesta that target this PBASLVCTL register will use the specified ttype on the PowerBus. CL_RD_NC is a Cache Line DMA Read with no intent to cache. It will always read 128 bytes from system memory. CI_PR_RD is a Cache Inhibited Partial Read. It will forward the read exactly as it was asked for in the OCI operation. This mode is required when accessing Centaur register space. Dial enums: CL_RD_NC=>0b0 CI_PR_RD=>0b1
16:17	RW	RW		PBASLVCTL2_READ_PREFETCH_CTL: Read Prefech Control No Prefetch Ahead - Fetch only current requested 128-byte cacheline. This is also the default. Auto Late Prefetch Ahead - Prefetch next cacheline after last read data returned for current cacheline. This mode may also be used if two masters need to share a buffer pair but the PBAMODE [dis_mstid_match_pref_inv] mode bit must be set to avoid a hang condition. Dial enums: DEFAULT=>0b00 NO_PREFETCH=>0b01 AUTO_LATE_PREFETCH=>0b10
18	RW	RW		PBASLVCTL2_BUF_INVALIDATE_CTL: Read Buffer Invalidate Control 0 : Do not invalidate read buffer data automatically <1 : Invalidate read buffer after 1st read data returned. This Mode is NOT VALID with any prefetch modes enabled. This mode must be enabled if Read Ttype = Cache Inhibited Partial Read.
19	RW	RW		PBASLVCTL2_BUF_ALLOC_W: Write Buffer Pair Allocation The Master ID that uses this PBASLVCTL may use only the allocated buffers. Buffer allocation is for a buffer pair. Multiple buffer pairs may be assigned. This bit must be set for the PBA to respond to Write operations through this PBASLVCTL register.
20	RW	RW		PBASLVCTL2_BUF_ALLOC_A: Read Buffer Pair A Allocation The Master ID that uses this PBASLVCTL may use only the allocated buffers. Buffer allocation is for a buffer pair. Multiple buffer pairs may be assigned. At least one read buffer must be allocated for teh PBA to respond to Read operations through this PBASLVCTL register.
21	RW	RW		PBASLVCTL2_BUF_ALLOC_B: Read Buffer Pair B Allocation The Master ID that uses this PBASLVCTL may use only the allocated buffers. Buffer allocation is for a buffer pair. Multiple buffer pairs may be assigned.
22	RW	RW		PBASLVCTL2_BUF_ALLOC_C: Read Buffer Pair C Allocation The Master ID that uses this PBASLVCTL may use only the allocated buffers. Buffer allocation is for a buffer pair. Multiple buffer pairs may be assigned.
23	RW	RW		PBASLVCTL2_RESERVED_23: Spare buffer allocation bit.
24	RW	RW		PBASLVCTL2_DIS_WRITE_GATHER: Disable Write Gather This bit disables gathering of write data in the buffer. This mode bit used only when PBASLVCTL[Write ttype] = DMA_PR_W. Otherwise it is ignored. OFF - Gather writes into the write buffer ON - Do not gather. Writes forwarded to Powerbus as written from OCI.
25:27	RW	RW		PBASLVCTL2_WR_GATHER_TIMEOUT: Write Gather Timeout Control These bits control how long the PBA should wait to gather write operations. This mode bit used only when PBASLVCTL[Write ttype] = DMA_PR_W. Otherwise it is ignored. When a write buffer is active, the PBA counts Write Gather Timeout Pulses that arrive every 64 OCI cycles, and uses the value in this register to divide the write gather timeout pulse frequency, and generate an internal hang pulse. If two hang pulses occur without a new write to the buffer, a write gather timeout occurs and the buffer is flushed to the Powerbus. Write gather timeouts must NOT be disabled if multiple masters are enabled to write through the PBA. 000 - Disable Write Gather Timeout. Write will be flushed under the following conditions: Need another write by the same master to a non-sequential address, Gathered data to cacheline boundary, Read by a master that uses this same SLVCTL register to the same address, or a PBASLVRST[SLV Reset(n)] for this PBASLVCTL. 100 - 2 Write Gather Pulses (64 to 128 OCI cycles, 64 cycles with no write) 101 - 4 Write Gather Pulses (192 to 256 OCI cycles, 128 cycles with no write) 110 - 8 Write Gather Pulses (448 to 512 OCI cycles, 256 cycles with no write) 111 - 16 Write Gather Pulses (960 to 1024 OCI cycles, 512 cycles with no write)
28:35	RW	RW		PBASLVCTL2_WRITE_TSIZE: Write Tsize These bits are valid when the PBASLVCTL[Write Ttype] = LCO_M or ATOMIC. They are used to specify the tsize bits for the powerbus operation. When PBASLVCTL[Write Ttype] = LCO_M, these bits provide a secondary encoding for the write defined as 00cc_ccc0. c_cccc is the chiplet ID of the L3 cache. When PBASLVCTL[Write Ttype] = Atomic RNW no fetch, these bits provide a secondary encoding for the atomic operation defined as fff00010. The fff specify the function to be applied to the operand. Only 8-byte operations are supported in Big Endian. Supported fff values: 000 - armw_add 001 - armw_and 010 - armw_or 011 - armw_xor
36:49	RW	RW		PBASLVCTL2_EXTADDR: PB Extaddr This bits are the PowerBus address bits (23:36) that may be used when forwarding the operation if the selected PBABARMSK bits are one.
50	RW	RW		PBASLVCTL2_RESERVED_50: Spare
51:63	RO	RO		constant=0b0000000000000

PBA Slave Control 3 Register
Addr:	0000000000068007 (PIB) 00000000C0040038 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBASLVCTL3
Constant(s):
Comments:	This register must be initialized by the OCC Firmware to allow PBA to forward requests to the PowerBus.. PBASLVCTL0, 1, 2 initialize to zero. PBASLVCTL3 initializes to allow access by FSI through OCB with LCO_M write ttype for a fast IPL. (0xD720_5400_0000_0000)
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0:50	TP.TPBR.PBA.PBAO.OCIREG.PBA_SLVCTL3_Q_0_INST.LATC.L2(0:50) [000000000000000000000000000000000000000000000000000]
Bit(s)	PIB	OCI		Dial: Description
0	RW	RW		PBASLVCTL3_ENABLE: OCI_Base_Address_Range_Enabled This bit must be set by software for the PBA to respond to an OCI request that targets Power Bus and matches the OCI MasterID Match Value. OFF - Ignore OCI operations ON - Accept OCI operations
1:3	RW	RW		PBASLVCTL3_MID_MATCH_VALUE: OCI Masterid Match Value These bits must be initialzed by software to indicate the OCI master id that will use this set of Base Address Registers when the OCI request targets the PowerBus region. Only ONE PBASLVCTLn may match any Master ID.
4	RW	RW		PBASLVCTL3_RESERVED_4: Spare
5:7	RW	RW		PBASLVCTL3_MID_CARE_MASK: OCI Masterid Care Mask These bits must be intialized by software to indicate which OCI Masterid bits must match the OCI Master ID Match Value. If only one OCI Master is using this PBASLVCTL , these bits must be set to 111.
8:10	RW	RW		PBASLVCTL3_WRITE_TTYPE: Write Ttype Forwarded write requests that target this PBASLVCTL register will use the specified write ttype on the PowerBus. DMA will use a DMA_PR_W to write 1 to 127 bytes or a CL_DMA_W_I to write the gathered 128 bytes. LCO_M is a Lateral Castout M that is used only at IPL time. Cache_Inj is a Cache Line DMA Cache Inject ttype that is used only at IPL time to write an L3 line that has already been initialized. CI_PR_WR is a Cache Inhibited Partial Write ttype implemented to write to Centaur register space. It will forward the write exactly as it was asked for in the OCI operation. Atomic is an Atomic RMW operation that should only be done as an 8-byte write. Dial enums: DMA=>0b000 LCO_M=>0b001 ATOMIC=>0b010 CACHE_INJ=>0b011 CI_PR_W=>0b100
11:14	RW	RW		PBASLVCTL3_RESERVED_11_14: Spare
15	RW	RW		PBASLVCTL3_READ_TTYPE: Read Ttype Forwarded read requesta that target this PBASLVCTL register will use the specified ttype on the PowerBus. CL_RD_NC is a Cache Line DMA Read with no intent to cache. It will always read 128 bytes from system memory. CI_PR_RD is a Cache Inhibited Partial Read. It will forward the read exactly as it was asked for in the OCI operation. This mode is required when accessing Centaur register space. Dial enums: CL_RD_NC=>0b0 CI_PR_RD=>0b1
16:17	RW	RW		PBASLVCTL3_READ_PREFETCH_CTL: Read Prefech Control No Prefetch Ahead - Fetch only current requested 128-byte cacheline. This is also the default. Auto Late Prefetch Ahead - Prefetch next cacheline after last read data returned for current cacheline. This mode may also be used if two masters need to share a buffer pair but the PBAMODE [dis_mstid_match_pref_inv] mode bit must be set to avoid a hang condition. Dial enums: DEFAULT=>0b00 NO_PREFETCH=>0b01 AUTO_LATE_PREFETCH=>0b10
18	RW	RW		PBASLVCTL3_BUF_INVALIDATE_CTL: Read Buffer Invalidate Control 0 : Do not invalidate read buffer data automatically <1 : Invalidate read buffer after 1st read data returned. This Mode is NOT VALID with any prefetch modes enabled. This mode must be enabled if Read Ttype = Cache Inhibited Partial Read.
19	RW	RW		PBASLVCTL3_BUF_ALLOC_W: Write Buffer Pair Allocation The Master ID that uses this PBASLVCTL may use only the allocated buffers. Buffer allocation is for a buffer pair. Multiple buffer pairs may be assigned. This bit must be set for the PBA to respond to Write operations through this PBASLVCTL register.
20	RW	RW		PBASLVCTL3_BUF_ALLOC_A: Read Buffer Pair A Allocation The Master ID that uses this PBASLVCTL may use only the allocated buffers. Buffer allocation is for a buffer pair. Multiple buffer pairs may be assigned. At least one read buffer must be allocated for teh PBA to respond to Read operations through this PBASLVCTL register.
21	RW	RW		PBASLVCTL3_BUF_ALLOC_B: Read Buffer Pair B Allocation The Master ID that uses this PBASLVCTL may use only the allocated buffers. Buffer allocation is for a buffer pair. Multiple buffer pairs may be assigned.
22	RW	RW		PBASLVCTL3_BUF_ALLOC_C: Read Buffer Pair C Allocation The Master ID that uses this PBASLVCTL may use only the allocated buffers. Buffer allocation is for a buffer pair. Multiple buffer pairs may be assigned.
23	RW	RW		PBASLVCTL3_RESERVED_23: Spare buffer allocation bit.
24	RW	RW		PBASLVCTL3_DIS_WRITE_GATHER: Disable Write Gather This bit disables gathering of write data in the buffer. This mode bit used only when PBASLVCTL[Write ttype] = DMA_PR_W. Otherwise it is ignored. OFF - Gather writes into the write buffer ON - Do not gather. Writes forwarded to Powerbus as written from OCI.
25:27	RW	RW		PBASLVCTL3_WR_GATHER_TIMEOUT: Write Gather Timeout Control These bits control how long the PBA should wait to gather write operations. This mode bit used only when PBASLVCTL[Write ttype] = DMA_PR_W. Otherwise it is ignored. When a write buffer is active, the PBA counts Write Gather Timeout Pulses that arrive every 64 OCI cycles, and uses the value in this register to divide the write gather timeout pulse frequency, and generate an internal hang pulse. If two hang pulses occur without a new write to the buffer, a write gather timeout occurs and the buffer is flushed to the Powerbus. Write gather timeouts must NOT be disabled if multiple masters are enabled to write through the PBA. 000 - Disable Write Gather Timeout. Write will be flushed under the following conditions: Need another write by the same master to a non-sequential address, Gathered data to cacheline boundary, Read by a master that uses this same SLVCTL register to the same address, or a PBASLVRST[SLV Reset(n)] for this PBASLVCTL. 100 - 2 Write Gather Pulses (64 to 128 OCI cycles, 64 cycles with no write) 101 - 4 Write Gather Pulses (192 to 256 OCI cycles, 128 cycles with no write) 110 - 8 Write Gather Pulses (448 to 512 OCI cycles, 256 cycles with no write) 111 - 16 Write Gather Pulses (960 to 1024 OCI cycles, 512 cycles with no write)
28:35	RW	RW		PBASLVCTL3_WRITE_TSIZE: Write Tsize These bits are valid when the PBASLVCTL[Write Ttype] = LCO_M or ATOMIC. They are used to specify the tsize bits for the powerbus operation. When PBASLVCTL[Write Ttype] = LCO_M, these bits provide a secondary encoding for the write defined as 00cc_ccc0. c_cccc is the chiplet ID of the L3 cache. When PBASLVCTL[Write Ttype] = Atomic RNW no fetch, these bits provide a secondary encoding for the atomic operation defined as fff00010. The fff specify the function to be applied to the operand. Only 8-byte operations are supported in Big Endian. Supported fff values: 000 - armw_add 001 - armw_and 010 - armw_or 011 - armw_xor
36:49	RW	RW		PBASLVCTL3_EXTADDR: PB Extaddr This bits are the PowerBus address bits (23:36) that may be used when forwarding the operation if the selected PBABARMSK bits are one.
50	RW	RW		PBASLVCTL3_RESERVED_50: Spare
51:63	RO	RO		constant=0b0000000000000

PBA Block Copy Download Engine Control Register
Addr:	0000000000068010 (PIB) 00000000C0040080 (OCI)
Name:	TP.TPBR.PBA.PBAO.BCDE_CTL
Constant(s):
Comments:	This register must be the Last register intialized (after the BCDE_SET, BCDE_PBADR and BCDE_OCIBAR) to start the Block Copy Download Engine.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.PBA.PBAO.OCIREG.PBA_BCDECTL_STOP1_Q_INST.LATC.L2(0) [0]
	1	TP.TPBR.PBA.PBAO.OCIREG.PBA_BCDECTL_START1_Q_INST.LATC.L2(0) [0]
Bit(s)	PIB	OCI		Dial: Description
0	RW	RW		BCDE_CTL_STOP: Stop BCDE This bit is written to 1 to stop the Block Copy Download Engine. The BCDE will stop when any pending OCI and PowerBus transactions have completed. If the BCDE has encountered a Data Hang condition on the Powerbus, forcing a stop will allow the engine to complete.
1	WOX	WOX		BCDE_CTL_START: Start BCDE This bit must be written to 1 to start the Block Copy Download Engine. The Stop bit must be zero for the BCDE to start. The BCDE will detect an error if the Start is set when the engine is already running.
2:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000000000

PBA Block Copy Download Engine Setup Register
Addr:	0000000000068011 (PIB) 00000000C0040088 (OCI)
Name:	TP.TPBR.PBA.PBAO.BCDE_SET
Constant(s):
Comments:	This register must be initialized to setup the BCDE.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPBR.PBA.PBAO.OCIREG.PBA_BCDESET_Q_0_INST.LATC.L2(0:7) [00000000]
Bit(s)	PIB	OCI		Dial: Description
0:1	RW	RW		BCDE_SET_RESERVED_0_1: Spare
2:7	RW	RW		BCDE_SET_COPY_LENGTH: Copy Length These bits define the number of 128 byte cachelines worth of data to transfer. 0x00 - No data transferr 0x01 - 128 bytes transfer 0x02 - 256 bytes transfer 0x03 - 384 bytes transfer . . . 0x1F - 3968 bytes transfer 0x20 - 4096 bytes transfer Others - Not supported
8:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000

PBA Block Copy Download Engine Status Register
Addr:	0000000000068012 (PIB) 00000000C0040090 (OCI)
Name:	TP.TPBR.PBA.PBAO.BCDE_STAT
Constant(s):
Comments:	This register may be read to determin the status of the BCDE.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPBR.PBA.PBAO.OCIREG.PBA_BCDESTAT_Q_0_INST.LATC.L2(0:7) [00000000]
	14:31	TP.TPBR.PBA.PBAO.OCIREG.PBA_BCDESTAT_Q_0_INST.LATC.L2(14:31) [000000000000000000]
Bit(s)	PIB	OCI		Dial: Description
0	ROX	ROX		BCDE_STAT_RUNNING: BCDE Running This bit is set after the BCDE_CTL[Start] is set to 1. It is cleared when the BCDE_STAT[Done] , [Stopped] , or [Error] bit is set.
1	ROX	ROX		BCDE_STAT_WAITING: BCDE Waiting This bit is set after the BCDE_CTL[Start] is set to 1 and BCDE is waiting to gain ownership of Buffer C or BCDE_CTL[Stop] is set to 1 and BCDE is waiting for pending operations to complete.
2:7	ROX	ROX		BCDE_STAT_WRCMP: BCDE Copy Write Complete These bits are valid only when the Running, Stopped, or Done bits are set in this register. These bits define the number of bytes worh of data that have been transferred to the SRAM without an error. 0x00 - No bytes transferred 0x01 - 128 bytes transferred 0x02 - 256 bytes transferred . . . 0x1F - 3968 bytes transferred 0x20 - 4096 bytes transferred
8:13	RO	RO		constant=0b000000
14:19	ROX	ROX		BCDE_STAT_RDCMP: BCDE Copy Read Complete These bits are valid only when the Running, Stopped, or Done bits are set in this register. These bits define the number of bytes read from System Memory without an error. 0x00 - No bytes read 0x01 - 128-byte read 0x02 - 256 bytes read . . . 0x1F - 3968 bytes read 0x20 - 4096 bytes read
20:28	ROX	ROX		BCDE_STAT_DEBUG: BCDE Debug Status These bits are a glimpse into the Block Copy Engine other state machine bits for debug purposes only. bit 0: rdtrans0 bit 1: wrtrans0 bit 2: waitfor0 bit 3: rdtrans1 bit 4: wrtrans1 bit 5: waitfor1 bit 6: finish bits 7:8 Reserved
29	ROX	ROX		BCDE_STAT_STOPPED: BCDE Stopped This bit is set and pba_occ_bcde_attn is asserted when the BCDE has been stopped cleanly by a write to BCDE_CTL[Stop]=1 and the originally defined byte transfer has not completed. This bit is reset by hardware when the BCDE_CTL register is written.
30	ROX	ROX		BCDE_STAT_ERROR: BCDE Error This bit is set and pba_occ_error is asserted when the BCDE has detected an error. It may also be set if an error was detected while stopping the BCDE. The PBAFIR indicates the detected error. This bit is reset by hardware when the BCDE_CTL register is written.
31	ROX	ROX		BCDE_STAT_DONE: BCDE Done This bit is set to 1 and pba_occ_bcde_attn is asserted when the Block Copy Engine has completed the transfer. It is reset by hardware when the BCDE_CTL register is written.
32:63	RO	RO		constant=0b00000000000000000000000000000000

PBA Block Copy Download Engine PowerBus Address Register
Addr:	0000000000068013 (PIB) 00000000C0040098 (OCI)
Name:	TP.TPBR.PBA.PBAO.BCDE_PBADR
Constant(s):
Comments:	This register must be initialized to setup the PowerBus address for the BCDE.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:42	TP.TPBR.PBA.PBAO.OCIREG.PBA_BCDEPBADR_Q_0_INST.LATC.L2(0:42) [0000000000000000000000000000000000000000000]
Bit(s)	PIB	OCI		Dial: Description
0:1	RW	RW		BCDE_PBADR_RESERVED_0_1: Spare
2:24	RW	RW		BCDE_PBADR_PB_OFFSET: PowerBus_Offset These bits define the starting PowerBus cacheline address to Read for the Block Copy Download Engine transfer. This address is used to select the PBABAR/BARMSK pair and will be remapped to the real PowerBus address. See Block Copy Engine PowerBus Address Map.
25:26	RW	RW		BCDE_PBADR_RESERVED_25_26: Spare
27:40	RW	RW		BCDE_PBADR_EXTADDR: Extended Address These bits define bits(23:36) of the PowerBus cache line address to use to Read for the Block Copy Download Engine transfer.
41:42	RW	RW		BCDE_PBADR_RESERVED_41_42: Spare
43:63	RO	RO		constant=0b000000000000000000000

PBA Block Copy Download Engine OCI Address Register
Addr:	0000000000068014 (PIB) 00000000C00400A0 (OCI)
Name:	TP.TPBR.PBA.PBAO.BCDE_OCIBAR
Constant(s):
Comments:	This register must be initialized to setup the OCI address for the BCDE.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:24	TP.TPBR.PBA.PBAO.OCIREG.PBA_BCDEOCIBAR_Q_0_INST.LATC.L2(0:24) [0000000000000000000000000]
Bit(s)	PIB	OCI		Dial: Description
0:24	RW	RW		BCDE_OCIBAR_ADDR: OCI_Base_Address These bits define the starting OCI 128-byte aligned address to Write for the Block Copy Download Engine transfer. 0:24 - Starting OCI Address.
25:63	RO	RO		constant=0b000000000000000000000000000000000000000

PBA Block Copy Upload Engine Control Register
Addr:	0000000000068015 (PIB) 00000000C00400A8 (OCI)
Name:	TP.TPBR.PBA.PBAO.BCUE_CTL
Constant(s):
Comments:	This register must be the Last register intialized (after the BCUE_SET, BCUE_PBADR and BCUE_OCIBAR) to start the Block Copy Upload Engine.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.PBA.PBAO.OCIREG.PBA_BCUECTL_STOP1_Q_INST.LATC.L2(0) [0]
	1	TP.TPBR.PBA.PBAO.OCIREG.PBA_BCUECTL_START1_Q_INST.LATC.L2(0) [0]
Bit(s)	PIB	OCI		Dial: Description
0	RW	RW		BCUE_CTL_STOP: Stop BCUE This bit is written to 1 to stop the Block Copy Upload Engine. The BCUE will stop when any pending OCI and PowerBus transactions have completed.
1	WOX	WOX		BCUE_CTL_START: Start BCUE This bit must be written to 1 to start the Block Copy Upload Engine. The Stop bit must be zero for the BCUE to start. The BCUE will detect an error if the Start is set when the engine is already running.
2:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000000000

PBA Block Copy Upload Engine Setup Register
Addr:	0000000000068016 (PIB) 00000000C00400B0 (OCI)
Name:	TP.TPBR.PBA.PBAO.BCUE_SET
Constant(s):
Comments:	This register must be initialized to setup the BCUE.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPBR.PBA.PBAO.OCIREG.PBA_BCUESET_Q_0_INST.LATC.L2(0:7) [00000000]
Bit(s)	PIB	OCI		Dial: Description
0:1	RW	RW		BCUE_SET_RESERVED_0_1: Spare
2:7	RW	RW		BCUE_SET_COPY_LENGTH: Copy Length These bits define the number of 128 byte cachelines worth of data to transfer. 0x00 - No data transferr 0x01 - 128 bytes transfer 0x02 - 256 bytes transfer 0x03 - 384 bytes transfer . . . 0x1F - 3968 bytes transfer 0x20 - 4096 bytes transfer Others - Not supported
8:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000

PBA Block Copy Upload Engine Status Register
Addr:	0000000000068017 (PIB) 00000000C00400B8 (OCI)
Name:	TP.TPBR.PBA.PBAO.BCUE_STAT
Constant(s):
Comments:	This register may be read to determin the status of the BCUE.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPBR.PBA.PBAO.OCIREG.PBA_BCUESTAT_Q_0_INST.LATC.L2(0:7) [00000000]
	14:31	TP.TPBR.PBA.PBAO.OCIREG.PBA_BCUESTAT_Q_0_INST.LATC.L2(14:31) [000000000000000000]
Bit(s)	PIB	OCI		Dial: Description
0	ROX	ROX		BCUE_STAT_RUNNING: BCUE Running This bit is set after the BCUE_CTL[Start] is set to 1. It is cleared when the BCUE_STAT[Done] , [Stopped] , or [Error] bit is set.
1	ROX	ROX		BCUE_STAT_WAITING: BCUE Waiting This bit is set after the BCUE_CTL[Start] is set to 1 and BCUE is waiting to gain ownership of Buffer C or BCUE_CTL[Stop] is set to 1 and BCUE is waiting for pending operations to complete.
2:7	ROX	ROX		BCUE_STAT_WRCMP: BCUE Copy Write Complete These bits are valid only when the Running, Stopped, or Done bits are set in this register. These bits define the number of bytes worh of data that have been transferred to system memory without an error. 0x00 - No bytes transferred 0x01 - 128 bytes transferred 0x02 - 256 bytes transferred . . . 0x1F - 3968 bytes transferred 0x20 - 4096 bytes transferred
8:13	RO	RO		constant=0b000000
14:19	ROX	ROX		BCUE_STAT_RDCMP: BCUE Copy Read Complete These bits are valid only when the Running, Stopped, or Done bits are set in this register. These bits define the number of bytes read from SRAM without an error. 0x00 - No bytes read 0x01 - 128-byte read 0x10 - 256 bytes read . . . 0x1F - 3968 bytes read 0x20 - 4096 bytes read
20:28	ROX	ROX		BCUE_STAT_DEBUG: BCUE Debug Status These bits are a glimpse into the Block Copy Engine other state machine bits for debug purposes only. bit 20: rdtrans0 bit 21: wrtrans0 bit 22: waitfor0 bit 23: rdtrans1 bit 24: wrtrans1 bit 25: waitfor1 bit 26: finish bits 27:28 Reserved
29	ROX	ROX		BCUE_STAT_STOPPED: BCUE Stopped This bit is set and pba_occ_bcue_attn is asserted when the BCUE has been stopped cleanly by a write to BCUE_CTL[Stop]=1 and the originally defined byte transfer has not completed. This bit is reset by hardware when the BCUE_CTL register is written.
30	ROX	ROX		BCUE_STAT_ERROR: BCUE Error This bit is set and pba_occ_error is asserted when the BCUE has detected an error. It may also be set if an error was detected while stopping the BCUE. The PBAFIR indicates the detected error. This bit is reset by hardware when the BCUE_CTL register is written.
31	ROX	ROX		BCUE_STAT_DONE: BCUE Done This bit is set to 1 and pba_occ_bcue_attn is asserted when the Block Copy Engine has completed the transfer. It is reset by hardware when the BCUE_CTL register is written.
32:63	RO	RO		constant=0b00000000000000000000000000000000

PBA Block Copy Upload Engine PowerBus Address Register
Addr:	0000000000068018 (PIB) 00000000C00400C0 (OCI)
Name:	TP.TPBR.PBA.PBAO.BCUE_PBADR
Constant(s):
Comments:	This register must be initialized to setup the PowerBus address for the BCUE.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:42	TP.TPBR.PBA.PBAO.OCIREG.PBA_BCUEPBADR_Q_0_INST.LATC.L2(0:42) [0000000000000000000000000000000000000000000]
Bit(s)	PIB	OCI		Dial: Description
0:1	RW	RW		BCUE_PBADR_RESERVED_0_1: Spare
2:24	RW	RW		BCUE_PBADR_PB_OFFSET: PowerBus_Offset These bits define the starting PowerBus cacheline address to Write for the Block Copy Upload Engine transfer. This address is used to select the PBABAR/BARMSK pair and will be remapped to the real PowerBus address. See Block Copy Engine PowerBus Address Map.
25:26	RW	RW		BCUE_PBADR_RESERVED_25_26: Spare
27:40	RW	RW		BCUE_PBADR_EXTADDR: Extended Address These bits define bits(23:36) of the PowerBus cache line address to use to Write for the Block Copy Upload Engine transfer.
41:42	RW	RW		BCUE_PBADR_RESERVED_41_42: Spare
43:63	RO	RO		constant=0b000000000000000000000

PBA Block Copy Upload Engine OCI Address Register
Addr:	0000000000068019 (PIB) 00000000C00400C8 (OCI)
Name:	TP.TPBR.PBA.PBAO.BCUE_OCIBAR
Constant(s):
Comments:	This register must be initialized to setup the OCI address for the BCUE.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:24	TP.TPBR.PBA.PBAO.OCIREG.PBA_BCUEOCIBAR_Q_0_INST.LATC.L2(0:24) [0000000000000000000000000]
Bit(s)	PIB	OCI		Dial: Description
0:24	RW	RW		BCUE_OCIBAR_ADDR: OCI_Base_Address These bits define the starting OCI 128-byte aligned address to Read for the Block Copy Upload Engine transfer. 0:24 - Starting OCI Address.
25:63	RO	RO		constant=0b000000000000000000000000000000000000000

PBA OCI Event Counters 0
Addr:	000000000006801A (PIB) 00000000C00400D0 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBAOCR0
Constant(s):
Comments:	This register contains a count of PBA buffer events. Counter 0 contains busy_rearb, counter 1 contains accept_rearb, Counter 2 contains Clr Prefetch and Counter 3 contains Drop PRefetch
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	44:63	TP.TPBR.PBA.PBAO.OCIREG.PBA_CHGRATE_ACCUM0_Q_0_INST.LATC.L2(0:19) [00000000000000000000]
Bit(s)	PIB	OCI		Dial: Description
0:43	RO	RO		constant=0b00000000000000000000000000000000000000000000
44:63	ROX	ROX		PBAOCR0_COUNT: OCI Event Count Based on PBAMODE[slv_event_mux] the corresponding buffers event counts are captured 00 - Buffer A ( Busy Rearb, Accept Rearb, Clr Prefetch, Drop Prefetch) 01 - Buffer B 10 - Buffer C 11 - not defined.

PBA OCI Event Counters 1
Addr:	000000000006801B (PIB) 00000000C00400D8 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBAOCR1
Constant(s):
Comments:	This register contains a count of PBA buffer events. Counter 0 contains busy_rearb, counter 1 contains accept_rearb, Counter 2 contains Clr Prefetch and Counter 3 contains Drop PRefetch
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	44:63	TP.TPBR.PBA.PBAO.OCIREG.PBA_CHGRATE_ACCUM1_Q_0_INST.LATC.L2(0:19) [00000000000000000000]
Bit(s)	PIB	OCI		Dial: Description
0:43	RO	RO		constant=0b00000000000000000000000000000000000000000000
44:63	ROX	ROX		PBAOCR1_COUNT: OCI Event Count Based on PBAMODE[slv_event_mux] the corresponding buffers event counts are captured 00 - Buffer A ( Busy Rearb, Accept Rearb, Clr Prefetch, Drop Prefetch) 01 - Buffer B 10 - Buffer C 11 - not defined.

PBA OCI Event Counters 2
Addr:	000000000006801C (PIB) 00000000C00400E0 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBAOCR2
Constant(s):
Comments:	This register contains a count of PBA buffer events. Counter 0 contains busy_rearb, counter 1 contains accept_rearb, Counter 2 contains Clr Prefetch and Counter 3 contains Drop PRefetch
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	44:63	TP.TPBR.PBA.PBAO.OCIREG.PBA_CHGRATE_ACCUM2_Q_0_INST.LATC.L2(0:19) [00000000000000000000]
Bit(s)	PIB	OCI		Dial: Description
0:43	RO	RO		constant=0b00000000000000000000000000000000000000000000
44:63	ROX	ROX		PBAOCR2_COUNT: OCI Event Count Based on PBAMODE[slv_event_mux] the corresponding buffers event counts are captured 00 - Buffer A ( Busy Rearb, Accept Rearb, Clr Prefetch, Drop Prefetch) 01 - Buffer B 10 - Buffer C 11 - not defined.

PBA OCI Event Counters 3
Addr:	000000000006801D (PIB) 00000000C00400E8 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBAOCR3
Constant(s):
Comments:	This register contains a count of PBA buffer events. Counter 0 contains busy_rearb, counter 1 contains accept_rearb, Counter 2 contains Clr Prefetch and Counter 3 contains Drop PRefetch
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	44:63	TP.TPBR.PBA.PBAO.OCIREG.PBA_CHGRATE_ACCUM3_Q_0_INST.LATC.L2(0:19) [00000000000000000000]
Bit(s)	PIB	OCI		Dial: Description
0:43	RO	RO		constant=0b00000000000000000000000000000000000000000000
44:63	ROX	ROX		PBAOCR3_COUNT: OCI Event Count Based on PBAMODE[slv_event_mux] the corresponding buffers event counts are captured 00 - Buffer A ( Busy Rearb, Accept Rearb, Clr Prefetch, Drop Prefetch) 01 - Buffer B 10 - Buffer C 11 - not defined.

PBA PBAX Send Transaction Register
Addr:	0000000000068020 (PIB) 00000000C0040100 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBAXSNDTX
Constant(s):
Comments:	This register contains the values that will be used by the PBAX Send engine to produce the PMISC PowerBus operation. This register is typically written by a GPE program (or OCC) to setup an operation in the normal functional path.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPBR.PBA.PBAO.OCIREG.PBAXSNDTX_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	59:63	TP.TPBR.PBA.PBAO.OCIREG.PBAXSNDTX_Q_0_INST.LATC.L2(32:36) [00000]
Bit(s)	PIB	OCI		Dial: Description
0:2	RW	RW		PBAXSNDTX_SND_SCOPE: PBAX Send Message Scope PowerBus scope used for the PMISC command 011 : GROUP 101 : VECTORED_GROUP Others: Reserved Note: Reserved fields are for Nodal, Remote Group Pump and other scopes. However, these are not supported and cannot be programmed as such. The Default is VECTORED GROUP scope.
3	RW	RW		PBAXSNDTX_SND_QID: PBAX Queue Id This bit controls which push queue is the target at the PBAX Receive. 0 : Sync Queue 1 : Doorbell Queue
4	RW	RW		PBAXSNDTX_SND_TYPE: PBAX Send Type 0 - Unicast 1 - Broadcast
5	RW	RW		PBAXSNDTX_SND_RESERVATION: PBAX Send Broadcast Reservation This bit controls if the PBAX Send Engine gains a reservation from the PBAX Receive engine before sending a PBAX Send Type = Broadcast. The reservation is acquired only if PBAXCFG[reservation_en] = 1. 0 - Reservation not required. 1 - Reservation required. Note: A reservation is necessary for real-time broadcasts.
6:7	RW	RW		PBAXSNDTX_RESERVED_6_7: Spare
8:11	RW	RW		PBAXSNDTX_SND_GROUPID: PBAX Send groupid(0:3) Value used by PBAX Send engine to indicate target(s) for PMISC message.
12:14	RW	RW		PBAXSNDTX_SND_CHIPID: PBAX Send Chipid(0:2) Value used by PBAX Send engine to indicate target(s) for PMISC message
15	RW	RW		PBAXSNDTX_RESERVED_15: Spare
16:31	RW	RW		PBAXSNDTX_VG_TARGE: PBAX Vectored Group Target(0:15) PowerBus target vector to used when configured for vectored group scope. Default is zero and must be intialized by software to efficiently target the PBAX command if starting out with Vectored Group scope. If the scope is increased to Vectored Group, the PBA will use a a Vg_Target = xFFFF.
32:58	RO	RO		constant=0b000000000000000000000000000
59	RW	RW		PBAXSNDTX_SND_STOP: PBAX Stop Sending This bit is written by software (keeping all other bits in the register the same) to stop the PBA when sending a multi packet message. The PBA will abandon sending the messages after the current one is sent, clear PBAXSNDSTAT[snd_in_progress], and assert pbax_occ_pbax_attn completion interrupt.
60:63	RW	RW		PBAXSNDTX_SND_CNT: PBAX Send Count(0:3) Number of 8B messages to send. 0 means send single 8B message. Setting to x1 to XF will cause a multi-packet meessage to be sent. XF means send 16 8B messages.

PBA PBAX Configuration Register
Addr:	0000000000068021 (PIB) 00000000C0040108 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBAXCFG
Constant(s):
Comments:	This register contains general setup and configuration information for the PBAX Send engine and the PBAX Receive engine. This register should not be written unless PBAXSNDSTAT[snd_in_progress]=0.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:40	TP.TPBR.PBA.PBAO.OCIREG.PBAXCFG_Q_0_INST.LATC.L2(0:40) [00000000000000000000000000000000000000000]
Bit(s)	PIB	OCI		Dial: Description
0	RW	RW		PBAXCFG_PBAX_EN: PBAX Send Facility Enable 0 - Disabled: writes to the PBAX DataHi Register will occur but the PowerBus PMISC operations will not take place. 1 - Enabled: writes to the PBAX DataHi Register will cause the atomic PowerBus PMISC Hi Data/Lo Data phases to occur.
1	RW	RW		PBAXCFG_RESERVATION_EN: PBAX Send Reservation Enable This bit enables requests to the Send Engine to gain a broadcast reservation from the Receive Engine. 0: Disabled 1: Enabled Architectural Note This bit is intended to be set (enabled) in the chip that is the power domain OCC Master which will be performing the real-time power measurement distribution and reset (disabled) in all other chips in the power domain. This keeps any other OCCs (including Voltage Masters) from producing reservations broadcasts that could lead to PBAX livelocks.
2	WOX	WOX		PBAXCFG_SND_RESET: PBAX Send Reset Setting this bit to a 1 on a register write clears the snd_error condition in the PBAXSNDSTAT register.
3	WOX	WOX		PBAXCFG_RCV_RESET: PBAX Receive Reset Setting this bit to a 1 on a register write clears the rcv_error condition in the PBAXRCVSTAT register.
4:7	RW	RW		PBAXCFG_RCV_GROUPID: Receive PBAX groupid Value that indicates this PBAs PBAX group affinity. This is matched to pbax_groupid of the PMISC Address phase.
8:10	RW	RW		PBAXCFG_RCV_CHIPID: Receive PBAX Chipid Value that indicates this PBAs PBAX Chipid within the PBAX group. Is matched to pbax_chipid of the Address phase if pbax_type=unicast.
11	RW	RW		PBAXCFG_RESERVED_11: Spare
12:19	RW	RW		PBAXCFG_RCV_BRDCST_GROUP: Receive PBAX Broadcast Group Vector that is indexed when decoded PMISC pbax_type=broadcast with the decoded PMISC pbax_chipid value. If the bit in this vector at the decoded bit location is a 1, then this receive engine will participate in the broadcast operation.
20:24	RW	RW		PBAXCFG_RCV_DATATO_DIV: PBAX Data Timeout Divider Divider for the 500 us PBAX hang pulse. A hang is detected after two divided hang pulses are received under the following conditions: - Data Hi packet accepted and timeout waiting for Data Lo packet. - Reservation aquired and timeout waiting for Data Hi packet. 00000 - Data Timeout is Disabled 00001 - divided hang pulse = PBAX hang pulse 00010 - divided hang pulse = PBAX hang pulse/2 00011 - divided hang pulse = PBAX hang pulse/3 . . . 11111 - divided hang pulse = PBAX hang pulse/31
25:26	RW	RW		PBAXCFG_RESERVED_25_26: Spare
27	RW	RW		PBAXCFG_SND_RETRY_COUNT_OVERCOM: PBAX Send Retry count overcommit Mode bit to count overcommit retries for the send retry threshold when sending PBAX commands on the powerbus.
28:35	RW	RW		PBAXCFG_SND_RETRY_THRESH: PBAX Send Retry Threshold Defines the maximum number of retry attempts by the Send Engine for any phase of the PBAX transaction set before the operation is dropped and status bit are set. This does not count PowerBus overcommit retries unless snd_retry_count_overcom bit is set. 0x00 : No Timeout 0x01 : 1 attempt 0x02 : 2 attempts .etc. 0xFF : 255 attempts
36:40	RW	RW		PBAXCFG_SND_RSVTO_DIV: PBAX Send Reservation Timeout Divider Divider for the 500us PBAX hang pulse. A hang is detected after two divided hang pulses are received after attempting to acquire a reservation with the PBAX Receive engine before declaring a Send Reservation Timeout error. 00000 - Send Reservation Timeout is Disabled 00001 - divided hang pulse = PBAX hang pulse 00010 - divided hang pulse = PBAX hang pulse/2 00011 - divided hang pulse = PBAX hang pulse/3 . . . 11111 - divided hang pulse = PBAX hang pulse/31
41:63	RO	RO		constant=0b00000000000000000000000

PBA PBAX Send Status Register
Addr:	0000000000068022 (PIB) 00000000C0040110 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBAXSNDSTAT
Constant(s):
Comments:	This register contains status values of PBAX Send engine.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPBR.PBA.PBAO.OCIREG.PBAXSNDSTAT_Q_0_INST.LATC.L2(0:15) [0000000000000000]
Bit(s)	PIB	OCI		Dial: Description
0	ROX	ROX		PBAXSNDSTAT_SND_IN_PROGRESS: PBAX Send In Progress If PBAXCFG[pbax_en=1](enabled), this bit is asserted by the hardware upon a write to PBAX Send Data Register[datahi] of the last piece of message data through the duration of the PowerBus PMISC DataHi/DataLo phases for the last piece of message data. Hardware resets this bit upon detection of a valid CRESP of the last PMISC PBAX phase for the last piece of message data AND pulses the pba_occ_pbax_attn interrupt. If PBAXCFG[pbax_en=0 ](disabled), this bit will not be set and the PBAX PMISC is not forwarded.
1	ROX	ROX		PBAXSNDSTAT_SND_ERROR: PBAX Send Error This bit is set when an error is detected while sending a PBAX request. The detailed reasons for setting this error bit are defined in the PBAFIR(bits tbd). If the correspond bit is set in the PBAOCCACT register, the pba_occ_error output pin is asserted. This bit is cleared by writing PBAXCFG[snd_reset] = 1.
2:3	ROX	ROX		PBAXSNDSTAT_SND_PHASE_STATUS: PBAX Send Status(0 to 1) Reset to 0 upon the successful write of the PBAX Send DataHi Register. Dial enums: PHASE1_SENDING=>0b10 PHASE2_SENDING=>0b01
4:7	ROX	ROX		PBAXSNDSTAT_SND_CNT_STATUS: PBAX Send Count Status(0 to 3) Number of PBAX messages sent when snd_in_progress=1. If snd_cnt=0 (a single 8B message), this will stay zero when send_in_progress clears. If snd_cnt=xF, this will count up to xF when the last 8B are sent and snd_in_progress clears. Reset to 0 upon the successful write of the PBAX Send DataHi Register.
8:15	ROX	ROX		PBAXSNDSTAT_SND_RETRY_COUNT: PBAX Send Retry Count The maximum number of retries performed for any of the phases of an PBAX operation. Valid only when snd_in_progress=0 Reset to 0 upon the successful write of the PBAX Send DataHi Register.
16:63	RO	RO		constant=0b000000000000000000000000000000000000000000000000

PBAX Receive Status Register
Addr:	0000000000068024 (PIB) 00000000C0040120 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBAXRCVSTAT
Constant(s):
Comments:	This register shows the status and progression of a incoming PBAX command through the PBAX Receive engine onto the Push queue.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:21	TP.TPBR.PBA.PBAO.OCIREG.PBAXRCVSTAT_Q_0_INST.LATC.L2(0:21) [0000000000000000000000]
Bit(s)	PIB	OCI		Dial: Description
0	ROX	ROX		PBAXRCVSTAT_RCV_IN_PROGRESS: PBAX Receive In Progress If pbax_en=1 (enabled), this bit is asserted by the hardware upon accepting a Pmisc PBAX DataHi phase operation. Hardware resets this bit when the OCI store operation completes. This bit is also reset if the PBAX detects an error and returns to the idle state. If PBAXSHCS [push_enable]=0 (disabled), this bit will not be set.
1	ROX	ROX		PBAXRCVSTAT_RCV_ERROR: PBAX Receive Error This bit is set when an error is detected while receiving a PBAX request or writing it to the OCI. The detailed reasons for setting this error bit are defined in the PBAFIR(axrcv_**). If the correspond bit is set in the PBAOCCACT register, the pba_occ_error output pin is asserted. This bit is cleared by writing PBAXCFG [rcv_reset] = 1
2	ROX	ROX		PBAXRCVSTAT_RCV_WRITE_IN_PROGRESS: PBAX Receive Write in Progress This bit is set when the PBAX is ready to forward to the OCI using the appropriate Push queue. It remains set until the write is complete.
3	ROX	ROX		PBAXRCVSTAT_RCV_RESERVATION_SET: PBAX Receive Reservation Set This bit is set the PBAX Receive engine has accepted a reservation from the PBAX Send Engine. It remains set until the matching PBAX command has been received and written.
4:21	ROX	ROX		PBAXRCVSTAT_RCV_CAPTURE: PBAX Receive Info Capture Captured when an error occurs while receiving a PMISC PBAX operation. Valid only if rcv_error is set. 4:7 powerbus source topologyID - ttag(0:3) 8:12 powerbus source unitID - ttag(4:8) 13:16 pbax_groupid 17:19 pbax_chipid 20 pbax_type 21 pbax_qid.
22:63	RO	RO		constant=0b000000000000000000000000000000000000000000

PBAX Push Base 0 Register
Addr:	0000000000068026 (PIB) 00000000C0040130 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBAXSHBR0
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:28	TP.TPBR.PBA.PBAO.OCIREG.PUSHQ#0.Q.PBAXSHBR_Q_0_INST.LATC.L2(0:28) [00000000000000000000000000000]
Bit(s)	PIB	OCI		Dial: Description
0:28	RW	RW		push_start
29:63	RO	RO		constant=0b00000000000000000000000000000000000

PBAX Push Control/Status 0 Register
Addr:	0000000000068027 (PIB) 00000000C0040138 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBAXSHCS0
Constant(s):
Comments:	Controls the behavior of Push Queue n. Writes to this register cause the queue hardware to be reset when the PBAXRCVSTAT[rcv_in_progress]=0. Writes to all bits except for push_en are ignored when PBAXRCVSTAT [ rcv_in_progress ] = 1. Firmware should read the register after writing to verify.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.PBA.PBAO.OCIREG.PUSHQ#0.Q.PUSH_FULL_Q_INST.LATC.L2(0) [0]
	1	TP.TPBR.PBA.PBAO.OCIREG.PUSHQ#0.Q.PUSH_EMPTY_Q_INST.LATC.L2(0) [0]
	2:10	TP.TPBR.PBA.PBAO.OCIREG.PUSHQ#0.Q.PBAXSHCS_Q_0_INST.LATC.L2(0:8) [000000000]
	13:17	TP.TPBR.PBA.PBAO.OCIREG.PUSHQ#0.Q.PUSH_WRITE_PTR_Q_0_INST.LATC.L2(0:4) [00000]
	21:25	TP.TPBR.PBA.PBAO.OCIREG.PUSHQ#0.Q.PUSH_READ_PTR_Q_0_INST.LATC.L2(0:4) [00000]
	31	TP.TPBR.PBA.PBAO.OCIREG.PUSHQ#0.Q.PBAXSHCS_Q_0_INST.LATC.L2(9) [0]
Bit(s)	PIB	OCI		Dial: Description
0	RWX_WCLRPART	RWX_WCLRPART		PBAXSHCS0_PUSH_FULL: Push Queue Full Reads indicate the Push Queue is full condition Any write to this register clears this indicator and clears push_write_ptr and push_read_ptr to 0s. (this is a means for resetting the queue hardware) Dial enums: NOT_FULL=>0b0 FULL=>0b1
1	RWX_WSETPART	RWX_WSETPART		PBAXSHCS0_PUSH_EMPTY: Push Queue Empty Any write to this register sets this indicator and clears push_write_ptr and push_read_ptr to 0s. (this is a means for resetting the queue hardware) Dial enums: NOT_EMPTY=>0b0 EMPTY=>0b1
2:3	RW	RW		PBAXSHCS0_RESERVED_2_3: Spare
4:5	RW	RW		PBAXSHCS0_PUSH_INTR_ACTION_0_1: Push Interrupt Action This field controls the condition which will assert the push interrupt signal (pba_occ_push0/1] for this channel to the OCB interrupt controller. b00 - Full (default upon hardware init) b01 - Not Full b10 - Empty b11 - Not Empty (doorbell queue setting)
6:10	RW	RW		PBAXSHCS0_PUSH_LENGTH: Push Queue length These bits define the depth of the Push Queue. (push_length +1) * 8B. This value may be changed only when push_enable=- and PBAXRCVSTAT[rcv_in_progress]=0. Value mapping: 0b00000: 8B (1 entry) 0b00001: 16B (2 entry) 0b00010: 24B (3 entry) 0b00011: 32B (4 entry) .etc. 0b11111: 256B (32 entry)
11:12	RO	RO		constant=0b00
13:17	RWX_WCLRPART	RWX_WCLRPART		PBAXSHCS0_PUSH_WRITE_PTR: Push write pointer Reads indicate the current Push Queue write pointer in increments of 8B. The actual address used is push_start + push_write_ptr || 000. Writes to this field are ignored. Hardware performs all modifications. This field is cleared upon a write to this register.
18:20	RO	RO		constant=0b000
21:25	RWX_WCLRPART	RWX_WCLRPART		PBAXSHCS0_PUSH_READ_PTR: Push read pointer Reads indicate the current Push Queue read pointer in increments of 8B. The actual address used is push_start + push_read_ptr || 000. This field is cleared upon a write to this register.
26:30	RO	RO		constant=0b00000
31	RW	RW		PBAXSHCS0_PUSH_ENABLE: Push Queue Enable If Disabled, PMISC PBAX commands are ignored and an error indication is set. Note: OCI Writes to PBAX Push Increment 0 Register to cause incrementation and any side effects are unaffected by the setting of this bit. Dial enums: DISABLED=>0b0 ENABLED=>0b1
32:63	RO	RO		constant=0b00000000000000000000000000000000 Dial enums: DISABLED=>0b0 ENABLED=>0b1

PBAX Push Increment 0 Register
Addr:	0000000000068028 (PIB) 00000000C0040140 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBAXSHINC0
Constant(s):
Comments:	Writes to this register cause the Push Queue Read pointer to increment by 1 modulo the Push Queue Size and will do so independent of the setting of PBAX Push Control/Status 0 Register[push_enable].
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	PIB	OCI		Dial: Description
0:63	RO	RO		constant=0b0000000000000000000000000000000000000000000000000000000000000000

PBAX Push Base 1 Register
Addr:	000000000006802A (PIB) 00000000C0040150 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBAXSHBR1
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:28	TP.TPBR.PBA.PBAO.OCIREG.PUSHQ#1.Q.PBAXSHBR_Q_0_INST.LATC.L2(0:28) [00000000000000000000000000000]
Bit(s)	PIB	OCI		Dial: Description
0:28	RW	RW		push_start
29:63	RO	RO		constant=0b00000000000000000000000000000000000

PBAX Push Control/Status 1 Register
Addr:	000000000006802B (PIB) 00000000C0040158 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBAXSHCS1
Constant(s):
Comments:	Controls the behavior of Push Queue n. Writes to this register cause the queue hardware to be reset when the PBAXRCVSTAT[rcv_in_progress]=0. Writes to all bits except for push_en are ignored when PBAXRCVSTAT [ rcv_in_progress ] = 1. Firmware should read the register after writing to verify.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.PBA.PBAO.OCIREG.PUSHQ#1.Q.PUSH_FULL_Q_INST.LATC.L2(0) [0]
	1	TP.TPBR.PBA.PBAO.OCIREG.PUSHQ#1.Q.PUSH_EMPTY_Q_INST.LATC.L2(0) [0]
	2:10	TP.TPBR.PBA.PBAO.OCIREG.PUSHQ#1.Q.PBAXSHCS_Q_0_INST.LATC.L2(0:8) [000000000]
	13:17	TP.TPBR.PBA.PBAO.OCIREG.PUSHQ#1.Q.PUSH_WRITE_PTR_Q_0_INST.LATC.L2(0:4) [00000]
	21:25	TP.TPBR.PBA.PBAO.OCIREG.PUSHQ#1.Q.PUSH_READ_PTR_Q_0_INST.LATC.L2(0:4) [00000]
	31	TP.TPBR.PBA.PBAO.OCIREG.PUSHQ#1.Q.PBAXSHCS_Q_0_INST.LATC.L2(9) [0]
Bit(s)	PIB	OCI		Dial: Description
0	RWX_WCLRPART	RWX_WCLRPART		PBAXSHCS1_PUSH_FULL: Push Queue Full Reads indicate the Push Queue is full condition Any write to this register clears this indicator and clears push_write_ptr and push_read_ptr to 0s. (this is a means for resetting the queue hardware) Dial enums: NOT_FULL=>0b0 FULL=>0b1
1	RWX_WSETPART	RWX_WSETPART		PBAXSHCS1_PUSH_EMPTY: Push Queue Empty Any write to this register sets this indicator and clears push_write_ptr and push_read_ptr to 0s. (this is a means for resetting the queue hardware) Dial enums: NOT_EMPTY=>0b0 EMPTY=>0b1
2:3	RW	RW		PBAXSHCS1_RESERVED_2_3: Spare
4:5	RW	RW		PBAXSHCS1_PUSH_INTR_ACTION_0_1: Push Interrupt Action This field controls the condition which will assert the push interrupt signal (pba_occ_push0/1] for this channel to the OCB interrupt controller. b00 - Full (default upon hardware init) b01 - Not Full b10 - Empty b11 - Not Empty (doorbell queue setting)
6:10	RW	RW		PBAXSHCS1_PUSH_LENGTH: Push Queue length These bits define the depth of the Push Queue. (push_length +1) * 8B. This value may be changed only when push_enable=- and PBAXRCVSTAT[rcv_in_progress]=0. Value mapping: 0b00000: 8B (1 entry) 0b00001: 16B (2 entry) 0b00010: 24B (3 entry) 0b00011: 32B (4 entry) .etc. 0b11111: 256B (32 entry)
11:12	RO	RO		constant=0b00
13:17	RWX_WCLRPART	RWX_WCLRPART		PBAXSHCS1_PUSH_WRITE_PTR: Push write pointer Reads indicate the current Push Queue write pointer in increments of 8B. The actual address used is push_start + push_write_ptr || 000. Writes to this field are ignored. Hardware performs all modifications. This field is cleared upon a write to this register.
18:20	RO	RO		constant=0b000
21:25	RWX_WCLRPART	RWX_WCLRPART		PBAXSHCS1_PUSH_READ_PTR: Push read pointer Reads indicate the current Push Queue read pointer in increments of 8B. The actual address used is push_start + push_read_ptr || 000. This field is cleared upon a write to this register.
26:30	RO	RO		constant=0b00000
31	RW	RW		PBAXSHCS1_PUSH_ENABLE: Push Queue Enable If Disabled, PMISC PBAX commands are ignored and an error indication is set. Note: OCI Writes to PBAX Push Increment 1 Register to cause incrementation and any side effects are unaffected by the setting of this bit. Dial enums: DISABLED=>0b0 ENABLED=>0b1
32:63	RO	RO		constant=0b00000000000000000000000000000000 Dial enums: DISABLED=>0b0 ENABLED=>0b1

PBAX Push Increment 1 Register
Addr:	000000000006802C (PIB) 00000000C0040160 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBAXSHINC1
Constant(s):
Comments:	Writes to this register cause the Push Queue Read pointer to increment by 1 modulo the Push Queue Size and will do so independent of the setting of PBAX Push Control/Status 0 Register[push_enable].
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	PIB	OCI		Dial: Description
0:63	RO	RO		constant=0b0000000000000000000000000000000000000000000000000000000000000000

PBA PBAX Inter-Chip Send Transaction Register
Addr:	0000000000068030 (PIB) 00000000C0040180 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBAXISNDTX
Constant(s):
Comments:	This register contains the values that will be used by the PBAX Send engine to produce the PMISC PowerBus operation. This register is typically written by a GPE program (or OCC) to setup an operation in the normal functional path. Note: This set of registers is intended for GPE usage
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPBR.PBA.PBAO.OCIREG.PBAXISNDTX_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	59:63	TP.TPBR.PBA.PBAO.OCIREG.PBAXISNDTX_Q_0_INST.LATC.L2(32:36) [00000]
Bit(s)	PIB	OCI		Dial: Description
0:2	RW	RW		PBAXISNDTX_SND_SCOPE: PBAX Send Message Scope PowerBus scope used for the PMISC command 011 : GROUP 101 : VECTORED_GROUP Others: Reserved Note: Reserved fields are for Nodal, Remote Group Pump and other scopes. However, these are not supported and cannot be programmed as such. The Default is VECTORED GROUP scope.
3	RW	RW		PBAXISNDTX_SND_QID: PBAX Queue Id This bit controls which push queue is the target at the PBAX Receive. 0 : Sync Queue 1 : Doorbell Queue
4	RW	RW		PBAXISNDTX_SND_TYPE: PBAX Send Type 0 - Unicast 1 - Broadcast
5	RW	RW		PBAXISNDTX_SND_RESERVATION: PBAX Send Broadcast Reservation This bit controls if the PBAX Send Engine gains a reservation from the PBAX Receive engine before sending a PBAX Send Type = Broadcast. The reservation is acquired only if PBAXCFG[reservation_en] = 1. 0 - Reservation not required. 1 - Reservation required. Note: A reservation is necessary for real-time broadcasts.
6:7	RW	RW		PBAXISNDTX_RESERVED_6_7: Spare
8:11	RW	RW		PBAXISNDTX_SND_GROUPID: PBAX Send groupid(0:3) Value used by PBAX Send engine to indicate target(s) for PMISC message.
12:14	RW	RW		PBAXISNDTX_SND_CHIPID: PBAX Send Chipid(0:2) Value used by PBAX Send engine to indicate target(s) for PMISC message
15	RW	RW		PBAXISNDTX_RESERVED_15: Spare
16:31	RW	RW		PBAXISNDTX_VG_TARGE: PBAX Vectored Group Target(0:15) PowerBus target vector to used when configured for vectored group scope. Default is zero and must be intialized by software to efficiently target the PBAX command if starting out with Vectored Group scope. If the scope is increased to Vectored Group, the PBA will use a a Vg_Target = xFFFF.
32:58	RO	RO		constant=0b000000000000000000000000000
59	RW	RW		PBAXISNDTX_SND_STOP: PBAX Stop Sending This bit is written by software (keeping all other bits in the register the same) to stop the PBA when sending a multi packet message. The PBA will abandon sending the messages after the current one is sent, clear PBAXSNDSTAT[snd_in_progress], and assert pbax_occ_pbax_attn completion interrupt.
60:63	RW	RW		PBAXISNDTX_SND_CNT: PBAX Send Count(0:3) Number of 8B messages to send. 0 means send single 8B message. Setting to x1 to XF will cause a multi-packet meessage to be sent. XF means send 16 8B messages.

PBA PBAX Inter-Chip Configuration Register
Addr:	0000000000068031 (PIB) 00000000C0040188 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBAXICFG
Constant(s):
Comments:	This register contains general setup and configuration information for the PBAX Send engine and the PBAX Receive engine. This register should not be written unless PBAXISNDSTAT[snd_in_progress]=0. Note: This set of registers is intended for GPE usage
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:40	TP.TPBR.PBA.PBAO.OCIREG.PBAXICFG_Q_0_INST.LATC.L2(0:40) [00000000000000000000000000000000000000000]
Bit(s)	PIB	OCI		Dial: Description
0	RW	RW		PBAXICFG_PBAX_EN: PBAX Send Facility Enable 0 - Disabled: writes to the PBAX DataHi Register will occur but the PowerBus PMISC operations will not take place. 1 - Enabled: writes to the PBAX DataHi Register will cause the atomic PowerBus PMISC Hi Data/Lo Data phases to occur.
1	RW	RW		PBAXICFG_RESERVATION_EN: PBAX Send Reservation Enable This bit enables requests to the Send Engine to gain a broadcast reservation from the Receive Engine. 0: Disabled 1: Enabled Architectural Note This bit is intended to be set (enabled) in the chip that is the power domain OCC Master which will be performing the real-time power measurement distribution and reset (disabled) in all other chips in the power domain. This keeps any other OCCs (including Voltage Masters) from producing reservations broadcasts that could lead to PBAX livelocks.
2	WOX	WOX		PBAXICFG_SND_RESET: PBAX Send Reset Setting this bit to a 1 on a register write clears the snd_error condition in the PBAXSNDSTAT register.
3	WOX	WOX		PBAXICFG_RCV_RESET: PBAX Receive Reset Setting this bit to a 1 on a register write clears the rcv_error condition in the PBAXRCVSTAT register.
4:7	RW	RW		PBAXICFG_RCV_GROUPID: Receive PBAX groupid Value that indicates this PBAs PBAX group affinity. This is matched to pbax_groupid of the PMISC Address phase.
8:10	RW	RW		PBAXICFG_RCV_CHIPID: Receive PBAX Chipid Value that indicates this PBAs PBAX Chipid within the PBAX group. Is matched to pbax_chipid of the Address phase if pbax_type=unicast.
11	RW	RW		PBAXICFG_RESERVED_11: Spare
12:19	RW	RW		PBAXICFG_RCV_BRDCST_GROUP: Receive PBAX Broadcast Group Vector that is indexed when decoded PMISC pbax_type=broadcast with the decoded PMISC pbax_chipid value. If the bit in this vector at the decoded bit location is a 1, then this receive engine will participate in the broadcast operation.
20:24	RW	RW		PBAXICFG_RCV_DATATO_DIV: PBAX Data Timeout Divider Divider for the 500us PBAX hang pulse. A hang is detected after two divided hang pulses are received under the following conditions: - Data Hi packet accepted and timeout waiting for Data Lo packet. - Reservation aquired and timeout waiting for Data Hi packet. 00000 - Data Timeout is Disabled 00001 - divided hang pulse = PBAX hang pulse 00010 - divided hang pulse = PBAX hang pulse/2 00011 - divided hang pulse = PBAX hang pulse/3 . . . 11111 - divided hang pulse = PBAX hang pulse/31
25:26	RW	RW		PBAXICFG_RESERVED_25_26: Spare
27	RW	RW		PBAXICFG_SND_RETRY_COUNT_OVERCOM: PBAX Send Retry count overcommit Mode bit to count overcommit retries for the send retry threshold when sending PBAX commands on the powerbus.
28:35	RW	RW		PBAXICFG_SND_RETRY_THRESH: PBAX Send Retry Threshold Defines the maximum number of retry attempts by the Send Engine for any phase of the PBAX transaction set before the operation is dropped and status bit are set. This does not count PowerBus overcommit retries unless snd_retry_count_overcom bit is set. 0x00 : No Timeout 0x01 : 1 attempt 0x02 : 2 attempts .etc. 0xFF : 255 attempts
36:40	RW	RW		PBAXICFG_SND_RSVTO_DIV: PBAX Send Reservation Timeout Divider Divider for the 500us PBAX hang pulse. A hang is detected after two divided hang pulses are received after attempting to acquire a reservation with the PBAX Receive engine before declaring a Send Reservation Timeout error. 00000 - Send Reservation Timeout is Disabled 00001 - divided hang pulse = PBAX hang pulse 00010 - divided hang pulse = PBAX hang pulse/2 00011 - divided hang pulse = PBAX hang pulse/3 . . . 11111 - divided hang pulse = PBAX hang pulse/31
41:63	RO	RO		constant=0b00000000000000000000000

PBA PBAX InterChip Send Status Register
Addr:	0000000000068032 (PIB) 00000000C0040190 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBAXISNDSTAT
Constant(s):
Comments:	This register contains status values of PBAX Send engine. Note: This set of registers is intended for GPE usage
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPBR.PBA.PBAO.OCIREG.PBAXISNDSTAT_Q_0_INST.LATC.L2(0:15) [0000000000000000]
Bit(s)	PIB	OCI		Dial: Description
0	ROX	ROX		PBAXISNDSTAT_SND_IN_PROGRESS: PBAX Send In Progress If PBAXCFG[pbax_en=1](enabled), this bit is asserted by the hardware upon a write to PBAX Send Data Register[datahi] of the last piece of message data through the duration of the PowerBus PMISC DataHi/DataLo phases for the last piece of message data. Hardware resets this bit upon detection of a valid CRESP of the last PMISC PBAX phase for the last piece of message data AND pulses the pba_occ_pbax_attn interrupt. If PBAXCFG[pbax_en=0 ](disabled), this bit will not be set and the PBAX PMISC is not forwarded.
1	ROX	ROX		PBAXISNDSTAT_SND_ERROR: PBAX Send Error This bit is set when an error is detected while sending a PBAX request. The detailed reasons for setting this error bit are defined in the PBAFIR(bits tbd). If the correspond bit is set in the PBAOCCACT register, the pba_occ_error output pin is asserted. This bit is cleared by writing PBAXCFG[snd_reset] = 1.
2:3	ROX	ROX		PBAXISNDSTAT_SND_PHASE_STATUS: PBAX Send Status(0 to 1) Reset to 0 upon the successful write of the PBAX Send DataHi Register. Dial enums: PHASE1_SENDING=>0b10 PHASE2_SENDING=>0b01
4:7	ROX	ROX		PBAXISNDSTAT_SND_CNT_STATUS: PBAX Send Count Status(0 to 3) Number of PBAX messages sent when snd_in_progress=1. If snd_cnt=0 (a single 8B message), this will stay zero when send_in_progress clears. If snd_cnt=xF, this will count up to xF when the last 8B are sent and snd_in_progress clears. Reset to 0 upon the successful write of the PBAX Send DataHi Register.
8:15	ROX	ROX		PBAXISNDSTAT_SND_RETRY_COUNT: PBAX Send Retry Count The maximum number of retries performed for any of the phases of an PBAX operation. Valid only when snd_in_progress=0 Reset to 0 upon the successful write of the PBAX Send DataHi Register.
16:63	RO	RO		constant=0b000000000000000000000000000000000000000000000000

PBAX Inter-Chip Receive Status Register
Addr:	0000000000068034 (PIB) 00000000C00401A0 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBAXIRCVSTAT
Constant(s):
Comments:	This register shows the status and progression of a incoming PBAX command through the PBAX Receive engine onto the Push queue. Note: This set of registers is intended for GPE usage
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:21	TP.TPBR.PBA.PBAO.OCIREG.PBAXIRCVSTAT_Q_0_INST.LATC.L2(0:21) [0000000000000000000000]
Bit(s)	PIB	OCI		Dial: Description
0	ROX	ROX		PBAXIRCVSTAT_RCV_IN_PROGRESS: PBAX Receive In Progress If pbax_en=1 (enabled), this bit is asserted by the hardware upon accepting a Pmisc PBAX DataHi phase operation. Hardware resets this bit when the OCI store operation completes. This bit is also reset if the PBAX detects an error and returns to the idle state. If PBAXSHCS [push_enable]=0 (disabled), this bit will not be set.
1	ROX	ROX		PBAXIRCVSTAT_RCV_ERROR: PBAX Receive Error This bit is set when an error is detected while receiving a PBAX request or writing it to the OCI. The detailed reasons for setting this error bit are defined in the PBAFIR(axrcv_**). If the correspond bit is set in the PBAOCCACT register, the pba_occ_error output pin is asserted. This bit is cleared by writing PBAXCFG [rcv_reset] = 1
2	ROX	ROX		PBAXIRCVSTAT_RCV_WRITE_IN_PROGRESS: PBAX Receive Write in Progress This bit is set when the PBAX is ready to forward to the OCI using the appropriate Push queue. It remains set until the write is complete.
3	ROX	ROX		PBAXIRCVSTAT_RCV_RESERVATION_SET: PBAX Receive Reservation Set This bit is set the PBAX Receive engine has accepted a reservation from the PBAX Send Engine. It remains set until the matching PBAX command has been received and written.
4:21	ROX	ROX		PBAXIRCVSTAT_RCV_CAPTURE: PBAX Receive Info Capture Captured when an error occurs while receiving a PMISC PBAX operation. Valid only if rcv_error is set. 4:7 powerbus source topologyID - ttag(0:3) 8:12 powerbus source unitID - ttag(4:8) 13:16 pbax_groupid 17:19 pbax_chipid 20 pbax_type 21 pbax_qid.
22:63	RO	RO		constant=0b000000000000000000000000000000000000000000

PBAX Inter-Chip Push Base 0 Register
Addr:	0000000000068036 (PIB) 00000000C00401B0 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBAXISHBR0
Constant(s):
Comments:	Note: This set of registers is intended for GPE usage
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:28	TP.TPBR.PBA.PBAO.OCIREG.PUSHQI#0.Q.PBAXSHBR_Q_0_INST.LATC.L2(0:28) [00000000000000000000000000000]
Bit(s)	PIB	OCI		Dial: Description
0:28	RW	RW		PBAXISHBR0_PUSH_START: PBAX Push Queue Start Starting address of Push Queue (aligned to the length of the queue 8B to 256B.) Bits(0:1) of this address should be set to 11 to target the SRAM.
29:63	RO	RO		constant=0b00000000000000000000000000000000000

PBAX Inter-Chip Push Control/Status 0 Register
Addr:	0000000000068037 (PIB) 00000000C00401B8 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBAXISHCS0
Constant(s):
Comments:	Controls the behavior of Push Queue n. Writes to this register cause the queue hardware to be reset when the PBAXIRCVSTAT[rcv_in_progress]=0. Writes to all bits except for push_en are ignored when PBAXIRCVSTAT [ rcv_in_progress ] = 1. Firmware should read the register after writing to verify. Note: This set of registers is intended for GPE usage
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.PBA.PBAO.OCIREG.PUSHQI#0.Q.PUSH_FULL_Q_INST.LATC.L2(0) [0]
	1	TP.TPBR.PBA.PBAO.OCIREG.PUSHQI#0.Q.PUSH_EMPTY_Q_INST.LATC.L2(0) [0]
	2:10	TP.TPBR.PBA.PBAO.OCIREG.PUSHQI#0.Q.PBAXSHCS_Q_0_INST.LATC.L2(0:8) [000000000]
	13:17	TP.TPBR.PBA.PBAO.OCIREG.PUSHQI#0.Q.PUSH_WRITE_PTR_Q_0_INST.LATC.L2(0:4) [00000]
	21:25	TP.TPBR.PBA.PBAO.OCIREG.PUSHQI#0.Q.PUSH_READ_PTR_Q_0_INST.LATC.L2(0:4) [00000]
	31	TP.TPBR.PBA.PBAO.OCIREG.PUSHQI#0.Q.PBAXSHCS_Q_0_INST.LATC.L2(9) [0]
Bit(s)	PIB	OCI		Dial: Description
0	RWX_WCLRPART	RWX_WCLRPART		PBAXISHCS0_PUSH_FULL: Push Queue Full Reads indicate the Push Queue is full condition Any write to this register clears this indicator and clears push_write_ptr and push_read_ptr to 0s. (this is a means for resetting the queue hardware) Dial enums: NOT_FULL=>0b0 FULL=>0b1
1	RWX_WSETPART	RWX_WSETPART		PBAXISHCS0_PUSH_EMPTY: Push Queue Empty Any write to this register sets this indicator and clears push_write_ptr and push_read_ptr to 0s. (this is a means for resetting the queue hardware) Dial enums: NOT_EMPTY=>0b0 EMPTY=>0b1
2:3	RW	RW		PBAXISHCS0_RESERVED_2_3: Spare
4:5	RW	RW		PBAXISHCS0_PUSH_INTR_ACTION_0_1: Push Interrupt Action This field controls the condition which will assert the push interrupt signal (pba_occ_push0/1] for this channel to the OCB interrupt controller. b00 - Full (default upon hardware init) b01 - Not Full b10 - Empty b11 - Not Empty (doorbell queue setting)
6:10	RW	RW		PBAXISHCS0_PUSH_LENGTH: Push Queue length These bits define the depth of the Push Queue. (push_length +1) * 8B. This value may be changed only when push_enable=- and PBAXRCVSTAT[rcv_in_progress]=0. Value mapping: 0b00000: 8B (1 entry) 0b00001: 16B (2 entry) 0b00010: 24B (3 entry) 0b00011: 32B (4 entry) .etc. 0b11111: 256B (32 entry)
11:12	RO	RO		constant=0b00
13:17	RWX_WCLRPART	RWX_WCLRPART		PBAXISHCS0_PUSH_WRITE_PTR: Push write pointer Reads indicate the current Push Queue write pointer in increments of 8B. The actual address used is push_start + push_write_ptr || 000. Writes to this field are ignored. Hardware performs all modifications. This field is cleared upon a write to this register.
18:20	RO	RO		constant=0b000
21:25	RWX_WCLRPART	RWX_WCLRPART		PBAXISHCS0_PUSH_READ_PTR: Push read pointer Reads indicate the current Push Queue read pointer in increments of 8B. The actual address used is push_start + push_read_ptr || 000. This field is cleared upon a write to this register.
26:30	RO	RO		constant=0b00000
31	RW	RW		PBAXISHCS0_PUSH_ENABLE: Push Queue Enable If Disabled, PMISC PBAX commands are ignored and an error indication is set. Note: OCI Writes to PBAX Push Increment 0 Register to cause incrementation and any side effects are unaffected by the setting of this bit. Dial enums: DISABLED=>0b0 ENABLED=>0b1
32:63	RO	RO		constant=0b00000000000000000000000000000000 Dial enums: DISABLED=>0b0 ENABLED=>0b1

PBAX Inter-Chip Push Increment 0 Register
Addr:	0000000000068038 (PIB) 00000000C00401C0 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBAXISHINC0
Constant(s):
Comments:	Writes to this register cause the Push Queue Read pointer to increment by 1 modulo the Push Queue Size and will do so independent of the setting of PBAX Push Control/Status 0 Register[push_enable].
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	PIB	OCI		Dial: Description
0:63	RO	RO		constant=0b0000000000000000000000000000000000000000000000000000000000000000

PBAX Inter-Chip Push Base 1 Register
Addr:	000000000006803A (PIB) 00000000C00401D0 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBAXISHBR1
Constant(s):
Comments:	Note: This set of registers is intended for GPE usage
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:28	TP.TPBR.PBA.PBAO.OCIREG.PUSHQI#1.Q.PBAXSHBR_Q_0_INST.LATC.L2(0:28) [00000000000000000000000000000]
Bit(s)	PIB	OCI		Dial: Description
0:28	RW	RW		PBAXISHBR1_PUSH_START: PBAX Push Queue Start Starting address of Push Queue (aligned to the length of the queue 8B to 256B.) Bits(0:1) of this address should be set to 11 to target the SRAM.
29:63	RO	RO		constant=0b00000000000000000000000000000000000

PBAX Inter-Chip Push Control/Status 1 Register
Addr:	000000000006803B (PIB) 00000000C00401D8 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBAXISHCS1
Constant(s):
Comments:	Controls the behavior of Push Queue n. Writes to this register cause the queue hardware to be reset when the PBAXIRCVSTAT[rcv_in_progress]=0. Writes to all bits except for push_en are ignored when PBAXIRCVSTAT [ rcv_in_progress ] = 1. Firmware should read the register after writing to verify. Note: This set of registers is intended for GPE usage
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.PBA.PBAO.OCIREG.PUSHQI#1.Q.PUSH_FULL_Q_INST.LATC.L2(0) [0]
	1	TP.TPBR.PBA.PBAO.OCIREG.PUSHQI#1.Q.PUSH_EMPTY_Q_INST.LATC.L2(0) [0]
	2:10	TP.TPBR.PBA.PBAO.OCIREG.PUSHQI#1.Q.PBAXSHCS_Q_0_INST.LATC.L2(0:8) [000000000]
	13:17	TP.TPBR.PBA.PBAO.OCIREG.PUSHQI#1.Q.PUSH_WRITE_PTR_Q_0_INST.LATC.L2(0:4) [00000]
	21:25	TP.TPBR.PBA.PBAO.OCIREG.PUSHQI#1.Q.PUSH_READ_PTR_Q_0_INST.LATC.L2(0:4) [00000]
	31	TP.TPBR.PBA.PBAO.OCIREG.PUSHQI#1.Q.PBAXSHCS_Q_0_INST.LATC.L2(9) [0]
Bit(s)	PIB	OCI		Dial: Description
0	RWX_WCLRPART	RWX_WCLRPART		PBAXISHCS1_PUSH_FULL: Push Queue Full Reads indicate the Push Queue is full condition Any write to this register clears this indicator and clears push_write_ptr and push_read_ptr to 0s. (this is a means for resetting the queue hardware) Dial enums: NOT_FULL=>0b0 FULL=>0b1
1	RWX_WSETPART	RWX_WSETPART		PBAXISHCS1_PUSH_EMPTY: Push Queue Empty Any write to this register sets this indicator and clears push_write_ptr and push_read_ptr to 0s. (this is a means for resetting the queue hardware) Dial enums: NOT_EMPTY=>0b0 EMPTY=>0b1
2:3	RW	RW		PBAXISHCS1_RESERVED_2_3: Spare
4:5	RW	RW		PBAXISHCS1_PUSH_INTR_ACTION_0_1: Push Interrupt Action This field controls the condition which will assert the push interrupt signal (pba_occ_push0/1] for this channel to the OCB interrupt controller. b00 - Full (default upon hardware init) b01 - Not Full b10 - Empty b11 - Not Empty (doorbell queue setting)
6:10	RW	RW		PBAXISHCS1_PUSH_LENGTH: Push Queue length These bits define the depth of the Push Queue. (push_length +1) * 8B. This value may be changed only when push_enable=- and PBAXRCVSTAT[rcv_in_progress]=0. Value mapping: 0b00000: 8B (1 entry) 0b00001: 16B (2 entry) 0b00010: 24B (3 entry) 0b00011: 32B (4 entry) .etc. 0b11111: 256B (32 entry)
11:12	RO	RO		constant=0b00
13:17	RWX_WCLRPART	RWX_WCLRPART		PBAXISHCS1_PUSH_WRITE_PTR: Push write pointer Reads indicate the current Push Queue write pointer in increments of 8B. The actual address used is push_start + push_write_ptr || 000. Writes to this field are ignored. Hardware performs all modifications. This field is cleared upon a write to this register.
18:20	RO	RO		constant=0b000
21:25	RWX_WCLRPART	RWX_WCLRPART		PBAXISHCS1_PUSH_READ_PTR: Push read pointer Reads indicate the current Push Queue read pointer in increments of 8B. The actual address used is push_start + push_read_ptr || 000. This field is cleared upon a write to this register.
26:30	RO	RO		constant=0b00000
31	RW	RW		PBAXISHCS1_PUSH_ENABLE: Push Queue Enable If Disabled, PMISC PBAX commands are ignored and an error indication is set. Note: OCI Writes to PBAX Push Increment 1 Register to cause incrementation and any side effects are unaffected by the setting of this bit. Dial enums: DISABLED=>0b0 ENABLED=>0b1
32:63	RO	RO		constant=0b00000000000000000000000000000000 Dial enums: DISABLED=>0b0 ENABLED=>0b1

PBAX Inter-Chip Push Increment 1 Register
Addr:	000000000006803C (PIB) 00000000C00401E0 (OCI)
Name:	TP.TPBR.PBA.PBAO.PBAXISHINC1
Constant(s):
Comments:	Writes to this register cause the Push Queue Read pointer to increment by 1 modulo the Push Queue Size and will do so independent of the setting of PBAX Push Control/Status 0 Register[push_enable].
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	PIB	OCI		Dial: Description
0:63	RO	RO		constant=0b0000000000000000000000000000000000000000000000000000000000000000

SRAM SRAM Mode Register
Addr:	000000000006A001 (SCOM) 00000000C0050008 (OCI)
Name:	TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_SRMR
Constant(s):	PU_SRAM_SRMR
Comments:	This register estashishes implemented modes of the SRAM controller.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_REGISTERS.SRMR_Q_0_INST.LATC.L2(0:15) [0000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	RW	RW		SRAM_SRMR_SRAM_ENABLE_REMAP: SRAM Enable Remap When this bit is set, the SRAM will remap an OCI request that targets within the 64-byte address in the SRMAP[sram_remap_source] to the address defined in the SRMAP[sram_remap_dest].
1	RW	RW		SRAM_SRMR_SRAM_ARB_EN_SEND_ALL_WRITES: SRAM Arbiter Send all Writes 0 - the internal SRAM Arbiter will prioritize just one pending write over read operations when the dispatch logic has indicated writes must be prioritized. 1 - the internal SRAM Arbiter will prioritize all pending write operations over read operations when the dispatch logic has indicated writes must be pioritized.
2	RW	RW		SRAM_SRMR_SRAM_DISABLE_LFSR: SRAM Dispatcher LFSR Disable 0 - allows LFSR in dispatcher to pseudo randomly rearb instead of addrack a PLB request 1 - disables LFSR in dispatcher
3:7	RW	RW		SRAM_SRMR_SRAM_LFSR_FAIRNESS_MASK: LFSR Fairness Mask this is a 5-bit mask for the LFSR pre-match. Mask bits control probability from 2:1 to 64:1 (ie. all bits set in the mask and only one bit needs to match)
8	RW	RW		SRAM_SRMR_SRAM_ERROR_INJECT_ENABLE: Error Injection Enable 0 - disable error inject logic in the SRAM tanks 1 - enables error inject logic in the SRAM tanks
9	RW	RW		SRAM_SRMR_SRAM_CTL_TRACE_EN: SRAM trace bus enable use to turn on/off trace bus logic for power savings
10	RW	RW		SRAM_SRMR_SRAM_CTL_TRACE_SEL: SRAM trace bus select 0 - select group 0 1 - selects group 1
11:15	RW	RW		SRAM_SRMR_SPARE: Implemented but unused
16:63	RO	RO		constant=0b000000000000000000000000000000000000000000000000

SRAM SRAM Remap Register
Addr:	000000000006A002 (SCOM) 00000000C0050010 (OCI)
Name:	TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_SRMAP
Constant(s):	PU_SRAM_SRMAP
Comments:	This register defines the 64-byte address range that is remapped
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:13	TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_REGISTERS.SRMAP_Q_0_INST.LATC.L2(0:13) [00000000000000]
	16:29	TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_REGISTERS.SRMAP_Q_0_INST.LATC.L2(14:27) [00000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:13	RW	RW		SRAM_SRMAP_SRAM_REMAP_SOURCE: SRAM source address to remap. A write or read that targets the SRAM and matches oci address[12:25] will automatically be remapped to the SRAM Destination address instead. Use of this register must be enabled in SRMOD[sram_enable_remap].
14:15	RO	RO		constant=0b00
16:29	RW	RW		SRAM_SRMAP_SRAM_REMAP_DEST: SRAM Destination address to remap. When a remap match has occurred, the oci address(12:25) is changed to this destination address when forwarded to the SRAM Tanklets.
30:63	RO	RO		constant=0b0000000000000000000000000000000000

SRAM SRAM Error Address Register
Addr:	000000000006A003 (SCOM) 00000000C0050018 (OCI)
Name:	TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_SREAR
Constant(s):	PU_SRAM_SREAR
Comments:	This register captures the read address when a read error occurs in the tanks
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:16	TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_REGISTERS.SREAR_Q_0_INST.LATC.L2(0:16) [00000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:16	RWX	RWX		SRAM_SREAR_SRAM_ERROR_ADDRESS: SRAM Error Address (capture of OCI address bits [12:28]). The first read error encountered will cause the address to be stored. Subsequent read errors will not overwrite this initial captured address until this register is written. This register can be written via an OCI write with any value, so to clear it requires an OCI write of all 0s. Note: The fail address of a partial write (RMW) to a line with an ECC error is not captured.
17:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000

SRAM SRAM Boot Vector Word 0 Register
Addr:	000000000006A004 (SCOM) 00000000C0050020 (OCI)
Name:	TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_SRBV0
Constant(s):	PU_SRAM_SRBV0
Comments:	This register contains boot vector instruction word 0
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_REGISTERS.SRBV0_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RW	RW		SRAM_SRBV0_BOOT_VECTOR_WORD0: Boot Vector Word 0 instruction word 0 returned from SRAM when PPC405 fetches from boot vector address. This register corresponds to address 0xFFFFFFF0 of the cacheline holding the boot vector.
32:63	RO	RO		constant=0b00000000000000000000000000000000

SRAM SRAM Boot Vector Word1 Register
Addr:	000000000006A005 (SCOM) 00000000C0050028 (OCI)
Name:	TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_SRBV1
Constant(s):	PU_SRAM_SRBV1
Comments:	This register contains boot vector instruction word 1
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_REGISTERS.SRBV1_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RW	RW		SRAM_SRBV1_BOOT_VECTOR_WORD1: Boot Vector Word 1 instruction word 1 returned from SRAM when PPC405 fetches from boot vector address.This register corresponds to address 0xFFFFFFF4 of the cacheline holding the boot vector.
32:63	RO	RO		constant=0b00000000000000000000000000000000

SRAM SRAM Boot Vector Word 2 Register
Addr:	000000000006A006 (SCOM) 00000000C0050030 (OCI)
Name:	TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_SRBV2
Constant(s):	PU_SRAM_SRBV2
Comments:	This register contains boot vector instruction word 2
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_REGISTERS.SRBV2_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RW	RW		SRAM_SRBV2_BOOT_VECTOR_WORD2: Boot Vector Word 2 instruction word 2 returned from SRAM when PPC405 fetches from boot vector address. This register corresponds to address 0xFFFFFFF8 of the cacheline holding the boot vector.
32:63	RO	RO		constant=0b00000000000000000000000000000000

SRAM SRAM Boot Vector Word 3 Register
Addr:	000000000006A007 (SCOM) 00000000C0050038 (OCI)
Name:	TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_SRBV3
Constant(s):	PU_SRAM_SRBV3
Comments:	This register contains boot vector instruction word 3
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_REGISTERS.SRBV3_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RW	RW		SRAM_SRBV3_BOOT_VECTOR_WORD3: Boot Vector Word 3 instruction word 3 returned from SRAM when PPC405 fetches from boot vector address. This register corresponds to address 0xFFFFFFFC of the cacheline holding the boot vector. Init value is a Branch Absolute 0x00000010
32:63	RO	RO		constant=0b00000000000000000000000000000000

SRAM SRAM Chicken Switch Register
Addr:	000000000006A008 (SCOM) 00000000C0050040 (OCI)
Name:	TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_SRCHSW
Constant(s):	PU_SRAM_SRCHSW
Comments:	This register contains chicken switches for SRAM controller
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:9	TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_REGISTERS.SRCHSW_Q_0_INST.LATC.L2(0:9) [0000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	RW	RW		SRAM_SRCHSW_CHKSW_WRFSM_DLY_DIS: Disables the default 3 cycle delay (PLB read request window) of a dispatched write machines request to arbiter
1	RW	RW		SRAM_SRCHSW_CHKSW_ALLOW1_RD: Allows one read at a time
2	RW	RW		SRAM_SRCHSW_CHKSW_ALLOW1_WR: Allows one write at a time
3	RW	RW		SRAM_SRCHSW_CHKSW_ALLOW1_RDWR: Allows one read or one write at a time
4	RW	RW		SRAM_SRCHSW_CHKSW_OCI_PARCHK_DIS: Disables parity checking on PLB inputs
5	RW	RW		SRAM_SRCHSW_CHKSW_TANK_RDDATA_PARCHK_DIS: Disables parity checking on tank read data
6	RW	RW		SRAM_SRCHSW_CHKSW_SPARE_6: spare
7	RW	RW		SRAM_SRCHSW_CHKSW_VAL_BE_ADDR_CHK_DIS: Disable valid byte enable and address checking in dispatcher
8:9	RW	RW		SRAM_SRCHSW_CHKSW_SO_SPARE: Spares
10:63	RO	RO		constant=0b000000000000000000000000000000000000000000000000000000

OCB_OCI OCC Interrupt Source 0 Register
Addr:	000000000006C000 (SCOM) 000000000006C001 (SCOM1) 000000000006C002 (SCOM2) 00000000C0060000 (OCI) 00000000C0060008 (OCI1) 00000000C0060010 (OCI2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OISR0
Constant(s):	PU_OCB_OCI_OISR0
Comments:	This register indicates the pending interrupts to the OCC as enabled by the OIMR0 and configured by the combination of OITR0 (Edge or Level) and OIEPR0 (Significant Edge or Polarity). See notes on OITR0 on the set (for injection) or clearing (for interrupt handling) of the bit in this register. These interrupts are used by Hcode.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_SRC0_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	OCI	OCI1	OCI2	Dial: Description
0	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_TRACE_TRIGGER: Asserted if the trace array logic analyzer logic has detected a trigger condition. CHANGE_EFFECT { if (~OIMR0 && ((~OITR0 && ~(OIEPR0 ^ OINKR0)) | ( OITR0 && ( OIEPR0 && (~OINKR0 ^ OISR0)) | (~OIEPR0 && OINKR0 ^ ~OISR0) ))) { if (~OIRR0A && ~OIRR0B && ~OIRR0C) ONISR0=1; if (~OIRR0A && ~OIRR0B && OIRR0C) OCISR0=1; if (~OIRR0A && OIRR0B && ~OIRR0C) OUISR0=1; if (~OIRR0A && OIRR0B && OIRR0C) ODISR0=1; if ( OIRR0A && ~OIRR0B && ~OIRR0C) G0ISR0=1; if ( OIRR0A && ~OIRR0B && OIRR0C) G1ISR0=1; if ( OIRR0A && OIRR0B && ~OIRR0C) G2ISR0=1; if ( OIRR0A && OIRR0B && OIRR0C) G3ISR0=1; OINKR0=1; } else { if (~OIRR0A && ~OIRR0B && ~OIRR0C) ONISR0=0; if (~OIRR0A && ~OIRR0B && OIRR0C) OCISR0=0; if (~OIRR0A && OIRR0B && ~OIRR0C) OUISR0=0; if (~OIRR0A && OIRR0B && OIRR0C) ODISR0=0; if ( OIRR0A && ~OIRR0B && ~OIRR0C) G0ISR0=0; if ( OIRR0A && ~OIRR0B && OIRR0C) G1ISR0=0; if ( OIRR0A && OIRR0B && ~OIRR0C) G2ISR0=0; if ( OIRR0A && OIRR0B && OIRR0C) G3ISR0=0; OINKR0=0; } } // Note: GxISR0[0] must be a chained action
1	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_OCC_ERROR: OCC LFIR recoverable interrupt wire. Indicates an unmasked OCC LFIR with action0/1="10" has asserted
2	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_GPE2_ERROR: Indicates the GPE2 reported an error that caused it to halt. Implemented as an OR of the four error outputs from the PPE.
3	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_GPE3_ERROR: Indicates the GPE3 reported an error that caused it to halt. Implemented as an OR of the four error outputs from the PPE.
4	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_CHECK_STOP_GPE2: Indicates system checkstop detected, use to interrupt the GPE2.
5	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_CHECK_STOP_GPE3: Indicates system checkstop detected, use to interrupt the GPE3.
6	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_OCC_MALF_ALERT: OCC LFIR classified as a malfunction alert.
7	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_PVREF_ERROR: Indicates that the Precision Voltage Reference (PVREF) circuit has detected an error and that iVRMs should be taken out of regulation. This interrupt is intended to be directed to the P-GPE. The signals forming this indication are located in the OCCMISC.
8	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_IPI2: Inter-processor interrupt 2 Allows synchronization between critical and non-critical code. The physical input is tied low. To inject an interrupt, please reference the Engineering Note in the OITR.
9	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_IPI3: Inter-processor interrupt 3 Allows synchronization between critical and non-critical code. The physical input is tied low. To inject an interrupt, please reference the Engineering Note in the OITR.
10	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_DEBUG_TRIGGER: Implemented but unused. The physical input is tied low.
11	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_SPARE: Implemented but unused. The physical input is tied low.
12	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_PBAX_PGPE_ATTN: Indicates that the PBAX send engine is busy. Falling edge indicates it is complete.
13	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_PBAX_PGPE_PUSH0: Indicates that PBA Streaming Channel 0 Push Queue has detected interrupt condition
14	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_PBAX_PGPE_PUSH1: Indicates that PBA Streaming Channel 1 Push Queue has detected interrupt condition
15	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_PBA_OVERCURRENT_INDICATOR: Async wire from Lightweight Estimation Engine in PBA.
16	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_PMC_PCB_INTR_TYPE0_PENDING: Indicates that a PCB type 0 interrupt is pending XDEV_CONNECT { OCB_BASE.OISR0.pmc_pcb_intr_type0_pending = OCB_AGEN. OPIT0PRa_OR }
17	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_PMC_PCB_INTR_TYPE1_PENDING: Indicates that a PCB type 1 interrupt is pending XDEV_CONNECT { OCB_BASE.OISR0.pmc_pcb_intr_type1_pending = OCB_AGEN. OPIT1PRa_OR }
18	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_PMC_PCB_INTR_TYPE2_PENDING: Indicates that a PCB type 2 interrupt is pending XDEV_CONNECT { OCB_BASE.OISR0.pmc_pcb_intr_type2_pending = OCB_AGEN. OPIT2PRa_OR }
19	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_PMC_PCB_INTR_TYPE3_PENDING: Indicates that a PCB type 3 interrupt is pending XDEV_CONNECT { OCB_BASE.OISR0.pmc_pcb_intr_type3_pending = OCB_AGEN. OPIT3PRa_OR }
20	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_PMC_PCB_INTR_TYPE4_PENDING: Indicates that a PCB type 4 interrupt is pending XDEV_CONNECT { OCB_BASE.OISR0.pmc_pcb_intr_type4_pending = OCB_AGEN. OPIT4PRa_OR }
21	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_PMC_PCB_INTR_TYPE5_PENDING: Indicates that a PCB type 5 interrupt is pending XDEV_CONNECT { OCB_BASE.OISR0.pmc_pcb_intr_type5_pending = OCB_AGEN. OPIT5PRa_OR }
22	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_PMC_PCB_INTR_TYPE6_PENDING: Indicates that a PCB type 6 interrupt is pending XDEV_CONNECT { OCB_BASE.OISR0.pmc_pcb_intr_type6_pending = OCB_AGEN. OPIT6PRa_OR }
23	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_PMC_PCB_INTR_TYPE7_PENDING: Indicates that a PCB type 7 interrupt is pending XDEV_CONNECT { OCB_BASE.OISR0.pmc_pcb_intr_type7_pending = OCB_AGEN. OPIT7PRa_OR }
24	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_PMC_PCB_INTR_TYPE8_PENDING: Indicates that a PCB type 8 interrupt is pending XDEV_CONNECT { OCB_BASE.OISR0.pmc_pcb_intr_type8_pending = OCB_AGEN. OPIT8PRb_OR }
25	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_PMC_PCB_INTR_TYPE9_PENDING: Indicates that a PCB type 9 interrupt is pending XDEV_CONNECT { OCB_BASE.OISR0.pmc_pcb_intr_type9_pending = OCB_AGEN. OPIT9PRb_OR }
26	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_PMC_PCB_INTR_TYPEA_PENDING: Indicates that a PCB type A interrupt is pending XDEV_CONNECT { OCB_BASE.OISR0.pmc_pcb_intr_typeA_pending = OCB_AGEN. OPITAPRc_OR }
27	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_PMC_PCB_INTR_TYPEB_PENDING: Indicates that a PCB type B interrupt is pending XDEV_CHANGE { OCB_BASE.OISR0.pmc_pcb_intr_typeB_pending = OCB_AGEN. OPITBPRc_OR }
28	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_PMC_PCB_INTR_TYPEC_PENDING: Indicates that a PCB type C interrupt is pending XDEV_CONNECT { OCB_BASE.OISR0.pmc_pcb_intr_typeC_pending = OCB_AGEN. OPITCPRc_OR }
29	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_PMC_PCB_INTR_TYPED_PENDING: Indicates that a PCB type D interrupt is pending XDEV_CONNECT { OCB_BASE.OISR0.pmc_pcb_intr_typeD_pending = OCB_AGEN. OPITDPRc_OR }
30	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_PMC_PCB_INTR_TYPEE_PENDING: Indicates that a PCB type E interrupt is pending XDEV_CONNECT { OCB_BASE.OISR0.pmc_pcb_intr_typeE_pending = OCB_AGEN. OPITEPRd_OR }
31	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR0_PMC_PCB_INTR_TYPEF_PENDING: Indicates that a PCB type F interrupt is pending XDEV_CONNECT { OCB_BASE.OISR0.pmc_pcb_intr_typeF_pending = OCB_AGEN. OPITFPRd_OR }
32:63	RO	RO	RO	RO	RO	RO	constant=0b00000000000000000000000000000000

OCB_OCI OCC Interrupt Mask 0 Register
Addr:	000000000006C004 (SCOM) 000000000006C005 (SCOM1) 000000000006C006 (SCOM2) 00000000C0060020 (OCI) 00000000C0060028 (OCI1) 00000000C0060030 (OCI2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIMR0
Constant(s):	PU_OCB_OCI_OIMR0
Comments:	This register masks IOISR0 interrupts to the OCC complex
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_MASK0_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	OCI	OCI1	OCI2	Dial: Description
0:31	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OIMR0_INTERRUPT_MASK_0: See OCC Interrupt Source 0 for bit definitions Masks the respective event from producing an interrupt to the OCC complex engines. The events are still captured in the OISR but are not reported via interrupt signals. 0 = Not Masked (e.g. Enabled) 1 = Masked WRITE_EFFECT { if (~OIMR0 && ((~OITR0 && ~(OIEPR0 ^ OINKR0 )) | ( OITR0 && ( OIEPR0 && (~OINKR0 ^ OISR0)) | (~OIEPR0 && OINKR0 ^ ~OISR0) ))) { if (~OIRR0A && ~OIRR0B && ~OIRR0C) ONISR0=1; if (~OIRR0A && ~OIRR0B && OIRR0C) OCISR0=1; if (~OIRR0A && OIRR0B && ~OIRR0C) OUISR0=1; if (~OIRR0A && OIRR0B && OIRR0C) ODISR0=1; if ( OIRR0A && ~OIRR0B && ~OIRR0C) G0ISR0=1; if ( OIRR0A && ~OIRR0B && OIRR0C) G1ISR0=1; if ( OIRR0A && OIRR0B && ~OIRR0C) G2ISR0=1; if ( OIRR0A && OIRR0B && OIRR0C) G3ISR0=1; OINKR0=1; } else { if (~OIRR0A && ~OIRR0B && ~OIRR0C) ONISR0=0; if (~OIRR0A && ~OIRR0B && OIRR0C) OCISR0=0; if (~OIRR0A && OIRR0B && ~OIRR0C) OUISR0=0; if (~OIRR0A && OIRR0B && OIRR0C) ODISR0=0; if ( OIRR0A && ~OIRR0B && ~OIRR0C) G0ISR0=0; if ( OIRR0A && ~OIRR0B && OIRR0C) G1ISR0=0; if ( OIRR0A && OIRR0B && ~OIRR0C) G2ISR0=0; if ( OIRR0A && OIRR0B && OIRR0C) G3ISR0=0; OINKR0=0; } } // Note: GxISR0[0] must be a chained action
32:63	RO	RO	RO	RO	RO	RO	constant=0b00000000000000000000000000000000

OCB_OCI OCC Interrupt Type 0 Register
Addr:	000000000006C008 (SCOM) 000000000006C009 (SCOM1) 000000000006C00A (SCOM2) 00000000C0060040 (OCI) 00000000C0060048 (OCI1) 00000000C0060050 (OCI2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OITR0
Constant(s):	PU_OCB_OCI_OITR0
Comments:	This register establishes the type of OISR0 interrupt that is monitored - level or edge
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_TYPE0_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	OCI	OCI1	OCI2	Dial: Description
0:31	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OITR0_INTERRUPT_TYPE_0: See OCC Interrupt Source 0 for bit definitions Establish the type of interrupt that is monitored. 0 = Level 1 = Edge When set to "Level": the respective OISR0 bit follows the value of the associated input source, with the polarity defined by the OIEPR0. Note: With this setting, direct OCI writes to the OISR0 bit should never be attempted, since the value will not be held and will immediately return to its previous state. When set to "Edge": the respective OISR0 bit will be set upon the transition (as defined by the OIEPR0) of the associated input source. Specifically, if the respective OIEPR0 bit is set to "Rising", a transition from 0 to 1 sets the bit; if the respective OIEPR0 bit is set to "Falling", a transition from 1 to 0 sets the bit. In this mode, the only way to clear the OISR0 bit is via a direct OCI write-CLEAR. Additionally, firmware can inject interrupts by direct OISR write- OR to the bit (where the OIEPR0 setting is a dont care). Engineering Note For firmware testing, a potential interrupt injection technique for "Level" interrupts is to override their definition to "Edge" and then use the OR register associated with the OISR0. This will allow the injected transition to stick as the logic will not follow the input interrupt signal. However, if the firmware is expecting to find status in the driving unit, this technique may not be appropriate, so it would make more sense to have the driving unit provide an interrupt inject mechanism itself. Interrupt bits intended for firmware use. i.e. not driven by a hardware source, are typically tied low unless otherwise specified. The preferred mechanism for injecting interrupts is to configure these bits as an "Edge" and use OR and CLEAR write operations to control the value of the interrupt.
32:63	RO	RO	RO	RO	RO	RO	constant=0b00000000000000000000000000000000

OCB_OCI OCC Interrupt Edge/Polarity 0 Register
Addr:	000000000006C00C (SCOM) 000000000006C00D (SCOM1) 000000000006C00E (SCOM2) 00000000C0060060 (OCI) 00000000C0060068 (OCI1) 00000000C0060070 (OCI2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIEPR0
Constant(s):	PU_OCB_OCI_OIEPR0
Comments:	This register establishes either the significant edge of a edge enabled OISR0 interrupt or the significant polarity of a level enabled that will be detected for enabled interrupt sources.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_EDGPOL0_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	OCI	OCI1	OCI2	Dial: Description
0:31	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OIEPR0_INTERRUPT_EDGE_POL_0: See OCC Interrupt Source 0 for bit definitions Establish the edge or polarity of interrupt. 0 = Falling/Low 1 = Rising/High When set the respective bit in the OITR0 is set to "Level", then the "Low" and "High" meanings apply as follows: If this bit is set to "Low", the respective OISR0 bit follows the inverted input to the OISR from the unit driving the signal. If this bit is set to "High", the respective OISR0 bit follows the direct input to the OISR0 from the unit driving the signal When set the respective bit in the OITR0 is set to "Edge", then the "Falling" and "Rising" meanings apply as follows: If this bit is set to "Falling", a transition from 1 to 0 of the input signal to the OISR0 sets the respective OISR0 bit. If this bit is set to "Rising", a transition from 0 to 1 of the input signal to the OISR0 sets the respective OISR0 bit.
32:63	RO	RO	RO	RO	RO	RO	constant=0b00000000000000000000000000000000

OCB_OCI OCC Interrupt Input 0 Knowledge Register
Addr:	000000000006C010 (SCOM) 00000000C0060080 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OINKR0
Constant(s):
Comments:	This register reflects the raw value of the input feeding the OISR0 for debug purposes.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_SRC0_DELAY_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_OINKR0_INTERRUPT_INPUT_0: See OCC Interrupt Source 0 for bit definitions. This reflects the raw value of the input feeding the OISR0, before being modified by the OITR, OIPR, or OIMR.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCC Interrupt Source 1 Register
Addr:	000000000006C020 (SCOM) 000000000006C021 (SCOM1) 000000000006C022 (SCOM2) 00000000C0060100 (OCI) 00000000C0060108 (OCI1) 00000000C0060110 (OCI2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OISR1
Constant(s):	PU_OCB_OCI_OISR1
Comments:	This register indicates the pending interrupts to the OCC as enabled by the OIMR and configured by the combination of OITR (Edge or Level) and OIEPR (Significant Edge or Polarity). See notes on OITR on the set (for injection) or clearing (for interrupt handling) of the bit in this register. These interrupts are used by the PPC405, GPE0 and GPE1
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_SRC1_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	OCI	OCI1	OCI2	Dial: Description
0	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_DEBUGGER: Debugger software on the FSP uses this bit to produce an interrupt. The physical input is tied low. The respective OITR bit must be set to "Edge" so that a WOR to this register will produce an interrupt. Lab/workaround hook. WRITE_EFFECT { if (~OIMR1 && ((~OITR1 && ~(OIEPR1 ^ OINKR1)) | ( OITR1 && ( OIEPR1 && (~OINKR1 ^ OISR1)) | (~OIEPR1 && OINKR1 ^ ~OISR1) ))) { if (~OIRR1A && ~OIRR1B && ~OIRR1C) ONISR1=1; if (~OIRR1A && ~OIRR1B && OIRR1C) OCISR1=1; if (~OIRR1A && OIRR1B && ~OIRR1C) OUISR1=1; if (~OIRR1A && OIRR1B && OIRR1C) ODISR1=1; if ( OIRR1A && ~OIRR1B && ~OIRR1C) G0ISR1=1; if ( OIRR1A && ~OIRR1B && OIRR1C) G1ISR1=1; if ( OIRR1A && OIRR1B && ~OIRR1C) G2ISR1=1; if ( OIRR1A && OIRR1B && OIRR1C) G3ISR1=1; OINKR1=1; } else { if (~OIRR1A && ~OIRR1B && ~OIRR1C) ONISR1=0; if (~OIRR1A && ~OIRR1B && OIRR1C) OCISR1=0; if (~OIRR1A && OIRR1B && ~OIRR1C) OUISR1=0; if (~OIRR1A && OIRR1B && OIRR1C) ODISR1=0; if ( OIRR1A && ~OIRR1B && ~OIRR1C) G0ISR1=0; if ( OIRR1A && ~OIRR1B && OIRR1C) G1ISR1=0; if ( OIRR1A && OIRR1B && ~OIRR1C) G2ISR1=0; if ( OIRR1A && OIRR1B && OIRR1C) G3ISR1=0; OINKR1=0; } } // Note: GxISR1[0] must be a chained action
1	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_TRACE_TRIGGER: Asserted if the trace array logic analyzer logic has detected a trigger condition.
2	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_SPARE: Implemented but unused. The physical input is tied low.
3	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_PBA_ERROR: Indicates that the attached PBA detected an error. This signal is asserted for an error that sets a bit in the PBA_FIR and also has the corresponding bit set in the PBA_OCC_ACTION register. Normally used to report problems detected with the BCE.
4	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_GPE0_ERROR: Indicates the GPE0 reported an error that caused it to halt. Implemented as an OR of the four error outputs from the PPE.
5	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_GPE1_ERROR: Indicates the GPE1 reported an error that caused it to halt. Implemented as an OR of the four error outputs from the PPE.
6	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_CHECK_STOP_PPC405: Indicates system checkstop detected, use to interrupt the PPC405.
7	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_EXTERNAL_TRAP: Comes from a chip pin to indicated that an external condition has arisen on which the OCC FW is to take action, if enabled. This might be used to indicated that the power supplies are in over-subscription mode and that fast action to reduce socket and associated memory power is required.
8	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_OCC_TIMER0: Indicates that timer0 in the OCB has popped Timer0 is a 16bit counter incremented with a 1us input pulse, implemented as an auto-reload programmable interval timer (PIT). CHANGE_EFFECT { OCB_BASE.OISR0.occ_timer0 = OCB_BASE.OTR0.timeout0 }
9	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_OCC_TIMER1: Indicates that timer1 in the OCB has popped Timer1 is a 16bit counter incremented with a 1us input pulse, implemented as an auto-reload programmable interval timer (PIT). CHANGE_EFFECT { OCB_BASE.OISR0.occ_timer1 = OCB_BASE.OTR1.timeout1 }
10	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_IPI0_HI_PRIORITY: Inter-processor interrupt 0 - treated as hi priority by firmware. Allows synchronization between critical and non-critical code. The physical input is tied low. To inject an interrupt, please reference the Engineering Note in the OITR.
11	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_IPI1_HI_PRIORITY: Inter-processor interrupt 1 - treated as hi priority by firmware. Allows synchronization between critical and non-critical code. The physical input is tied low. To inject an interrupt, please reference the Engineering Note in the OITR.
12	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_IPI4_HI_PRIORITY: Inter-processor interrupt 4 - treated as hi priority by firmware. Allows synchronization between critical and non-critical code. The physical input is tied low. To inject an interrupt, please reference the Engineering Note in the OITR.
13	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_I2CM_INTR: OR of 3 I2CM interrupt signals. The actual interrupt signals can be read in OCCMISC[I2CM_intr_status]
14	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_SPARE_14: Implemented but unused. The physical input is tied low.
15	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_DCM_INTF_ONGOING: OCB Wire from interchip interface. Planned to be polled but interrupt connected for potential future use.
16	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_PBAX_OCC_SEND_ATTN: Indicates that the PBAX send engine is busy. Falling edge indicates it is complete.
17	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_PBAX_OCC_PUSH0: Indicates that PBA Streaming Channel 0 Push Queue has detected interrupt condition
18	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_PBAX_OCC_PUSH1: Indicates that PBA Streaming Channel 1 Push Queue has detected interrupt condition
19	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_PBA_BCDE_ATTN: Indicates that BCDE in the attached PBA detected has an attention condition (non error) Typically, this indicates that a Block Copy Download Engine has completed a requested activity
20	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_PBA_BCUE_ATTN: Indicates that BCUE in the attached PBA detected has an attention condition (non error) Typically, this indicates that a Block Copy Upload Engine has completed a requested activity
21	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_OCC_STRM0_PULL: Indicates that Streaming Channel 0 Pull Queue as detected the condition enabled in OCBSLSC0
22	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_OCC_STRM0_PUSH: Indicates that Streaming Channel 0 Push Queue as detected the condition enabled in OCBSHSC0
23	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_OCC_STRM1_PULL: Indicates that Streaming Channel 1 Pull Queue as detected the condition enabled in OCBSLSC1
24	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_OCC_STRM1_PUSH: Indicates that Streaming Channel 1 Push Queue as detected the condition enabled in OCBSHSC1
25	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_OCC_STRM2_PULL: Indicates that Streaming Channel 2 Pull Queue as detected the condition enabled in OCBSLSC2
26	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_OCC_STRM2_PUSH: Indicates that Streaming Channel 2 Push Queue as detected the condition enabled in OCBSHSC2
27	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_OCC_STRM3_PULL: Indicates that Streaming Channel 3 Pull Queue as detected the condition enabled in OCBSLSC3
28	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_OCC_STRM3_PUSH: Indicates that Streaming Channel 3 Push Queue as detected the condition enabled in OCBSHSC3
29	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_IPI0_LO_PRIORITY: Inter-processor interrupt 0 - treated as low priority by firmware. Allows synchronization between critical and non-critical code. The physical input is tied low. To inject an interrupt, please reference the Engineering Note in the OITR.
30	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_IPI1_LO_PRIORITY: Inter-processor interrupt 1 - treated as low priority by firmware. Allows synchronization between critical and non-critical code. The physical input is tied low. To inject an interrupt, please reference the Engineering Note in the OITR.
31	ROX	WOX_CLEAR	WOX_OR	ROX	WOX_CLEAR	WOX_OR	OCB_OCI_OISR1_IPI4_LO_PRIORITY: Inter-processor interrupt 4 - treated as low priority by firmware. Allows synchronization between critical and non-critical code. The physical input is tied low. To inject an interrupt, please reference the Engineering Note in the OITR.
32:63	RO	RO	RO	RO	RO	RO	constant=0b00000000000000000000000000000000

OCB_OCI OCC Interrupt Mask 1 Register
Addr:	000000000006C024 (SCOM) 000000000006C025 (SCOM1) 000000000006C026 (SCOM2) 00000000C0060120 (OCI) 00000000C0060128 (OCI1) 00000000C0060130 (OCI2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIMR1
Constant(s):	PU_OCB_OCI_OIMR1
Comments:	This register masks IOISR0 interrupts to the OCC complex
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_MASK1_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	OCI	OCI1	OCI2	Dial: Description
0:31	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OIMR1_INTERRUPT_MASK_1: See OCC Interrupt Source 1 for bit definitions Masks the respective event from producing an interrupt to the OCC complex engines. The events are still captured in the OISR but are not reported via interrupt signals. 0 = Not Masked (e.g. Enabled) 1 = Masked WRITE_EFFECT { if (~OIMR1 && ((~OITR1 && ~(OIEPR1 ^ OINKR1 )) | ( OITR1 && ( OIEPR1 && (~OINKR1 ^ OISR1)) | (~OIEPR1 && OINKR1 ^ ~OISR1) ))) { if (~OIRR1A && ~OIRR1B && ~OIRR1C) ONISR1=1; if (~OIRR1A && ~OIRR1B && OIRR1C) OCISR1=1; if (~OIRR1A && OIRR1B && ~OIRR1C) OUISR1=1; if (~OIRR1A && OIRR1B && OIRR1C) ODISR1=1; if ( OIRR1A && ~OIRR1B && ~OIRR1C) G0ISR1=1; if ( OIRR1A && ~OIRR1B && OIRR1C) G1ISR1=1; if ( OIRR1A && OIRR1B && ~OIRR1C) G2ISR1=1; if ( OIRR1A && OIRR1B && OIRR1C) G3ISR1=1; OINKR1=1; } else { if (~OIRR1A && ~OIRR1B && ~OIRR1C) ONISR1=0; if (~OIRR1A && ~OIRR1B && OIRR1C) OCISR1=0; if (~OIRR1A && OIRR1B && ~OIRR1C) OUISR1=0; if (~OIRR1A && OIRR1B && OIRR1C) ODISR1=0; if ( OIRR1A && ~OIRR1B && ~OIRR1C) G0ISR1=0; if ( OIRR1A && ~OIRR1B && OIRR1C) G1ISR1=0; if ( OIRR1A && OIRR1B && ~OIRR1C) G2ISR1=0; if ( OIRR1A && OIRR1B && OIRR1C) G3ISR1=0; OINKR1=0; } } // Note: GxISR1[0] must be a chained action
32:63	RO	RO	RO	RO	RO	RO	constant=0b00000000000000000000000000000000

OCB_OCI OCC Interrupt Type 1 Register
Addr:	000000000006C028 (SCOM) 000000000006C029 (SCOM1) 000000000006C02A (SCOM2) 00000000C0060140 (OCI) 00000000C0060148 (OCI1) 00000000C0060150 (OCI2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OITR1
Constant(s):	PU_OCB_OCI_OITR1
Comments:	This register establishes the type of OISR0 interrupt that is monitored - level or edge
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_TYPE1_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	OCI	OCI1	OCI2	Dial: Description
0:31	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OITR1_INTERRUPT_TYPE_1: See OCC Interrupt Source 1 for bit definitions Establish the type of interrupt that is monitored. 0 = Level 1 = Edge When set to "Level": the respective OISR1 bit follows the value of the associated input source, with the polarity defined by the OIEPR1. Note: With this setting, direct OCI writes to the OISR1 bit should never be attempted, since the value will not be held and will immediately return to its previous state. When set to "Edge": the respective OISR1 bit will be set upon the transition (as defined by the OIEPR1) of the associated input source. Specifically, if the respective OIEPR1 bit is set to "Rising", a transition from 0 to 1 sets the bit; if the respective OIEPR1 bit is set to "Falling", a transition from 1 to 0 sets the bit. In this mode, the only way to clear the OISR1 bit is via a direct OCI write-CLEAR. Additionally, firmware can inject interrupts by direct OISR write- OR to the bit (where the OIEPR1 setting is a dont care). Engineering Note For firmware testing, a potential interrupt injection technique for "Level" interrupts is to override their definition to "Edge" and then use the OR register associated with the OISR1. This will allow the injected transition to stick as the logic will not follow the input interrupt signal. However, if the firmware is expecting to find status in the driving unit, this technique may not be appropriate, so it would make more sense to have the driving unit provide an interrupt inject mechanism itself. Interrupt bits intended for firmware use. i.e. not driven by a hardware source, are typically tied low unless otherwise specified. The preferred mechanism for injecting interrupts is to configure these bits as an "Edge" and use OR and CLEAR write operations to control the value of the interrupt.
32:63	RO	RO	RO	RO	RO	RO	constant=0b00000000000000000000000000000000

OCB_OCI OCC Interrupt Edge/Polarity 1 Register
Addr:	000000000006C02C (SCOM) 000000000006C02D (SCOM1) 000000000006C02E (SCOM2) 00000000C0060160 (OCI) 00000000C0060168 (OCI1) 00000000C0060170 (OCI2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIEPR1
Constant(s):	PU_OCB_OCI_OIEPR1
Comments:	This register establishes either the significant edge of a edge enabled OISR0 interrupt or the significant polarity of a level enabled that will be detected for enabled interrupt sources.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_EDGPOL1_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	OCI	OCI1	OCI2	Dial: Description
0:31	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OIEPR1_INTERRUPT_EDGE_POL_1: See OCC Interrupt Source 1 for bit definitions Establish the edge or polarity of interrupt. 0 = Falling/Low 1 = Rising/High When set the respective bit in the OITR1 is set to "Level", then the "Low" and "High" meanings apply as follows: If this bit is set to "Low", the respective OISR1 bit follows the inverted input to the OISR from the unit driving the signal. If this bit is set to "High", the respective OISR1 bit follows the direct input to the OISR1 from the unit driving the signal When set the respective bit in the OITR1 is set to "Edge", then the "Falling" and "Rising" meanings apply as follows: If this bit is set to "Falling", a transition from 1 to 0 of the input signal to the OISR1 sets the respective OISR1 bit. If this bit is set to "Rising", a transition from 0 to 1 of the input signal to the OISR1 sets the respective OISR1 bit.
32:63	RO	RO	RO	RO	RO	RO	constant=0b00000000000000000000000000000000

OCB_OCI OCC Interrupt Input 1 Knowledge Register
Addr:	000000000006C030 (SCOM) 00000000C0060180 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OINKR1
Constant(s):
Comments:	This register reflects the raw value of the input feeding the OISR0 for debug purposes.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_SRC1_DELAY_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_OINKR1_INTERRUPT_INPUT_1: See OCC Interrupt Source 1 for bit definitions. This reflects the raw value of the input feeding the OISR1, before being modified by the OITR, OIPR, or OIMR.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC Interrupt 0 Route A Register
Addr:	000000000006C040 (SCOM) 000000000006C041 (SCOM1) 000000000006C042 (SCOM2) 00000000C0060200 (OCI) 00000000C0060208 (OCI1) 00000000C0060210 (OCI2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR0A
Constant(s):	PU_OCB_OCI_OIRR0A
Comments:	This register (in bitwise combination with the other 2 respective Route n registers) determines the engine that a respective interrupt bit from OISRA is routed. RouteA RouteB RouteC Target 0 0 0 OCC Non-Critical Interrupt 0 0 1 OCC Critical Interrupt 0 1 0 OCC Unconditional Interrupt 0 1 1 OCC Debug Halt Input 1 0 0 PPE0 External Interrupt 1 0 1 PPE1 External Interrupt 1 1 0 PPE2 External Interrupt 1 1 1 PPE3 External Interrupt
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_OIRR0A_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	OCI	OCI1	OCI2	Dial: Description
0:31	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OIRR0A_INTERRUPT_ROUTE_0_A: See OCC Interrupt Source 0 for bit definitions Each interrupt source can be routed to two engines. The target engine receiving the interrupt can be determined by looking at [OIRRA0, OIRRB0, OIRRC0] and [OIRRA1, OIRRB1, OIRRC1]
32:63	RO	RO	RO	RO	RO	RO	constant=0b00000000000000000000000000000000

OCC Interrupt 0 Route B Register
Addr:	000000000006C044 (SCOM) 000000000006C045 (SCOM1) 000000000006C046 (SCOM2) 00000000C0060220 (OCI) 00000000C0060228 (OCI1) 00000000C0060230 (OCI2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR0B
Constant(s):	PU_OCB_OCI_OIRR0B
Comments:	This register (in bitwise combination with the other 2 respective Route n registers) determines the engine that a respective interrupt bit from OISRA is routed. RouteA RouteB RouteC Target 0 0 0 OCC Non-Critical Interrupt 0 0 1 OCC Critical Interrupt 0 1 0 OCC Unconditional Interrupt 0 1 1 OCC Debug Halt Input 1 0 0 PPE0 External Interrupt 1 0 1 PPE1 External Interrupt 1 1 0 PPE2 External Interrupt 1 1 1 PPE3 External Interrupt
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_OIRR0B_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	OCI	OCI1	OCI2	Dial: Description
0:31	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OIRR0B_INTERRUPT_ROUTE_0_B: See OCC Interrupt Source 0 for bit definitions Each interrupt source can be routed to two engines. The target engine receiving the interrupt can be determined by looking at [OIRRA0, OIRRB0, OIRRC0] and [OIRRA1, OIRRB1, OIRRC1]
32:63	RO	RO	RO	RO	RO	RO	constant=0b00000000000000000000000000000000

OCC Interrupt 0 Route C Register
Addr:	000000000006C048 (SCOM) 000000000006C049 (SCOM1) 000000000006C04A (SCOM2) 00000000C0060240 (OCI) 00000000C0060248 (OCI1) 00000000C0060250 (OCI2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR0C
Constant(s):	PU_OCB_OCI_OIRR0C
Comments:	This register (in bitwise combination with the other 2 respective Route n registers) determines the engine that a respective interrupt bit from OISRA is routed. RouteA RouteB RouteC Target 0 0 0 OCC Non-Critical Interrupt 0 0 1 OCC Critical Interrupt 0 1 0 OCC Unconditional Interrupt 0 1 1 OCC Debug Halt Input 1 0 0 PPE0 External Interrupt 1 0 1 PPE1 External Interrupt 1 1 0 PPE2 External Interrupt 1 1 1 PPE3 External Interrupt
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_OIRR0C_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	OCI	OCI1	OCI2	Dial: Description
0:31	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OIRR0C_INTERRUPT_ROUTE_0_C: See OCC Interrupt Source 0 for bit definitions Each interrupt source can be routed to two engines. The target engine receiving the interrupt can be determined by looking at [OIRRA0, OIRRB0, OIRRC0] and [OIRRA1, OIRRB1, OIRRC1]
32:63	RO	RO	RO	RO	RO	RO	constant=0b00000000000000000000000000000000

OCC Interrupt 1 Route A Register
Addr:	000000000006C050 (SCOM) 000000000006C051 (SCOM1) 000000000006C052 (SCOM2) 00000000C0060280 (OCI) 00000000C0060288 (OCI1) 00000000C0060290 (OCI2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR1A
Constant(s):	PU_OCB_OCI_OIRR1A
Comments:	This register (in bitwise combination with the other 2 respective Route n registers) determines the engine that a respective interrupt bit from OISRA is routed. RouteA RouteB RouteC Target 0 0 0 OCC Non-Critical Interrupt 0 0 1 OCC Critical Interrupt 0 1 0 OCC Unconditional Interrupt 0 1 1 OCC Debug Halt Input 1 0 0 PPE0 External Interrupt 1 0 1 PPE1 External Interrupt 1 1 0 PPE2 External Interrupt 1 1 1 PPE3 External Interrupt
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_OIRR1A_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	OCI	OCI1	OCI2	Dial: Description
0:31	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OIRR1A_INTERRUPT_ROUTE_1_A: See OCC Interrupt Source 1 for bit definitions Each interrupt source can be routed to two engines. The target engine receiving the interrupt can be determined by looking at [OIRRA0, OIRRB0, OIRRC0] and [OIRRA1, OIRRB1, OIRRC1]
32:63	RO	RO	RO	RO	RO	RO	constant=0b00000000000000000000000000000000

OCC Interrupt 1 Route B Register
Addr:	000000000006C054 (SCOM) 000000000006C055 (SCOM1) 000000000006C056 (SCOM2) 00000000C00602A0 (OCI) 00000000C00602A8 (OCI1) 00000000C00602B0 (OCI2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR1B
Constant(s):	PU_OCB_OCI_OIRR1B
Comments:	This register (in bitwise combination with the other 2 respective Route n registers) determines the engine that a respective interrupt bit from OISRA is routed. RouteA RouteB RouteC Target 0 0 0 OCC Non-Critical Interrupt 0 0 1 OCC Critical Interrupt 0 1 0 OCC Unconditional Interrupt 0 1 1 OCC Debug Halt Input 1 0 0 PPE0 External Interrupt 1 0 1 PPE1 External Interrupt 1 1 0 PPE2 External Interrupt 1 1 1 PPE3 External Interrupt
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_OIRR1B_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	OCI	OCI1	OCI2	Dial: Description
0:31	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OIRR1B_INTERRUPT_ROUTE_1_B: See OCC Interrupt Source 1 for bit definitions Each interrupt source can be routed to two engines. The target engine receiving the interrupt can be determined by looking at [OIRRA0, OIRRB0, OIRRC0] and [OIRRA1, OIRRB1, OIRRC1]
32:63	RO	RO	RO	RO	RO	RO	constant=0b00000000000000000000000000000000

OCC Interrupt 1 Route C Register
Addr:	000000000006C058 (SCOM) 000000000006C059 (SCOM1) 000000000006C05A (SCOM2) 00000000C00602C0 (OCI) 00000000C00602C8 (OCI1) 00000000C00602D0 (OCI2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR1C
Constant(s):	PU_OCB_OCI_OIRR1C
Comments:	This register (in bitwise combination with the other 2 respective Route n registers) determines the engine that a respective interrupt bit from OISRA is routed. RouteA RouteB RouteC Target 0 0 0 OCC Non-Critical Interrupt 0 0 1 OCC Critical Interrupt 0 1 0 OCC Unconditional Interrupt 0 1 1 OCC Debug Halt Input 1 0 0 PPE0 External Interrupt 1 0 1 PPE1 External Interrupt 1 1 0 PPE2 External Interrupt 1 1 1 PPE3 External Interrupt
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_OIRR1C_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	OCI	OCI1	OCI2	Dial: Description
0:31	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OIRR1C_INTERRUPT_ROUTE_1_C: See OCC Interrupt Source 1 for bit definitions Each interrupt source can be routed to two engines. The target engine receiving the interrupt can be determined by looking at [OIRRA0, OIRRB0, OIRRC0] and [OIRRA1, OIRRB1, OIRRC1]
32:63	RO	RO	RO	RO	RO	RO	constant=0b00000000000000000000000000000000

OCB_OCI OCC Non-Critical Interrupt Status 0 Register
Addr:	000000000006C060 (SCOM) 00000000C0060300 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ONISR0
Constant(s):	PU_OCB_OCI_ONISR0
Comments:	Reading this pseudo-register returns a vector of all pending unmasked non-critical OISR0 interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_ONISR0_STATUS(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		interrupt_noncrit_status_0
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCC Critical Interrupt Status 0 Register
Addr:	000000000006C061 (SCOM) 00000000C0060308 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCISR0
Constant(s):	PU_OCB_OCI_OCISR0
Comments:	Reading this pseudo-register returns a vector of all pending unmasked critical OISR0 interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_OCISR0_STATUS(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		interrupt_crit_status_0
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCC Unconditional Interrupt Status 0 Register
Addr:	000000000006C062 (SCOM) 00000000C0060310 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OUISR0
Constant(s):	PU_OCB_OCI_OUISR0
Comments:	Reading this pseudo-register returns a vector of all pending unmasked debug OISR0 interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_OUISR0_STATUS(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		interrupt_uncon_status_0
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCC Debug Interrupt Status 0 Register
Addr:	000000000006C063 (SCOM) 00000000C0060318 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ODISR0
Constant(s):	PU_OCB_OCI_ODISR0
Comments:	Reading this pseudo-register returns a vector of all pending unmasked debug OISR0 interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_ODISR0_STATUS(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		interrupt_debug_status_0
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE0 Interrupt Status 0 Register
Addr:	000000000006C064 (SCOM) 00000000C0060320 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_G0ISR0
Constant(s):	PU_OCB_OCI_G0ISR0
Comments:	Reading this pseudo-register returns a vector of all pending unmasked GPE0 OISR0 interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_G0ISR0_STATUS(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		interrupt_gpe0_status_0
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE1 Interrupt Status 0 Register
Addr:	000000000006C065 (SCOM) 00000000C0060328 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_G1ISR0
Constant(s):	PU_OCB_OCI_G1ISR0
Comments:	Reading this pseudo-register returns a vector of all pending unmasked GPE1 OISR0 interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_G1ISR0_STATUS(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		interrupt_gpe1_status_0
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE2 Interrupt Status 0 Register
Addr:	000000000006C066 (SCOM) 00000000C0060330 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_G2ISR0
Constant(s):	PU_OCB_OCI_G2ISR0
Comments:	Reading this pseudo-register returns a vector of all pending unmasked GPE2 OISR0 interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_G2ISR0_STATUS(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		interrupt_gpe2_status_0
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE3 Interrupt Status 0 Register
Addr:	000000000006C067 (SCOM) 00000000C0060338 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_G3ISR0
Constant(s):	PU_OCB_OCI_G3ISR0
Comments:	Reading this pseudo-register returns a vector of all pending unmasked GPE3 OISR0 interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_G3ISR0_STATUS(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		interrupt_gpe3_status_0
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCC Non-Critical Interrupt Status 1 Register
Addr:	000000000006C070 (SCOM) 00000000C0060380 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ONISR1
Constant(s):	PU_OCB_OCI_ONISR1
Comments:	Reading this pseudo-register returns a vector of all pending unmasked non-critical OISR0 interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_ONISR1_STATUS(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		interrupt_noncrit_status_1
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCC Critical Interrupt Status 1 Register
Addr:	000000000006C071 (SCOM) 00000000C0060388 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCISR1
Constant(s):	PU_OCB_OCI_OCISR1
Comments:	Reading this pseudo-register returns a vector of all pending unmasked critical OISR0 interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_OCISR1_STATUS(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		interrupt_crit_status_1
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCC Unconditional Interrupt Status 1 Register
Addr:	000000000006C072 (SCOM) 00000000C0060390 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OUISR1
Constant(s):	PU_OCB_OCI_OUISR1
Comments:	Reading this pseudo-register returns a vector of all pending unmasked debug OISR0 interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_OUISR1_STATUS(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		interrupt_uncon_status_1
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCC Debug Interrupt Status 1 Register
Addr:	000000000006C073 (SCOM) 00000000C0060398 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ODISR1
Constant(s):	PU_OCB_OCI_ODISR1
Comments:	Reading this pseudo-register returns a vector of all pending unmasked debug OISR0 interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_ODISR1_STATUS(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		interrupt_debug_status_1
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE0 Interrupt Status 1 Register
Addr:	000000000006C074 (SCOM) 00000000C00603A0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_G0ISR1
Constant(s):	PU_OCB_OCI_G0ISR1
Comments:	Reading this pseudo-register returns a vector of all pending unmasked GPE0 OISR0 interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_G0ISR1_STATUS(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		interrupt_gpe0_status_1
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE1 Interrupt Status 1 Register
Addr:	000000000006C075 (SCOM) 00000000C00603A8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_G1ISR1
Constant(s):	PU_OCB_OCI_G1ISR1
Comments:	Reading this pseudo-register returns a vector of all pending unmasked GPE1 OISR0 interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_G1ISR1_STATUS(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		interrupt_gpe1_status_1
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE2 Interrupt Status 1 Register
Addr:	000000000006C076 (SCOM) 00000000C00603B0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_G2ISR1
Constant(s):	PU_OCB_OCI_G2ISR1
Comments:	Reading this pseudo-register returns a vector of all pending unmasked GPE2 OISR0 interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_G2ISR1_STATUS(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		interrupt_gpe2_status_1
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI GPE3 Interrupt Status 1 Register
Addr:	000000000006C077 (SCOM) 00000000C00603B8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_G3ISR1
Constant(s):	PU_OCB_OCI_G3ISR1
Comments:	Reading this pseudo-register returns a vector of all pending unmasked GPE3 OISR0 interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITP_G3ISR1_STATUS(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		interrupt_gpe3_status_1
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCC Miscellaneous Register
Addr:	000000000006C080 (SCOM) 000000000006C081 (SCOM1) 000000000006C082 (SCOM2) 00000000C0060400 (OCI) 00000000C0060408 (OCI1) 00000000C0060410 (OCI2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCMISC
Constant(s):	PU_OCB_OCI_OCCMISC
Comments:	Note - FIG:OCB_OCI_OCCMISC.attr(atrxstickmask) = "6-7, 16-18", should be added into the figtree attributes, but that breaks the auto parsing - it is added later.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:5	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.OCCMISC_Q_INST.LATC.L2(0:5) [000000]
	6:7	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.PVREF_ASYNC.LATC.CSDFFQ1.L2(0:1) [00]
	8:15	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.OCCMISC_Q_INST.LATC.L2(8:15) [00000000]
	16:18	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.I2CM_ASYNC.LATC.CSDFFQ1.L2(0:2) [000]
Bit(s)	SCOM	SCOM1	SCOM2	OCI	OCI1	OCI2	Dial: Description
0	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OCCMISC_CORE_EXT_INTR: Core External Interrupt Setting this bit to a 1 causes a wire to pulse to the PSI Host Bridge to allow the presentation of an external interrupt to a core thread. The core thread to be interrupted is controlled by the XIVR - OCC register, SCOM 02010916. In order for a subsequent interrupt to be requested, this bit must be reset to 0 and then set to 1 (e.g. a rising edge must be created)
1:3	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OCCMISC_EXT_INTR_REASON: Used by Firmware to record reason for the above interrupt.
4:5	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OCCMISC_PVREF_ERROR_EN: Enables the PVREF_ERROR_GROSS and PVREF_ERROR_FINE inputs respectively, after they are captured by the next two bits of this register. After applying the respective enables, the two are then ORd to assert the PVREF_FAIL indication, which sets the OISR and is also sent as an output to be delivered unlatched to all VREGs and CMEs on the chip to indicate that on-chip voltage regulation is now suspect.
6	ROX	NCX	NCX	ROX	NCX	NCX	OCB_OCI_OCCMISC_PVREF_ERROR_GROSS: Gross Error indication directly from the Precision Voltage Reference.
7	ROX	NCX	NCX	ROX	NCX	NCX	OCB_OCI_OCCMISC_PVREF_ERROR_FINE: Fine Error indication directly from the Precision Voltage Reference.
8	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OCCMISC_FIRMWARE_FAULT: Sets OCCLFIR[occ_complex_fault] to indicate an OCC error occurred.
9	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OCCMISC_FIRMWARE_NOTIFY: Sets OCCLFIR[occ_complex_notify] to indicate an OCC event occurred that needs attention from another firmware entity.
10:15	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OCCMISC_SPARE: Implemented but not used
16:18	ROX	NCX	NCX	ROX	NCX	NCX	OCB_OCI_OCCMISC_I2CM_INTR_STATUS: Interrupt status from I2CM
19:63	RO	RO	RO	RO	RO	RO	constant=0b000000000000000000000000000000000000000000000

OCB_OCI OCC HTM Control Register
Addr:	000000000006C083 (SCOM) 00000000C0060418 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OHTMCR
Constant(s):	PU_OCB_OCI_OHTMCR
Comments:	Register to control the OCC HTM logic as well as how different events can set a halt to stop the HTM and halt the PPC405
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:18	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.OCC_OHTMCR_Q_INST.LATC.L2(0:18) [0000000000000000000]
	20:21	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.OCC_OHTMCR_Q_INST.LATC.L2(20:21) [00]
	23:27	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.OCC_OHTMCR_Q_INST.LATC.L2(23:27) [00000]
	31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.HALT_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0:1	RW	RW		OCB_OCI_OHTMCR_HTM_SRC_SEL: Select OCC source to drive out htm data 00 - htm off 01 - plb data 10 - 405 data 11 - Selected GPE from HTM_GPE_SRC_SEL
2	RW	RW		OCB_OCI_OHTMCR_HTM_STOP: HTM Stop Signal setting this bit will cause the HTM stop signal to be sent to the NHTM to indicate to stop collecting OCC
3:5	RW	RW		OCB_OCI_OHTMCR_HTM_MARKER_SLAVE_ADRS: HTM Slave Address Marker used to match against the slave address in the PLB HTM stream to generate markers
6:7	RW	RW		OCB_OCI_OHTMCR_EVENT2HALT_MODE: Event to Halt Mode: 00 - Off 01 - Halt on Event 10 - Halt some delay after Event 11 - unused (off)
8:18	RW	RW		OCB_OCI_OHTMCR_EVENT2HALT_EN: Enable Trace Trigger Event(0:10) to cause a halt as programmed by field event2halt_mode 0 - disabled 1 - enabled
19	RO	RO		constant=0b0
20:21	RW	RW		OCB_OCI_OHTMCR_HTM_GPE_SRC_SEL: Select GPE source to drive out HTM Data 00 - GPE0 01 - GPE1 10 - GPE2 11 - GPE3
22	RO	RO		constant=0b0
23	RW	RW		OCB_OCI_OHTMCR_EVENT2HALT_OCC: Enabled halt event causes the PPC405 to halt.
24	RW	RW		OCB_OCI_OHTMCR_EVENT2HALT_GPE0: Enabled halt event causes the GPE0 to halt.
25	RW	RW		OCB_OCI_OHTMCR_EVENT2HALT_GPE1: Enabled halt event causes the GPE1 to halt.
26	RW	RW		OCB_OCI_OHTMCR_EVENT2HALT_GPE2: Enabled halt event causes the GPE2 to halt.
27	RW	RW		OCB_OCI_OHTMCR_EVENT2HALT_GPE3: Enabled halt event causes the GPE3 to halt.
28:30	RO	RO		constant=0b000
31	ROX	ROX		OCB_OCI_OHTMCR_EVENT2HALT_HALT_STATE: Event-driven Halt This bit reflects the value of the event-driven halt condition that is sent to the targets as indicated in bits 23:27. Writing this register will clear the event-driven halt condition.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCC Event Halt Delay Register
Addr:	000000000006C084 (SCOM) 00000000C0060420 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OEHDR
Constant(s):	PU_OCB_OCI_OEHDR
Comments:	Register to delay the setting of the HTM & PPC405 halt after some event occurs
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:19	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.HALT_DELAY_CTR_Q_INST.LATC.L2(0:19) [00000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:19	RWX	RWX		OCB_OCI_OEHDR_EVENT2HALT_DELAY: Event to Halt Delay Counter This field contains the amount of delay to wait between a Trigger Event occurring and Debug Halt being asserted. Only valid if event2halt_mode=10.
20:63	RO	RO		constant=0b00000000000000000000000000000000000000000000

OCB_OCI OCC OCI Configuration Register
Addr:	000000000006C085 (SCOM) 00000000C0060428 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCICFG
Constant(s):	PU_OCB_OCI_OCICFG
Comments:	Register to hold configuration facilities for the OCI
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.OCC_OCICFG_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:1	RW	RW		OCB_OCI_OCICFG_M0_PRIORITY: Set OCI Master0 Arbitration Priority (GPE0) 00 : lowest 01 : low 10 : high 11 : highest
2:3	RW	RW		OCB_OCI_OCICFG_M1_PRIORITY: Set OCI Master1 Arbitration Priority (GPE1) 00 : lowest 01 : low 10 : high 11 : highest
4:5	RW	RW		OCB_OCI_OCICFG_M2_PRIORITY: Set OCI Master2 Arbitration Priority (GPE2) 00 : lowest 01 : low 10 : high 11 : highest
6:7	RW	RW		OCB_OCI_OCICFG_M3_PRIORITY: Set OCI Master3 Arbitration Priority (GPE3) 00 : lowest 01 : low 10 : high 11 : highest
8:9	RW	RW		OCB_OCI_OCICFG_M4_PRIORITY: Set OCI Master4 Arbitration Priority (PBA) 00 : lowest 01 : low 10 : high 11 : highest
10:11	RW	RW		OCB_OCI_OCICFG_M5_PRIORITY: Set OCI Master5 Arbitration Priority (PPC405 IC) 00 : lowest 01 : low 10 : high 11 : highest
12:13	RW	RW		OCB_OCI_OCICFG_M6_PRIORITY: Set OCI Master6 Arbitration Priority (OCB) 00 : lowest 01 : low 10 : high 11 : highest
14:15	RW	RW		OCB_OCI_OCICFG_M7_PRIORITY: Set OCI Master7 Arbitration Priority (PPC405 DC) 00 : lowest 01 : low 10 : high 11 : highest
16	RW	RW		OCB_OCI_OCICFG_M0_PRIORITY_SEL: selects between the m0_priority register setting and the GPE0 requested priority value 0 : select m0_priority 1 : select gpe0_oci_m_priority
17	RW	RW		OCB_OCI_OCICFG_M1_PRIORITY_SEL: selects between the m1_priority register setting and the GPE1 requested priority value 0 : select m1_priority 1 : select gpe1_oci_m_priority
18	RW	RW		OCB_OCI_OCICFG_M2_PRIORITY_SEL: selects between the m2_priority register setting and the GPE2 requested priority value 0 : select m2_priority 1 : select gpe2_oci_m_priority
19	RW	RW		OCB_OCI_OCICFG_M3_PRIORITY_SEL: selects between the m3_priority register setting and the GPE3 requested priority value 0 : select m3_priority 1 : select gpe3_oci_m_priority
20	RW	RW		OCB_OCI_OCICFG_OCICFG_RESERVED_20: Implemented but not used. Master 4 (PBA) priority always come from m4_priority field.
21	RW	RW		OCB_OCI_OCICFG_M5_PRIORITY_SEL: selects between the m5_priority register setting and the icu 405 priority value 0 select m5_priority 1 select c405icu_oci_m_priority
22	RW	RW		OCB_OCI_OCICFG_OCICFG_RESERVED_23: Implemented but not used. Master 6 (OCB) priority always come from m6_priority field.
23	RW	RW		OCB_OCI_OCICFG_M7_PRIORITY_SEL: selects between the m7_priority register setting and the dcu 405 priority value 0 : select m7_priority 1 : select c405dcu_oci_m_priority
24	RW	RW		OCB_OCI_OCICFG_PLBARB_LOCKERR: causes PLB arbiter to lock up and hold the address and masterid of a request that gets a timeout
25:31	RW	RW		OCB_OCI_OCICFG_SPARE_24_31: Spare chicken switches
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCB Status Register
Addr:	000000000006C086 (SCOM) 00000000C0060430 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSTAT
Constant(s):
Comments:	This register indicates the state of offchip interfaces. Note: In P9 these were OISR interrupt sources.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.OCBSTAT_Q_0_INST.LATC.L2(0:15) [0000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		OCB_OCI_OCBSTAT_ADCFSM_ONGOING: Indicates the A2D Collection state machine in the PSS unit is currently busy
1	ROX	ROX		OCB_OCI_OCBSTAT_SPARE_1: Implemented and tied to 0
2	ROX	ROX		OCB_OCI_OCBSTAT_PMC_O2S_0A_ONGOING: Indicates the A O2S bridge for AVS Interface 0 has an ongoing transaction
3	ROX	ROX		OCB_OCI_OCBSTAT_PMC_O2S_0B_ONGOING: Indicates the B O2S bridge for AVS Interface 0 has an ongoing transaction
4	ROX	ROX		OCB_OCI_OCBSTAT_PMC_O2S_1A_ONGOING: Indicates the A O2S bridge for AVS Interface 1 has an ongoing transaction
5	ROX	ROX		OCB_OCI_OCBSTAT_PMC_O2S_1B_ONGOING: Indicates the B O2S bridge for AVS Interface 1 has an ongoing transaction
6	ROX	ROX		OCB_OCI_OCBSTAT_PMC_O2S_2A_ONGOING: Indicates the A O2S bridge for AVS Interface 2 has an ongoing transaction
7	ROX	ROX		OCB_OCI_OCBSTAT_PMC_O2S_2B_ONGOING: Indicates the B O2S bridge for AVS Interface 2 has an ongoing transaction
8	ROX	ROX		OCB_OCI_OCBSTAT_AVS_SLAVE0: Indicates that the VRM Slave attached to AVS bus 0 has signaled attention.
9	ROX	ROX		OCB_OCI_OCBSTAT_AVS_SLAVE1: Indicates that the VRM Slave attached to AVS bus 1 has signaled attention.
10	ROX	ROX		OCB_OCI_OCBSTAT_AVS_SLAVE2: Indicates that the VRM Slave attached to AVS bus 2 has signaled attention.
11	ROX	ROX		OCB_OCI_OCBSTAT_SPARE_11: Implemented and tied to 0
12	ROX	ROX		OCB_OCI_OCBSTAT_DERP0_ONGOING: Indicates the divide assist engine 0 is performing a calculation
13	ROX	ROX		OCB_OCI_OCBSTAT_DERP1_ONGOING: Indicates the divide assist engine 1 is performing a calculation
14	ROX	ROX		OCB_OCI_OCBSTAT_DERP2_ONGOING: Indicates the divide assist engine 2 is performing a calculation
15	ROX	ROX		OCB_OCI_OCBSTAT_DERP3_ONGOING: Indicates the divide assist engine 3 is performing a calculation
16:63	RO	RO		constant=0b000000000000000000000000000000000000000000000000

OCB_OCI OCB OCC Heartbeat Register
Addr:	000000000006C08F (SCOM) 00000000C0060478 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCHBR
Constant(s):	PU_OCB_OCI_OCCHBR
Comments:	The OCCHBR controls the behavior of the OCC heartbeat function
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.HBCOUNTER.HEARTBEAT_Q_0_INST.LATC.L2(0:15) [0000000000000000]
	16	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.HBCOUNTER.HEARTBEAT_EN_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0:15	RWX	RWX		OCB_OCI_OCCHBR_OCC_HEARTBEAT_COUNT: When written, this field defines the starting value for a counter that increments at ~1us if OCC_HEARTBEAT_EN=1 and the counter value is non-zero. If OCC_HEARTBEAT_EN=0 or the counter value is 0, the counter does not increment. If OCC_HEARTBEAT_EN=1 and this counter becomes 0 (either due a written value or due to the counter wrapping) constitutes the loss of the OCC heartbeat and will surface an attention via [TBD] LFIR(TBD). The pulses used for this field come from a free running pervasive hang timer pulse (PM_Hang_Pulse) programmed to be ~32ns that has a 5 bit precounter whose carryout forms a resultant ~1us decrement pulse. Upon writing this register with OCC_HEARTBEAT_EN=1, the precounter is cleared and will begin counting upon the next PM_Hang_Pulse. This PM_Hang_Pulse may arrive immediately or a full duration later. With a (2^15)-1 range and an ~1us incrementation time yields a heartbeat range of 1us (+0/-32ns) (value 0xFFFF) to 65.535 ms (+0/-32ns) (value 0x0001). The value chosen to be written For debug purposes only, writing 0x0000 will cause an immediate heartbeat_lost if OCC_HEARTBEAT_EN = 1. Reads return the current value of the counter value.
16	RW	RW		OCB_OCI_OCCHBR_OCC_HEARTBEAT_EN: OCC Heartbeat Timer Enable Dial enums: DISABLE_THE_OCC_HEARTBEAT_FUNCTION__THE_OCC_HEARTBEAT_COUNTER_WILL_NOT_INCREMENT_AND_NO_HEARTBEAT_LOSS_EVENTS_ARE_TRIGGERED_TO_THE_TBD_FIR_=>0b0 ENABLE_THE_OCC_HEARTBEAT_FUNCTION_=>0b1
17:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000 Dial enums: DISABLE_THE_OCC_HEARTBEAT_FUNCTION__THE_OCC_HEARTBEAT_COUNTER_WILL_NOT_INCREMENT_AND_NO_HEARTBEAT_LOSS_EVENTS_ARE_TRIGGERED_TO_THE_TBD_FIR_=>0b0 ENABLE_THE_OCC_HEARTBEAT_FUNCTION_=>0b1

OCB_OCI Core Configuration Status Register
Addr:	000000000006C090 (SCOM) 000000000006C091 (SCOM1) 000000000006C092 (SCOM2) 00000000C0060480 (OCI) 00000000C0060488 (OCI1) 00000000C0060490 (OCI2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_CCSR
Constant(s):	PU_OCB_OCI_CCSR
Comments:	This register is the "master" centralized register used by SBE, PGPE and OCC to indicate which Core Chiplet regions are configured for enablement (including partial good support). Reference the QCSR for the associated cache subunits in the Quads. This register is not used by the hardware logic. These are status bits that are used by SBE, OCC, and GPE firmware to determine which core chiplets "exist".
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.CCSR_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	OCI	OCI1	OCI2	Dial: Description
0:31	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_CCSR_CORE_CONFIG: Bit per physical Core Chiplet indicating, when set to 1, that it is configured and therefore available to target. (where Bit 0 corresponds to Core Chiplet 0, Bit 1 corresponds to Core Chiplet 1, etc.)
32:63	RO	RO	RO	RO	RO	RO	constant=0b00000000000000000000000000000000

OCB_OCI OCB Timebase Register
Addr:	000000000006C09F (SCOM) 00000000C00604F8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OTBR
Constant(s):	PU_OCB_OCI_OTBR
Comments:	This register provides access to the free-running timebase register for intended use by the GPEs, with a functionality identical to the low order word of the QME Timebase Register (QTBR). Note: For P10 this register is now writable in order to synchronize the timebase between the QME and OCC complexes. A GPE can read one of the QME timebases and write that value adding an adjust for data return plus update latency. A write to this register should take priority over a counter increment.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.TIMEBASE_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RWX	RWX		OCB_OCI_OTBR_OCB_TIMEBASE: OCB Timebase Free-running counter whose least significant bit increments at the same rate as the QME timer input pulse, which will be configured to run at PAU clock/64. (At 2Ghz this will rise every 32ns, and this counter will wrap every 137 seconds). Firmware must perform all delta calculations (including accounting for the wrap condition) to perform elapsed time functions.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCC Scratch 0
Addr:	000000000006C0A0 (SCOM) 000000000006C0A1 (SCOM1) 000000000006C0A2 (SCOM2) 00000000C0060500 (OCI) 00000000C0060508 (OCI1) 00000000C0060510 (OCI2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCS0
Constant(s):	PU_OCB_OCI_OCCS0
Comments:	The OCCSR0 register is a scratch register that can be used by OCC firmware.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.OCCS0_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	OCI	OCI1	OCI2	Dial: Description
0:31	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OCCS0_OCC_SCRATCH_0: Scratch Data 0
32:63	RO	RO	RO	RO	RO	RO	constant=0b00000000000000000000000000000000

OCB_OCI OCC Scratch 1
Addr:	000000000006C0A3 (SCOM) 000000000006C0A4 (SCOM1) 000000000006C0A5 (SCOM2) 00000000C0060518 (OCI) 00000000C0060520 (OCI1) 00000000C0060528 (OCI2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCS1
Constant(s):	PU_OCB_OCI_OCCS1
Comments:	The OCCSR0 register is a scratch register that can be used by OCC firmware.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.OCCS1_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	OCI	OCI1	OCI2	Dial: Description
0:31	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OCCS1_OCC_SCRATCH_1: Scratch Data 1
32:63	RO	RO	RO	RO	RO	RO	constant=0b00000000000000000000000000000000

OCB_OCI OCC Scratch 2
Addr:	000000000006C0A6 (SCOM) 000000000006C0A7 (SCOM1) 000000000006C0A8 (SCOM2) 00000000C0060530 (OCI) 00000000C0060538 (OCI1) 00000000C0060540 (OCI2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCS2
Constant(s):	PU_OCB_OCI_OCCS2
Comments:	The OCCSR0 register is a scratch register that can be used by OCC firmware.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.OCCS2_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	OCI	OCI1	OCI2	Dial: Description
0:31	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OCCS2_OCC_SCRATCH_2: Scratch Data 2
32:63	RO	RO	RO	RO	RO	RO	constant=0b00000000000000000000000000000000

OCB_OCI OCC Scratch 3
Addr:	000000000006C0A9 (SCOM) 000000000006C0AA (SCOM1) 000000000006C0AB (SCOM2) 00000000C0060548 (OCI) 00000000C0060550 (OCI1) 00000000C0060558 (OCI2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCS3
Constant(s):
Comments:	The OCCSR0 register is a scratch register that can be used by OCC firmware.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.OCCS3_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	OCI	OCI1	OCI2	Dial: Description
0:31	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OCCS3_OCC_SCRATCH_3: Scratch Data 3
32:63	RO	RO	RO	RO	RO	RO	constant=0b00000000000000000000000000000000

OCB_OCI OCC Flags 0
Addr:	000000000006C0AC (SCOM) 000000000006C0AD (SCOM1) 000000000006C0AE (SCOM2) 00000000C0060560 (OCI) 00000000C0060568 (OCI1) 00000000C0060570 (OCI2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG0
Constant(s):
Comments:	The OCCFLG register is a scratch register that can be used by OCC firmware for flag setting
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.OCCFLG0_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	OCI	OCI1	OCI2	Dial: Description
0:31	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OCCFLG0_OCC_FLAGS: Flags that are defined by OCC Firmware
32:63	RO	RO	RO	RO	RO	RO	constant=0b00000000000000000000000000000000

OCB_OCI OCC Flags 1
Addr:	000000000006C0AF (SCOM) 000000000006C0B0 (SCOM1) 000000000006C0B1 (SCOM2) 00000000C0060578 (OCI) 00000000C0060580 (OCI1) 00000000C0060588 (OCI2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG1
Constant(s):
Comments:	The OCCFLG register is a scratch register that can be used by OCC firmware for flag setting
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.OCCFLG1_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	OCI	OCI1	OCI2	Dial: Description
0:31	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OCCFLG1_OCC_FLAGS: Flags that are defined by OCC Firmware
32:63	RO	RO	RO	RO	RO	RO	constant=0b00000000000000000000000000000000

OCB_OCI OCC Flags 2
Addr:	000000000006C0B2 (SCOM) 000000000006C0B3 (SCOM1) 000000000006C0B4 (SCOM2) 00000000C0060590 (OCI) 00000000C0060598 (OCI1) 00000000C00605A0 (OCI2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG2
Constant(s):
Comments:	The OCCFLG register is a scratch register that can be used by OCC firmware for flag setting
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.OCCFLG2_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	OCI	OCI1	OCI2	Dial: Description
0:31	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OCCFLG2_OCC_FLAGS: Flags that are defined by OCC Firmware
32:63	RO	RO	RO	RO	RO	RO	constant=0b00000000000000000000000000000000

OCB_OCI OCC Flags 3
Addr:	000000000006C0B5 (SCOM) 000000000006C0B6 (SCOM1) 000000000006C0B7 (SCOM2) 00000000C00605A8 (OCI) 00000000C00605B0 (OCI1) 00000000C00605B8 (OCI2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG3
Constant(s):
Comments:	The OCCFLG register is a scratch register that can be used by OCC firmware for flag setting
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.OCCFLG3_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	OCI	OCI1	OCI2	Dial: Description
0:31	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OCCFLG3_OCC_FLAGS: Flags that are defined by OCC Firmware
32:63	RO	RO	RO	RO	RO	RO	constant=0b00000000000000000000000000000000

OCB_OCI OCC Flags 4
Addr:	000000000006C0B8 (SCOM) 000000000006C0B9 (SCOM1) 000000000006C0BA (SCOM2) 00000000C00605C0 (OCI) 00000000C00605C8 (OCI1) 00000000C00605D0 (OCI2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG4
Constant(s):
Comments:	The OCCFLG register is a scratch register that can be used by OCC firmware for flag setting
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.OCCFLG4_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	OCI	OCI1	OCI2	Dial: Description
0:31	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OCCFLG4_OCC_FLAGS: Flags that are defined by OCC Firmware
32:63	RO	RO	RO	RO	RO	RO	constant=0b00000000000000000000000000000000

OCB_OCI OCC Flags 5
Addr:	000000000006C0BB (SCOM) 000000000006C0BC (SCOM1) 000000000006C0BD (SCOM2) 00000000C00605D8 (OCI) 00000000C00605E0 (OCI1) 00000000C00605E8 (OCI2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG5
Constant(s):
Comments:	The OCCFLG register is a scratch register that can be used by OCC firmware for flag setting
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.OCCFLG5_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	OCI	OCI1	OCI2	Dial: Description
0:31	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OCCFLG5_OCC_FLAGS: Flags that are defined by OCC Firmware
32:63	RO	RO	RO	RO	RO	RO	constant=0b00000000000000000000000000000000

OCB_OCI OCC Flags 6
Addr:	000000000006C0BE (SCOM) 000000000006C0BF (SCOM1) 000000000006C0C0 (SCOM2) 00000000C00605F0 (OCI) 00000000C00605F8 (OCI1) 00000000C0060600 (OCI2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG6
Constant(s):
Comments:	The OCCFLG register is a scratch register that can be used by OCC firmware for flag setting
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.OCCFLG6_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	OCI	OCI1	OCI2	Dial: Description
0:31	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OCCFLG6_OCC_FLAGS: Flags that are defined by OCC Firmware
32:63	RO	RO	RO	RO	RO	RO	constant=0b00000000000000000000000000000000

OCB_OCI OCC Flags 7
Addr:	000000000006C0C1 (SCOM) 000000000006C0C2 (SCOM1) 000000000006C0C3 (SCOM2) 00000000C0060608 (OCI) 00000000C0060610 (OCI1) 00000000C0060618 (OCI2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG7
Constant(s):
Comments:	The OCCFLG register is a scratch register that can be used by OCC firmware for flag setting
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.OCCFLG7_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	OCI	OCI1	OCI2	Dial: Description
0:31	RW	WO_CLEAR	WO_OR	RW	WO_CLEAR	WO_OR	OCB_OCI_OCCFLG7_OCC_FLAGS: Flags that are defined by OCC Firmware
32:63	RO	RO	RO	RO	RO	RO	constant=0b00000000000000000000000000000000

OCB_OCI OCC Timer Register 0
Addr:	000000000006C100 (SCOM) 00000000C0060800 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OTR0
Constant(s):	PU_OCB_OCI_OTR0
Comments:	Timer control and status for OCC timer 0
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITPTIMER0.TIMEOUT_Q_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITPTIMER0.CTRL_Q_INST.LATC.L2(0) [0]
	2	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITPTIMER0.AUTO_RELOAD_Q_INST.LATC.L2(0) [0]
	3:15	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITPTIMER0.RSVD_Q_0_INST.LATC.L2(0:12) [0000000000000]
	16:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITPTIMER0.TIMER_Q_0_INST.LATC.L2(0:15) [0000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	RWX_WCLEAR	RWX_WCLEAR		OCB_OCI_OTR0_TIMEOUT_0: This bit is set by hardware on any 1 -> 0 transition of the timer. This value of this bit is provided to the interrupt controller as the occ_timer0 status. The interrupt controller would typically be programmed to recognize occ_timer0 as an active-high, level sensitive interrupt. This bit is reset by writing the register with a 1 in this bit position. If the hardware timer value transition from 1 -> 0 occurs concurrently with the updating of this register to perform a reset, then this bit is reset and the hardware transition is lost.
1	WO	WO		OCB_OCI_OTR0_CONTROL_0: Reading this bit always returns 0. If the register is written with a 1 in this bit position, then all other fields other than timeout are updated. Otherwise the write has no effect other than to clear the timeout_0 field if the timeout_0 bit is set in the write data. If the register is written with a 1 in this bit position and a 0 in the timeout bit position which occurs concurrently with the hardware timer value making a 1 -> 0 transition, the timeout_0 bit will be set per the previous timer_0 settings.
2	RW	RW		OCB_OCI_OTR0_AUTO_RELOAD_0: If set, the timer operates in auto-reload mode. In auto-reload mode, every timeout of the timer sets the timeout_0 bit and reinitializes the timer counter from the hidden auto-reload value. If clear, then a timeout of the timer simply sets the timeout_0 bit. This field can only be written if the control_0 bit is set on a write of the register.
3:15	RW	RW		OCB_OCI_OTR0_SPARE_0: Writes store the value only if the control_0 bit is set on a write of this register. Reads return the last value written.
16:31	RWX	RWX		OCB_OCI_OTR0_TIMER_0: When the register is read, this field returns the current value of the hardware timer. When written, the value of the field goes into the hardware timer and the hidden auto-reload register, and the hardware timer begins to decrement. This field can only be written if the control_0 bit is set on a write of the register.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCC Timer Register 1
Addr:	000000000006C101 (SCOM) 00000000C0060808 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OTR1
Constant(s):	PU_OCB_OCI_OTR1
Comments:	Timer control and status for OCC timer 0
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITPTIMER1.TIMEOUT_Q_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITPTIMER1.CTRL_Q_INST.LATC.L2(0) [0]
	2	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITPTIMER1.AUTO_RELOAD_Q_INST.LATC.L2(0) [0]
	3:15	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITPTIMER1.RSVD_Q_0_INST.LATC.L2(0:12) [0000000000000]
	16:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.ITPTIMER1.TIMER_Q_0_INST.LATC.L2(0:15) [0000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	RWX_WCLEAR	RWX_WCLEAR		OCB_OCI_OTR1_TIMEOUT_1: This bit is set by hardware on any 1 -> 0 transition of the timer. This value of this bit is provided to the interrupt controller as the occ_timer1 status. The interrupt controller would typically be programmed to recognize occ_timer1 as an active-high, level sensitive interrupt. This bit is reset by writing the register with a 1 in this bit position. If the hardware timer value transition from 1 -> 0 occurs concurrently with the updating of this register to perform a reset, then this bit is reset and the hardware transition is lost.
1	WO	WO		OCB_OCI_OTR1_CONTROL_1: Reading this bit always returns 0. If the register is written with a 1 in this bit position, then all other fields other than timeout are updated. Otherwise the write has no effect other than to clear the timeout_1 field if the timeout_1 bit is set in the write data. If the register is written with a 1 in this bit position and a 0 in the timeout bit position which occurs concurrently with the hardware timer value making a 1 -> 0 transition, the timeout_1 bit will be set per the previous timer_1 settings.
2	RW	RW		OCB_OCI_OTR1_AUTO_RELOAD_1: If set, the timer operates in auto-reload mode. In auto-reload mode, every timeout of the timer sets the timeout_1 bit and reinitializes the timer counter from the hidden auto-reload value. If clear, then a timeout of the timer simply sets the timeout_1 bit. This field can only be written if the control_1 bit is set on a write of the register.
3:15	RW	RW		OCB_OCI_OTR1_SPARE_1: Writes store the value only if the control_1 bit is set on a write of this register. Reads return the last value written.
16:31	RWX	RWX		OCB_OCI_OTR1_TIMER_1: When the register is read, this field returns the current value of the hardware timer. When written, the value of the field goes into the hardware timer and the hidden auto-reload register, and the hardware timer begins to decrement. This field can only be written if the control_1 bit is set on a write of the register.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI Divide Enablement Register for PPE 0
Addr:	000000000006C180 (SCOM) 00000000C0060C00 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_DERP0
Constant(s):
Comments:	Provides an Unsigned Integer Divide function, since PPE does not support a divide instruction. Writing either all 8B or just the upper 4B of this register (DIVIDEND) initiates a hardware state machine to perform an iterative divide algorithm. Attempting to divide by Zero, or writing to eithjer field in this register when a DIVIDE operation is already ongoing, causes the DORP0 register to be set to all 1s and resets the divide state machine logic. Intended usage is to write the DERP0 and poll for the ones complement of DORP00(0:63) to be non-zero (meaning no longer a value of all 1s). Note that unlike most OCB registers, this register can be accessed using 8B transactions to write (or read) with a single OCI transaction. The intent is for the GPEs to access via 8B operations for efficiency. 4B writes to the lower 4B of this register (DIVISOR) will change its value but do not initiate a calculation. NOTE: Per convention DERP/DORP0 are assigned to GPE0
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.COE0.DERP_DIVIDEND_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.OCB.COE0.DERP_DIVISOR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RW	RW		OCB_OCI_DERP0_DIVIDEND: Numerator. Unsigned Value that is being divided. WRITE_EFFECT { DORP0.REMAINDER=0xFFFFFFFF; DORP0.QUOTIENT=0xFFFFFFFF; } AFTER_DELAY[small] { if (DERP0.DIVISOR != 0x0) { DORP0.QUOTIENT = cast(DERP0.DIVIDEND,uint32) / cast(DERP0.DIVISOR,uint32); DORP0.REMAINDER = cast(DERP0.DIVIDEND,uint32) % cast(DERP0.DIVISOR,uint32); } } // note: model the divide operation when these 4 bytes are written
32:63	RW	RW		OCB_OCI_DERP0_DIVISOR: Denominator. Unsigned Value by which to divide. Note: Setting this to zero is not a valid operation. // note: writing just these 4bytes does not have effect on the DORP

OCB_OCI Divide Result Output 0 for PPE 0
Addr:	000000000006C181 (SCOM) 00000000C0060C08 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_DORP0
Constant(s):
Comments:	Provides the unsigned result of the division after the DERP0 is written. When the iterative hardware state machine is actively computing a divide request, SCOM reads to this register return a value of all 1s which is not a valid result (Engineering note: the latches in this register can be used in the actual calculation). If an illegal operation is attempted, this register is actually written by hardware to all 1s. Once a valid divide operation is complete, reads to this register return the result of the previously requested divide operation. Note that unlike most OCB registers, this register can be accessed using 8B (or 4B) transactions to read with a single OCI transaction. The intent is for GPE to access via 8B operations for efficiency.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.COE0.DORP_QUOTIENT_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.OCB.COE0.DORP_REMAINDER_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_DORP0_QUOTIENT: Result of the DERP-requested divide operation: DIVIDEND div DIVISOR
32:63	ROX	ROX		OCB_OCI_DORP0_REMAINDER: Remainder (outcome of the MODULO operation): DIVIDEND mod DIVISOR

OCB_OCI Divide Enablement Register for PPE 1
Addr:	000000000006C182 (SCOM) 00000000C0060C10 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_DERP1
Constant(s):
Comments:	Provides an Unsigned Integer Divide function, since PPE does not support a divide instruction. Writing either all 8B or just the upper 4B of this register (DIVIDEND) initiates a hardware state machine to perform an iterative divide algorithm. Attempting to divide by Zero, or writing to eithjer field in this register when a DIVIDE operation is already ongoing, causes the DORP0 register to be set to all 1s and resets the divide state machine logic. Intended usage is to write the DERP0 and poll for the ones complement of DORP00(0:63) to be non-zero (meaning no longer a value of all 1s). Note that unlike most OCB registers, this register can be accessed using 8B transactions to write (or read) with a single OCI transaction. The intent is for the GPEs to access via 8B operations for efficiency. 4B writes to the lower 4B of this register (DIVISOR) will change its value but do not initiate a calculation. NOTE: Per convention DERP/DORP0 are assigned to GPE0
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.COE1.DERP_DIVIDEND_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.OCB.COE1.DERP_DIVISOR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RW	RW		OCB_OCI_DERP1_DIVIDEND: Numerator. Unsigned Value that is being divided. WRITE_EFFECT { DORP1.REMAINDER=0xFFFFFFFF; DORP1.QUOTIENT=0xFFFFFFFF; } AFTER_DELAY[small] { if (DERP1.DIVISOR != 0x0) { DORP1.QUOTIENT = cast(DERP1.DIVIDEND,uint32) / cast(DERP1.DIVISOR,uint32); DORP1.REMAINDER = cast(DERP1.DIVIDEND,uint32) % cast(DERP1.DIVISOR,uint32); } } // note: model the divide operation when these 4 bytes are written
32:63	RW	RW		OCB_OCI_DERP1_DIVISOR: Denominator. Unsigned Value by which to divide. Note: Setting this to zero is not a valid operation. // note: writing just these 4bytes does not have effect on the DORP

OCB_OCI Divide Result Output 1 for PPE 1
Addr:	000000000006C183 (SCOM) 00000000C0060C18 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_DORP1
Constant(s):
Comments:	Provides the unsigned result of the division after the DERP0 is written. When the iterative hardware state machine is actively computing a divide request, SCOM reads to this register return a value of all 1s which is not a valid result (Engineering note: the latches in this register can be used in the actual calculation). If an illegal operation is attempted, this register is actually written by hardware to all 1s. Once a valid divide operation is complete, reads to this register return the result of the previously requested divide operation. Note that unlike most OCB registers, this register can be accessed using 8B (or 4B) transactions to read with a single OCI transaction. The intent is for GPE to access via 8B operations for efficiency.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.COE1.DORP_QUOTIENT_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.OCB.COE1.DORP_REMAINDER_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_DORP1_QUOTIENT: Result of the DERP-requested divide operation: DIVIDEND div DIVISOR
32:63	ROX	ROX		OCB_OCI_DORP1_REMAINDER: Remainder (outcome of the MODULO operation): DIVIDEND mod DIVISOR

OCB_OCI Divide Enablement Register for PPE 2
Addr:	000000000006C184 (SCOM) 00000000C0060C20 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_DERP2
Constant(s):
Comments:	Provides an Unsigned Integer Divide function, since PPE does not support a divide instruction. Writing either all 8B or just the upper 4B of this register (DIVIDEND) initiates a hardware state machine to perform an iterative divide algorithm. Attempting to divide by Zero, or writing to eithjer field in this register when a DIVIDE operation is already ongoing, causes the DORP0 register to be set to all 1s and resets the divide state machine logic. Intended usage is to write the DERP0 and poll for the ones complement of DORP00(0:63) to be non-zero (meaning no longer a value of all 1s). Note that unlike most OCB registers, this register can be accessed using 8B transactions to write (or read) with a single OCI transaction. The intent is for the GPEs to access via 8B operations for efficiency. 4B writes to the lower 4B of this register (DIVISOR) will change its value but do not initiate a calculation. NOTE: Per convention DERP/DORP0 are assigned to GPE0
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.COE2.DERP_DIVIDEND_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.OCB.COE2.DERP_DIVISOR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RW	RW		OCB_OCI_DERP2_DIVIDEND: Numerator. Unsigned Value that is being divided. WRITE_EFFECT { DORP2.REMAINDER=0xFFFFFFFF; DORP2.QUOTIENT=0xFFFFFFFF; } AFTER_DELAY[small] { if (DERP2.DIVISOR != 0x0) { DORP2.QUOTIENT = cast(DERP2.DIVIDEND,uint32) / cast(DERP2.DIVISOR,uint32); DORP2.REMAINDER = cast(DERP2.DIVIDEND,uint32) % cast(DERP2.DIVISOR,uint32); } } // note: model the divide operation when these 4 bytes are written
32:63	RW	RW		OCB_OCI_DERP2_DIVISOR: Denominator. Unsigned Value by which to divide. Note: Setting this to zero is not a valid operation. // note: writing just these 4bytes does not have effect on the DORP

OCB_OCI Divide Result Output 2 for PPE 2
Addr:	000000000006C185 (SCOM) 00000000C0060C28 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_DORP2
Constant(s):
Comments:	Provides the unsigned result of the division after the DERP0 is written. When the iterative hardware state machine is actively computing a divide request, SCOM reads to this register return a value of all 1s which is not a valid result (Engineering note: the latches in this register can be used in the actual calculation). If an illegal operation is attempted, this register is actually written by hardware to all 1s. Once a valid divide operation is complete, reads to this register return the result of the previously requested divide operation. Note that unlike most OCB registers, this register can be accessed using 8B (or 4B) transactions to read with a single OCI transaction. The intent is for GPE to access via 8B operations for efficiency.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.COE2.DORP_QUOTIENT_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.OCB.COE2.DORP_REMAINDER_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_DORP2_QUOTIENT: Result of the DERP-requested divide operation: DIVIDEND div DIVISOR
32:63	ROX	ROX		OCB_OCI_DORP2_REMAINDER: Remainder (outcome of the MODULO operation): DIVIDEND mod DIVISOR

OCB_OCI Divide Enablement Register for PPE 3
Addr:	000000000006C186 (SCOM) 00000000C0060C30 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_DERP3
Constant(s):
Comments:	Provides an Unsigned Integer Divide function, since PPE does not support a divide instruction. Writing either all 8B or just the upper 4B of this register (DIVIDEND) initiates a hardware state machine to perform an iterative divide algorithm. Attempting to divide by Zero, or writing to eithjer field in this register when a DIVIDE operation is already ongoing, causes the DORP0 register to be set to all 1s and resets the divide state machine logic. Intended usage is to write the DERP0 and poll for the ones complement of DORP00(0:63) to be non-zero (meaning no longer a value of all 1s). Note that unlike most OCB registers, this register can be accessed using 8B transactions to write (or read) with a single OCI transaction. The intent is for the GPEs to access via 8B operations for efficiency. 4B writes to the lower 4B of this register (DIVISOR) will change its value but do not initiate a calculation. NOTE: Per convention DERP/DORP0 are assigned to GPE0
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.COE3.DERP_DIVIDEND_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.OCB.COE3.DERP_DIVISOR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RW	RW		OCB_OCI_DERP3_DIVIDEND: Numerator. Unsigned Value that is being divided. WRITE_EFFECT { DORP3.REMAINDER=0xFFFFFFFF; DORP3.QUOTIENT=0xFFFFFFFF; } AFTER_DELAY[small] { if (DERP3.DIVISOR != 0x0) { DORP3.QUOTIENT = cast(DERP3.DIVIDEND,uint32) / cast(DERP3.DIVISOR,uint32); DORP3.REMAINDER = cast(DERP3.DIVIDEND,uint32) % cast(DERP3.DIVISOR,uint32); } } // note: model the divide operation when these 4 bytes are written
32:63	RW	RW		OCB_OCI_DERP3_DIVISOR: Denominator. Unsigned Value by which to divide. Note: Setting this to zero is not a valid operation. // note: writing just these 4bytes does not have effect on the DORP

OCB_OCI Divide Result Output 3 for PPE 3
Addr:	000000000006C187 (SCOM) 00000000C0060C38 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_DORP3
Constant(s):
Comments:	Provides the unsigned result of the division after the DERP0 is written. When the iterative hardware state machine is actively computing a divide request, SCOM reads to this register return a value of all 1s which is not a valid result (Engineering note: the latches in this register can be used in the actual calculation). If an illegal operation is attempted, this register is actually written by hardware to all 1s. Once a valid divide operation is complete, reads to this register return the result of the previously requested divide operation. Note that unlike most OCB registers, this register can be accessed using 8B (or 4B) transactions to read with a single OCI transaction. The intent is for GPE to access via 8B operations for efficiency.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.COE3.DORP_QUOTIENT_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.OCB.COE3.DORP_REMAINDER_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_DORP3_QUOTIENT: Result of the DERP-requested divide operation: DIVIDEND div DIVISOR
32:63	ROX	ROX		OCB_OCI_DORP3_REMAINDER: Remainder (outcome of the MODULO operation): DIVIDEND mod DIVISOR

OCB_OCI OCB Stream Pull Base 0 Register
Addr:	000000000006C200 (SCOM) 00000000C0061000 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLBR0
Constant(s):	PU_OCB_OCI_OCBSLBR0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.PULL_OCI_BASE_REGION_LT_0_INST.LATC.L2(0:2) [000]
	3:28	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.PULL_START_ADDR_LT_0_INST.LATC.L2(0:25) [00000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:2	RW	RW		pull_oci_region
3:28	RW	RW		pull_start
29:63	RO	RO		constant=0b00000000000000000000000000000000000

OCB_OCI OCB Stream Pull Control/Status 0 Register
Addr:	000000000006C201 (SCOM) 00000000C0061008 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLCS0
Constant(s):	PU_OCB_OCI_OCBSLCS0
Comments:	Writes to this register cause the Pull Queue to be reset.OCB0
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.PULL_FULL_LT_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.PULL_EMPTY_LT_INST.LATC.L2(0) [0]
	2:3	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.RESERVED_PULL_LT_0_INST.LATC.L2(0:1) [00]
	4:5	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.PULL_INTR_ACTION_LT_0_INST.LATC.L2(0:1) [00]
	6:10	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.PULL_LENGTH_LT_0_INST.LATC.L2(0:4) [00000]
	13:17	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.PULL_WRITE_PTR_LT_0_INST.LATC.L2(0:4) [00000]
	21:25	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.PULL_READ_PTR_LT_0_INST.LATC.L2(0:4) [00000]
	31	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.PULL_ENABLE_LT_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0	RWX_WCLRPART	RWX_WCLRPART		OCB_OCI_OCBSLCS0_PULL_FULL: Reads indicate the Pull Queue is full condition Any write to this register clears this indicator and clears pull_write_ptr and pull_read_ptr to 0s. (this is a means for resetting the queue hardware) RWX_WCLRPART Dial enums: NOT_FULL=>0b0 FULL=>0b1
1	RWX_WSETPART	RWX_WSETPART		OCB_OCI_OCBSLCS0_PULL_EMPTY: Reads indicate the Pull Queue empty condition Any write to this register sets this indicator and clears pull_write_ptr and pull_read_ptr to 0s. (this is a means for resetting the queue hardware) RWX_WSETPART Dial enums: NOT_EMPTY=>0b0 EMPTY=>0b1
2:3	RW	RW		OCB_OCI_OCBSLCS0_SPARE: Implemented but not used Writes store the value. Reads return the last value written.
4:5	RW	RW		OCB_OCI_OCBSLCS0_PULL_INTR_ACTION_0_1: Pull Interrupt Action This field controls the condition which will assert the pull interrupt signal for this channel to the OCB interrupt controller. b00 = Full (default upon hardware init) b01 = Non Full b10 = Empty (the more useful firmware default) b11 = Not Empty
6:10	RW	RW		OCB_OCI_OCBSLCS0_PULL_LENGTH: Pull Queue length in (pull_length + 1) * 8B Value mapping: 0b00000: 8B 0b00001: 16B 0b00010: 24B 0b00011: 32B 0b00100: 40B 0b00101: 48B 0b00110: 56B 0b00111: 64B 0b01000: 72B 0b01001: 80B 0b01010: 88B 0b01011: 96B 0b01100: 104B 0b01101: 112B 0b01110: 120B 0b01111: 128B 0b10000: 136B 0b10001: 144B 0b10010: 152B 0b10011: 160B 0b10100: 168B 0b10101: 176B 0b10110: 184B 0b10111: 192B 0b11000: 200B 0b11001: 208B 0b11010: 216B 0b11011: 224B 0b11100: 232B 0b11101: 240B 0b11110: 248B 0b11111: 256B
11:12	RO	RO		constant=0b00
13:17	RWX_WCLRPART	RWX_WCLRPART		OCB_OCI_OCBSLCS0_PULL_WRITE_PTR: Pull write pointer Reads indicate the current Pull Queue write pointer in increments of 8B. The actual address used is pull_oci_region || pull_start + pull_write_ptr || 00000. Writes to this field are ignored. Hardware performs all modifications. This field is cleared upon a write to this register. ROX_WCLRPART
18:20	RO	RO		constant=0b000
21:25	RWX_WCLRPART	RWX_WCLRPART		OCB_OCI_OCBSLCS0_PULL_READ_PTR: Pull read pointer Reads indicate the current Pull Queue read pointer in increments of 8B. The actual address used is pull_oci_region || pull_start + pull_write_ptr || 00000. This field is cleared upon a write to this register. ROX_WCLRPART
26:30	RO	RO		constant=0b00000
31	RW	RW		OCB_OCI_OCBSLCS0_PULL_ENABLE: Enables the Pull Queue function If Disabled, PIB Reads to OCB Data 0 Register to perform a pull will result in an "offline" PIB error back to the PIB Master. Note: OCI Reads to OCB Stream Pull Increment 0 Register to cause incrementation are unaffected by the setting of this bit. Full and/or empty conditions may still arise to the OCC even if this bit indicates disabled. Dial enums: DISABLED=>0b0 ENABLED=>0b1
32:63	RO	RO		constant=0b00000000000000000000000000000000 Dial enums: DISABLED=>0b0 ENABLED=>0b1

OCB_OCI OCB Stream Pull Increment 0 Register
Addr:	000000000006C202 (SCOM) 00000000C0061010 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLI0
Constant(s):	PU_OCB_OCI_OCBSLI0
Comments:	Reads to this register cause the Pull Queue Write pointer to increment by 1 modulo the Pull Queue Size and will do so independent of the setting of OCB Control/Status 0 Register[ocb_stream_mode], OCB Control/Status 0 Register[ocb_stream_type] or OCB Stream Pull Control/Status 0 Register[pull_enable]. This allows OCC firmware to be manipulating these pointers while the other side is using the channel in an indirect or linear mode concurrently.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:63	RO	RO		constant=0b0000000000000000000000000000000000000000000000000000000000000000

OCB_OCI OCB Stream Push Base 0 Register
Addr:	000000000006C203 (SCOM) 00000000C0061018 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHBR0
Constant(s):	PU_OCB_OCI_OCBSHBR0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.PUSH_OCI_BASE_REGION_LT_0_INST.LATC.L2(0:2) [000]
	3:28	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.PUSH_START_ADDR_LT_0_INST.LATC.L2(0:25) [00000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:2	RW	RW		push_oci_region
3:28	RW	RW		push_start
29:63	RO	RO		constant=0b00000000000000000000000000000000000

OCB_OCI OCB Stream Push Control/Status 0 Register
Addr:	000000000006C204 (SCOM) 00000000C0061020 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHCS0
Constant(s):	PU_OCB_OCI_OCBSHCS0
Comments:	Controls the behavior of Push Queue n. Writes to this register cause the queue hardware to be reset.
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.PUSH_FULL_LT_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.PUSH_EMPTY_LT_INST.LATC.L2(0) [0]
	2:3	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.RESERVED_PUSH_LT_0_INST.LATC.L2(0:1) [00]
	4:5	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.PUSH_INTR_ACTION_LT_0_INST.LATC.L2(0:1) [00]
	6:10	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.PUSH_LENGTH_LT_0_INST.LATC.L2(0:4) [00000]
	13:17	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.PUSH_WRITE_PTR_LT_0_INST.LATC.L2(0:4) [00000]
	21:25	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.PUSH_READ_PTR_LT_0_INST.LATC.L2(0:4) [00000]
	31	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.PUSH_ENABLE_LT_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0	RWX_WCLRPART	RWX_WCLRPART		OCB_OCI_OCBSHCS0_PUSH_FULL: Reads indicate the Push Queue is full condition Any write to this register clears this indicator and clears push_write_ptr and push_read_ptr to 0s. (this is a means for resetting the queue hardware) RWX_WCLR Dial enums: NOT_FULL=>0b0 FULL=>0b1
1	RWX_WSETPART	RWX_WSETPART		OCB_OCI_OCBSHCS0_PUSH_EMPTY: Read indicate the Push Queue empty condition Any write to this register sets this indicator and clears push_write_ptr and push_read_ptr to 0s. (this is a means for resetting the queue hardware) RWX_WSETPART Dial enums: NOT_EMPTY=>0b0 EMPTY=>0b1
2:3	RW	RW		OCB_OCI_OCBSHCS0_SPARE: Implemented by not used Writes store the value. Reads return the last value written.
4:5	RW	RW		OCB_OCI_OCBSHCS0_PUSH_INTR_ACTION_0_1: Push Interrupt Action This field controls the condition which will assert the push interrupt signal for this channel to the OCB interrupt controller. b00 = Full (default upon hardware init) b01 = Non Full b10 = Empty b11 = Not Empty
6:10	RW	RW		OCB_OCI_OCBSHCS0_PUSH_LENGTH: Push Queue length in (push_length + 1) * 8B Value mapping: 0b00000: 8B 0b00001: 16B 0b00010: 24B 0b00011: 32B 0b00100: 40B 0b00101: 48B 0b00110: 56B 0b00111: 64B 0b01000: 72B 0b01001: 80B 0b01010: 88B 0b01011: 96B 0b01100: 104B 0b01101: 112B 0b01110: 120B 0b01111: 128B 0b10000: 136B 0b10001: 144B 0b10010: 152B 0b10011: 160B 0b10100: 168B 0b10101: 176B 0b10110: 184B 0b10111: 192B 0b11000: 200B 0b11001: 208B 0b11010: 216B 0b11011: 224B 0b11100: 232B 0b11101: 240B 0b11110: 248B 0b11111: 256B
11:12	RO	RO		constant=0b00
13:17	RWX_WCLRPART	RWX_WCLRPART		OCB_OCI_OCBSHCS0_PUSH_WRITE_PTR: Push write pointer Reads indicate the current Push Queue write pointer in increments of 8B. The actual address used is push_oci_region || push_start + push_write_ptr || 00000. Writes to this field are ignored. Hardware performs all modifications. This field is cleared upon a write to this register. ROX_WCLRPART
18:20	RO	RO		constant=0b000
21:25	RWX_WCLRPART	RWX_WCLRPART		OCB_OCI_OCBSHCS0_PUSH_READ_PTR: Push read pointer Reads indicate the current Push Queue read pointer in increments of 8B. The actual address used is push_oci_region || push_start + push_read_ptr || 00000. This field is cleared upon a write to this register. ROX_WCLRPART
26:30	RO	RO		constant=0b00000
31	RW	RW		OCB_OCI_OCBSHCS0_PUSH_ENABLE: Enables the Push Queue function If Disabled, PIB Writes to OCB Data 0 Register to perform a push will result in an "offline" PIB error back to the PIB Master. Note: OCI Writes to OCB Stream Push Increment 0 Register to cause incrementation are unaffected by the setting of this bit. Full and/or empty conditions may still arise to the OCC even if this bit indicates disabled. Dial enums: DISABLED=>0b0 ENABLED=>0b1
32:63	RO	RO		constant=0b00000000000000000000000000000000 Dial enums: DISABLED=>0b0 ENABLED=>0b1

OCB_OCI OCB Stream Push Increment 0 Register
Addr:	000000000006C205 (SCOM) 00000000C0061028 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHI0
Constant(s):	PU_OCB_OCI_OCBSHI0
Comments:	Writes to this register cause the Push Queue Read pointer to increment by 1 modulo the Push Queue Size and will do so independent of the setting of OCB Control/Status 0 Register[ocb_stream_mode], OCB Control/Status 0 Register[ocb_stream_type] or OCB Stream Push Control/Status 0 Register[push_enable]. This allows OCC firmware to be manipulating these pointers while the other side is using the channel in an indirect or linear mode concurrently.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:63	RO	RO		constant=0b0000000000000000000000000000000000000000000000000000000000000000

OCB_OCI OCB Stream Error Status 0 Register
Addr:	000000000006C206 (SCOM) 00000000C0061030 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSES0
Constant(s):	PU_OCB_OCI_OCBSES0
Comments:	Indicates errors that occur in an indirect channel when in a streaming mode (linear or circular)
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.PUSH_READ_UNDERFLOW_LT_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.PULL_WRITE_OVERFLOW_LT_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0	RWX	RWX		OCB_OCI_OCBSES0_PUSH_READ_UNDERFLOW: Push Queue Read Underflow Underflow is defined as a store to the push_read_incr facility is done and the push_empty facility is already set. This bit is cleared only by a firmware write of this bit to 0. Dial enums: UNDERFLOW_NOT_DETECTED=>0b0 UNDERFLOW_DETECTED=>0b1
1	RWX	RWX		OCB_OCI_OCBSES0_PULL_WRITE_OVERFLOW: Pull Queue Write Overflow Overflow is defined as a load to the pull_write_incr facility is done and the pull_full facility is already set. This bit is cleared only by a firmware write of this bit to 0. Dial enums: OVERFLOW_NOT_DETECTED=>0b0 OVERFLOW_DETECTED=>0b1
2:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000000000 Dial enums: OVERFLOW_NOT_DETECTED=>0b0 OVERFLOW_DETECTED=>0b1

OCB_OCI OCB Linear Write Window Control 0 Register
Addr:	000000000006C208 (SCOM) 00000000C0061040 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWCR0
Constant(s):	PU_OCB_OCI_OCBLWCR0
Comments:	This OCI accessible register controls the Linear Write Window access facility.
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.LINEAR_WINDOW_ENABLE_LT_INST.LATC.L2(0) [0]
	1:2	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.LIN_WIN_WR_CTRL_SPARE_LT_0_INST.LATC.L2(0:1) [00]
	3:19	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.LINEAR_WINDOW_BAR_LT_0_INST.LATC.L2(0:16) [00000000000000000]
	20:31	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.LINEAR_WINDOW_MASK_LT_0_INST.LATC.L2(0:11) [000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	RW	RW		OCB_OCI_OCBLWCR0_LINEAR_WINDOW_ENABLE: Linear Window Enable 0: Window facility disabled. See Power Management Specification, section "Indirect Bridge Operation" for the effects of this bit for a write operation as it is dependent on the setting of trusted mode. 1: Window facility enabled. If OCBCSR0.ocb_stream_type= "linear", Linear Window BAR and Mask are valid and operations are to be honored. sc_resp codes are the same as for the OCB indirect facility to reflect the status of the OCI operation.
1:2	RW	RW		OCB_OCI_OCBLWCR0_SPARE_0: Implemented by not used Writes store the value. Reads return the last value written.
3:19	RW	RW		OCB_OCI_OCBLWCR0_LINEAR_WINDOW_BAR: Linear Window Base Address Register Defines OCI address(12:28) - 17 bits to define the starting offset within the region addressed
20:31	RW	RW		OCB_OCI_OCBLWCR0_LINEAR_WINDOW_MASK: Linear Window Address Mask Register Masks OCI address (17:28) - 12 bits to define the window size
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCB Linear Write Window Status 0 Register
Addr:	000000000006C20A (SCOM) 00000000C0061050 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWSR0
Constant(s):	PU_OCB_OCI_OCBLWSR0
Comments:	This OCI accessible register provides status of the Linear Write Window access facility.
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.LINEAR_WINDOW_SCRESP_LT_0_INST.LATC.L2(0:2) [000]
	3:7	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.LIN_WIN_STATUS_SPARE_LT_0_INST.LATC.L2(0:4) [00000]
Bit(s)	SCOM	OCI		Dial: Description
0:2	ROX	ROX		OCB_OCI_OCBLWSR0_LINEAR_WINDOW_SCRESP: Linear Window PIB SC Response If OCBLWCR.linear_window_enable=1, this field contains the last PIB response code sent (potentially allowing OCC FW to tell if attempts were made to use the window.
3:7	RO	RO		OCB_OCI_OCBLWSR0_SPARE0: Implemented but not used
8:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000

OCB_OCI OCB Linear Window Write Base 0 Register
Addr:	000000000006C20C (SCOM) 00000000C0061060 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWSBR0
Constant(s):	PU_OCB_OCI_OCBLWSBR0
Comments:	This OCI accessible register that defines the placement of the SRAM base address for use by the OCB Linear Write Window function of the indirect channel.
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.LINEAR_WINDOW_REGION_LT_0_INST.LATC.L2(0:2) [000]
	3:9	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.LINEAR_WINDOW_BASE_LT_0_INST.LATC.L2(0:6) [0000000]
Bit(s)	SCOM	OCI		Dial: Description
0:2	RW	RW		OCB_OCI_OCBLWSBR0_LINEAR_WINDOW_REGION: Linear Window Region If linear_window_enable=1, this field defines the OCI region (OCI Address(0:2) that is enabled for accessing the Linear Window. If the value written into OCBAR0 does not match this value and the OCBDR0 is accessed, a PIB scresp error is produced. Only the SRAM region (0b111) is supported.
3:9	RW	RW		OCB_OCI_OCBLWSBR0_LINEAR_WINDOW_BASE: Linear Window Base If linear_window_enable=1, establishes OCI Address(5:11); 128B aliases still apply (eg. OCI Address(3:4)
10:63	RO	RO		constant=0b000000000000000000000000000000000000000000000000000000

OCB_OCI OCB Stream Pull Base 1 Register
Addr:	000000000006C210 (SCOM) 00000000C0061080 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLBR1
Constant(s):	PU_OCB_OCI_OCBSLBR1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.PULL_OCI_BASE_REGION_LT_0_INST.LATC.L2(0:2) [000]
	3:28	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.PULL_START_ADDR_LT_0_INST.LATC.L2(0:25) [00000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:2	RW	RW		pull_oci_region
3:28	RW	RW		pull_start
29:63	RO	RO		constant=0b00000000000000000000000000000000000

OCB_OCI OCB Stream Pull Control/Status 1 Register
Addr:	000000000006C211 (SCOM) 00000000C0061088 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLCS1
Constant(s):	PU_OCB_OCI_OCBSLCS1
Comments:	Writes to this register cause the Pull Queue to be reset.OCB0
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.PULL_FULL_LT_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.PULL_EMPTY_LT_INST.LATC.L2(0) [0]
	2:3	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.RESERVED_PULL_LT_0_INST.LATC.L2(0:1) [00]
	4:5	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.PULL_INTR_ACTION_LT_0_INST.LATC.L2(0:1) [00]
	6:10	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.PULL_LENGTH_LT_0_INST.LATC.L2(0:4) [00000]
	13:17	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.PULL_WRITE_PTR_LT_0_INST.LATC.L2(0:4) [00000]
	21:25	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.PULL_READ_PTR_LT_0_INST.LATC.L2(0:4) [00000]
	31	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.PULL_ENABLE_LT_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0	RWX_WCLRPART	RWX_WCLRPART		OCB_OCI_OCBSLCS1_PULL_FULL: Reads indicate the Pull Queue is full condition Any write to this register clears this indicator and clears pull_write_ptr and pull_read_ptr to 0s. (this is a means for resetting the queue hardware) RWX_WCLRPART Dial enums: NOT_FULL=>0b0 FULL=>0b1
1	RWX_WSETPART	RWX_WSETPART		OCB_OCI_OCBSLCS1_PULL_EMPTY: Reads indicate the Pull Queue empty condition Any write to this register sets this indicator and clears pull_write_ptr and pull_read_ptr to 0s. (this is a means for resetting the queue hardware) RWX_WSETPART Dial enums: NOT_EMPTY=>0b0 EMPTY=>0b1
2:3	RW	RW		OCB_OCI_OCBSLCS1_SPARE: Implemented but not used Writes store the value. Reads return the last value written.
4:5	RW	RW		OCB_OCI_OCBSLCS1_PULL_INTR_ACTION_0_1: Pull Interrupt Action This field controls the condition which will assert the pull interrupt signal for this channel to the OCB interrupt controller. b00 = Full (default upon hardware init) b01 = Non Full b10 = Empty (the more useful firmware default) b11 = Not Empty
6:10	RW	RW		OCB_OCI_OCBSLCS1_PULL_LENGTH: Pull Queue length in (pull_length + 1) * 8B Value mapping: 0b00000: 8B 0b00001: 16B 0b00010: 24B 0b00011: 32B 0b00100: 40B 0b00101: 48B 0b00110: 56B 0b00111: 64B 0b01000: 72B 0b01001: 80B 0b01010: 88B 0b01011: 96B 0b01100: 104B 0b01101: 112B 0b01110: 120B 0b01111: 128B 0b10000: 136B 0b10001: 144B 0b10010: 152B 0b10011: 160B 0b10100: 168B 0b10101: 176B 0b10110: 184B 0b10111: 192B 0b11000: 200B 0b11001: 208B 0b11010: 216B 0b11011: 224B 0b11100: 232B 0b11101: 240B 0b11110: 248B 0b11111: 256B
11:12	RO	RO		constant=0b00
13:17	RWX_WCLRPART	RWX_WCLRPART		OCB_OCI_OCBSLCS1_PULL_WRITE_PTR: Pull write pointer Reads indicate the current Pull Queue write pointer in increments of 8B. The actual address used is pull_oci_region || pull_start + pull_write_ptr || 00000. Writes to this field are ignored. Hardware performs all modifications. This field is cleared upon a write to this register. ROX_WCLRPART
18:20	RO	RO		constant=0b000
21:25	RWX_WCLRPART	RWX_WCLRPART		OCB_OCI_OCBSLCS1_PULL_READ_PTR: Pull read pointer Reads indicate the current Pull Queue read pointer in increments of 8B. The actual address used is pull_oci_region || pull_start + pull_write_ptr || 00000. This field is cleared upon a write to this register. ROX_WCLRPART
26:30	RO	RO		constant=0b00000
31	RW	RW		OCB_OCI_OCBSLCS1_PULL_ENABLE: Enables the Pull Queue function If Disabled, PIB Reads to OCB Data 1 Register to perform a pull will result in an "offline" PIB error back to the PIB Master. Note: OCI Reads to OCB Stream Pull Increment 1 Register to cause incrementation are unaffected by the setting of this bit. Full and/or empty conditions may still arise to the OCC even if this bit indicates disabled. Dial enums: DISABLED=>0b0 ENABLED=>0b1
32:63	RO	RO		constant=0b00000000000000000000000000000000 Dial enums: DISABLED=>0b0 ENABLED=>0b1

OCB_OCI OCB Stream Pull Increment 1 Register
Addr:	000000000006C212 (SCOM) 00000000C0061090 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLI1
Constant(s):	PU_OCB_OCI_OCBSLI1
Comments:	Reads to this register cause the Pull Queue Write pointer to increment by 1 modulo the Pull Queue Size and will do so independent of the setting of OCB Control/Status 0 Register[ocb_stream_mode], OCB Control/Status 0 Register[ocb_stream_type] or OCB Stream Pull Control/Status 0 Register[pull_enable]. This allows OCC firmware to be manipulating these pointers while the other side is using the channel in an indirect or linear mode concurrently.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:63	RO	RO		constant=0b0000000000000000000000000000000000000000000000000000000000000000

OCB_OCI OCB Stream Push Base 1 Register
Addr:	000000000006C213 (SCOM) 00000000C0061098 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHBR1
Constant(s):	PU_OCB_OCI_OCBSHBR1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.PUSH_OCI_BASE_REGION_LT_0_INST.LATC.L2(0:2) [000]
	3:28	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.PUSH_START_ADDR_LT_0_INST.LATC.L2(0:25) [00000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:2	RW	RW		push_oci_region
3:28	RW	RW		push_start
29:63	RO	RO		constant=0b00000000000000000000000000000000000

OCB_OCI OCB Stream Push Control/Status 1 Register
Addr:	000000000006C214 (SCOM) 00000000C00610A0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHCS1
Constant(s):	PU_OCB_OCI_OCBSHCS1
Comments:	Controls the behavior of Push Queue n. Writes to this register cause the queue hardware to be reset.
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.PUSH_FULL_LT_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.PUSH_EMPTY_LT_INST.LATC.L2(0) [0]
	2:3	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.RESERVED_PUSH_LT_0_INST.LATC.L2(0:1) [00]
	4:5	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.PUSH_INTR_ACTION_LT_0_INST.LATC.L2(0:1) [00]
	6:10	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.PUSH_LENGTH_LT_0_INST.LATC.L2(0:4) [00000]
	13:17	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.PUSH_WRITE_PTR_LT_0_INST.LATC.L2(0:4) [00000]
	21:25	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.PUSH_READ_PTR_LT_0_INST.LATC.L2(0:4) [00000]
	31	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.PUSH_ENABLE_LT_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0	RWX_WCLRPART	RWX_WCLRPART		OCB_OCI_OCBSHCS1_PUSH_FULL: Reads indicate the Push Queue is full condition Any write to this register clears this indicator and clears push_write_ptr and push_read_ptr to 0s. (this is a means for resetting the queue hardware) RWX_WCLR Dial enums: NOT_FULL=>0b0 FULL=>0b1
1	RWX_WSETPART	RWX_WSETPART		OCB_OCI_OCBSHCS1_PUSH_EMPTY: Read indicate the Push Queue empty condition Any write to this register sets this indicator and clears push_write_ptr and push_read_ptr to 0s. (this is a means for resetting the queue hardware) RWX_WSETPART Dial enums: NOT_EMPTY=>0b0 EMPTY=>0b1
2:3	RW	RW		OCB_OCI_OCBSHCS1_SPARE: Implemented by not used Writes store the value. Reads return the last value written.
4:5	RW	RW		OCB_OCI_OCBSHCS1_PUSH_INTR_ACTION_0_1: Push Interrupt Action This field controls the condition which will assert the push interrupt signal for this channel to the OCB interrupt controller. b00 = Full (default upon hardware init) b01 = Non Full b10 = Empty b11 = Not Empty
6:10	RW	RW		OCB_OCI_OCBSHCS1_PUSH_LENGTH: Push Queue length in (push_length + 1) * 8B Value mapping: 0b00000: 8B 0b00001: 16B 0b00010: 24B 0b00011: 32B 0b00100: 40B 0b00101: 48B 0b00110: 56B 0b00111: 64B 0b01000: 72B 0b01001: 80B 0b01010: 88B 0b01011: 96B 0b01100: 104B 0b01101: 112B 0b01110: 120B 0b01111: 128B 0b10000: 136B 0b10001: 144B 0b10010: 152B 0b10011: 160B 0b10100: 168B 0b10101: 176B 0b10110: 184B 0b10111: 192B 0b11000: 200B 0b11001: 208B 0b11010: 216B 0b11011: 224B 0b11100: 232B 0b11101: 240B 0b11110: 248B 0b11111: 256B
11:12	RO	RO		constant=0b00
13:17	RWX_WCLRPART	RWX_WCLRPART		OCB_OCI_OCBSHCS1_PUSH_WRITE_PTR: Push write pointer Reads indicate the current Push Queue write pointer in increments of 8B. The actual address used is push_oci_region || push_start + push_write_ptr || 00000. Writes to this field are ignored. Hardware performs all modifications. This field is cleared upon a write to this register. ROX_WCLRPART
18:20	RO	RO		constant=0b000
21:25	RWX_WCLRPART	RWX_WCLRPART		OCB_OCI_OCBSHCS1_PUSH_READ_PTR: Push read pointer Reads indicate the current Push Queue read pointer in increments of 8B. The actual address used is push_oci_region || push_start + push_read_ptr || 00000. This field is cleared upon a write to this register. ROX_WCLRPART
26:30	RO	RO		constant=0b00000
31	RW	RW		OCB_OCI_OCBSHCS1_PUSH_ENABLE: Enables the Push Queue function If Disabled, PIB Writes to OCB Data 1 Register to perform a push will result in an "offline" PIB error back to the PIB Master. Note: OCI Writes to OCB Stream Push Increment 1 Register to cause incrementation are unaffected by the setting of this bit. Full and/or empty conditions may still arise to the OCC even if this bit indicates disabled. Dial enums: DISABLED=>0b0 ENABLED=>0b1
32:63	RO	RO		constant=0b00000000000000000000000000000000 Dial enums: DISABLED=>0b0 ENABLED=>0b1

OCB_OCI OCB Stream Push Increment 1 Register
Addr:	000000000006C215 (SCOM) 00000000C00610A8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHI1
Constant(s):	PU_OCB_OCI_OCBSHI1
Comments:	Writes to this register cause the Push Queue Read pointer to increment by 1 modulo the Push Queue Size and will do so independent of the setting of OCB Control/Status 0 Register[ocb_stream_mode], OCB Control/Status 0 Register[ocb_stream_type] or OCB Stream Push Control/Status 0 Register[push_enable]. This allows OCC firmware to be manipulating these pointers while the other side is using the channel in an indirect or linear mode concurrently.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:63	RO	RO		constant=0b0000000000000000000000000000000000000000000000000000000000000000

OCB_OCI OCB Stream Error Status 1 Register
Addr:	000000000006C216 (SCOM) 00000000C00610B0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSES1
Constant(s):	PU_OCB_OCI_OCBSES1
Comments:	Indicates errors that occur in an indirect channel when in a streaming mode (linear or circular)
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.PUSH_READ_UNDERFLOW_LT_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.PULL_WRITE_OVERFLOW_LT_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0	RWX	RWX		OCB_OCI_OCBSES1_PUSH_READ_UNDERFLOW: Push Queue Read Underflow Underflow is defined as a store to the push_read_incr facility is done and the push_empty facility is already set. This bit is cleared only by a firmware write of this bit to 0. Dial enums: UNDERFLOW_NOT_DETECTED=>0b0 UNDERFLOW_DETECTED=>0b1
1	RWX	RWX		OCB_OCI_OCBSES1_PULL_WRITE_OVERFLOW: Pull Queue Write Overflow Overflow is defined as a load to the pull_write_incr facility is done and the pull_full facility is already set. This bit is cleared only by a firmware write of this bit to 0. Dial enums: OVERFLOW_NOT_DETECTED=>0b0 OVERFLOW_DETECTED=>0b1
2:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000000000 Dial enums: OVERFLOW_NOT_DETECTED=>0b0 OVERFLOW_DETECTED=>0b1

OCB_OCI OCB Linear Write Window Control 1 Register
Addr:	000000000006C218 (SCOM) 00000000C00610C0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWCR1
Constant(s):	PU_OCB_OCI_OCBLWCR1
Comments:	This OCI accessible register controls the Linear Write Window access facility.
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.LINEAR_WINDOW_ENABLE_LT_INST.LATC.L2(0) [0]
	1:2	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.LIN_WIN_WR_CTRL_SPARE_LT_0_INST.LATC.L2(0:1) [00]
	3:19	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.LINEAR_WINDOW_BAR_LT_0_INST.LATC.L2(0:16) [00000000000000000]
	20:31	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.LINEAR_WINDOW_MASK_LT_0_INST.LATC.L2(0:11) [000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	RW	RW		OCB_OCI_OCBLWCR1_LINEAR_WINDOW_ENABLE: Linear Window Enable 0: Window facility disabled. See Power Management Specification, section "Indirect Bridge Operation" for the effects of this bit for a write operation as it is dependent on the setting of trusted mode. 1: Window facility enabled. If OCBCSR1.ocb_stream_type= "linear", Linear Window BAR and Mask are valid and operations are to be honored. sc_resp codes are the same as for the OCB indirect facility to reflect the status of the OCI operation.
1:2	RW	RW		OCB_OCI_OCBLWCR1_SPARE_0: Implemented by not used Writes store the value. Reads return the last value written.
3:19	RW	RW		OCB_OCI_OCBLWCR1_LINEAR_WINDOW_BAR: Linear Window Base Address Register Defines OCI address(12:28) - 17 bits to define the starting offset within the region addressed
20:31	RW	RW		OCB_OCI_OCBLWCR1_LINEAR_WINDOW_MASK: Linear Window Address Mask Register Masks OCI address (17:28) - 12 bits to define the window size
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCB Linear Write Window Status 1 Register
Addr:	000000000006C21A (SCOM) 00000000C00610D0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWSR1
Constant(s):	PU_OCB_OCI_OCBLWSR1
Comments:	This OCI accessible register provides status of the Linear Write Window access facility.
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.LINEAR_WINDOW_SCRESP_LT_0_INST.LATC.L2(0:2) [000]
	3:7	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.LIN_WIN_STATUS_SPARE_LT_0_INST.LATC.L2(0:4) [00000]
Bit(s)	SCOM	OCI		Dial: Description
0:2	ROX	ROX		OCB_OCI_OCBLWSR1_LINEAR_WINDOW_SCRESP: Linear Window PIB SC Response If OCBLWCR.linear_window_enable=1, this field contains the last PIB response code sent (potentially allowing OCC FW to tell if attempts were made to use the window.
3:7	RO	RO		OCB_OCI_OCBLWSR1_SPARE0: Implemented but not used
8:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000

OCB_OCI OCB Linear Window Write Base 1 Register
Addr:	000000000006C21C (SCOM) 00000000C00610E0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWSBR1
Constant(s):	PU_OCB_OCI_OCBLWSBR1
Comments:	This OCI accessible register that defines the placement of the SRAM base address for use by the OCB Linear Write Window function of the indirect channel.
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.LINEAR_WINDOW_REGION_LT_0_INST.LATC.L2(0:2) [000]
	3:9	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.LINEAR_WINDOW_BASE_LT_0_INST.LATC.L2(0:6) [0000000]
Bit(s)	SCOM	OCI		Dial: Description
0:2	RW	RW		OCB_OCI_OCBLWSBR1_LINEAR_WINDOW_REGION: Linear Window Region If linear_window_enable=1, this field defines the OCI region (OCI Address(0:2) that is enabled for accessing the Linear Window. If the value written into OCBAR1 does not match this value and the OCBDR1 is accessed, a PIB scresp error is produced. Only the SRAM region (0b111) is supported.
3:9	RW	RW		OCB_OCI_OCBLWSBR1_LINEAR_WINDOW_BASE: Linear Window Base If linear_window_enable=1, establishes OCI Address(5:11); 128B aliases still apply (eg. OCI Address(3:4)
10:63	RO	RO		constant=0b000000000000000000000000000000000000000000000000000000

OCB_OCI OCB Stream Pull Base 2 Register
Addr:	000000000006C220 (SCOM) 00000000C0061100 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLBR2
Constant(s):	PU_OCB_OCI_OCBSLBR2
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.PULL_OCI_BASE_REGION_LT_0_INST.LATC.L2(0:2) [000]
	3:28	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.PULL_START_ADDR_LT_0_INST.LATC.L2(0:25) [00000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:2	RW	RW		pull_oci_region
3:28	RW	RW		pull_start
29:63	RO	RO		constant=0b00000000000000000000000000000000000

OCB_OCI OCB Stream Pull Control/Status 2 Register
Addr:	000000000006C221 (SCOM) 00000000C0061108 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLCS2
Constant(s):	PU_OCB_OCI_OCBSLCS2
Comments:	Writes to this register cause the Pull Queue to be reset.OCB0
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.PULL_FULL_LT_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.PULL_EMPTY_LT_INST.LATC.L2(0) [0]
	2:3	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.RESERVED_PULL_LT_0_INST.LATC.L2(0:1) [00]
	4:5	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.PULL_INTR_ACTION_LT_0_INST.LATC.L2(0:1) [00]
	6:10	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.PULL_LENGTH_LT_0_INST.LATC.L2(0:4) [00000]
	13:17	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.PULL_WRITE_PTR_LT_0_INST.LATC.L2(0:4) [00000]
	21:25	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.PULL_READ_PTR_LT_0_INST.LATC.L2(0:4) [00000]
	31	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.PULL_ENABLE_LT_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0	RWX_WCLRPART	RWX_WCLRPART		OCB_OCI_OCBSLCS2_PULL_FULL: Reads indicate the Pull Queue is full condition Any write to this register clears this indicator and clears pull_write_ptr and pull_read_ptr to 0s. (this is a means for resetting the queue hardware) RWX_WCLRPART Dial enums: NOT_FULL=>0b0 FULL=>0b1
1	RWX_WSETPART	RWX_WSETPART		OCB_OCI_OCBSLCS2_PULL_EMPTY: Reads indicate the Pull Queue empty condition Any write to this register sets this indicator and clears pull_write_ptr and pull_read_ptr to 0s. (this is a means for resetting the queue hardware) RWX_WSETPART Dial enums: NOT_EMPTY=>0b0 EMPTY=>0b1
2:3	RW	RW		OCB_OCI_OCBSLCS2_SPARE: Implemented but not used Writes store the value. Reads return the last value written.
4:5	RW	RW		OCB_OCI_OCBSLCS2_PULL_INTR_ACTION_0_1: Pull Interrupt Action This field controls the condition which will assert the pull interrupt signal for this channel to the OCB interrupt controller. b00 = Full (default upon hardware init) b01 = Non Full b10 = Empty (the more useful firmware default) b11 = Not Empty
6:10	RW	RW		OCB_OCI_OCBSLCS2_PULL_LENGTH: Pull Queue length in (pull_length + 1) * 8B Value mapping: 0b00000: 8B 0b00001: 16B 0b00010: 24B 0b00011: 32B 0b00100: 40B 0b00101: 48B 0b00110: 56B 0b00111: 64B 0b01000: 72B 0b01001: 80B 0b01010: 88B 0b01011: 96B 0b01100: 104B 0b01101: 112B 0b01110: 120B 0b01111: 128B 0b10000: 136B 0b10001: 144B 0b10010: 152B 0b10011: 160B 0b10100: 168B 0b10101: 176B 0b10110: 184B 0b10111: 192B 0b11000: 200B 0b11001: 208B 0b11010: 216B 0b11011: 224B 0b11100: 232B 0b11101: 240B 0b11110: 248B 0b11111: 256B
11:12	RO	RO		constant=0b00
13:17	RWX_WCLRPART	RWX_WCLRPART		OCB_OCI_OCBSLCS2_PULL_WRITE_PTR: Pull write pointer Reads indicate the current Pull Queue write pointer in increments of 8B. The actual address used is pull_oci_region || pull_start + pull_write_ptr || 00000. Writes to this field are ignored. Hardware performs all modifications. This field is cleared upon a write to this register. ROX_WCLRPART
18:20	RO	RO		constant=0b000
21:25	RWX_WCLRPART	RWX_WCLRPART		OCB_OCI_OCBSLCS2_PULL_READ_PTR: Pull read pointer Reads indicate the current Pull Queue read pointer in increments of 8B. The actual address used is pull_oci_region || pull_start + pull_write_ptr || 00000. This field is cleared upon a write to this register. ROX_WCLRPART
26:30	RO	RO		constant=0b00000
31	RW	RW		OCB_OCI_OCBSLCS2_PULL_ENABLE: Enables the Pull Queue function If Disabled, PIB Reads to OCB Data 2 Register to perform a pull will result in an "offline" PIB error back to the PIB Master. Note: OCI Reads to OCB Stream Pull Increment 2 Register to cause incrementation are unaffected by the setting of this bit. Full and/or empty conditions may still arise to the OCC even if this bit indicates disabled. Dial enums: DISABLED=>0b0 ENABLED=>0b1
32:63	RO	RO		constant=0b00000000000000000000000000000000 Dial enums: DISABLED=>0b0 ENABLED=>0b1

OCB_OCI OCB Stream Pull Increment 2 Register
Addr:	000000000006C222 (SCOM) 00000000C0061110 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLI2
Constant(s):	PU_OCB_OCI_OCBSLI2
Comments:	Reads to this register cause the Pull Queue Write pointer to increment by 1 modulo the Pull Queue Size and will do so independent of the setting of OCB Control/Status 0 Register[ocb_stream_mode], OCB Control/Status 0 Register[ocb_stream_type] or OCB Stream Pull Control/Status 0 Register[pull_enable]. This allows OCC firmware to be manipulating these pointers while the other side is using the channel in an indirect or linear mode concurrently.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:63	RO	RO		constant=0b0000000000000000000000000000000000000000000000000000000000000000

OCB_OCI OCB Stream Push Base 2 Register
Addr:	000000000006C223 (SCOM) 00000000C0061118 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHBR2
Constant(s):	PU_OCB_OCI_OCBSHBR2
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.PUSH_OCI_BASE_REGION_LT_0_INST.LATC.L2(0:2) [000]
	3:28	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.PUSH_START_ADDR_LT_0_INST.LATC.L2(0:25) [00000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:2	RW	RW		push_oci_region
3:28	RW	RW		push_start
29:63	RO	RO		constant=0b00000000000000000000000000000000000

OCB_OCI OCB Stream Push Control/Status 2 Register
Addr:	000000000006C224 (SCOM) 00000000C0061120 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHCS2
Constant(s):	PU_OCB_OCI_OCBSHCS2
Comments:	Controls the behavior of Push Queue n. Writes to this register cause the queue hardware to be reset.
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.PUSH_FULL_LT_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.PUSH_EMPTY_LT_INST.LATC.L2(0) [0]
	2:3	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.RESERVED_PUSH_LT_0_INST.LATC.L2(0:1) [00]
	4:5	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.PUSH_INTR_ACTION_LT_0_INST.LATC.L2(0:1) [00]
	6:10	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.PUSH_LENGTH_LT_0_INST.LATC.L2(0:4) [00000]
	13:17	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.PUSH_WRITE_PTR_LT_0_INST.LATC.L2(0:4) [00000]
	21:25	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.PUSH_READ_PTR_LT_0_INST.LATC.L2(0:4) [00000]
	31	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.PUSH_ENABLE_LT_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0	RWX_WCLRPART	RWX_WCLRPART		OCB_OCI_OCBSHCS2_PUSH_FULL: Reads indicate the Push Queue is full condition Any write to this register clears this indicator and clears push_write_ptr and push_read_ptr to 0s. (this is a means for resetting the queue hardware) RWX_WCLR Dial enums: NOT_FULL=>0b0 FULL=>0b1
1	RWX_WSETPART	RWX_WSETPART		OCB_OCI_OCBSHCS2_PUSH_EMPTY: Read indicate the Push Queue empty condition Any write to this register sets this indicator and clears push_write_ptr and push_read_ptr to 0s. (this is a means for resetting the queue hardware) RWX_WSETPART Dial enums: NOT_EMPTY=>0b0 EMPTY=>0b1
2:3	RW	RW		OCB_OCI_OCBSHCS2_SPARE: Implemented by not used Writes store the value. Reads return the last value written.
4:5	RW	RW		OCB_OCI_OCBSHCS2_PUSH_INTR_ACTION_0_1: Push Interrupt Action This field controls the condition which will assert the push interrupt signal for this channel to the OCB interrupt controller. b00 = Full (default upon hardware init) b01 = Non Full b10 = Empty b11 = Not Empty
6:10	RW	RW		OCB_OCI_OCBSHCS2_PUSH_LENGTH: Push Queue length in (push_length + 1) * 8B Value mapping: 0b00000: 8B 0b00001: 16B 0b00010: 24B 0b00011: 32B 0b00100: 40B 0b00101: 48B 0b00110: 56B 0b00111: 64B 0b01000: 72B 0b01001: 80B 0b01010: 88B 0b01011: 96B 0b01100: 104B 0b01101: 112B 0b01110: 120B 0b01111: 128B 0b10000: 136B 0b10001: 144B 0b10010: 152B 0b10011: 160B 0b10100: 168B 0b10101: 176B 0b10110: 184B 0b10111: 192B 0b11000: 200B 0b11001: 208B 0b11010: 216B 0b11011: 224B 0b11100: 232B 0b11101: 240B 0b11110: 248B 0b11111: 256B
11:12	RO	RO		constant=0b00
13:17	RWX_WCLRPART	RWX_WCLRPART		OCB_OCI_OCBSHCS2_PUSH_WRITE_PTR: Push write pointer Reads indicate the current Push Queue write pointer in increments of 8B. The actual address used is push_oci_region || push_start + push_write_ptr || 00000. Writes to this field are ignored. Hardware performs all modifications. This field is cleared upon a write to this register. ROX_WCLRPART
18:20	RO	RO		constant=0b000
21:25	RWX_WCLRPART	RWX_WCLRPART		OCB_OCI_OCBSHCS2_PUSH_READ_PTR: Push read pointer Reads indicate the current Push Queue read pointer in increments of 8B. The actual address used is push_oci_region || push_start + push_read_ptr || 00000. This field is cleared upon a write to this register. ROX_WCLRPART
26:30	RO	RO		constant=0b00000
31	RW	RW		OCB_OCI_OCBSHCS2_PUSH_ENABLE: Enables the Push Queue function If Disabled, PIB Writes to OCB Data 2 Register to perform a push will result in an "offline" PIB error back to the PIB Master. Note: OCI Writes to OCB Stream Push Increment 2 Register to cause incrementation are unaffected by the setting of this bit. Full and/or empty conditions may still arise to the OCC even if this bit indicates disabled. Dial enums: DISABLED=>0b0 ENABLED=>0b1
32:63	RO	RO		constant=0b00000000000000000000000000000000 Dial enums: DISABLED=>0b0 ENABLED=>0b1

OCB_OCI OCB Stream Push Increment 2 Register
Addr:	000000000006C225 (SCOM) 00000000C0061128 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHI2
Constant(s):	PU_OCB_OCI_OCBSHI2
Comments:	Writes to this register cause the Push Queue Read pointer to increment by 1 modulo the Push Queue Size and will do so independent of the setting of OCB Control/Status 0 Register[ocb_stream_mode], OCB Control/Status 0 Register[ocb_stream_type] or OCB Stream Push Control/Status 0 Register[push_enable]. This allows OCC firmware to be manipulating these pointers while the other side is using the channel in an indirect or linear mode concurrently.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:63	RO	RO		constant=0b0000000000000000000000000000000000000000000000000000000000000000

OCB_OCI OCB Stream Error Status 2 Register
Addr:	000000000006C226 (SCOM) 00000000C0061130 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSES2
Constant(s):	PU_OCB_OCI_OCBSES2
Comments:	Indicates errors that occur in an indirect channel when in a streaming mode (linear or circular)
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.PUSH_READ_UNDERFLOW_LT_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.PULL_WRITE_OVERFLOW_LT_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0	RWX	RWX		OCB_OCI_OCBSES2_PUSH_READ_UNDERFLOW: Push Queue Read Underflow Underflow is defined as a store to the push_read_incr facility is done and the push_empty facility is already set. This bit is cleared only by a firmware write of this bit to 0. Dial enums: UNDERFLOW_NOT_DETECTED=>0b0 UNDERFLOW_DETECTED=>0b1
1	RWX	RWX		OCB_OCI_OCBSES2_PULL_WRITE_OVERFLOW: Pull Queue Write Overflow Overflow is defined as a load to the pull_write_incr facility is done and the pull_full facility is already set. This bit is cleared only by a firmware write of this bit to 0. Dial enums: OVERFLOW_NOT_DETECTED=>0b0 OVERFLOW_DETECTED=>0b1
2:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000000000 Dial enums: OVERFLOW_NOT_DETECTED=>0b0 OVERFLOW_DETECTED=>0b1

OCB_OCI OCB Linear Write Window Control 2 Register
Addr:	000000000006C228 (SCOM) 00000000C0061140 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWCR2
Constant(s):	PU_OCB_OCI_OCBLWCR2
Comments:	This OCI accessible register controls the Linear Write Window access facility.
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.LINEAR_WINDOW_ENABLE_LT_INST.LATC.L2(0) [0]
	1:2	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.LIN_WIN_WR_CTRL_SPARE_LT_0_INST.LATC.L2(0:1) [00]
	3:19	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.LINEAR_WINDOW_BAR_LT_0_INST.LATC.L2(0:16) [00000000000000000]
	20:31	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.LINEAR_WINDOW_MASK_LT_0_INST.LATC.L2(0:11) [000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	RW	RW		OCB_OCI_OCBLWCR2_LINEAR_WINDOW_ENABLE: Linear Window Enable 0: Window facility disabled. See Power Management Specification, section "Indirect Bridge Operation" for the effects of this bit for a write operation as it is dependent on the setting of trusted mode. 1: Window facility enabled. If OCBCSR2.ocb_stream_type= "linear", Linear Window BAR and Mask are valid and operations are to be honored. sc_resp codes are the same as for the OCB indirect facility to reflect the status of the OCI operation.
1:2	RW	RW		OCB_OCI_OCBLWCR2_SPARE_0: Implemented by not used Writes store the value. Reads return the last value written.
3:19	RW	RW		OCB_OCI_OCBLWCR2_LINEAR_WINDOW_BAR: Linear Window Base Address Register Defines OCI address(12:28) - 17 bits to define the starting offset within the region addressed
20:31	RW	RW		OCB_OCI_OCBLWCR2_LINEAR_WINDOW_MASK: Linear Window Address Mask Register Masks OCI address (17:28) - 12 bits to define the window size
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCB Linear Write Window Status 2 Register
Addr:	000000000006C22A (SCOM) 00000000C0061150 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWSR2
Constant(s):	PU_OCB_OCI_OCBLWSR2
Comments:	This OCI accessible register provides status of the Linear Write Window access facility.
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.LINEAR_WINDOW_SCRESP_LT_0_INST.LATC.L2(0:2) [000]
	3:7	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.LIN_WIN_STATUS_SPARE_LT_0_INST.LATC.L2(0:4) [00000]
Bit(s)	SCOM	OCI		Dial: Description
0:2	ROX	ROX		OCB_OCI_OCBLWSR2_LINEAR_WINDOW_SCRESP: Linear Window PIB SC Response If OCBLWCR.linear_window_enable=1, this field contains the last PIB response code sent (potentially allowing OCC FW to tell if attempts were made to use the window.
3:7	RO	RO		OCB_OCI_OCBLWSR2_SPARE0: Implemented but not used
8:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000

OCB_OCI OCB Linear Window Write Base 2 Register
Addr:	000000000006C22C (SCOM) 00000000C0061160 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWSBR2
Constant(s):	PU_OCB_OCI_OCBLWSBR2
Comments:	This OCI accessible register that defines the placement of the SRAM base address for use by the OCB Linear Write Window function of the indirect channel.
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.LINEAR_WINDOW_REGION_LT_0_INST.LATC.L2(0:2) [000]
	3:9	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.LINEAR_WINDOW_BASE_LT_0_INST.LATC.L2(0:6) [0000000]
Bit(s)	SCOM	OCI		Dial: Description
0:2	RW	RW		OCB_OCI_OCBLWSBR2_LINEAR_WINDOW_REGION: Linear Window Region If linear_window_enable=1, this field defines the OCI region (OCI Address(0:2) that is enabled for accessing the Linear Window. If the value written into OCBAR2 does not match this value and the OCBDR2 is accessed, a PIB scresp error is produced. Only the SRAM region (0b111) is supported.
3:9	RW	RW		OCB_OCI_OCBLWSBR2_LINEAR_WINDOW_BASE: Linear Window Base If linear_window_enable=1, establishes OCI Address(5:11); 128B aliases still apply (eg. OCI Address(3:4)
10:63	RO	RO		constant=0b000000000000000000000000000000000000000000000000000000

OCB_OCI OCB Stream Pull Base 3 Register
Addr:	000000000006C230 (SCOM) 00000000C0061180 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLBR3
Constant(s):	PU_OCB_OCI_OCBSLBR3
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.PULL_OCI_BASE_REGION_LT_0_INST.LATC.L2(0:2) [000]
	3:28	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.PULL_START_ADDR_LT_0_INST.LATC.L2(0:25) [00000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:2	RW	RW		pull_oci_region
3:28	RW	RW		pull_start
29:63	RO	RO		constant=0b00000000000000000000000000000000000

OCB_OCI OCB Stream Pull Control/Status 3 Register
Addr:	000000000006C231 (SCOM) 00000000C0061188 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLCS3
Constant(s):	PU_OCB_OCI_OCBSLCS3
Comments:	Writes to this register cause the Pull Queue to be reset.OCB0
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.PULL_FULL_LT_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.PULL_EMPTY_LT_INST.LATC.L2(0) [0]
	2:3	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.RESERVED_PULL_LT_0_INST.LATC.L2(0:1) [00]
	4:5	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.PULL_INTR_ACTION_LT_0_INST.LATC.L2(0:1) [00]
	6:10	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.PULL_LENGTH_LT_0_INST.LATC.L2(0:4) [00000]
	13:17	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.PULL_WRITE_PTR_LT_0_INST.LATC.L2(0:4) [00000]
	21:25	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.PULL_READ_PTR_LT_0_INST.LATC.L2(0:4) [00000]
	31	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.PULL_ENABLE_LT_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0	RWX_WCLRPART	RWX_WCLRPART		OCB_OCI_OCBSLCS3_PULL_FULL: Reads indicate the Pull Queue is full condition Any write to this register clears this indicator and clears pull_write_ptr and pull_read_ptr to 0s. (this is a means for resetting the queue hardware) RWX_WCLRPART Dial enums: NOT_FULL=>0b0 FULL=>0b1
1	RWX_WSETPART	RWX_WSETPART		OCB_OCI_OCBSLCS3_PULL_EMPTY: Reads indicate the Pull Queue empty condition Any write to this register sets this indicator and clears pull_write_ptr and pull_read_ptr to 0s. (this is a means for resetting the queue hardware) RWX_WSETPART Dial enums: NOT_EMPTY=>0b0 EMPTY=>0b1
2:3	RW	RW		OCB_OCI_OCBSLCS3_SPARE: Implemented but not used Writes store the value. Reads return the last value written.
4:5	RW	RW		OCB_OCI_OCBSLCS3_PULL_INTR_ACTION_0_1: Pull Interrupt Action This field controls the condition which will assert the pull interrupt signal for this channel to the OCB interrupt controller. b00 = Full (default upon hardware init) b01 = Non Full b10 = Empty (the more useful firmware default) b11 = Not Empty
6:10	RW	RW		OCB_OCI_OCBSLCS3_PULL_LENGTH: Pull Queue length in (pull_length + 1) * 8B Value mapping: 0b00000: 8B 0b00001: 16B 0b00010: 24B 0b00011: 32B 0b00100: 40B 0b00101: 48B 0b00110: 56B 0b00111: 64B 0b01000: 72B 0b01001: 80B 0b01010: 88B 0b01011: 96B 0b01100: 104B 0b01101: 112B 0b01110: 120B 0b01111: 128B 0b10000: 136B 0b10001: 144B 0b10010: 152B 0b10011: 160B 0b10100: 168B 0b10101: 176B 0b10110: 184B 0b10111: 192B 0b11000: 200B 0b11001: 208B 0b11010: 216B 0b11011: 224B 0b11100: 232B 0b11101: 240B 0b11110: 248B 0b11111: 256B
11:12	RO	RO		constant=0b00
13:17	RWX_WCLRPART	RWX_WCLRPART		OCB_OCI_OCBSLCS3_PULL_WRITE_PTR: Pull write pointer Reads indicate the current Pull Queue write pointer in increments of 8B. The actual address used is pull_oci_region || pull_start + pull_write_ptr || 00000. Writes to this field are ignored. Hardware performs all modifications. This field is cleared upon a write to this register. ROX_WCLRPART
18:20	RO	RO		constant=0b000
21:25	RWX_WCLRPART	RWX_WCLRPART		OCB_OCI_OCBSLCS3_PULL_READ_PTR: Pull read pointer Reads indicate the current Pull Queue read pointer in increments of 8B. The actual address used is pull_oci_region || pull_start + pull_write_ptr || 00000. This field is cleared upon a write to this register. ROX_WCLRPART
26:30	RO	RO		constant=0b00000
31	RW	RW		OCB_OCI_OCBSLCS3_PULL_ENABLE: Enables the Pull Queue function If Disabled, PIB Reads to OCB Data 3 Register to perform a pull will result in an "offline" PIB error back to the PIB Master. Note: OCI Reads to OCB Stream Pull Increment 3 Register to cause incrementation are unaffected by the setting of this bit. Full and/or empty conditions may still arise to the OCC even if this bit indicates disabled. Dial enums: DISABLED=>0b0 ENABLED=>0b1
32:63	RO	RO		constant=0b00000000000000000000000000000000 Dial enums: DISABLED=>0b0 ENABLED=>0b1

OCB_OCI OCB Stream Pull Increment 3 Register
Addr:	000000000006C232 (SCOM) 00000000C0061190 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLI3
Constant(s):	PU_OCB_OCI_OCBSLI3
Comments:	Reads to this register cause the Pull Queue Write pointer to increment by 1 modulo the Pull Queue Size and will do so independent of the setting of OCB Control/Status 0 Register[ocb_stream_mode], OCB Control/Status 0 Register[ocb_stream_type] or OCB Stream Pull Control/Status 0 Register[pull_enable]. This allows OCC firmware to be manipulating these pointers while the other side is using the channel in an indirect or linear mode concurrently.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:63	RO	RO		constant=0b0000000000000000000000000000000000000000000000000000000000000000

OCB_OCI OCB Stream Push Base 3 Register
Addr:	000000000006C233 (SCOM) 00000000C0061198 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHBR3
Constant(s):	PU_OCB_OCI_OCBSHBR3
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.PUSH_OCI_BASE_REGION_LT_0_INST.LATC.L2(0:2) [000]
	3:28	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.PUSH_START_ADDR_LT_0_INST.LATC.L2(0:25) [00000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:2	RW	RW		push_oci_region
3:28	RW	RW		push_start
29:63	RO	RO		constant=0b00000000000000000000000000000000000

OCB_OCI OCB Stream Push Control/Status 3 Register
Addr:	000000000006C234 (SCOM) 00000000C00611A0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHCS3
Constant(s):	PU_OCB_OCI_OCBSHCS3
Comments:	Controls the behavior of Push Queue n. Writes to this register cause the queue hardware to be reset.
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.PUSH_FULL_LT_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.PUSH_EMPTY_LT_INST.LATC.L2(0) [0]
	2:3	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.RESERVED_PUSH_LT_0_INST.LATC.L2(0:1) [00]
	4:5	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.PUSH_INTR_ACTION_LT_0_INST.LATC.L2(0:1) [00]
	6:10	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.PUSH_LENGTH_LT_0_INST.LATC.L2(0:4) [00000]
	13:17	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.PUSH_WRITE_PTR_LT_0_INST.LATC.L2(0:4) [00000]
	21:25	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.PUSH_READ_PTR_LT_0_INST.LATC.L2(0:4) [00000]
	31	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.PUSH_ENABLE_LT_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0	RWX_WCLRPART	RWX_WCLRPART		OCB_OCI_OCBSHCS3_PUSH_FULL: Reads indicate the Push Queue is full condition Any write to this register clears this indicator and clears push_write_ptr and push_read_ptr to 0s. (this is a means for resetting the queue hardware) RWX_WCLR Dial enums: NOT_FULL=>0b0 FULL=>0b1
1	RWX_WSETPART	RWX_WSETPART		OCB_OCI_OCBSHCS3_PUSH_EMPTY: Read indicate the Push Queue empty condition Any write to this register sets this indicator and clears push_write_ptr and push_read_ptr to 0s. (this is a means for resetting the queue hardware) RWX_WSETPART Dial enums: NOT_EMPTY=>0b0 EMPTY=>0b1
2:3	RW	RW		OCB_OCI_OCBSHCS3_SPARE: Implemented by not used Writes store the value. Reads return the last value written.
4:5	RW	RW		OCB_OCI_OCBSHCS3_PUSH_INTR_ACTION_0_1: Push Interrupt Action This field controls the condition which will assert the push interrupt signal for this channel to the OCB interrupt controller. b00 = Full (default upon hardware init) b01 = Non Full b10 = Empty b11 = Not Empty
6:10	RW	RW		OCB_OCI_OCBSHCS3_PUSH_LENGTH: Push Queue length in (push_length + 1) * 8B Value mapping: 0b00000: 8B 0b00001: 16B 0b00010: 24B 0b00011: 32B 0b00100: 40B 0b00101: 48B 0b00110: 56B 0b00111: 64B 0b01000: 72B 0b01001: 80B 0b01010: 88B 0b01011: 96B 0b01100: 104B 0b01101: 112B 0b01110: 120B 0b01111: 128B 0b10000: 136B 0b10001: 144B 0b10010: 152B 0b10011: 160B 0b10100: 168B 0b10101: 176B 0b10110: 184B 0b10111: 192B 0b11000: 200B 0b11001: 208B 0b11010: 216B 0b11011: 224B 0b11100: 232B 0b11101: 240B 0b11110: 248B 0b11111: 256B
11:12	RO	RO		constant=0b00
13:17	RWX_WCLRPART	RWX_WCLRPART		OCB_OCI_OCBSHCS3_PUSH_WRITE_PTR: Push write pointer Reads indicate the current Push Queue write pointer in increments of 8B. The actual address used is push_oci_region || push_start + push_write_ptr || 00000. Writes to this field are ignored. Hardware performs all modifications. This field is cleared upon a write to this register. ROX_WCLRPART
18:20	RO	RO		constant=0b000
21:25	RWX_WCLRPART	RWX_WCLRPART		OCB_OCI_OCBSHCS3_PUSH_READ_PTR: Push read pointer Reads indicate the current Push Queue read pointer in increments of 8B. The actual address used is push_oci_region || push_start + push_read_ptr || 00000. This field is cleared upon a write to this register. ROX_WCLRPART
26:30	RO	RO		constant=0b00000
31	RW	RW		OCB_OCI_OCBSHCS3_PUSH_ENABLE: Enables the Push Queue function If Disabled, PIB Writes to OCB Data 3 Register to perform a push will result in an "offline" PIB error back to the PIB Master. Note: OCI Writes to OCB Stream Push Increment 3 Register to cause incrementation are unaffected by the setting of this bit. Full and/or empty conditions may still arise to the OCC even if this bit indicates disabled. Dial enums: DISABLED=>0b0 ENABLED=>0b1
32:63	RO	RO		constant=0b00000000000000000000000000000000 Dial enums: DISABLED=>0b0 ENABLED=>0b1

OCB_OCI OCB Stream Push Increment 3 Register
Addr:	000000000006C235 (SCOM) 00000000C00611A8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHI3
Constant(s):	PU_OCB_OCI_OCBSHI3
Comments:	Writes to this register cause the Push Queue Read pointer to increment by 1 modulo the Push Queue Size and will do so independent of the setting of OCB Control/Status 0 Register[ocb_stream_mode], OCB Control/Status 0 Register[ocb_stream_type] or OCB Stream Push Control/Status 0 Register[push_enable]. This allows OCC firmware to be manipulating these pointers while the other side is using the channel in an indirect or linear mode concurrently.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:63	RO	RO		constant=0b0000000000000000000000000000000000000000000000000000000000000000

OCB_OCI OCB Stream Error Status 3 Register
Addr:	000000000006C236 (SCOM) 00000000C00611B0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSES3
Constant(s):	PU_OCB_OCI_OCBSES3
Comments:	Indicates errors that occur in an indirect channel when in a streaming mode (linear or circular)
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.PUSH_READ_UNDERFLOW_LT_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.PULL_WRITE_OVERFLOW_LT_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0	RWX	RWX		OCB_OCI_OCBSES3_PUSH_READ_UNDERFLOW: Push Queue Read Underflow Underflow is defined as a store to the push_read_incr facility is done and the push_empty facility is already set. This bit is cleared only by a firmware write of this bit to 0. Dial enums: UNDERFLOW_NOT_DETECTED=>0b0 UNDERFLOW_DETECTED=>0b1
1	RWX	RWX		OCB_OCI_OCBSES3_PULL_WRITE_OVERFLOW: Pull Queue Write Overflow Overflow is defined as a load to the pull_write_incr facility is done and the pull_full facility is already set. This bit is cleared only by a firmware write of this bit to 0. Dial enums: OVERFLOW_NOT_DETECTED=>0b0 OVERFLOW_DETECTED=>0b1
2:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000000000 Dial enums: OVERFLOW_NOT_DETECTED=>0b0 OVERFLOW_DETECTED=>0b1

OCB_OCI OCB Linear Write Window Control 3 Register
Addr:	000000000006C238 (SCOM) 00000000C00611C0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWCR3
Constant(s):	PU_OCB_OCI_OCBLWCR3
Comments:	This OCI accessible register controls the Linear Write Window access facility.
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.LINEAR_WINDOW_ENABLE_LT_INST.LATC.L2(0) [0]
	1:2	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.LIN_WIN_WR_CTRL_SPARE_LT_0_INST.LATC.L2(0:1) [00]
	3:19	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.LINEAR_WINDOW_BAR_LT_0_INST.LATC.L2(0:16) [00000000000000000]
	20:31	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.LINEAR_WINDOW_MASK_LT_0_INST.LATC.L2(0:11) [000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	RW	RW		OCB_OCI_OCBLWCR3_LINEAR_WINDOW_ENABLE: Linear Window Enable 0: Window facility disabled. See Power Management Specification, section "Indirect Bridge Operation" for the effects of this bit for a write operation as it is dependent on the setting of trusted mode. 1: Window facility enabled. If OCBCSR3.ocb_stream_type= "linear", Linear Window BAR and Mask are valid and operations are to be honored. sc_resp codes are the same as for the OCB indirect facility to reflect the status of the OCI operation.
1:2	RW	RW		OCB_OCI_OCBLWCR3_SPARE_0: Implemented by not used Writes store the value. Reads return the last value written.
3:19	RW	RW		OCB_OCI_OCBLWCR3_LINEAR_WINDOW_BAR: Linear Window Base Address Register Defines OCI address(12:28) - 17 bits to define the starting offset within the region addressed
20:31	RW	RW		OCB_OCI_OCBLWCR3_LINEAR_WINDOW_MASK: Linear Window Address Mask Register Masks OCI address (17:28) - 12 bits to define the window size
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCB Linear Write Window Status 3 Register
Addr:	000000000006C23A (SCOM) 00000000C00611D0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWSR3
Constant(s):	PU_OCB_OCI_OCBLWSR3
Comments:	This OCI accessible register provides status of the Linear Write Window access facility.
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.LINEAR_WINDOW_SCRESP_LT_0_INST.LATC.L2(0:2) [000]
	3:7	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.LIN_WIN_STATUS_SPARE_LT_0_INST.LATC.L2(0:4) [00000]
Bit(s)	SCOM	OCI		Dial: Description
0:2	ROX	ROX		OCB_OCI_OCBLWSR3_LINEAR_WINDOW_SCRESP: Linear Window PIB SC Response If OCBLWCR.linear_window_enable=1, this field contains the last PIB response code sent (potentially allowing OCC FW to tell if attempts were made to use the window.
3:7	RO	RO		OCB_OCI_OCBLWSR3_SPARE0: Implemented but not used
8:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000

OCB_OCI OCB Linear Window Write Base 3 Register
Addr:	000000000006C23C (SCOM) 00000000C00611E0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWSBR3
Constant(s):	PU_OCB_OCI_OCBLWSBR3
Comments:	This OCI accessible register that defines the placement of the SRAM base address for use by the OCB Linear Write Window function of the indirect channel.
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.LINEAR_WINDOW_REGION_LT_0_INST.LATC.L2(0:2) [000]
	3:9	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.LINEAR_WINDOW_BASE_LT_0_INST.LATC.L2(0:6) [0000000]
Bit(s)	SCOM	OCI		Dial: Description
0:2	RW	RW		OCB_OCI_OCBLWSBR3_LINEAR_WINDOW_REGION: Linear Window Region If linear_window_enable=1, this field defines the OCI region (OCI Address(0:2) that is enabled for accessing the Linear Window. If the value written into OCBAR3 does not match this value and the OCBDR3 is accessed, a PIB scresp error is produced. Only the SRAM region (0b111) is supported.
3:9	RW	RW		OCB_OCI_OCBLWSBR3_LINEAR_WINDOW_BASE: Linear Window Base If linear_window_enable=1, establishes OCI Address(5:11); 128B aliases still apply (eg. OCI Address(3:4)
10:63	RO	RO		constant=0b000000000000000000000000000000000000000000000000000000

OCC PCB Interrupt Type 0 QME 0 Register
Addr:	000000000006C400 (SCOM) 00000000C0062000 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q0
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT0Q0RR_PCB_INTR_PAYLOAD: Type 0 PCB interrupt packet content from QME 0 READ_EFFECT { OPIT0PRa.pcb_intr_type_0_pending_0=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 0 QME 1 Register
Addr:	000000000006C401 (SCOM) 00000000C0062008 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q1
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 1. Receipt of such an interrupt packet causes the setting of the Type 1 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT0Q1RR_PCB_INTR_PAYLOAD: Type 0 PCB interrupt packet content from QME 1 READ_EFFECT { OPIT0PRa.pcb_intr_type_0_pending_1=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 0 QME 2 Register
Addr:	000000000006C402 (SCOM) 00000000C0062010 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q2
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 2. Receipt of such an interrupt packet causes the setting of the Type 2 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT0Q2RR_PCB_INTR_PAYLOAD: Type 0 PCB interrupt packet content from QME 2 READ_EFFECT { OPIT0PRa.pcb_intr_type_0_pending_2=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 0 QME 3 Register
Addr:	000000000006C403 (SCOM) 00000000C0062018 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q3
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 3. Receipt of such an interrupt packet causes the setting of the Type 3 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT0Q3RR_PCB_INTR_PAYLOAD: Type 0 PCB interrupt packet content from QME 3 READ_EFFECT { OPIT0PRa.pcb_intr_type_0_pending_3=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 0 QME 4 Register
Addr:	000000000006C404 (SCOM) 00000000C0062020 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q4
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 4. Receipt of such an interrupt packet causes the setting of the Type 4 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT0Q4RR_PCB_INTR_PAYLOAD: Type 0 PCB interrupt packet content from QME 4 READ_EFFECT { OPIT0PRa.pcb_intr_type_0_pending_4=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 0 QME 5 Register
Addr:	000000000006C405 (SCOM) 00000000C0062028 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q5
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 5. Receipt of such an interrupt packet causes the setting of the Type 5 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT0Q5RR_PCB_INTR_PAYLOAD: Type 0 PCB interrupt packet content from QME 5 READ_EFFECT { OPIT0PRa.pcb_intr_type_0_pending_5=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 0 QME 6 Register
Addr:	000000000006C406 (SCOM) 00000000C0062030 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q6
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 6. Receipt of such an interrupt packet causes the setting of the Type 6 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT0Q6RR_PCB_INTR_PAYLOAD: Type 0 PCB interrupt packet content from QME 6 READ_EFFECT { OPIT0PRa.pcb_intr_type_0_pending_6=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 0 QME 7 Register
Addr:	000000000006C407 (SCOM) 00000000C0062038 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q7
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 7. Receipt of such an interrupt packet causes the setting of the Type 7 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT0Q7RR_PCB_INTR_PAYLOAD: Type 0 PCB interrupt packet content from QME 7 READ_EFFECT { OPIT0PRa.pcb_intr_type_0_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 1 QME 0 Register
Addr:	000000000006C408 (SCOM) 00000000C0062040 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q0
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT1Q0RR_PCB_INTR_PAYLOAD: Type 1 PCB interrupt packet content from QME 0 READ_EFFECT { OPIT1PRa.pcb_intr_type_1_pending_0=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 1 QME 1 Register
Addr:	000000000006C409 (SCOM) 00000000C0062048 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q1
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 1. Receipt of such an interrupt packet causes the setting of the Type 1 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT1Q1RR_PCB_INTR_PAYLOAD: Type 1 PCB interrupt packet content from QME 1 READ_EFFECT { OPIT1PRa.pcb_intr_type_1_pending_1=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 1 QME 2 Register
Addr:	000000000006C40A (SCOM) 00000000C0062050 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q2
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 2. Receipt of such an interrupt packet causes the setting of the Type 2 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT1Q2RR_PCB_INTR_PAYLOAD: Type 1 PCB interrupt packet content from QME 2 READ_EFFECT { OPIT1PRa.pcb_intr_type_1_pending_2=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 1 QME 3 Register
Addr:	000000000006C40B (SCOM) 00000000C0062058 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q3
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 3. Receipt of such an interrupt packet causes the setting of the Type 3 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT1Q3RR_PCB_INTR_PAYLOAD: Type 1 PCB interrupt packet content from QME 3 READ_EFFECT { OPIT1PRa.pcb_intr_type_1_pending_3=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 1 QME 4 Register
Addr:	000000000006C40C (SCOM) 00000000C0062060 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q4
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 4. Receipt of such an interrupt packet causes the setting of the Type 4 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT1Q4RR_PCB_INTR_PAYLOAD: Type 1 PCB interrupt packet content from QME 4 READ_EFFECT { OPIT1PRa.pcb_intr_type_1_pending_4=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 1 QME 5 Register
Addr:	000000000006C40D (SCOM) 00000000C0062068 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q5
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 5. Receipt of such an interrupt packet causes the setting of the Type 5 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT1Q5RR_PCB_INTR_PAYLOAD: Type 1 PCB interrupt packet content from QME 5 READ_EFFECT { OPIT1PRa.pcb_intr_type_1_pending_5=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 1 QME 6 Register
Addr:	000000000006C40E (SCOM) 00000000C0062070 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q6
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 6. Receipt of such an interrupt packet causes the setting of the Type 6 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT1Q6RR_PCB_INTR_PAYLOAD: Type 1 PCB interrupt packet content from QME 6 READ_EFFECT { OPIT1PRa.pcb_intr_type_1_pending_6=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 1 QME 7 Register
Addr:	000000000006C40F (SCOM) 00000000C0062078 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q7
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 7. Receipt of such an interrupt packet causes the setting of the Type 7 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT1Q7RR_PCB_INTR_PAYLOAD: Type 1 PCB interrupt packet content from QME 7 READ_EFFECT { OPIT1PRa.pcb_intr_type_1_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 2 QME 0 Register
Addr:	000000000006C410 (SCOM) 00000000C0062080 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q0
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT2Q0RR_PCB_INTR_PAYLOAD: Type 2 PCB interrupt packet content from QME 0 READ_EFFECT { OPIT2PRa.pcb_intr_type_2_pending_0=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 2 QME 1 Register
Addr:	000000000006C411 (SCOM) 00000000C0062088 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q1
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 1. Receipt of such an interrupt packet causes the setting of the Type 1 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT2Q1RR_PCB_INTR_PAYLOAD: Type 2 PCB interrupt packet content from QME 1 READ_EFFECT { OPIT2PRa.pcb_intr_type_2_pending_1=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 2 QME 2 Register
Addr:	000000000006C412 (SCOM) 00000000C0062090 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q2
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 2. Receipt of such an interrupt packet causes the setting of the Type 2 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT2Q2RR_PCB_INTR_PAYLOAD: Type 2 PCB interrupt packet content from QME 2 READ_EFFECT { OPIT2PRa.pcb_intr_type_2_pending_2=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 2 QME 3 Register
Addr:	000000000006C413 (SCOM) 00000000C0062098 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q3
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 3. Receipt of such an interrupt packet causes the setting of the Type 3 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT2Q3RR_PCB_INTR_PAYLOAD: Type 2 PCB interrupt packet content from QME 3 READ_EFFECT { OPIT2PRa.pcb_intr_type_2_pending_3=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 2 QME 4 Register
Addr:	000000000006C414 (SCOM) 00000000C00620A0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q4
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 4. Receipt of such an interrupt packet causes the setting of the Type 4 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT2Q4RR_PCB_INTR_PAYLOAD: Type 2 PCB interrupt packet content from QME 4 READ_EFFECT { OPIT2PRa.pcb_intr_type_2_pending_4=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 2 QME 5 Register
Addr:	000000000006C415 (SCOM) 00000000C00620A8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q5
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 5. Receipt of such an interrupt packet causes the setting of the Type 5 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT2Q5RR_PCB_INTR_PAYLOAD: Type 2 PCB interrupt packet content from QME 5 READ_EFFECT { OPIT2PRa.pcb_intr_type_2_pending_5=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 2 QME 6 Register
Addr:	000000000006C416 (SCOM) 00000000C00620B0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q6
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 6. Receipt of such an interrupt packet causes the setting of the Type 6 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT2Q6RR_PCB_INTR_PAYLOAD: Type 2 PCB interrupt packet content from QME 6 READ_EFFECT { OPIT2PRa.pcb_intr_type_2_pending_6=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 2 QME 7 Register
Addr:	000000000006C417 (SCOM) 00000000C00620B8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q7
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 7. Receipt of such an interrupt packet causes the setting of the Type 7 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT2Q7RR_PCB_INTR_PAYLOAD: Type 2 PCB interrupt packet content from QME 7 READ_EFFECT { OPIT2PRa.pcb_intr_type_2_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 3 QME 0 Register
Addr:	000000000006C418 (SCOM) 00000000C00620C0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q0
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT3Q0RR_PCB_INTR_PAYLOAD: Type 3 PCB interrupt packet content from QME 0 READ_EFFECT { OPIT3PRa.pcb_intr_type_3_pending_0=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 3 QME 1 Register
Addr:	000000000006C419 (SCOM) 00000000C00620C8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q1
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 1. Receipt of such an interrupt packet causes the setting of the Type 1 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT3Q1RR_PCB_INTR_PAYLOAD: Type 3 PCB interrupt packet content from QME 1 READ_EFFECT { OPIT3PRa.pcb_intr_type_3_pending_1=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 3 QME 2 Register
Addr:	000000000006C41A (SCOM) 00000000C00620D0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q2
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 2. Receipt of such an interrupt packet causes the setting of the Type 2 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT3Q2RR_PCB_INTR_PAYLOAD: Type 3 PCB interrupt packet content from QME 2 READ_EFFECT { OPIT3PRa.pcb_intr_type_3_pending_2=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 3 QME 3 Register
Addr:	000000000006C41B (SCOM) 00000000C00620D8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q3
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 3. Receipt of such an interrupt packet causes the setting of the Type 3 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT3Q3RR_PCB_INTR_PAYLOAD: Type 3 PCB interrupt packet content from QME 3 READ_EFFECT { OPIT3PRa.pcb_intr_type_3_pending_3=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 3 QME 4 Register
Addr:	000000000006C41C (SCOM) 00000000C00620E0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q4
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 4. Receipt of such an interrupt packet causes the setting of the Type 4 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT3Q4RR_PCB_INTR_PAYLOAD: Type 3 PCB interrupt packet content from QME 4 READ_EFFECT { OPIT3PRa.pcb_intr_type_3_pending_4=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 3 QME 5 Register
Addr:	000000000006C41D (SCOM) 00000000C00620E8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q5
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 5. Receipt of such an interrupt packet causes the setting of the Type 5 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT3Q5RR_PCB_INTR_PAYLOAD: Type 3 PCB interrupt packet content from QME 5 READ_EFFECT { OPIT3PRa.pcb_intr_type_3_pending_5=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 3 QME 6 Register
Addr:	000000000006C41E (SCOM) 00000000C00620F0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q6
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 6. Receipt of such an interrupt packet causes the setting of the Type 6 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT3Q6RR_PCB_INTR_PAYLOAD: Type 3 PCB interrupt packet content from QME 6 READ_EFFECT { OPIT3PRa.pcb_intr_type_3_pending_6=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 3 QME 7 Register
Addr:	000000000006C41F (SCOM) 00000000C00620F8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q7
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 7. Receipt of such an interrupt packet causes the setting of the Type 7 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT3Q7RR_PCB_INTR_PAYLOAD: Type 3 PCB interrupt packet content from QME 7 READ_EFFECT { OPIT3PRa.pcb_intr_type_3_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 4 QME 0 Register
Addr:	000000000006C420 (SCOM) 00000000C0062100 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q0
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT4Q0RR_PCB_INTR_PAYLOAD: Type 4 PCB interrupt packet content from QME 0 READ_EFFECT { OPIT4PRa.pcb_intr_type_4_pending_0=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 4 QME 1 Register
Addr:	000000000006C421 (SCOM) 00000000C0062108 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q1
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 1. Receipt of such an interrupt packet causes the setting of the Type 1 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT4Q1RR_PCB_INTR_PAYLOAD: Type 4 PCB interrupt packet content from QME 1 READ_EFFECT { OPIT4PRa.pcb_intr_type_4_pending_1=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 4 QME 2 Register
Addr:	000000000006C422 (SCOM) 00000000C0062110 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q2
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 2. Receipt of such an interrupt packet causes the setting of the Type 2 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT4Q2RR_PCB_INTR_PAYLOAD: Type 4 PCB interrupt packet content from QME 2 READ_EFFECT { OPIT4PRa.pcb_intr_type_4_pending_2=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 4 QME 3 Register
Addr:	000000000006C423 (SCOM) 00000000C0062118 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q3
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 3. Receipt of such an interrupt packet causes the setting of the Type 3 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT4Q3RR_PCB_INTR_PAYLOAD: Type 4 PCB interrupt packet content from QME 3 READ_EFFECT { OPIT4PRa.pcb_intr_type_4_pending_3=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 4 QME 4 Register
Addr:	000000000006C424 (SCOM) 00000000C0062120 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q4
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 4. Receipt of such an interrupt packet causes the setting of the Type 4 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT4Q4RR_PCB_INTR_PAYLOAD: Type 4 PCB interrupt packet content from QME 4 READ_EFFECT { OPIT4PRa.pcb_intr_type_4_pending_4=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 4 QME 5 Register
Addr:	000000000006C425 (SCOM) 00000000C0062128 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q5
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 5. Receipt of such an interrupt packet causes the setting of the Type 5 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT4Q5RR_PCB_INTR_PAYLOAD: Type 4 PCB interrupt packet content from QME 5 READ_EFFECT { OPIT4PRa.pcb_intr_type_4_pending_5=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 4 QME 6 Register
Addr:	000000000006C426 (SCOM) 00000000C0062130 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q6
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 6. Receipt of such an interrupt packet causes the setting of the Type 6 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT4Q6RR_PCB_INTR_PAYLOAD: Type 4 PCB interrupt packet content from QME 6 READ_EFFECT { OPIT4PRa.pcb_intr_type_4_pending_6=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 4 QME 7 Register
Addr:	000000000006C427 (SCOM) 00000000C0062138 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q7
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 7. Receipt of such an interrupt packet causes the setting of the Type 7 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT4Q7RR_PCB_INTR_PAYLOAD: Type 4 PCB interrupt packet content from QME 7 READ_EFFECT { OPIT4PRa.pcb_intr_type_4_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 5 QME 0 Register
Addr:	000000000006C428 (SCOM) 00000000C0062140 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q0
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT5Q0RR_PCB_INTR_PAYLOAD: Type 5 PCB interrupt packet content from QME 0 READ_EFFECT { OPIT5PRa.pcb_intr_type_5_pending_0=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 5 QME 1 Register
Addr:	000000000006C429 (SCOM) 00000000C0062148 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q1
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 1. Receipt of such an interrupt packet causes the setting of the Type 1 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT5Q1RR_PCB_INTR_PAYLOAD: Type 5 PCB interrupt packet content from QME 1 READ_EFFECT { OPIT5PRa.pcb_intr_type_5_pending_1=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 5 QME 2 Register
Addr:	000000000006C42A (SCOM) 00000000C0062150 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q2
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 2. Receipt of such an interrupt packet causes the setting of the Type 2 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT5Q2RR_PCB_INTR_PAYLOAD: Type 5 PCB interrupt packet content from QME 2 READ_EFFECT { OPIT5PRa.pcb_intr_type_5_pending_2=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 5 QME 3 Register
Addr:	000000000006C42B (SCOM) 00000000C0062158 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q3
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 3. Receipt of such an interrupt packet causes the setting of the Type 3 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT5Q3RR_PCB_INTR_PAYLOAD: Type 5 PCB interrupt packet content from QME 3 READ_EFFECT { OPIT5PRa.pcb_intr_type_5_pending_3=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 5 QME 4 Register
Addr:	000000000006C42C (SCOM) 00000000C0062160 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q4
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 4. Receipt of such an interrupt packet causes the setting of the Type 4 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT5Q4RR_PCB_INTR_PAYLOAD: Type 5 PCB interrupt packet content from QME 4 READ_EFFECT { OPIT5PRa.pcb_intr_type_5_pending_4=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 5 QME 5 Register
Addr:	000000000006C42D (SCOM) 00000000C0062168 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q5
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 5. Receipt of such an interrupt packet causes the setting of the Type 5 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT5Q5RR_PCB_INTR_PAYLOAD: Type 5 PCB interrupt packet content from QME 5 READ_EFFECT { OPIT5PRa.pcb_intr_type_5_pending_5=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 5 QME 6 Register
Addr:	000000000006C42E (SCOM) 00000000C0062170 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q6
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 6. Receipt of such an interrupt packet causes the setting of the Type 6 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT5Q6RR_PCB_INTR_PAYLOAD: Type 5 PCB interrupt packet content from QME 6 READ_EFFECT { OPIT5PRa.pcb_intr_type_5_pending_6=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 5 QME 7 Register
Addr:	000000000006C42F (SCOM) 00000000C0062178 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q7
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 7. Receipt of such an interrupt packet causes the setting of the Type 7 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT5Q7RR_PCB_INTR_PAYLOAD: Type 5 PCB interrupt packet content from QME 7 READ_EFFECT { OPIT5PRa.pcb_intr_type_5_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 6 QME 0 Register
Addr:	000000000006C430 (SCOM) 00000000C0062180 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q0
Constant(s):	PU_OCB_OCI_OPIT6Q0
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT6Q0RR_PCB_INTR_PAYLOAD: Type 6 PCB interrupt packet content from QME 0 READ_EFFECT { OPIT6PRa.pcb_intr_type_6_pending_0=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 6 QME 1 Register
Addr:	000000000006C431 (SCOM) 00000000C0062188 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q1
Constant(s):	PU_OCB_OCI_OPIT6Q1
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 1. Receipt of such an interrupt packet causes the setting of the Type 1 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT6Q1RR_PCB_INTR_PAYLOAD: Type 6 PCB interrupt packet content from QME 1 READ_EFFECT { OPIT6PRa.pcb_intr_type_6_pending_1=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 6 QME 2 Register
Addr:	000000000006C432 (SCOM) 00000000C0062190 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q2
Constant(s):	PU_OCB_OCI_OPIT6Q2
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 2. Receipt of such an interrupt packet causes the setting of the Type 2 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT6Q2RR_PCB_INTR_PAYLOAD: Type 6 PCB interrupt packet content from QME 2 READ_EFFECT { OPIT6PRa.pcb_intr_type_6_pending_2=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 6 QME 3 Register
Addr:	000000000006C433 (SCOM) 00000000C0062198 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q3
Constant(s):	PU_OCB_OCI_OPIT6Q3
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 3. Receipt of such an interrupt packet causes the setting of the Type 3 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT6Q3RR_PCB_INTR_PAYLOAD: Type 6 PCB interrupt packet content from QME 3 READ_EFFECT { OPIT6PRa.pcb_intr_type_6_pending_3=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 6 QME 4 Register
Addr:	000000000006C434 (SCOM) 00000000C00621A0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q4
Constant(s):	PU_OCB_OCI_OPIT6Q4
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 4. Receipt of such an interrupt packet causes the setting of the Type 4 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT6Q4RR_PCB_INTR_PAYLOAD: Type 6 PCB interrupt packet content from QME 4 READ_EFFECT { OPIT6PRa.pcb_intr_type_6_pending_4=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 6 QME 5 Register
Addr:	000000000006C435 (SCOM) 00000000C00621A8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q5
Constant(s):	PU_OCB_OCI_OPIT6Q5
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 5. Receipt of such an interrupt packet causes the setting of the Type 5 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT6Q5RR_PCB_INTR_PAYLOAD: Type 6 PCB interrupt packet content from QME 5 READ_EFFECT { OPIT6PRa.pcb_intr_type_6_pending_5=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 6 QME 6 Register
Addr:	000000000006C436 (SCOM) 00000000C00621B0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q6
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 6. Receipt of such an interrupt packet causes the setting of the Type 6 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT6Q6RR_PCB_INTR_PAYLOAD: Type 6 PCB interrupt packet content from QME 6 READ_EFFECT { OPIT6PRa.pcb_intr_type_6_pending_6=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 6 QME 7 Register
Addr:	000000000006C437 (SCOM) 00000000C00621B8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q7
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 7. Receipt of such an interrupt packet causes the setting of the Type 7 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT6Q7RR_PCB_INTR_PAYLOAD: Type 6 PCB interrupt packet content from QME 7 READ_EFFECT { OPIT6PRa.pcb_intr_type_6_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 7 QME 0 Register
Addr:	000000000006C438 (SCOM) 00000000C00621C0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q0
Constant(s):	PU_OCB_OCI_OPIT7Q0
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT7Q0RR_PCB_INTR_PAYLOAD: Type 7 PCB interrupt packet content from QME 0 READ_EFFECT { OPIT7PRa.pcb_intr_type_7_pending_0=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 7 QME 1 Register
Addr:	000000000006C439 (SCOM) 00000000C00621C8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q1
Constant(s):	PU_OCB_OCI_OPIT7Q1
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 1. Receipt of such an interrupt packet causes the setting of the Type 1 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT7Q1RR_PCB_INTR_PAYLOAD: Type 7 PCB interrupt packet content from QME 1 READ_EFFECT { OPIT7PRa.pcb_intr_type_7_pending_1=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 7 QME 2 Register
Addr:	000000000006C43A (SCOM) 00000000C00621D0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q2
Constant(s):	PU_OCB_OCI_OPIT7Q2
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 2. Receipt of such an interrupt packet causes the setting of the Type 2 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT7Q2RR_PCB_INTR_PAYLOAD: Type 7 PCB interrupt packet content from QME 2 READ_EFFECT { OPIT7PRa.pcb_intr_type_7_pending_2=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 7 QME 3 Register
Addr:	000000000006C43B (SCOM) 00000000C00621D8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q3
Constant(s):	PU_OCB_OCI_OPIT7Q3
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 3. Receipt of such an interrupt packet causes the setting of the Type 3 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT7Q3RR_PCB_INTR_PAYLOAD: Type 7 PCB interrupt packet content from QME 3 READ_EFFECT { OPIT7PRa.pcb_intr_type_7_pending_3=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 7 QME 4 Register
Addr:	000000000006C43C (SCOM) 00000000C00621E0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q4
Constant(s):	PU_OCB_OCI_OPIT7Q4
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 4. Receipt of such an interrupt packet causes the setting of the Type 4 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT7Q4RR_PCB_INTR_PAYLOAD: Type 7 PCB interrupt packet content from QME 4 READ_EFFECT { OPIT7PRa.pcb_intr_type_7_pending_4=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 7 QME 5 Register
Addr:	000000000006C43D (SCOM) 00000000C00621E8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q5
Constant(s):	PU_OCB_OCI_OPIT7Q5
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 5. Receipt of such an interrupt packet causes the setting of the Type 5 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT7Q5RR_PCB_INTR_PAYLOAD: Type 7 PCB interrupt packet content from QME 5 READ_EFFECT { OPIT7PRa.pcb_intr_type_7_pending_5=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 7 QME 6 Register
Addr:	000000000006C43E (SCOM) 00000000C00621F0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q6
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 6. Receipt of such an interrupt packet causes the setting of the Type 6 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT7Q6RR_PCB_INTR_PAYLOAD: Type 7 PCB interrupt packet content from QME 6 READ_EFFECT { OPIT7PRa.pcb_intr_type_7_pending_6=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 7 QME 7 Register
Addr:	000000000006C43F (SCOM) 00000000C00621F8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q7
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 7. Receipt of such an interrupt packet causes the setting of the Type 7 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT7Q7RR_PCB_INTR_PAYLOAD: Type 7 PCB interrupt packet content from QME 7 READ_EFFECT { OPIT7PRa.pcb_intr_type_7_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 0 Register
Addr:	000000000006C440 (SCOM) 00000000C0062200 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C0
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT0PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C0RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C0RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 0 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_0=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 1 Register
Addr:	000000000006C441 (SCOM) 00000000C0062208 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C1
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 1 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 1 pending bit in OPIT1PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT1PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C1RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C1RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 1 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_1=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 2 Register
Addr:	000000000006C442 (SCOM) 00000000C0062210 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C2
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 2 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 2 pending bit in OPIT2PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT2PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C2RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C2RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 2 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_2=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 3 Register
Addr:	000000000006C443 (SCOM) 00000000C0062218 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C3
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 3 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 3 pending bit in OPIT3PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT3PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C3RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C3RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 3 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_3=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 4 Register
Addr:	000000000006C444 (SCOM) 00000000C0062220 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C4
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 4 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 4 pending bit in OPIT4PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT4PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C4RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C4RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 4 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_4=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 5 Register
Addr:	000000000006C445 (SCOM) 00000000C0062228 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C5
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 5 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 5 pending bit in OPIT5PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT5PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C5RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C5RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 5 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_5=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 6 Register
Addr:	000000000006C446 (SCOM) 00000000C0062230 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C6
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 6 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 6 pending bit in OPIT6PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT6PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C6RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C6RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 6 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_6=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 7 Register
Addr:	000000000006C447 (SCOM) 00000000C0062238 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C7
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 7 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 7 pending bit in OPIT7PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT7PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C7RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C7RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 7 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 8 Register
Addr:	000000000006C448 (SCOM) 00000000C0062240 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C8
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 8 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 8 pending bit in OPIT8PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT8PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C8RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C8RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 8 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_8=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 9 Register
Addr:	000000000006C449 (SCOM) 00000000C0062248 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C9
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 9 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 9 pending bit in OPIT9PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT9PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C9RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C9RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 9 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_9=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 10 Register
Addr:	000000000006C44A (SCOM) 00000000C0062250 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C10
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 10 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 10 pending bit in OPIT10PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT10PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C10RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C10RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 10 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_10=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 11 Register
Addr:	000000000006C44B (SCOM) 00000000C0062258 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C11
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 11 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 11 pending bit in OPIT11PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT11PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C11RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C11RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 11 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_11=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 12 Register
Addr:	000000000006C44C (SCOM) 00000000C0062260 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C12
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 12 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 12 pending bit in OPIT12PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT12PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C12RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C12RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 12 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_12=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 13 Register
Addr:	000000000006C44D (SCOM) 00000000C0062268 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C13
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 13 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 13 pending bit in OPIT13PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT13PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C13RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C13RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 13 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_13=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 14 Register
Addr:	000000000006C44E (SCOM) 00000000C0062270 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C14
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 14 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 14 pending bit in OPIT14PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT14PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C14RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C14RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 14 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_14=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 15 Register
Addr:	000000000006C44F (SCOM) 00000000C0062278 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C15
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 15 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 15 pending bit in OPIT15PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT15PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C15RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C15RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 15 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_15=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 16 Register
Addr:	000000000006C450 (SCOM) 00000000C0062280 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C16
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 16 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 16 pending bit in OPIT16PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT16PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C16RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C16RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 16 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_16=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 17 Register
Addr:	000000000006C451 (SCOM) 00000000C0062288 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C17
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 17 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 17 pending bit in OPIT17PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT17PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C17RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C17RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 17 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_17=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 18 Register
Addr:	000000000006C452 (SCOM) 00000000C0062290 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C18
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 18 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 18 pending bit in OPIT18PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT18PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C18RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C18RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 18 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_18=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 19 Register
Addr:	000000000006C453 (SCOM) 00000000C0062298 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C19
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 19 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 19 pending bit in OPIT19PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT19PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C19RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C19RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 19 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_19=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 20 Register
Addr:	000000000006C454 (SCOM) 00000000C00622A0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C20
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 20 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 20 pending bit in OPIT20PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT20PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C20RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C20RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 20 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_20=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 21 Register
Addr:	000000000006C455 (SCOM) 00000000C00622A8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C21
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 21 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 21 pending bit in OPIT21PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT21PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C21RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C21RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 21 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_21=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 22 Register
Addr:	000000000006C456 (SCOM) 00000000C00622B0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C22
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 22 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 22 pending bit in OPIT22PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT22PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C22RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C22RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 22 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_22=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 23 Register
Addr:	000000000006C457 (SCOM) 00000000C00622B8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C23
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 23 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 23 pending bit in OPIT23PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT23PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C23RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C23RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 23 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_23=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 24 Register
Addr:	000000000006C458 (SCOM) 00000000C00622C0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C24
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 24 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 24 pending bit in OPIT24PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT24PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C24RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C24RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 24 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_24=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 25 Register
Addr:	000000000006C459 (SCOM) 00000000C00622C8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C25
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 25 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 25 pending bit in OPIT25PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT25PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C25RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C25RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 25 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_25=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 26 Register
Addr:	000000000006C45A (SCOM) 00000000C00622D0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C26
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 26 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 26 pending bit in OPIT26PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT26PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C26RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C26RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 26 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_26=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 27 Register
Addr:	000000000006C45B (SCOM) 00000000C00622D8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C27
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 27 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 27 pending bit in OPIT27PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT27PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C27RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C27RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 27 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_27=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 28 Register
Addr:	000000000006C45C (SCOM) 00000000C00622E0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C28
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 28 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 28 pending bit in OPIT28PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT28PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C28RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C28RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 28 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_28=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 29 Register
Addr:	000000000006C45D (SCOM) 00000000C00622E8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C29
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 29 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 29 pending bit in OPIT29PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT29PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C29RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C29RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 29 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_29=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 30 Register
Addr:	000000000006C45E (SCOM) 00000000C00622F0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C30
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 30 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 30 pending bit in OPIT30PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT30PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C30RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C30RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 30 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_30=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 31 Register
Addr:	000000000006C45F (SCOM) 00000000C00622F8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C31
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 31 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 31 pending bit in OPIT31PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT31PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C31RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C31RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 31 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_31=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 0 Register
Addr:	000000000006C460 (SCOM) 00000000C0062300 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C0
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT0PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C0RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C0RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 0 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_0=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 1 Register
Addr:	000000000006C461 (SCOM) 00000000C0062308 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C1
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 1 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 1 pending bit in OPIT1PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT1PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C1RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C1RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 1 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_1=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 2 Register
Addr:	000000000006C462 (SCOM) 00000000C0062310 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C2
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 2 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 2 pending bit in OPIT2PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT2PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C2RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C2RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 2 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_2=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 3 Register
Addr:	000000000006C463 (SCOM) 00000000C0062318 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C3
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 3 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 3 pending bit in OPIT3PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT3PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C3RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C3RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 3 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_3=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 4 Register
Addr:	000000000006C464 (SCOM) 00000000C0062320 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C4
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 4 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 4 pending bit in OPIT4PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT4PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C4RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C4RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 4 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_4=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 5 Register
Addr:	000000000006C465 (SCOM) 00000000C0062328 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C5
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 5 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 5 pending bit in OPIT5PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT5PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C5RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C5RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 5 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_5=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 6 Register
Addr:	000000000006C466 (SCOM) 00000000C0062330 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C6
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 6 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 6 pending bit in OPIT6PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT6PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C6RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C6RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 6 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_6=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 7 Register
Addr:	000000000006C467 (SCOM) 00000000C0062338 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C7
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 7 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 7 pending bit in OPIT7PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT7PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C7RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C7RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 7 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 8 Register
Addr:	000000000006C468 (SCOM) 00000000C0062340 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C8
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 8 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 8 pending bit in OPIT8PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT8PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C8RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C8RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 8 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_8=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 9 Register
Addr:	000000000006C469 (SCOM) 00000000C0062348 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C9
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 9 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 9 pending bit in OPIT9PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT9PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C9RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C9RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 9 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_9=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 10 Register
Addr:	000000000006C46A (SCOM) 00000000C0062350 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C10
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 10 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 10 pending bit in OPIT10PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT10PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C10RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C10RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 10 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_10=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 11 Register
Addr:	000000000006C46B (SCOM) 00000000C0062358 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C11
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 11 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 11 pending bit in OPIT11PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT11PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C11RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C11RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 11 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_11=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 12 Register
Addr:	000000000006C46C (SCOM) 00000000C0062360 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C12
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 12 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 12 pending bit in OPIT12PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT12PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C12RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C12RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 12 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_12=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 13 Register
Addr:	000000000006C46D (SCOM) 00000000C0062368 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C13
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 13 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 13 pending bit in OPIT13PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT13PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C13RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C13RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 13 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_13=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 14 Register
Addr:	000000000006C46E (SCOM) 00000000C0062370 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C14
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 14 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 14 pending bit in OPIT14PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT14PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C14RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C14RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 14 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_14=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 15 Register
Addr:	000000000006C46F (SCOM) 00000000C0062378 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C15
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 15 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 15 pending bit in OPIT15PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT15PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C15RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C15RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 15 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_15=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 16 Register
Addr:	000000000006C470 (SCOM) 00000000C0062380 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C16
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 16 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 16 pending bit in OPIT16PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT16PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C16RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C16RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 16 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_16=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 17 Register
Addr:	000000000006C471 (SCOM) 00000000C0062388 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C17
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 17 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 17 pending bit in OPIT17PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT17PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C17RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C17RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 17 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_17=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 18 Register
Addr:	000000000006C472 (SCOM) 00000000C0062390 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C18
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 18 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 18 pending bit in OPIT18PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT18PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C18RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C18RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 18 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_18=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 19 Register
Addr:	000000000006C473 (SCOM) 00000000C0062398 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C19
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 19 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 19 pending bit in OPIT19PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT19PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C19RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C19RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 19 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_19=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 20 Register
Addr:	000000000006C474 (SCOM) 00000000C00623A0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C20
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 20 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 20 pending bit in OPIT20PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT20PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C20RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C20RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 20 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_20=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 21 Register
Addr:	000000000006C475 (SCOM) 00000000C00623A8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C21
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 21 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 21 pending bit in OPIT21PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT21PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C21RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C21RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 21 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_21=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 22 Register
Addr:	000000000006C476 (SCOM) 00000000C00623B0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C22
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 22 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 22 pending bit in OPIT22PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT22PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C22RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C22RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 22 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_22=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 23 Register
Addr:	000000000006C477 (SCOM) 00000000C00623B8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C23
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 23 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 23 pending bit in OPIT23PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT23PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C23RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C23RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 23 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_23=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 24 Register
Addr:	000000000006C478 (SCOM) 00000000C00623C0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C24
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 24 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 24 pending bit in OPIT24PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT24PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C24RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C24RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 24 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_24=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 25 Register
Addr:	000000000006C479 (SCOM) 00000000C00623C8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C25
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 25 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 25 pending bit in OPIT25PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT25PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C25RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C25RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 25 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_25=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 26 Register
Addr:	000000000006C47A (SCOM) 00000000C00623D0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C26
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 26 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 26 pending bit in OPIT26PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT26PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C26RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C26RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 26 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_26=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 27 Register
Addr:	000000000006C47B (SCOM) 00000000C00623D8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C27
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 27 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 27 pending bit in OPIT27PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT27PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C27RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C27RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 27 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_27=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 28 Register
Addr:	000000000006C47C (SCOM) 00000000C00623E0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C28
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 28 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 28 pending bit in OPIT28PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT28PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C28RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C28RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 28 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_28=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 29 Register
Addr:	000000000006C47D (SCOM) 00000000C00623E8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C29
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 29 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 29 pending bit in OPIT29PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT29PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C29RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C29RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 29 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_29=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 30 Register
Addr:	000000000006C47E (SCOM) 00000000C00623F0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C30
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 30 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 30 pending bit in OPIT30PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT30PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C30RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C30RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 30 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_30=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 31 Register
Addr:	000000000006C47F (SCOM) 00000000C00623F8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C31
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 31 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 31 pending bit in OPIT31PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT31PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C31RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C31RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 31 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_31=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type A Summary Vector 0 Register
Addr:	000000000006C480 (SCOM) 00000000C0062400 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITASV0
Constant(s):
Comments:	This register provides access to type A Summary Notification Vectors. Type A and Type B interrupts write 4 different bits across 4 Summary Vectors (16 bits total) into a position determined by the number of the QME sourcing the interrupt. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPITAPR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts. Note: If the QME source is needed, first Read_CLEAR the pending register, then read this summary vector using a 0x04XX address. Then optionally read the pending vector (with or without clear) to see if any new interrupts arrived.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV0_Q_0_INST.LATC.L2(0:3) [0000]
	4:7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV0_Q_4_INST.LATC.L2(4:7) [0000]
	8:11	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV0_Q_8_INST.LATC.L2(8:11) [0000]
	12:15	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV0_Q_12_INST.LATC.L2(12:15) [0000]
	16:19	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV0_Q_16_INST.LATC.L2(16:19) [0000]
	20:23	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV0_Q_20_INST.LATC.L2(20:23) [0000]
	24:27	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV0_Q_24_INST.LATC.L2(24:27) [0000]
	28:31	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV0_Q_28_INST.LATC.L2(28:31) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0:3	ROX	ROX		OCB_OCI_OPITASV0RR_PCB_INTR_PAYLOAD_QUAD_0: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 0 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_0=0; } // clear appropriate pending bit
4:7	ROX	ROX		OCB_OCI_OPITASV0RR_PCB_INTR_PAYLOAD_QUAD_1: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 1 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_1=0; } // clear appropriate pending bit
8:11	ROX	ROX		OCB_OCI_OPITASV0RR_PCB_INTR_PAYLOAD_QUAD_2: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 2 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_2=0; } // clear appropriate pending bit
12:15	ROX	ROX		OCB_OCI_OPITASV0RR_PCB_INTR_PAYLOAD_QUAD_3: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 3 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_3=0; } // clear appropriate pending bit
16:19	ROX	ROX		OCB_OCI_OPITASV0RR_PCB_INTR_PAYLOAD_QUAD_4: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 4 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_4=0; } // clear appropriate pending bit
20:23	ROX	ROX		OCB_OCI_OPITASV0RR_PCB_INTR_PAYLOAD_QUAD_5: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 5 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_5=0; } // clear appropriate pending bit
24:27	ROX	ROX		OCB_OCI_OPITASV0RR_PCB_INTR_PAYLOAD_QUAD_6: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 6 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_6=0; } // clear appropriate pending bit
28:31	ROX	ROX		OCB_OCI_OPITASV0RR_PCB_INTR_PAYLOAD_QUAD_7: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 7 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type A Summary Vector 1 Register
Addr:	000000000006C481 (SCOM) 00000000C0062408 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITASV1
Constant(s):
Comments:	This register provides access to type A Summary Notification Vectors. Type A and Type B interrupts write 4 different bits across 4 Summary Vectors (16 bits total) into a position determined by the number of the QME sourcing the interrupt. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPITAPR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts. Note: If the QME source is needed, first Read_CLEAR the pending register, then read this summary vector using a 0x04XX address. Then optionally read the pending vector (with or without clear) to see if any new interrupts arrived.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV1_Q_0_INST.LATC.L2(0:3) [0000]
	4:7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV1_Q_4_INST.LATC.L2(4:7) [0000]
	8:11	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV1_Q_8_INST.LATC.L2(8:11) [0000]
	12:15	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV1_Q_12_INST.LATC.L2(12:15) [0000]
	16:19	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV1_Q_16_INST.LATC.L2(16:19) [0000]
	20:23	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV1_Q_20_INST.LATC.L2(20:23) [0000]
	24:27	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV1_Q_24_INST.LATC.L2(24:27) [0000]
	28:31	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV1_Q_28_INST.LATC.L2(28:31) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0:3	ROX	ROX		OCB_OCI_OPITASV1RR_PCB_INTR_PAYLOAD_QUAD_0: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 0 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_0=0; } // clear appropriate pending bit
4:7	ROX	ROX		OCB_OCI_OPITASV1RR_PCB_INTR_PAYLOAD_QUAD_1: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 1 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_1=0; } // clear appropriate pending bit
8:11	ROX	ROX		OCB_OCI_OPITASV1RR_PCB_INTR_PAYLOAD_QUAD_2: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 2 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_2=0; } // clear appropriate pending bit
12:15	ROX	ROX		OCB_OCI_OPITASV1RR_PCB_INTR_PAYLOAD_QUAD_3: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 3 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_3=0; } // clear appropriate pending bit
16:19	ROX	ROX		OCB_OCI_OPITASV1RR_PCB_INTR_PAYLOAD_QUAD_4: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 4 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_4=0; } // clear appropriate pending bit
20:23	ROX	ROX		OCB_OCI_OPITASV1RR_PCB_INTR_PAYLOAD_QUAD_5: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 5 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_5=0; } // clear appropriate pending bit
24:27	ROX	ROX		OCB_OCI_OPITASV1RR_PCB_INTR_PAYLOAD_QUAD_6: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 6 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_6=0; } // clear appropriate pending bit
28:31	ROX	ROX		OCB_OCI_OPITASV1RR_PCB_INTR_PAYLOAD_QUAD_7: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 7 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type A Summary Vector 2 Register
Addr:	000000000006C482 (SCOM) 00000000C0062410 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITASV2
Constant(s):
Comments:	This register provides access to type A Summary Notification Vectors. Type A and Type B interrupts write 4 different bits across 4 Summary Vectors (16 bits total) into a position determined by the number of the QME sourcing the interrupt. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPITAPR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts. Note: If the QME source is needed, first Read_CLEAR the pending register, then read this summary vector using a 0x04XX address. Then optionally read the pending vector (with or without clear) to see if any new interrupts arrived.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV2_Q_0_INST.LATC.L2(0:3) [0000]
	4:7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV2_Q_4_INST.LATC.L2(4:7) [0000]
	8:11	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV2_Q_8_INST.LATC.L2(8:11) [0000]
	12:15	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV2_Q_12_INST.LATC.L2(12:15) [0000]
	16:19	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV2_Q_16_INST.LATC.L2(16:19) [0000]
	20:23	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV2_Q_20_INST.LATC.L2(20:23) [0000]
	24:27	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV2_Q_24_INST.LATC.L2(24:27) [0000]
	28:31	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV2_Q_28_INST.LATC.L2(28:31) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0:3	ROX	ROX		OCB_OCI_OPITASV2RR_PCB_INTR_PAYLOAD_QUAD_0: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 0 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_0=0; } // clear appropriate pending bit
4:7	ROX	ROX		OCB_OCI_OPITASV2RR_PCB_INTR_PAYLOAD_QUAD_1: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 1 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_1=0; } // clear appropriate pending bit
8:11	ROX	ROX		OCB_OCI_OPITASV2RR_PCB_INTR_PAYLOAD_QUAD_2: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 2 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_2=0; } // clear appropriate pending bit
12:15	ROX	ROX		OCB_OCI_OPITASV2RR_PCB_INTR_PAYLOAD_QUAD_3: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 3 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_3=0; } // clear appropriate pending bit
16:19	ROX	ROX		OCB_OCI_OPITASV2RR_PCB_INTR_PAYLOAD_QUAD_4: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 4 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_4=0; } // clear appropriate pending bit
20:23	ROX	ROX		OCB_OCI_OPITASV2RR_PCB_INTR_PAYLOAD_QUAD_5: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 5 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_5=0; } // clear appropriate pending bit
24:27	ROX	ROX		OCB_OCI_OPITASV2RR_PCB_INTR_PAYLOAD_QUAD_6: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 6 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_6=0; } // clear appropriate pending bit
28:31	ROX	ROX		OCB_OCI_OPITASV2RR_PCB_INTR_PAYLOAD_QUAD_7: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 7 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type A Summary Vector 3 Register
Addr:	000000000006C483 (SCOM) 00000000C0062418 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITASV3
Constant(s):
Comments:	This register provides access to type A Summary Notification Vectors. Type A and Type B interrupts write 4 different bits across 4 Summary Vectors (16 bits total) into a position determined by the number of the QME sourcing the interrupt. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPITAPR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts. Note: If the QME source is needed, first Read_CLEAR the pending register, then read this summary vector using a 0x04XX address. Then optionally read the pending vector (with or without clear) to see if any new interrupts arrived.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV3_Q_0_INST.LATC.L2(0:3) [0000]
	4:7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV3_Q_4_INST.LATC.L2(4:7) [0000]
	8:11	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV3_Q_8_INST.LATC.L2(8:11) [0000]
	12:15	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV3_Q_12_INST.LATC.L2(12:15) [0000]
	16:19	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV3_Q_16_INST.LATC.L2(16:19) [0000]
	20:23	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV3_Q_20_INST.LATC.L2(20:23) [0000]
	24:27	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV3_Q_24_INST.LATC.L2(24:27) [0000]
	28:31	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV3_Q_28_INST.LATC.L2(28:31) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0:3	ROX	ROX		OCB_OCI_OPITASV3RR_PCB_INTR_PAYLOAD_QUAD_0: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 0 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_0=0; } // clear appropriate pending bit
4:7	ROX	ROX		OCB_OCI_OPITASV3RR_PCB_INTR_PAYLOAD_QUAD_1: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 1 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_1=0; } // clear appropriate pending bit
8:11	ROX	ROX		OCB_OCI_OPITASV3RR_PCB_INTR_PAYLOAD_QUAD_2: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 2 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_2=0; } // clear appropriate pending bit
12:15	ROX	ROX		OCB_OCI_OPITASV3RR_PCB_INTR_PAYLOAD_QUAD_3: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 3 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_3=0; } // clear appropriate pending bit
16:19	ROX	ROX		OCB_OCI_OPITASV3RR_PCB_INTR_PAYLOAD_QUAD_4: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 4 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_4=0; } // clear appropriate pending bit
20:23	ROX	ROX		OCB_OCI_OPITASV3RR_PCB_INTR_PAYLOAD_QUAD_5: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 5 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_5=0; } // clear appropriate pending bit
24:27	ROX	ROX		OCB_OCI_OPITASV3RR_PCB_INTR_PAYLOAD_QUAD_6: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 6 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_6=0; } // clear appropriate pending bit
28:31	ROX	ROX		OCB_OCI_OPITASV3RR_PCB_INTR_PAYLOAD_QUAD_7: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 7 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type B Summary Vector 0 Register
Addr:	000000000006C484 (SCOM) 00000000C0062420 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBSV0
Constant(s):
Comments:	This register provides access to type A Summary Notification Vectors. Type A and Type B interrupts write 4 different bits across 4 Summary Vectors (16 bits total) into a position determined by the number of the QME sourcing the interrupt. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPITAPR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts. Note: If the QME source is needed, first Read_CLEAR the pending register, then read this summary vector using a 0x04XX address. Then optionally read the pending vector (with or without clear) to see if any new interrupts arrived.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV0_Q_0_INST.LATC.L2(0:3) [0000]
	4:7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV0_Q_4_INST.LATC.L2(4:7) [0000]
	8:11	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV0_Q_8_INST.LATC.L2(8:11) [0000]
	12:15	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV0_Q_12_INST.LATC.L2(12:15) [0000]
	16:19	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV0_Q_16_INST.LATC.L2(16:19) [0000]
	20:23	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV0_Q_20_INST.LATC.L2(20:23) [0000]
	24:27	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV0_Q_24_INST.LATC.L2(24:27) [0000]
	28:31	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV0_Q_28_INST.LATC.L2(28:31) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0:3	ROX	ROX		OCB_OCI_OPITBSV0RR_PCB_INTR_PAYLOAD_QUAD_0: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 0 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_0=0; } // clear appropriate pending bit
4:7	ROX	ROX		OCB_OCI_OPITBSV0RR_PCB_INTR_PAYLOAD_QUAD_1: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 1 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_1=0; } // clear appropriate pending bit
8:11	ROX	ROX		OCB_OCI_OPITBSV0RR_PCB_INTR_PAYLOAD_QUAD_2: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 2 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_2=0; } // clear appropriate pending bit
12:15	ROX	ROX		OCB_OCI_OPITBSV0RR_PCB_INTR_PAYLOAD_QUAD_3: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 3 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_3=0; } // clear appropriate pending bit
16:19	ROX	ROX		OCB_OCI_OPITBSV0RR_PCB_INTR_PAYLOAD_QUAD_4: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 4 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_4=0; } // clear appropriate pending bit
20:23	ROX	ROX		OCB_OCI_OPITBSV0RR_PCB_INTR_PAYLOAD_QUAD_5: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 5 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_5=0; } // clear appropriate pending bit
24:27	ROX	ROX		OCB_OCI_OPITBSV0RR_PCB_INTR_PAYLOAD_QUAD_6: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 6 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_6=0; } // clear appropriate pending bit
28:31	ROX	ROX		OCB_OCI_OPITBSV0RR_PCB_INTR_PAYLOAD_QUAD_7: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 7 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type B Summary Vector 1 Register
Addr:	000000000006C485 (SCOM) 00000000C0062428 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBSV1
Constant(s):
Comments:	This register provides access to type A Summary Notification Vectors. Type A and Type B interrupts write 4 different bits across 4 Summary Vectors (16 bits total) into a position determined by the number of the QME sourcing the interrupt. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPITAPR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts. Note: If the QME source is needed, first Read_CLEAR the pending register, then read this summary vector using a 0x04XX address. Then optionally read the pending vector (with or without clear) to see if any new interrupts arrived.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV1_Q_0_INST.LATC.L2(0:3) [0000]
	4:7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV1_Q_4_INST.LATC.L2(4:7) [0000]
	8:11	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV1_Q_8_INST.LATC.L2(8:11) [0000]
	12:15	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV1_Q_12_INST.LATC.L2(12:15) [0000]
	16:19	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV1_Q_16_INST.LATC.L2(16:19) [0000]
	20:23	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV1_Q_20_INST.LATC.L2(20:23) [0000]
	24:27	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV1_Q_24_INST.LATC.L2(24:27) [0000]
	28:31	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV1_Q_28_INST.LATC.L2(28:31) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0:3	ROX	ROX		OCB_OCI_OPITBSV1RR_PCB_INTR_PAYLOAD_QUAD_0: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 0 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_0=0; } // clear appropriate pending bit
4:7	ROX	ROX		OCB_OCI_OPITBSV1RR_PCB_INTR_PAYLOAD_QUAD_1: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 1 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_1=0; } // clear appropriate pending bit
8:11	ROX	ROX		OCB_OCI_OPITBSV1RR_PCB_INTR_PAYLOAD_QUAD_2: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 2 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_2=0; } // clear appropriate pending bit
12:15	ROX	ROX		OCB_OCI_OPITBSV1RR_PCB_INTR_PAYLOAD_QUAD_3: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 3 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_3=0; } // clear appropriate pending bit
16:19	ROX	ROX		OCB_OCI_OPITBSV1RR_PCB_INTR_PAYLOAD_QUAD_4: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 4 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_4=0; } // clear appropriate pending bit
20:23	ROX	ROX		OCB_OCI_OPITBSV1RR_PCB_INTR_PAYLOAD_QUAD_5: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 5 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_5=0; } // clear appropriate pending bit
24:27	ROX	ROX		OCB_OCI_OPITBSV1RR_PCB_INTR_PAYLOAD_QUAD_6: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 6 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_6=0; } // clear appropriate pending bit
28:31	ROX	ROX		OCB_OCI_OPITBSV1RR_PCB_INTR_PAYLOAD_QUAD_7: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 7 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type B Summary Vector 2 Register
Addr:	000000000006C486 (SCOM) 00000000C0062430 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBSV2
Constant(s):
Comments:	This register provides access to type A Summary Notification Vectors. Type A and Type B interrupts write 4 different bits across 4 Summary Vectors (16 bits total) into a position determined by the number of the QME sourcing the interrupt. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPITAPR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts. Note: If the QME source is needed, first Read_CLEAR the pending register, then read this summary vector using a 0x04XX address. Then optionally read the pending vector (with or without clear) to see if any new interrupts arrived.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV2_Q_0_INST.LATC.L2(0:3) [0000]
	4:7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV2_Q_4_INST.LATC.L2(4:7) [0000]
	8:11	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV2_Q_8_INST.LATC.L2(8:11) [0000]
	12:15	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV2_Q_12_INST.LATC.L2(12:15) [0000]
	16:19	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV2_Q_16_INST.LATC.L2(16:19) [0000]
	20:23	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV2_Q_20_INST.LATC.L2(20:23) [0000]
	24:27	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV2_Q_24_INST.LATC.L2(24:27) [0000]
	28:31	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV2_Q_28_INST.LATC.L2(28:31) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0:3	ROX	ROX		OCB_OCI_OPITBSV2RR_PCB_INTR_PAYLOAD_QUAD_0: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 0 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_0=0; } // clear appropriate pending bit
4:7	ROX	ROX		OCB_OCI_OPITBSV2RR_PCB_INTR_PAYLOAD_QUAD_1: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 1 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_1=0; } // clear appropriate pending bit
8:11	ROX	ROX		OCB_OCI_OPITBSV2RR_PCB_INTR_PAYLOAD_QUAD_2: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 2 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_2=0; } // clear appropriate pending bit
12:15	ROX	ROX		OCB_OCI_OPITBSV2RR_PCB_INTR_PAYLOAD_QUAD_3: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 3 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_3=0; } // clear appropriate pending bit
16:19	ROX	ROX		OCB_OCI_OPITBSV2RR_PCB_INTR_PAYLOAD_QUAD_4: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 4 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_4=0; } // clear appropriate pending bit
20:23	ROX	ROX		OCB_OCI_OPITBSV2RR_PCB_INTR_PAYLOAD_QUAD_5: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 5 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_5=0; } // clear appropriate pending bit
24:27	ROX	ROX		OCB_OCI_OPITBSV2RR_PCB_INTR_PAYLOAD_QUAD_6: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 6 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_6=0; } // clear appropriate pending bit
28:31	ROX	ROX		OCB_OCI_OPITBSV2RR_PCB_INTR_PAYLOAD_QUAD_7: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 7 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type B Summary Vector 3 Register
Addr:	000000000006C487 (SCOM) 00000000C0062438 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBSV3
Constant(s):
Comments:	This register provides access to type A Summary Notification Vectors. Type A and Type B interrupts write 4 different bits across 4 Summary Vectors (16 bits total) into a position determined by the number of the QME sourcing the interrupt. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPITAPR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts. Note: If the QME source is needed, first Read_CLEAR the pending register, then read this summary vector using a 0x04XX address. Then optionally read the pending vector (with or without clear) to see if any new interrupts arrived.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV3_Q_0_INST.LATC.L2(0:3) [0000]
	4:7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV3_Q_4_INST.LATC.L2(4:7) [0000]
	8:11	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV3_Q_8_INST.LATC.L2(8:11) [0000]
	12:15	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV3_Q_12_INST.LATC.L2(12:15) [0000]
	16:19	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV3_Q_16_INST.LATC.L2(16:19) [0000]
	20:23	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV3_Q_20_INST.LATC.L2(20:23) [0000]
	24:27	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV3_Q_24_INST.LATC.L2(24:27) [0000]
	28:31	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV3_Q_28_INST.LATC.L2(28:31) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0:3	ROX	ROX		OCB_OCI_OPITBSV3RR_PCB_INTR_PAYLOAD_QUAD_0: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 0 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_0=0; } // clear appropriate pending bit
4:7	ROX	ROX		OCB_OCI_OPITBSV3RR_PCB_INTR_PAYLOAD_QUAD_1: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 1 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_1=0; } // clear appropriate pending bit
8:11	ROX	ROX		OCB_OCI_OPITBSV3RR_PCB_INTR_PAYLOAD_QUAD_2: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 2 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_2=0; } // clear appropriate pending bit
12:15	ROX	ROX		OCB_OCI_OPITBSV3RR_PCB_INTR_PAYLOAD_QUAD_3: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 3 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_3=0; } // clear appropriate pending bit
16:19	ROX	ROX		OCB_OCI_OPITBSV3RR_PCB_INTR_PAYLOAD_QUAD_4: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 4 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_4=0; } // clear appropriate pending bit
20:23	ROX	ROX		OCB_OCI_OPITBSV3RR_PCB_INTR_PAYLOAD_QUAD_5: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 5 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_5=0; } // clear appropriate pending bit
24:27	ROX	ROX		OCB_OCI_OPITBSV3RR_PCB_INTR_PAYLOAD_QUAD_6: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 6 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_6=0; } // clear appropriate pending bit
28:31	ROX	ROX		OCB_OCI_OPITBSV3RR_PCB_INTR_PAYLOAD_QUAD_7: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 7 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCC PCB Interrupt Type C Summary Vector Register
Addr:	000000000006C488 (SCOM) 00000000C0062440 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITCSV
Constant(s):
Comments:	This register provides access to type C Summary Notification Vectors. Type C and D interrupts write 4 bits into a single summary vector in the likewise determined position. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPITCPR. Reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts. Note: Hcode should never use the offset address 0x05XX due to window conditions. Hcode should first read the pending vector into a variable, then read the summary vector from address 0x04XX, then WR_CLEAR the pending vector using the variable.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITCSV_Q_0_INST.LATC.L2(0:3) [0000]
	4:7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITCSV_Q_4_INST.LATC.L2(4:7) [0000]
	8:11	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITCSV_Q_8_INST.LATC.L2(8:11) [0000]
	12:15	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITCSV_Q_12_INST.LATC.L2(12:15) [0000]
	16:19	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITCSV_Q_16_INST.LATC.L2(16:19) [0000]
	20:23	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITCSV_Q_20_INST.LATC.L2(20:23) [0000]
	24:27	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITCSV_Q_24_INST.LATC.L2(24:27) [0000]
	28:31	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITCSV_Q_28_INST.LATC.L2(28:31) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0:3	ROX	ROX		OCB_OCI_OPITCSVRR_PCB_INTR_PAYLOAD_QUAD_0: Type C PCB Interrupt packet content(20:23) from Quad 0 READ_EFFECT { OPITCPRc.pcb_intr_type_C_pending_0=0; } // clear appropriate pending bit
4:7	ROX	ROX		OCB_OCI_OPITCSVRR_PCB_INTR_PAYLOAD_QUAD_1: Type C PCB Interrupt packet content(20:23) from Quad 1 READ_EFFECT { OPITCPRc.pcb_intr_type_C_pending_1=0; } // clear appropriate pending bit
8:11	ROX	ROX		OCB_OCI_OPITCSVRR_PCB_INTR_PAYLOAD_QUAD_2: Type C PCB Interrupt packet content(20:23) from Quad 2 READ_EFFECT { OPITCPRc.pcb_intr_type_C_pending_2=0; } // clear appropriate pending bit
12:15	ROX	ROX		OCB_OCI_OPITCSVRR_PCB_INTR_PAYLOAD_QUAD_3: Type C PCB Interrupt packet content(20:23) from Quad 3 READ_EFFECT { OPITCPRc.pcb_intr_type_C_pending_3=0; } // clear appropriate pending bit
16:19	ROX	ROX		OCB_OCI_OPITCSVRR_PCB_INTR_PAYLOAD_QUAD_4: Type C PCB Interrupt packet content(20:23) from Quad 4 READ_EFFECT { OPITCPRc.pcb_intr_type_C_pending_4=0; } // clear appropriate pending bit
20:23	ROX	ROX		OCB_OCI_OPITCSVRR_PCB_INTR_PAYLOAD_QUAD_5: Type C PCB Interrupt packet content(20:23) from Quad 5 READ_EFFECT { OPITCPRc.pcb_intr_type_C_pending_5=0; } // clear appropriate pending bit
24:27	ROX	ROX		OCB_OCI_OPITCSVRR_PCB_INTR_PAYLOAD_QUAD_6: Type C PCB Interrupt packet content(20:23) from Quad 6 READ_EFFECT { OPITCPRc.pcb_intr_type_C_pending_6=0; } // clear appropriate pending bit
28:31	ROX	ROX		OCB_OCI_OPITCSVRR_PCB_INTR_PAYLOAD_QUAD_7: Type C PCB Interrupt packet content(20:23) from Quad 7 READ_EFFECT { OPITCPRc.pcb_intr_type_C_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCC PCB Interrupt Type D Summary Vector Register
Addr:	000000000006C48C (SCOM) 00000000C0062460 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITDSV
Constant(s):
Comments:	This register provides access to type C Summary Notification Vectors. Type C and D interrupts write 4 bits into a single summary vector in the likewise determined position. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPITCPR. Reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts. Note: Hcode should never use the offset address 0x05XX due to window conditions. Hcode should first read the pending vector into a variable, then read the summary vector from address 0x04XX, then WR_CLEAR the pending vector using the variable.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITDSV_Q_0_INST.LATC.L2(0:3) [0000]
	4:7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITDSV_Q_4_INST.LATC.L2(4:7) [0000]
	8:11	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITDSV_Q_8_INST.LATC.L2(8:11) [0000]
	12:15	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITDSV_Q_12_INST.LATC.L2(12:15) [0000]
	16:19	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITDSV_Q_16_INST.LATC.L2(16:19) [0000]
	20:23	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITDSV_Q_20_INST.LATC.L2(20:23) [0000]
	24:27	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITDSV_Q_24_INST.LATC.L2(24:27) [0000]
	28:31	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITDSV_Q_28_INST.LATC.L2(28:31) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0:3	ROX	ROX		OCB_OCI_OPITDSVRR_PCB_INTR_PAYLOAD_QUAD_0: Type D PCB Interrupt packet content(20:23) from Quad 0 READ_EFFECT { OPITDPRc.pcb_intr_type_D_pending_0=0; } // clear appropriate pending bit
4:7	ROX	ROX		OCB_OCI_OPITDSVRR_PCB_INTR_PAYLOAD_QUAD_1: Type D PCB Interrupt packet content(20:23) from Quad 1 READ_EFFECT { OPITDPRc.pcb_intr_type_D_pending_1=0; } // clear appropriate pending bit
8:11	ROX	ROX		OCB_OCI_OPITDSVRR_PCB_INTR_PAYLOAD_QUAD_2: Type D PCB Interrupt packet content(20:23) from Quad 2 READ_EFFECT { OPITDPRc.pcb_intr_type_D_pending_2=0; } // clear appropriate pending bit
12:15	ROX	ROX		OCB_OCI_OPITDSVRR_PCB_INTR_PAYLOAD_QUAD_3: Type D PCB Interrupt packet content(20:23) from Quad 3 READ_EFFECT { OPITDPRc.pcb_intr_type_D_pending_3=0; } // clear appropriate pending bit
16:19	ROX	ROX		OCB_OCI_OPITDSVRR_PCB_INTR_PAYLOAD_QUAD_4: Type D PCB Interrupt packet content(20:23) from Quad 4 READ_EFFECT { OPITDPRc.pcb_intr_type_D_pending_4=0; } // clear appropriate pending bit
20:23	ROX	ROX		OCB_OCI_OPITDSVRR_PCB_INTR_PAYLOAD_QUAD_5: Type D PCB Interrupt packet content(20:23) from Quad 5 READ_EFFECT { OPITDPRc.pcb_intr_type_D_pending_5=0; } // clear appropriate pending bit
24:27	ROX	ROX		OCB_OCI_OPITDSVRR_PCB_INTR_PAYLOAD_QUAD_6: Type D PCB Interrupt packet content(20:23) from Quad 6 READ_EFFECT { OPITDPRc.pcb_intr_type_D_pending_6=0; } // clear appropriate pending bit
28:31	ROX	ROX		OCB_OCI_OPITDSVRR_PCB_INTR_PAYLOAD_QUAD_7: Type D PCB Interrupt packet content(20:23) from Quad 7 READ_EFFECT { OPITDPRc.pcb_intr_type_D_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCC PCB Interrupt Type E Summary Vector Register
Addr:	000000000006C490 (SCOM) 00000000C0062480 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITESV
Constant(s):
Comments:	This register provides access to type E Summary Notification Vectors. Type E and F interrupts write 4 bits but only if the pending bit for that position is not already set to create a "lock" mechanism of the first zero value received, and requires the pending bit cleared before another can be accepted. To clear a locked field, use the WR_CLEAR to the pending register, which allows atomic operation in case another field is written by a PIG at the same time. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPITEPR. Reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts. Note: Hcode should never use the offset address 0x05XX due to window conditions. Hcode should first read the pending vector into a variable, then read the summary vector from address 0x04XX, then WR_CLEAR the pending vector using the variable.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITESV_Q_0_INST.LATC.L2(0:3) [0000]
	4:7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITESV_Q_4_INST.LATC.L2(4:7) [0000]
	8:11	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITESV_Q_8_INST.LATC.L2(8:11) [0000]
	12:15	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITESV_Q_12_INST.LATC.L2(12:15) [0000]
	16:19	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITESV_Q_16_INST.LATC.L2(16:19) [0000]
	20:23	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITESV_Q_20_INST.LATC.L2(20:23) [0000]
	24:27	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITESV_Q_24_INST.LATC.L2(24:27) [0000]
	28:31	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITESV_Q_28_INST.LATC.L2(28:31) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0:3	ROX	ROX		OCB_OCI_OPITESVRR_PCB_INTR_PAYLOAD_QUAD_0: Type E PCB Interrupt packet content(20:23) from Quad 0 READ_EFFECT { OPITEPRd.pcb_intr_type_E_pending_0=0; } // clear appropriate pending bit
4:7	ROX	ROX		OCB_OCI_OPITESVRR_PCB_INTR_PAYLOAD_QUAD_1: Type E PCB Interrupt packet content(20:23) from Quad 1 READ_EFFECT { OPITEPRd.pcb_intr_type_E_pending_0=0; } // clear appropriate pending bit
8:11	ROX	ROX		OCB_OCI_OPITESVRR_PCB_INTR_PAYLOAD_QUAD_2: Type E PCB Interrupt packet content(20:23) from Quad 2 READ_EFFECT { OPITEPRd.pcb_intr_type_E_pending_0=0; } // clear appropriate pending bit
12:15	ROX	ROX		OCB_OCI_OPITESVRR_PCB_INTR_PAYLOAD_QUAD_3: Type E PCB Interrupt packet content(20:23) from Quad 3 READ_EFFECT { OPITEPRd.pcb_intr_type_E_pending_0=0; } // clear appropriate pending bit
16:19	ROX	ROX		OCB_OCI_OPITESVRR_PCB_INTR_PAYLOAD_QUAD_4: Type E PCB Interrupt packet content(20:23) from Quad 4 READ_EFFECT { OPITEPRd.pcb_intr_type_E_pending_0=0; } // clear appropriate pending bit
20:23	ROX	ROX		OCB_OCI_OPITESVRR_PCB_INTR_PAYLOAD_QUAD_5: Type E PCB Interrupt packet content(20:23) from Quad 5 READ_EFFECT { OPITEPRd.pcb_intr_type_E_pending_0=0; } // clear appropriate pending bit
24:27	ROX	ROX		OCB_OCI_OPITESVRR_PCB_INTR_PAYLOAD_QUAD_6: Type E PCB Interrupt packet content(20:23) from Quad 6 READ_EFFECT { OPITEPRd.pcb_intr_type_E_pending_0=0; } // clear appropriate pending bit
28:31	ROX	ROX		OCB_OCI_OPITESVRR_PCB_INTR_PAYLOAD_QUAD_7: Type E PCB Interrupt packet content(20:23) from Quad 7 READ_EFFECT { OPITEPRd.pcb_intr_type_E_pending_0=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCC PCB Interrupt Type F Summary Vector Register
Addr:	000000000006C494 (SCOM) 00000000C00624A0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITFSV
Constant(s):
Comments:	This register provides access to type E Summary Notification Vectors. Type E and F interrupts write 4 bits but only if the pending bit for that position is not already set to create a "lock" mechanism of the first zero value received, and requires the pending bit cleared before another can be accepted. To clear a locked field, use the WR_CLEAR to the pending register, which allows atomic operation in case another field is written by a PIG at the same time. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPITEPR. Reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts. Note: Hcode should never use the offset address 0x05XX due to window conditions. Hcode should first read the pending vector into a variable, then read the summary vector from address 0x04XX, then WR_CLEAR the pending vector using the variable.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITFSV_Q_0_INST.LATC.L2(0:3) [0000]
	4:7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITFSV_Q_4_INST.LATC.L2(4:7) [0000]
	8:11	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITFSV_Q_8_INST.LATC.L2(8:11) [0000]
	12:15	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITFSV_Q_12_INST.LATC.L2(12:15) [0000]
	16:19	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITFSV_Q_16_INST.LATC.L2(16:19) [0000]
	20:23	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITFSV_Q_20_INST.LATC.L2(20:23) [0000]
	24:27	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITFSV_Q_24_INST.LATC.L2(24:27) [0000]
	28:31	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITFSV_Q_28_INST.LATC.L2(28:31) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0:3	ROX	ROX		OCB_OCI_OPITFSVRR_PCB_INTR_PAYLOAD_QUAD_0: Type F PCB Interrupt packet content(20:23) from Quad 0 READ_EFFECT { OPITFPRd.pcb_intr_type_F_pending_0=0; } // clear appropriate pending bit
4:7	ROX	ROX		OCB_OCI_OPITFSVRR_PCB_INTR_PAYLOAD_QUAD_1: Type F PCB Interrupt packet content(20:23) from Quad 1 READ_EFFECT { OPITFPRd.pcb_intr_type_F_pending_0=0; } // clear appropriate pending bit
8:11	ROX	ROX		OCB_OCI_OPITFSVRR_PCB_INTR_PAYLOAD_QUAD_2: Type F PCB Interrupt packet content(20:23) from Quad 2 READ_EFFECT { OPITFPRd.pcb_intr_type_F_pending_0=0; } // clear appropriate pending bit
12:15	ROX	ROX		OCB_OCI_OPITFSVRR_PCB_INTR_PAYLOAD_QUAD_3: Type F PCB Interrupt packet content(20:23) from Quad 3 READ_EFFECT { OPITFPRd.pcb_intr_type_F_pending_0=0; } // clear appropriate pending bit
16:19	ROX	ROX		OCB_OCI_OPITFSVRR_PCB_INTR_PAYLOAD_QUAD_4: Type F PCB Interrupt packet content(20:23) from Quad 4 READ_EFFECT { OPITFPRd.pcb_intr_type_F_pending_0=0; } // clear appropriate pending bit
20:23	ROX	ROX		OCB_OCI_OPITFSVRR_PCB_INTR_PAYLOAD_QUAD_5: Type F PCB Interrupt packet content(20:23) from Quad 5 READ_EFFECT { OPITFPRd.pcb_intr_type_F_pending_0=0; } // clear appropriate pending bit
24:27	ROX	ROX		OCB_OCI_OPITFSVRR_PCB_INTR_PAYLOAD_QUAD_6: Type F PCB Interrupt packet content(20:23) from Quad 6 READ_EFFECT { OPITFPRd.pcb_intr_type_F_pending_0=0; } // clear appropriate pending bit
28:31	ROX	ROX		OCB_OCI_OPITFSVRR_PCB_INTR_PAYLOAD_QUAD_7: Type F PCB Interrupt packet content(20:23) from Quad 7 READ_EFFECT { OPITFPRd.pcb_intr_type_F_pending_0=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 0 QME 0 Reset Register
Addr:	000000000006C500 (SCOM) 00000000C0062800 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q0RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT0Q0RR_PCB_INTR_PAYLOAD: Type 0 PCB interrupt packet content from QME 0 READ_EFFECT { OPIT0PRa.pcb_intr_type_0_pending_0=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 0 QME 1 Reset Register
Addr:	000000000006C501 (SCOM) 00000000C0062808 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q1RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT1PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT1PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT0Q1RR_PCB_INTR_PAYLOAD: Type 0 PCB interrupt packet content from QME 1 READ_EFFECT { OPIT0PRa.pcb_intr_type_0_pending_1=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 0 QME 2 Reset Register
Addr:	000000000006C502 (SCOM) 00000000C0062810 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q2RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT2PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT2PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT0Q2RR_PCB_INTR_PAYLOAD: Type 0 PCB interrupt packet content from QME 2 READ_EFFECT { OPIT0PRa.pcb_intr_type_0_pending_2=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 0 QME 3 Reset Register
Addr:	000000000006C503 (SCOM) 00000000C0062818 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q3RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT3PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT3PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT0Q3RR_PCB_INTR_PAYLOAD: Type 0 PCB interrupt packet content from QME 3 READ_EFFECT { OPIT0PRa.pcb_intr_type_0_pending_3=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 0 QME 4 Reset Register
Addr:	000000000006C504 (SCOM) 00000000C0062820 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q4RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT4PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT4PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT0Q4RR_PCB_INTR_PAYLOAD: Type 0 PCB interrupt packet content from QME 4 READ_EFFECT { OPIT0PRa.pcb_intr_type_0_pending_4=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 0 QME 5 Reset Register
Addr:	000000000006C505 (SCOM) 00000000C0062828 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q5RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT5PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT5PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT0Q5RR_PCB_INTR_PAYLOAD: Type 0 PCB interrupt packet content from QME 5 READ_EFFECT { OPIT0PRa.pcb_intr_type_0_pending_5=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 0 QME 6 Reset Register
Addr:	000000000006C506 (SCOM) 00000000C0062830 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q6RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT6PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT6PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT0Q6RR_PCB_INTR_PAYLOAD: Type 0 PCB interrupt packet content from QME 6 READ_EFFECT { OPIT0PRa.pcb_intr_type_0_pending_6=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 0 QME 7 Reset Register
Addr:	000000000006C507 (SCOM) 00000000C0062838 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q7RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT7PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT7PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT0Q7RR_PCB_INTR_PAYLOAD: Type 0 PCB interrupt packet content from QME 7 READ_EFFECT { OPIT0PRa.pcb_intr_type_0_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 1 QME 0 Reset Register
Addr:	000000000006C508 (SCOM) 00000000C0062840 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q0RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT1Q0RR_PCB_INTR_PAYLOAD: Type 1 PCB interrupt packet content from QME 0 READ_EFFECT { OPIT1PRa.pcb_intr_type_1_pending_0=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 1 QME 1 Reset Register
Addr:	000000000006C509 (SCOM) 00000000C0062848 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q1RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT1PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT1PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT1Q1RR_PCB_INTR_PAYLOAD: Type 1 PCB interrupt packet content from QME 1 READ_EFFECT { OPIT1PRa.pcb_intr_type_1_pending_1=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 1 QME 2 Reset Register
Addr:	000000000006C50A (SCOM) 00000000C0062850 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q2RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT2PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT2PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT1Q2RR_PCB_INTR_PAYLOAD: Type 1 PCB interrupt packet content from QME 2 READ_EFFECT { OPIT1PRa.pcb_intr_type_1_pending_2=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 1 QME 3 Reset Register
Addr:	000000000006C50B (SCOM) 00000000C0062858 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q3RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT3PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT3PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT1Q3RR_PCB_INTR_PAYLOAD: Type 1 PCB interrupt packet content from QME 3 READ_EFFECT { OPIT1PRa.pcb_intr_type_1_pending_3=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 1 QME 4 Reset Register
Addr:	000000000006C50C (SCOM) 00000000C0062860 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q4RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT4PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT4PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT1Q4RR_PCB_INTR_PAYLOAD: Type 1 PCB interrupt packet content from QME 4 READ_EFFECT { OPIT1PRa.pcb_intr_type_1_pending_4=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 1 QME 5 Reset Register
Addr:	000000000006C50D (SCOM) 00000000C0062868 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q5RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT5PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT5PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT1Q5RR_PCB_INTR_PAYLOAD: Type 1 PCB interrupt packet content from QME 5 READ_EFFECT { OPIT1PRa.pcb_intr_type_1_pending_5=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 1 QME 6 Reset Register
Addr:	000000000006C50E (SCOM) 00000000C0062870 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q6RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT6PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT6PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT1Q6RR_PCB_INTR_PAYLOAD: Type 1 PCB interrupt packet content from QME 6 READ_EFFECT { OPIT1PRa.pcb_intr_type_1_pending_6=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 1 QME 7 Reset Register
Addr:	000000000006C50F (SCOM) 00000000C0062878 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q7RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT7PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT7PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT1Q7RR_PCB_INTR_PAYLOAD: Type 1 PCB interrupt packet content from QME 7 READ_EFFECT { OPIT1PRa.pcb_intr_type_1_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 2 QME 0 Reset Register
Addr:	000000000006C510 (SCOM) 00000000C0062880 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q0RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT2Q0RR_PCB_INTR_PAYLOAD: Type 2 PCB interrupt packet content from QME 0 READ_EFFECT { OPIT2PRa.pcb_intr_type_2_pending_0=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 2 QME 1 Reset Register
Addr:	000000000006C511 (SCOM) 00000000C0062888 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q1RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT1PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT1PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT2Q1RR_PCB_INTR_PAYLOAD: Type 2 PCB interrupt packet content from QME 1 READ_EFFECT { OPIT2PRa.pcb_intr_type_2_pending_1=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 2 QME 2 Reset Register
Addr:	000000000006C512 (SCOM) 00000000C0062890 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q2RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT2PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT2PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT2Q2RR_PCB_INTR_PAYLOAD: Type 2 PCB interrupt packet content from QME 2 READ_EFFECT { OPIT2PRa.pcb_intr_type_2_pending_2=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 2 QME 3 Reset Register
Addr:	000000000006C513 (SCOM) 00000000C0062898 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q3RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT3PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT3PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT2Q3RR_PCB_INTR_PAYLOAD: Type 2 PCB interrupt packet content from QME 3 READ_EFFECT { OPIT2PRa.pcb_intr_type_2_pending_3=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 2 QME 4 Reset Register
Addr:	000000000006C514 (SCOM) 00000000C00628A0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q4RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT4PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT4PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT2Q4RR_PCB_INTR_PAYLOAD: Type 2 PCB interrupt packet content from QME 4 READ_EFFECT { OPIT2PRa.pcb_intr_type_2_pending_4=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 2 QME 5 Reset Register
Addr:	000000000006C515 (SCOM) 00000000C00628A8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q5RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT5PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT5PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT2Q5RR_PCB_INTR_PAYLOAD: Type 2 PCB interrupt packet content from QME 5 READ_EFFECT { OPIT2PRa.pcb_intr_type_2_pending_5=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 2 QME 6 Reset Register
Addr:	000000000006C516 (SCOM) 00000000C00628B0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q6RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT6PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT6PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT2Q6RR_PCB_INTR_PAYLOAD: Type 2 PCB interrupt packet content from QME 6 READ_EFFECT { OPIT2PRa.pcb_intr_type_2_pending_6=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 2 QME 7 Reset Register
Addr:	000000000006C517 (SCOM) 00000000C00628B8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q7RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT7PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT7PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT2Q7RR_PCB_INTR_PAYLOAD: Type 2 PCB interrupt packet content from QME 7 READ_EFFECT { OPIT2PRa.pcb_intr_type_2_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 3 QME 0 Reset Register
Addr:	000000000006C518 (SCOM) 00000000C00628C0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q0RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT3Q0RR_PCB_INTR_PAYLOAD: Type 3 PCB interrupt packet content from QME 0 READ_EFFECT { OPIT3PRa.pcb_intr_type_3_pending_0=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 3 QME 1 Reset Register
Addr:	000000000006C519 (SCOM) 00000000C00628C8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q1RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT1PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT1PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT3Q1RR_PCB_INTR_PAYLOAD: Type 3 PCB interrupt packet content from QME 1 READ_EFFECT { OPIT3PRa.pcb_intr_type_3_pending_1=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 3 QME 2 Reset Register
Addr:	000000000006C51A (SCOM) 00000000C00628D0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q2RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT2PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT2PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT3Q2RR_PCB_INTR_PAYLOAD: Type 3 PCB interrupt packet content from QME 2 READ_EFFECT { OPIT3PRa.pcb_intr_type_3_pending_2=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 3 QME 3 Reset Register
Addr:	000000000006C51B (SCOM) 00000000C00628D8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q3RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT3PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT3PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT3Q3RR_PCB_INTR_PAYLOAD: Type 3 PCB interrupt packet content from QME 3 READ_EFFECT { OPIT3PRa.pcb_intr_type_3_pending_3=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 3 QME 4 Reset Register
Addr:	000000000006C51C (SCOM) 00000000C00628E0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q4RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT4PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT4PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT3Q4RR_PCB_INTR_PAYLOAD: Type 3 PCB interrupt packet content from QME 4 READ_EFFECT { OPIT3PRa.pcb_intr_type_3_pending_4=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 3 QME 5 Reset Register
Addr:	000000000006C51D (SCOM) 00000000C00628E8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q5RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT5PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT5PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT3Q5RR_PCB_INTR_PAYLOAD: Type 3 PCB interrupt packet content from QME 5 READ_EFFECT { OPIT3PRa.pcb_intr_type_3_pending_5=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 3 QME 6 Reset Register
Addr:	000000000006C51E (SCOM) 00000000C00628F0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q6RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT6PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT6PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT3Q6RR_PCB_INTR_PAYLOAD: Type 3 PCB interrupt packet content from QME 6 READ_EFFECT { OPIT3PRa.pcb_intr_type_3_pending_6=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 3 QME 7 Reset Register
Addr:	000000000006C51F (SCOM) 00000000C00628F8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q7RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT7PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT7PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT3Q7RR_PCB_INTR_PAYLOAD: Type 3 PCB interrupt packet content from QME 7 READ_EFFECT { OPIT3PRa.pcb_intr_type_3_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 4 QME 0 Reset Register
Addr:	000000000006C520 (SCOM) 00000000C0062900 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q0RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT4Q0RR_PCB_INTR_PAYLOAD: Type 4 PCB interrupt packet content from QME 0 READ_EFFECT { OPIT4PRa.pcb_intr_type_4_pending_0=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 4 QME 1 Reset Register
Addr:	000000000006C521 (SCOM) 00000000C0062908 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q1RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT1PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT1PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT4Q1RR_PCB_INTR_PAYLOAD: Type 4 PCB interrupt packet content from QME 1 READ_EFFECT { OPIT4PRa.pcb_intr_type_4_pending_1=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 4 QME 2 Reset Register
Addr:	000000000006C522 (SCOM) 00000000C0062910 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q2RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT2PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT2PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT4Q2RR_PCB_INTR_PAYLOAD: Type 4 PCB interrupt packet content from QME 2 READ_EFFECT { OPIT4PRa.pcb_intr_type_4_pending_2=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 4 QME 3 Reset Register
Addr:	000000000006C523 (SCOM) 00000000C0062918 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q3RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT3PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT3PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT4Q3RR_PCB_INTR_PAYLOAD: Type 4 PCB interrupt packet content from QME 3 READ_EFFECT { OPIT4PRa.pcb_intr_type_4_pending_3=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 4 QME 4 Reset Register
Addr:	000000000006C524 (SCOM) 00000000C0062920 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q4RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT4PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT4PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT4Q4RR_PCB_INTR_PAYLOAD: Type 4 PCB interrupt packet content from QME 4 READ_EFFECT { OPIT4PRa.pcb_intr_type_4_pending_4=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 4 QME 5 Reset Register
Addr:	000000000006C525 (SCOM) 00000000C0062928 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q5RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT5PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT5PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT4Q5RR_PCB_INTR_PAYLOAD: Type 4 PCB interrupt packet content from QME 5 READ_EFFECT { OPIT4PRa.pcb_intr_type_4_pending_5=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 4 QME 6 Reset Register
Addr:	000000000006C526 (SCOM) 00000000C0062930 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q6RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT6PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT6PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT4Q6RR_PCB_INTR_PAYLOAD: Type 4 PCB interrupt packet content from QME 6 READ_EFFECT { OPIT4PRa.pcb_intr_type_4_pending_6=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 4 QME 7 Reset Register
Addr:	000000000006C527 (SCOM) 00000000C0062938 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q7RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT7PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT7PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT4Q7RR_PCB_INTR_PAYLOAD: Type 4 PCB interrupt packet content from QME 7 READ_EFFECT { OPIT4PRa.pcb_intr_type_4_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 5 QME 0 Reset Register
Addr:	000000000006C528 (SCOM) 00000000C0062940 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q0RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT5Q0RR_PCB_INTR_PAYLOAD: Type 5 PCB interrupt packet content from QME 0 READ_EFFECT { OPIT5PRa.pcb_intr_type_5_pending_0=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 5 QME 1 Reset Register
Addr:	000000000006C529 (SCOM) 00000000C0062948 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q1RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT1PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT1PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT5Q1RR_PCB_INTR_PAYLOAD: Type 5 PCB interrupt packet content from QME 1 READ_EFFECT { OPIT5PRa.pcb_intr_type_5_pending_1=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 5 QME 2 Reset Register
Addr:	000000000006C52A (SCOM) 00000000C0062950 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q2RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT2PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT2PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT5Q2RR_PCB_INTR_PAYLOAD: Type 5 PCB interrupt packet content from QME 2 READ_EFFECT { OPIT5PRa.pcb_intr_type_5_pending_2=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 5 QME 3 Reset Register
Addr:	000000000006C52B (SCOM) 00000000C0062958 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q3RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT3PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT3PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT5Q3RR_PCB_INTR_PAYLOAD: Type 5 PCB interrupt packet content from QME 3 READ_EFFECT { OPIT5PRa.pcb_intr_type_5_pending_3=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 5 QME 4 Reset Register
Addr:	000000000006C52C (SCOM) 00000000C0062960 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q4RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT4PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT4PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT5Q4RR_PCB_INTR_PAYLOAD: Type 5 PCB interrupt packet content from QME 4 READ_EFFECT { OPIT5PRa.pcb_intr_type_5_pending_4=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 5 QME 5 Reset Register
Addr:	000000000006C52D (SCOM) 00000000C0062968 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q5RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT5PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT5PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT5Q5RR_PCB_INTR_PAYLOAD: Type 5 PCB interrupt packet content from QME 5 READ_EFFECT { OPIT5PRa.pcb_intr_type_5_pending_5=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 5 QME 6 Reset Register
Addr:	000000000006C52E (SCOM) 00000000C0062970 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q6RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT6PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT6PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT5Q6RR_PCB_INTR_PAYLOAD: Type 5 PCB interrupt packet content from QME 6 READ_EFFECT { OPIT5PRa.pcb_intr_type_5_pending_6=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 5 QME 7 Reset Register
Addr:	000000000006C52F (SCOM) 00000000C0062978 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q7RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT7PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT7PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT5Q7RR_PCB_INTR_PAYLOAD: Type 5 PCB interrupt packet content from QME 7 READ_EFFECT { OPIT5PRa.pcb_intr_type_5_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 6 QME 0 Reset Register
Addr:	000000000006C530 (SCOM) 00000000C0062980 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q0RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT6Q0RR_PCB_INTR_PAYLOAD: Type 6 PCB interrupt packet content from QME 0 READ_EFFECT { OPIT6PRa.pcb_intr_type_6_pending_0=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 6 QME 1 Reset Register
Addr:	000000000006C531 (SCOM) 00000000C0062988 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q1RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT1PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT1PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT6Q1RR_PCB_INTR_PAYLOAD: Type 6 PCB interrupt packet content from QME 1 READ_EFFECT { OPIT6PRa.pcb_intr_type_6_pending_1=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 6 QME 2 Reset Register
Addr:	000000000006C532 (SCOM) 00000000C0062990 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q2RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT2PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT2PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT6Q2RR_PCB_INTR_PAYLOAD: Type 6 PCB interrupt packet content from QME 2 READ_EFFECT { OPIT6PRa.pcb_intr_type_6_pending_2=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 6 QME 3 Reset Register
Addr:	000000000006C533 (SCOM) 00000000C0062998 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q3RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT3PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT3PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT6Q3RR_PCB_INTR_PAYLOAD: Type 6 PCB interrupt packet content from QME 3 READ_EFFECT { OPIT6PRa.pcb_intr_type_6_pending_3=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 6 QME 4 Reset Register
Addr:	000000000006C534 (SCOM) 00000000C00629A0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q4RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT4PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT4PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT6Q4RR_PCB_INTR_PAYLOAD: Type 6 PCB interrupt packet content from QME 4 READ_EFFECT { OPIT6PRa.pcb_intr_type_6_pending_4=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 6 QME 5 Reset Register
Addr:	000000000006C535 (SCOM) 00000000C00629A8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q5RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT5PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT5PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT6Q5RR_PCB_INTR_PAYLOAD: Type 6 PCB interrupt packet content from QME 5 READ_EFFECT { OPIT6PRa.pcb_intr_type_6_pending_5=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 6 QME 6 Reset Register
Addr:	000000000006C536 (SCOM) 00000000C00629B0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q6RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT6PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT6PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT6Q6RR_PCB_INTR_PAYLOAD: Type 6 PCB interrupt packet content from QME 6 READ_EFFECT { OPIT6PRa.pcb_intr_type_6_pending_6=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 6 QME 7 Reset Register
Addr:	000000000006C537 (SCOM) 00000000C00629B8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q7RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT7PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT7PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT6Q7RR_PCB_INTR_PAYLOAD: Type 6 PCB interrupt packet content from QME 7 READ_EFFECT { OPIT6PRa.pcb_intr_type_6_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 7 QME 0 Reset Register
Addr:	000000000006C538 (SCOM) 00000000C00629C0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q0RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT0PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT7Q0RR_PCB_INTR_PAYLOAD: Type 7 PCB interrupt packet content from QME 0 READ_EFFECT { OPIT7PRa.pcb_intr_type_7_pending_0=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 7 QME 1 Reset Register
Addr:	000000000006C539 (SCOM) 00000000C00629C8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q1RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT1PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT1PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT7Q1RR_PCB_INTR_PAYLOAD: Type 7 PCB interrupt packet content from QME 1 READ_EFFECT { OPIT7PRa.pcb_intr_type_7_pending_1=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 7 QME 2 Reset Register
Addr:	000000000006C53A (SCOM) 00000000C00629D0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q2RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT2PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT2PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT7Q2RR_PCB_INTR_PAYLOAD: Type 7 PCB interrupt packet content from QME 2 READ_EFFECT { OPIT7PRa.pcb_intr_type_7_pending_2=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 7 QME 3 Reset Register
Addr:	000000000006C53B (SCOM) 00000000C00629D8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q3RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT3PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT3PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT7Q3RR_PCB_INTR_PAYLOAD: Type 7 PCB interrupt packet content from QME 3 READ_EFFECT { OPIT7PRa.pcb_intr_type_7_pending_3=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 7 QME 4 Reset Register
Addr:	000000000006C53C (SCOM) 00000000C00629E0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q4RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT4PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT4PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT7Q4RR_PCB_INTR_PAYLOAD: Type 7 PCB interrupt packet content from QME 4 READ_EFFECT { OPIT7PRa.pcb_intr_type_7_pending_4=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 7 QME 5 Reset Register
Addr:	000000000006C53D (SCOM) 00000000C00629E8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q5RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT5PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT5PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT7Q5RR_PCB_INTR_PAYLOAD: Type 7 PCB interrupt packet content from QME 5 READ_EFFECT { OPIT7PRa.pcb_intr_type_7_pending_5=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 7 QME 6 Reset Register
Addr:	000000000006C53E (SCOM) 00000000C00629F0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q6RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT6PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT6PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT7Q6RR_PCB_INTR_PAYLOAD: Type 7 PCB interrupt packet content from QME 6 READ_EFFECT { OPIT7PRa.pcb_intr_type_7_pending_6=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 7 QME 7 Reset Register
Addr:	000000000006C53F (SCOM) 00000000C00629F8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q7RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from QME 0. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT7PR. Note that Type 0:7 interrupts always overwrite the payload in this register to capture the most recent. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT7PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:31	ROX	ROX		OCB_OCI_OPIT7Q7RR_PCB_INTR_PAYLOAD: Type 7 PCB interrupt packet content from QME 7 READ_EFFECT { OPIT7PRa.pcb_intr_type_7_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 0 Reset Register
Addr:	000000000006C540 (SCOM) 00000000C0062A00 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C0RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT0PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C0RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C0RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 0 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_0=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 1 Reset Register
Addr:	000000000006C541 (SCOM) 00000000C0062A08 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C1RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 1 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 1 pending bit in OPIT1PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT1PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C1RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C1RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 1 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_1=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 2 Reset Register
Addr:	000000000006C542 (SCOM) 00000000C0062A10 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C2RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 2 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 2 pending bit in OPIT2PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT2PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C2RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C2RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 2 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_2=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 3 Reset Register
Addr:	000000000006C543 (SCOM) 00000000C0062A18 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C3RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 3 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 3 pending bit in OPIT3PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT3PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C3RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C3RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 3 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_3=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 4 Reset Register
Addr:	000000000006C544 (SCOM) 00000000C0062A20 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C4RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 4 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 4 pending bit in OPIT4PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT4PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C4RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C4RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 4 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_4=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 5 Reset Register
Addr:	000000000006C545 (SCOM) 00000000C0062A28 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C5RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 5 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 5 pending bit in OPIT5PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT5PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C5RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C5RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 5 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_5=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 6 Reset Register
Addr:	000000000006C546 (SCOM) 00000000C0062A30 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C6RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 6 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 6 pending bit in OPIT6PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT6PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C6RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C6RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 6 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_6=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 7 Reset Register
Addr:	000000000006C547 (SCOM) 00000000C0062A38 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C7RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 7 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 7 pending bit in OPIT7PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT7PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C7RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C7RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 7 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 8 Reset Register
Addr:	000000000006C548 (SCOM) 00000000C0062A40 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C8RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 8 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 8 pending bit in OPIT8PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT8PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C8RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C8RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 8 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_8=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 9 Reset Register
Addr:	000000000006C549 (SCOM) 00000000C0062A48 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C9RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 9 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 9 pending bit in OPIT9PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT9PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C9RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C9RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 9 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_9=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 10 Reset Register
Addr:	000000000006C54A (SCOM) 00000000C0062A50 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C10RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 10 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 10 pending bit in OPIT10PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT10PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C10RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C10RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 10 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_10=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 11 Reset Register
Addr:	000000000006C54B (SCOM) 00000000C0062A58 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C11RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 11 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 11 pending bit in OPIT11PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT11PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C11RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C11RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 11 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_11=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 12 Reset Register
Addr:	000000000006C54C (SCOM) 00000000C0062A60 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C12RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 12 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 12 pending bit in OPIT12PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT12PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C12RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C12RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 12 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_12=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 13 Reset Register
Addr:	000000000006C54D (SCOM) 00000000C0062A68 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C13RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 13 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 13 pending bit in OPIT13PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT13PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C13RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C13RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 13 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_13=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 14 Reset Register
Addr:	000000000006C54E (SCOM) 00000000C0062A70 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C14RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 14 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 14 pending bit in OPIT14PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT14PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C14RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C14RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 14 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_14=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 15 Reset Register
Addr:	000000000006C54F (SCOM) 00000000C0062A78 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C15RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 15 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 15 pending bit in OPIT15PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT15PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C15RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C15RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 15 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_15=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 16 Reset Register
Addr:	000000000006C550 (SCOM) 00000000C0062A80 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C16RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 16 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 16 pending bit in OPIT16PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT16PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C16RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C16RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 16 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_16=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 17 Reset Register
Addr:	000000000006C551 (SCOM) 00000000C0062A88 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C17RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 17 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 17 pending bit in OPIT17PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT17PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C17RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C17RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 17 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_17=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 18 Reset Register
Addr:	000000000006C552 (SCOM) 00000000C0062A90 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C18RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 18 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 18 pending bit in OPIT18PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT18PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C18RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C18RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 18 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_18=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 19 Reset Register
Addr:	000000000006C553 (SCOM) 00000000C0062A98 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C19RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 19 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 19 pending bit in OPIT19PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT19PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C19RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C19RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 19 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_19=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 20 Reset Register
Addr:	000000000006C554 (SCOM) 00000000C0062AA0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C20RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 20 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 20 pending bit in OPIT20PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT20PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C20RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C20RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 20 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_20=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 21 Reset Register
Addr:	000000000006C555 (SCOM) 00000000C0062AA8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C21RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 21 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 21 pending bit in OPIT21PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT21PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C21RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C21RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 21 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_21=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 22 Reset Register
Addr:	000000000006C556 (SCOM) 00000000C0062AB0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C22RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 22 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 22 pending bit in OPIT22PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT22PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C22RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C22RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 22 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_22=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 23 Reset Register
Addr:	000000000006C557 (SCOM) 00000000C0062AB8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C23RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 23 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 23 pending bit in OPIT23PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT23PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C23RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C23RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 23 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_23=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 24 Reset Register
Addr:	000000000006C558 (SCOM) 00000000C0062AC0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C24RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 24 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 24 pending bit in OPIT24PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT24PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C24RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C24RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 24 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_24=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 25 Reset Register
Addr:	000000000006C559 (SCOM) 00000000C0062AC8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C25RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 25 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 25 pending bit in OPIT25PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT25PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C25RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C25RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 25 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_25=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 26 Reset Register
Addr:	000000000006C55A (SCOM) 00000000C0062AD0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C26RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 26 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 26 pending bit in OPIT26PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT26PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C26RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C26RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 26 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_26=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 27 Reset Register
Addr:	000000000006C55B (SCOM) 00000000C0062AD8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C27RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 27 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 27 pending bit in OPIT27PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT27PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C27RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C27RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 27 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_27=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 28 Reset Register
Addr:	000000000006C55C (SCOM) 00000000C0062AE0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C28RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 28 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 28 pending bit in OPIT28PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT28PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C28RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C28RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 28 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_28=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 29 Reset Register
Addr:	000000000006C55D (SCOM) 00000000C0062AE8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C29RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 29 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 29 pending bit in OPIT29PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT29PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C29RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C29RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 29 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_29=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 30 Reset Register
Addr:	000000000006C55E (SCOM) 00000000C0062AF0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C30RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 30 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 30 pending bit in OPIT30PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT30PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C30RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C30RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 30 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_30=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 8 Core 31 Reset Register
Addr:	000000000006C55F (SCOM) 00000000C0062AF8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C31RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 31 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 31 pending bit in OPIT31PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT31PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT8C31RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT8C31RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 31 READ_EFFECT { OPIT8PRb.pcb_intr_type_8_pending_31=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 0 Reset Register
Addr:	000000000006C560 (SCOM) 00000000C0062B00 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C0RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 0 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 0 pending bit in OPIT0PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT0PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C0RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C0RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 0 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_0=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 1 Reset Register
Addr:	000000000006C561 (SCOM) 00000000C0062B08 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C1RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 1 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 1 pending bit in OPIT1PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT1PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C1RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C1RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 1 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_1=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 2 Reset Register
Addr:	000000000006C562 (SCOM) 00000000C0062B10 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C2RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 2 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 2 pending bit in OPIT2PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT2PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C2RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C2RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 2 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_2=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 3 Reset Register
Addr:	000000000006C563 (SCOM) 00000000C0062B18 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C3RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 3 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 3 pending bit in OPIT3PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT3PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C3RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C3RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 3 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_3=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 4 Reset Register
Addr:	000000000006C564 (SCOM) 00000000C0062B20 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C4RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 4 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 4 pending bit in OPIT4PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT4PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C4RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C4RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 4 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_4=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 5 Reset Register
Addr:	000000000006C565 (SCOM) 00000000C0062B28 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C5RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 5 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 5 pending bit in OPIT5PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT5PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C5RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C5RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 5 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_5=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 6 Reset Register
Addr:	000000000006C566 (SCOM) 00000000C0062B30 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C6RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 6 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 6 pending bit in OPIT6PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT6PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C6RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C6RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 6 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_6=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 7 Reset Register
Addr:	000000000006C567 (SCOM) 00000000C0062B38 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C7RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 7 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 7 pending bit in OPIT7PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT7PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C7RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C7RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 7 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 8 Reset Register
Addr:	000000000006C568 (SCOM) 00000000C0062B40 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C8RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 8 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 8 pending bit in OPIT8PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT8PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C8RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C8RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 8 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_8=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 9 Reset Register
Addr:	000000000006C569 (SCOM) 00000000C0062B48 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C9RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 9 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 9 pending bit in OPIT9PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT9PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C9RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C9RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 9 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_9=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 10 Reset Register
Addr:	000000000006C56A (SCOM) 00000000C0062B50 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C10RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 10 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 10 pending bit in OPIT10PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT10PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C10RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C10RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 10 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_10=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 11 Reset Register
Addr:	000000000006C56B (SCOM) 00000000C0062B58 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C11RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 11 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 11 pending bit in OPIT11PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT11PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C11RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C11RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 11 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_11=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 12 Reset Register
Addr:	000000000006C56C (SCOM) 00000000C0062B60 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C12RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 12 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 12 pending bit in OPIT12PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT12PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C12RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C12RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 12 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_12=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 13 Reset Register
Addr:	000000000006C56D (SCOM) 00000000C0062B68 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C13RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 13 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 13 pending bit in OPIT13PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT13PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C13RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C13RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 13 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_13=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 14 Reset Register
Addr:	000000000006C56E (SCOM) 00000000C0062B70 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C14RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 14 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 14 pending bit in OPIT14PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT14PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C14RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C14RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 14 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_14=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 15 Reset Register
Addr:	000000000006C56F (SCOM) 00000000C0062B78 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C15RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 15 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 15 pending bit in OPIT15PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT15PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C15RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C15RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 15 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_15=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 16 Reset Register
Addr:	000000000006C570 (SCOM) 00000000C0062B80 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C16RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 16 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 16 pending bit in OPIT16PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT16PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C16RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C16RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 16 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_16=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 17 Reset Register
Addr:	000000000006C571 (SCOM) 00000000C0062B88 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C17RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 17 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 17 pending bit in OPIT17PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT17PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C17RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C17RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 17 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_17=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 18 Reset Register
Addr:	000000000006C572 (SCOM) 00000000C0062B90 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C18RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 18 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 18 pending bit in OPIT18PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT18PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C18RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C18RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 18 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_18=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 19 Reset Register
Addr:	000000000006C573 (SCOM) 00000000C0062B98 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C19RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 19 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 19 pending bit in OPIT19PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT19PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C19RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C19RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 19 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_19=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 20 Reset Register
Addr:	000000000006C574 (SCOM) 00000000C0062BA0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C20RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 20 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 20 pending bit in OPIT20PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT20PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C20RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C20RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 20 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_20=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 21 Reset Register
Addr:	000000000006C575 (SCOM) 00000000C0062BA8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C21RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 21 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 21 pending bit in OPIT21PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT21PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C21RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C21RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 21 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_21=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 22 Reset Register
Addr:	000000000006C576 (SCOM) 00000000C0062BB0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C22RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 22 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 22 pending bit in OPIT22PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT22PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C22RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C22RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 22 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_22=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 23 Reset Register
Addr:	000000000006C577 (SCOM) 00000000C0062BB8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C23RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 23 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 23 pending bit in OPIT23PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT23PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C23RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C23RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 23 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_23=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 24 Reset Register
Addr:	000000000006C578 (SCOM) 00000000C0062BC0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C24RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 24 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 24 pending bit in OPIT24PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT24PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C24RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C24RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 24 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_24=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 25 Reset Register
Addr:	000000000006C579 (SCOM) 00000000C0062BC8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C25RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 25 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 25 pending bit in OPIT25PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT25PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C25RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C25RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 25 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_25=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 26 Reset Register
Addr:	000000000006C57A (SCOM) 00000000C0062BD0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C26RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 26 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 26 pending bit in OPIT26PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT26PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C26RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C26RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 26 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_26=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 27 Reset Register
Addr:	000000000006C57B (SCOM) 00000000C0062BD8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C27RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 27 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 27 pending bit in OPIT27PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT27PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C27RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C27RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 27 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_27=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 28 Reset Register
Addr:	000000000006C57C (SCOM) 00000000C0062BE0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C28RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 28 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 28 pending bit in OPIT28PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT28PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C28RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C28RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 28 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_28=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 29 Reset Register
Addr:	000000000006C57D (SCOM) 00000000C0062BE8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C29RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 29 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 29 pending bit in OPIT29PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT29PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C29RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C29RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 29 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_29=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 30 Reset Register
Addr:	000000000006C57E (SCOM) 00000000C0062BF0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C30RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 30 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 30 pending bit in OPIT30PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT30PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C30RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C30RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 30 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_30=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type 9 Core 31 Reset Register
Addr:	000000000006C57F (SCOM) 00000000C0062BF8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C31RR
Constant(s):
Comments:	This register gives access to the PCB Power Management Type 31 interrupt packet content received from Core 8. Receipt of such an interrupt packet causes the setting of the Type 31 pending bit in OPIT31PR. Note that Type 8-9 interrupts always overwrite the payload in this register to capture the most recent, regardless if one is already Pending. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPIT31PR, while reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM	OCI		Dial: Description
0:12	RO	RO		constant=0b0000000000000
13:14	ROX	ROX		OCB_OCI_OPIT9C31RR_PCB_INTR_SOURCE_CORE: Will contain the source core for debug information
15:31	ROX	ROX		OCB_OCI_OPIT9C31RR_PCB_INTR_PAYLOAD: Type [an] PCB interrupt packet content from Core 31 READ_EFFECT { OPIT9PRb.pcb_intr_type_9_pending_31=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type A Summary Vector 0 Reset Register
Addr:	000000000006C580 (SCOM) 00000000C0062C00 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITASV0RR
Constant(s):
Comments:	This register provides access to type A Summary Notification Vectors. Type A and Type B interrupts write 4 different bits across 4 Summary Vectors (16 bits total) into a position determined by the number of the QME sourcing the interrupt. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPITAPR. Reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts. Note: If the QME source is needed, first Read_CLEAR the pending register, then read this summary vector using a 0x04XX address. Then optionally read the pending vector (with or without clear) to see if any new interrupts arrived.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV0_Q_0_INST.LATC.L2(0:3) [0000]
	4:7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV0_Q_4_INST.LATC.L2(4:7) [0000]
	8:11	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV0_Q_8_INST.LATC.L2(8:11) [0000]
	12:15	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV0_Q_12_INST.LATC.L2(12:15) [0000]
	16:19	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV0_Q_16_INST.LATC.L2(16:19) [0000]
	20:23	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV0_Q_20_INST.LATC.L2(20:23) [0000]
	24:27	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV0_Q_24_INST.LATC.L2(24:27) [0000]
	28:31	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV0_Q_28_INST.LATC.L2(28:31) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0:3	ROX	ROX		OCB_OCI_OPITASV0RR_PCB_INTR_PAYLOAD_QUAD_0: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 0 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_0=0; } // clear appropriate pending bit
4:7	ROX	ROX		OCB_OCI_OPITASV0RR_PCB_INTR_PAYLOAD_QUAD_1: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 1 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_1=0; } // clear appropriate pending bit
8:11	ROX	ROX		OCB_OCI_OPITASV0RR_PCB_INTR_PAYLOAD_QUAD_2: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 2 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_2=0; } // clear appropriate pending bit
12:15	ROX	ROX		OCB_OCI_OPITASV0RR_PCB_INTR_PAYLOAD_QUAD_3: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 3 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_3=0; } // clear appropriate pending bit
16:19	ROX	ROX		OCB_OCI_OPITASV0RR_PCB_INTR_PAYLOAD_QUAD_4: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 4 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_4=0; } // clear appropriate pending bit
20:23	ROX	ROX		OCB_OCI_OPITASV0RR_PCB_INTR_PAYLOAD_QUAD_5: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 5 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_5=0; } // clear appropriate pending bit
24:27	ROX	ROX		OCB_OCI_OPITASV0RR_PCB_INTR_PAYLOAD_QUAD_6: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 6 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_6=0; } // clear appropriate pending bit
28:31	ROX	ROX		OCB_OCI_OPITASV0RR_PCB_INTR_PAYLOAD_QUAD_7: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 7 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type A Summary Vector 1 Reset Register
Addr:	000000000006C581 (SCOM) 00000000C0062C08 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITASV1RR
Constant(s):
Comments:	This register provides access to type A Summary Notification Vectors. Type A and Type B interrupts write 4 different bits across 4 Summary Vectors (16 bits total) into a position determined by the number of the QME sourcing the interrupt. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPITAPR. Reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts. Note: If the QME source is needed, first Read_CLEAR the pending register, then read this summary vector using a 0x04XX address. Then optionally read the pending vector (with or without clear) to see if any new interrupts arrived.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV1_Q_0_INST.LATC.L2(0:3) [0000]
	4:7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV1_Q_4_INST.LATC.L2(4:7) [0000]
	8:11	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV1_Q_8_INST.LATC.L2(8:11) [0000]
	12:15	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV1_Q_12_INST.LATC.L2(12:15) [0000]
	16:19	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV1_Q_16_INST.LATC.L2(16:19) [0000]
	20:23	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV1_Q_20_INST.LATC.L2(20:23) [0000]
	24:27	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV1_Q_24_INST.LATC.L2(24:27) [0000]
	28:31	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV1_Q_28_INST.LATC.L2(28:31) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0:3	ROX	ROX		OCB_OCI_OPITASV1RR_PCB_INTR_PAYLOAD_QUAD_0: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 0 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_0=0; } // clear appropriate pending bit
4:7	ROX	ROX		OCB_OCI_OPITASV1RR_PCB_INTR_PAYLOAD_QUAD_1: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 1 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_1=0; } // clear appropriate pending bit
8:11	ROX	ROX		OCB_OCI_OPITASV1RR_PCB_INTR_PAYLOAD_QUAD_2: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 2 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_2=0; } // clear appropriate pending bit
12:15	ROX	ROX		OCB_OCI_OPITASV1RR_PCB_INTR_PAYLOAD_QUAD_3: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 3 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_3=0; } // clear appropriate pending bit
16:19	ROX	ROX		OCB_OCI_OPITASV1RR_PCB_INTR_PAYLOAD_QUAD_4: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 4 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_4=0; } // clear appropriate pending bit
20:23	ROX	ROX		OCB_OCI_OPITASV1RR_PCB_INTR_PAYLOAD_QUAD_5: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 5 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_5=0; } // clear appropriate pending bit
24:27	ROX	ROX		OCB_OCI_OPITASV1RR_PCB_INTR_PAYLOAD_QUAD_6: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 6 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_6=0; } // clear appropriate pending bit
28:31	ROX	ROX		OCB_OCI_OPITASV1RR_PCB_INTR_PAYLOAD_QUAD_7: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 7 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type A Summary Vector 2 Reset Register
Addr:	000000000006C582 (SCOM) 00000000C0062C10 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITASV2RR
Constant(s):
Comments:	This register provides access to type A Summary Notification Vectors. Type A and Type B interrupts write 4 different bits across 4 Summary Vectors (16 bits total) into a position determined by the number of the QME sourcing the interrupt. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPITAPR. Reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts. Note: If the QME source is needed, first Read_CLEAR the pending register, then read this summary vector using a 0x04XX address. Then optionally read the pending vector (with or without clear) to see if any new interrupts arrived.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV2_Q_0_INST.LATC.L2(0:3) [0000]
	4:7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV2_Q_4_INST.LATC.L2(4:7) [0000]
	8:11	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV2_Q_8_INST.LATC.L2(8:11) [0000]
	12:15	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV2_Q_12_INST.LATC.L2(12:15) [0000]
	16:19	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV2_Q_16_INST.LATC.L2(16:19) [0000]
	20:23	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV2_Q_20_INST.LATC.L2(20:23) [0000]
	24:27	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV2_Q_24_INST.LATC.L2(24:27) [0000]
	28:31	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV2_Q_28_INST.LATC.L2(28:31) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0:3	ROX	ROX		OCB_OCI_OPITASV2RR_PCB_INTR_PAYLOAD_QUAD_0: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 0 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_0=0; } // clear appropriate pending bit
4:7	ROX	ROX		OCB_OCI_OPITASV2RR_PCB_INTR_PAYLOAD_QUAD_1: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 1 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_1=0; } // clear appropriate pending bit
8:11	ROX	ROX		OCB_OCI_OPITASV2RR_PCB_INTR_PAYLOAD_QUAD_2: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 2 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_2=0; } // clear appropriate pending bit
12:15	ROX	ROX		OCB_OCI_OPITASV2RR_PCB_INTR_PAYLOAD_QUAD_3: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 3 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_3=0; } // clear appropriate pending bit
16:19	ROX	ROX		OCB_OCI_OPITASV2RR_PCB_INTR_PAYLOAD_QUAD_4: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 4 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_4=0; } // clear appropriate pending bit
20:23	ROX	ROX		OCB_OCI_OPITASV2RR_PCB_INTR_PAYLOAD_QUAD_5: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 5 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_5=0; } // clear appropriate pending bit
24:27	ROX	ROX		OCB_OCI_OPITASV2RR_PCB_INTR_PAYLOAD_QUAD_6: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 6 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_6=0; } // clear appropriate pending bit
28:31	ROX	ROX		OCB_OCI_OPITASV2RR_PCB_INTR_PAYLOAD_QUAD_7: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 7 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type A Summary Vector 3 Reset Register
Addr:	000000000006C583 (SCOM) 00000000C0062C18 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITASV3RR
Constant(s):
Comments:	This register provides access to type A Summary Notification Vectors. Type A and Type B interrupts write 4 different bits across 4 Summary Vectors (16 bits total) into a position determined by the number of the QME sourcing the interrupt. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPITAPR. Reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts. Note: If the QME source is needed, first Read_CLEAR the pending register, then read this summary vector using a 0x04XX address. Then optionally read the pending vector (with or without clear) to see if any new interrupts arrived.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV3_Q_0_INST.LATC.L2(0:3) [0000]
	4:7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV3_Q_4_INST.LATC.L2(4:7) [0000]
	8:11	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV3_Q_8_INST.LATC.L2(8:11) [0000]
	12:15	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV3_Q_12_INST.LATC.L2(12:15) [0000]
	16:19	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV3_Q_16_INST.LATC.L2(16:19) [0000]
	20:23	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV3_Q_20_INST.LATC.L2(20:23) [0000]
	24:27	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV3_Q_24_INST.LATC.L2(24:27) [0000]
	28:31	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITASV3_Q_28_INST.LATC.L2(28:31) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0:3	ROX	ROX		OCB_OCI_OPITASV3RR_PCB_INTR_PAYLOAD_QUAD_0: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 0 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_0=0; } // clear appropriate pending bit
4:7	ROX	ROX		OCB_OCI_OPITASV3RR_PCB_INTR_PAYLOAD_QUAD_1: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 1 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_1=0; } // clear appropriate pending bit
8:11	ROX	ROX		OCB_OCI_OPITASV3RR_PCB_INTR_PAYLOAD_QUAD_2: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 2 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_2=0; } // clear appropriate pending bit
12:15	ROX	ROX		OCB_OCI_OPITASV3RR_PCB_INTR_PAYLOAD_QUAD_3: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 3 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_3=0; } // clear appropriate pending bit
16:19	ROX	ROX		OCB_OCI_OPITASV3RR_PCB_INTR_PAYLOAD_QUAD_4: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 4 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_4=0; } // clear appropriate pending bit
20:23	ROX	ROX		OCB_OCI_OPITASV3RR_PCB_INTR_PAYLOAD_QUAD_5: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 5 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_5=0; } // clear appropriate pending bit
24:27	ROX	ROX		OCB_OCI_OPITASV3RR_PCB_INTR_PAYLOAD_QUAD_6: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 6 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_6=0; } // clear appropriate pending bit
28:31	ROX	ROX		OCB_OCI_OPITASV3RR_PCB_INTR_PAYLOAD_QUAD_7: Type A PCB Interrupt packet content(8+a*4:11+a*4) from Quad 7 READ_EFFECT { OPITAPRc.pcb_intr_type_A_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type B Summary Vector 0 Reset Register
Addr:	000000000006C584 (SCOM) 00000000C0062C20 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBSV0RR
Constant(s):
Comments:	This register provides access to type A Summary Notification Vectors. Type A and Type B interrupts write 4 different bits across 4 Summary Vectors (16 bits total) into a position determined by the number of the QME sourcing the interrupt. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPITAPR. Reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts. Note: If the QME source is needed, first Read_CLEAR the pending register, then read this summary vector using a 0x04XX address. Then optionally read the pending vector (with or without clear) to see if any new interrupts arrived.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV0_Q_0_INST.LATC.L2(0:3) [0000]
	4:7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV0_Q_4_INST.LATC.L2(4:7) [0000]
	8:11	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV0_Q_8_INST.LATC.L2(8:11) [0000]
	12:15	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV0_Q_12_INST.LATC.L2(12:15) [0000]
	16:19	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV0_Q_16_INST.LATC.L2(16:19) [0000]
	20:23	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV0_Q_20_INST.LATC.L2(20:23) [0000]
	24:27	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV0_Q_24_INST.LATC.L2(24:27) [0000]
	28:31	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV0_Q_28_INST.LATC.L2(28:31) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0:3	ROX	ROX		OCB_OCI_OPITBSV0RR_PCB_INTR_PAYLOAD_QUAD_0: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 0 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_0=0; } // clear appropriate pending bit
4:7	ROX	ROX		OCB_OCI_OPITBSV0RR_PCB_INTR_PAYLOAD_QUAD_1: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 1 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_1=0; } // clear appropriate pending bit
8:11	ROX	ROX		OCB_OCI_OPITBSV0RR_PCB_INTR_PAYLOAD_QUAD_2: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 2 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_2=0; } // clear appropriate pending bit
12:15	ROX	ROX		OCB_OCI_OPITBSV0RR_PCB_INTR_PAYLOAD_QUAD_3: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 3 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_3=0; } // clear appropriate pending bit
16:19	ROX	ROX		OCB_OCI_OPITBSV0RR_PCB_INTR_PAYLOAD_QUAD_4: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 4 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_4=0; } // clear appropriate pending bit
20:23	ROX	ROX		OCB_OCI_OPITBSV0RR_PCB_INTR_PAYLOAD_QUAD_5: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 5 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_5=0; } // clear appropriate pending bit
24:27	ROX	ROX		OCB_OCI_OPITBSV0RR_PCB_INTR_PAYLOAD_QUAD_6: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 6 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_6=0; } // clear appropriate pending bit
28:31	ROX	ROX		OCB_OCI_OPITBSV0RR_PCB_INTR_PAYLOAD_QUAD_7: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 7 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type B Summary Vector 1 Reset Register
Addr:	000000000006C585 (SCOM) 00000000C0062C28 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBSV1RR
Constant(s):
Comments:	This register provides access to type A Summary Notification Vectors. Type A and Type B interrupts write 4 different bits across 4 Summary Vectors (16 bits total) into a position determined by the number of the QME sourcing the interrupt. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPITAPR. Reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts. Note: If the QME source is needed, first Read_CLEAR the pending register, then read this summary vector using a 0x04XX address. Then optionally read the pending vector (with or without clear) to see if any new interrupts arrived.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV1_Q_0_INST.LATC.L2(0:3) [0000]
	4:7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV1_Q_4_INST.LATC.L2(4:7) [0000]
	8:11	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV1_Q_8_INST.LATC.L2(8:11) [0000]
	12:15	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV1_Q_12_INST.LATC.L2(12:15) [0000]
	16:19	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV1_Q_16_INST.LATC.L2(16:19) [0000]
	20:23	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV1_Q_20_INST.LATC.L2(20:23) [0000]
	24:27	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV1_Q_24_INST.LATC.L2(24:27) [0000]
	28:31	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV1_Q_28_INST.LATC.L2(28:31) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0:3	ROX	ROX		OCB_OCI_OPITBSV1RR_PCB_INTR_PAYLOAD_QUAD_0: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 0 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_0=0; } // clear appropriate pending bit
4:7	ROX	ROX		OCB_OCI_OPITBSV1RR_PCB_INTR_PAYLOAD_QUAD_1: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 1 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_1=0; } // clear appropriate pending bit
8:11	ROX	ROX		OCB_OCI_OPITBSV1RR_PCB_INTR_PAYLOAD_QUAD_2: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 2 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_2=0; } // clear appropriate pending bit
12:15	ROX	ROX		OCB_OCI_OPITBSV1RR_PCB_INTR_PAYLOAD_QUAD_3: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 3 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_3=0; } // clear appropriate pending bit
16:19	ROX	ROX		OCB_OCI_OPITBSV1RR_PCB_INTR_PAYLOAD_QUAD_4: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 4 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_4=0; } // clear appropriate pending bit
20:23	ROX	ROX		OCB_OCI_OPITBSV1RR_PCB_INTR_PAYLOAD_QUAD_5: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 5 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_5=0; } // clear appropriate pending bit
24:27	ROX	ROX		OCB_OCI_OPITBSV1RR_PCB_INTR_PAYLOAD_QUAD_6: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 6 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_6=0; } // clear appropriate pending bit
28:31	ROX	ROX		OCB_OCI_OPITBSV1RR_PCB_INTR_PAYLOAD_QUAD_7: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 7 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type B Summary Vector 2 Reset Register
Addr:	000000000006C586 (SCOM) 00000000C0062C30 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBSV2RR
Constant(s):
Comments:	This register provides access to type A Summary Notification Vectors. Type A and Type B interrupts write 4 different bits across 4 Summary Vectors (16 bits total) into a position determined by the number of the QME sourcing the interrupt. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPITAPR. Reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts. Note: If the QME source is needed, first Read_CLEAR the pending register, then read this summary vector using a 0x04XX address. Then optionally read the pending vector (with or without clear) to see if any new interrupts arrived.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV2_Q_0_INST.LATC.L2(0:3) [0000]
	4:7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV2_Q_4_INST.LATC.L2(4:7) [0000]
	8:11	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV2_Q_8_INST.LATC.L2(8:11) [0000]
	12:15	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV2_Q_12_INST.LATC.L2(12:15) [0000]
	16:19	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV2_Q_16_INST.LATC.L2(16:19) [0000]
	20:23	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV2_Q_20_INST.LATC.L2(20:23) [0000]
	24:27	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV2_Q_24_INST.LATC.L2(24:27) [0000]
	28:31	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV2_Q_28_INST.LATC.L2(28:31) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0:3	ROX	ROX		OCB_OCI_OPITBSV2RR_PCB_INTR_PAYLOAD_QUAD_0: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 0 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_0=0; } // clear appropriate pending bit
4:7	ROX	ROX		OCB_OCI_OPITBSV2RR_PCB_INTR_PAYLOAD_QUAD_1: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 1 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_1=0; } // clear appropriate pending bit
8:11	ROX	ROX		OCB_OCI_OPITBSV2RR_PCB_INTR_PAYLOAD_QUAD_2: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 2 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_2=0; } // clear appropriate pending bit
12:15	ROX	ROX		OCB_OCI_OPITBSV2RR_PCB_INTR_PAYLOAD_QUAD_3: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 3 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_3=0; } // clear appropriate pending bit
16:19	ROX	ROX		OCB_OCI_OPITBSV2RR_PCB_INTR_PAYLOAD_QUAD_4: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 4 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_4=0; } // clear appropriate pending bit
20:23	ROX	ROX		OCB_OCI_OPITBSV2RR_PCB_INTR_PAYLOAD_QUAD_5: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 5 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_5=0; } // clear appropriate pending bit
24:27	ROX	ROX		OCB_OCI_OPITBSV2RR_PCB_INTR_PAYLOAD_QUAD_6: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 6 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_6=0; } // clear appropriate pending bit
28:31	ROX	ROX		OCB_OCI_OPITBSV2RR_PCB_INTR_PAYLOAD_QUAD_7: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 7 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC PCB Interrupt Type B Summary Vector 3 Reset Register
Addr:	000000000006C587 (SCOM) 00000000C0062C38 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBSV3RR
Constant(s):
Comments:	This register provides access to type A Summary Notification Vectors. Type A and Type B interrupts write 4 different bits across 4 Summary Vectors (16 bits total) into a position determined by the number of the QME sourcing the interrupt. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPITAPR. Reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts. Note: If the QME source is needed, first Read_CLEAR the pending register, then read this summary vector using a 0x04XX address. Then optionally read the pending vector (with or without clear) to see if any new interrupts arrived.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV3_Q_0_INST.LATC.L2(0:3) [0000]
	4:7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV3_Q_4_INST.LATC.L2(4:7) [0000]
	8:11	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV3_Q_8_INST.LATC.L2(8:11) [0000]
	12:15	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV3_Q_12_INST.LATC.L2(12:15) [0000]
	16:19	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV3_Q_16_INST.LATC.L2(16:19) [0000]
	20:23	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV3_Q_20_INST.LATC.L2(20:23) [0000]
	24:27	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV3_Q_24_INST.LATC.L2(24:27) [0000]
	28:31	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBSV3_Q_28_INST.LATC.L2(28:31) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0:3	ROX	ROX		OCB_OCI_OPITBSV3RR_PCB_INTR_PAYLOAD_QUAD_0: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 0 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_0=0; } // clear appropriate pending bit
4:7	ROX	ROX		OCB_OCI_OPITBSV3RR_PCB_INTR_PAYLOAD_QUAD_1: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 1 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_1=0; } // clear appropriate pending bit
8:11	ROX	ROX		OCB_OCI_OPITBSV3RR_PCB_INTR_PAYLOAD_QUAD_2: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 2 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_2=0; } // clear appropriate pending bit
12:15	ROX	ROX		OCB_OCI_OPITBSV3RR_PCB_INTR_PAYLOAD_QUAD_3: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 3 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_3=0; } // clear appropriate pending bit
16:19	ROX	ROX		OCB_OCI_OPITBSV3RR_PCB_INTR_PAYLOAD_QUAD_4: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 4 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_4=0; } // clear appropriate pending bit
20:23	ROX	ROX		OCB_OCI_OPITBSV3RR_PCB_INTR_PAYLOAD_QUAD_5: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 5 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_5=0; } // clear appropriate pending bit
24:27	ROX	ROX		OCB_OCI_OPITBSV3RR_PCB_INTR_PAYLOAD_QUAD_6: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 6 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_6=0; } // clear appropriate pending bit
28:31	ROX	ROX		OCB_OCI_OPITBSV3RR_PCB_INTR_PAYLOAD_QUAD_7: Type B PCB Interrupt packet content(8+a*4:11+a*4) from Quad 7 READ_EFFECT { OPITBPRc.pcb_intr_type_B_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCC PCB Interrupt Type C Summary Vector Register
Addr:	000000000006C588 (SCOM) 00000000C0062C40 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITCSVRR
Constant(s):
Comments:	This register provides access to type C Summary Notification Vectors. Type C and D interrupts write 4 bits into a single summary vector in the likewise determined position. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPITCPR. Reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts. Note: Hcode should never use the offset address 0x05XX due to window conditions. Hcode should first read the pending vector into a variable, then read the summary vector from address 0x04XX, then WR_CLEAR the pending vector using the variable.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITCSV_Q_0_INST.LATC.L2(0:3) [0000]
	4:7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITCSV_Q_4_INST.LATC.L2(4:7) [0000]
	8:11	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITCSV_Q_8_INST.LATC.L2(8:11) [0000]
	12:15	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITCSV_Q_12_INST.LATC.L2(12:15) [0000]
	16:19	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITCSV_Q_16_INST.LATC.L2(16:19) [0000]
	20:23	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITCSV_Q_20_INST.LATC.L2(20:23) [0000]
	24:27	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITCSV_Q_24_INST.LATC.L2(24:27) [0000]
	28:31	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITCSV_Q_28_INST.LATC.L2(28:31) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0:3	ROX	ROX		OCB_OCI_OPITCSVRR_PCB_INTR_PAYLOAD_QUAD_0: Type C PCB Interrupt packet content(20:23) from Quad 0 READ_EFFECT { OPITCPRc.pcb_intr_type_C_pending_0=0; } // clear appropriate pending bit
4:7	ROX	ROX		OCB_OCI_OPITCSVRR_PCB_INTR_PAYLOAD_QUAD_1: Type C PCB Interrupt packet content(20:23) from Quad 1 READ_EFFECT { OPITCPRc.pcb_intr_type_C_pending_1=0; } // clear appropriate pending bit
8:11	ROX	ROX		OCB_OCI_OPITCSVRR_PCB_INTR_PAYLOAD_QUAD_2: Type C PCB Interrupt packet content(20:23) from Quad 2 READ_EFFECT { OPITCPRc.pcb_intr_type_C_pending_2=0; } // clear appropriate pending bit
12:15	ROX	ROX		OCB_OCI_OPITCSVRR_PCB_INTR_PAYLOAD_QUAD_3: Type C PCB Interrupt packet content(20:23) from Quad 3 READ_EFFECT { OPITCPRc.pcb_intr_type_C_pending_3=0; } // clear appropriate pending bit
16:19	ROX	ROX		OCB_OCI_OPITCSVRR_PCB_INTR_PAYLOAD_QUAD_4: Type C PCB Interrupt packet content(20:23) from Quad 4 READ_EFFECT { OPITCPRc.pcb_intr_type_C_pending_4=0; } // clear appropriate pending bit
20:23	ROX	ROX		OCB_OCI_OPITCSVRR_PCB_INTR_PAYLOAD_QUAD_5: Type C PCB Interrupt packet content(20:23) from Quad 5 READ_EFFECT { OPITCPRc.pcb_intr_type_C_pending_5=0; } // clear appropriate pending bit
24:27	ROX	ROX		OCB_OCI_OPITCSVRR_PCB_INTR_PAYLOAD_QUAD_6: Type C PCB Interrupt packet content(20:23) from Quad 6 READ_EFFECT { OPITCPRc.pcb_intr_type_C_pending_6=0; } // clear appropriate pending bit
28:31	ROX	ROX		OCB_OCI_OPITCSVRR_PCB_INTR_PAYLOAD_QUAD_7: Type C PCB Interrupt packet content(20:23) from Quad 7 READ_EFFECT { OPITCPRc.pcb_intr_type_C_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCC PCB Interrupt Type D Summary Vector Register
Addr:	000000000006C58C (SCOM) 00000000C0062C60 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITDSVRR
Constant(s):
Comments:	This register provides access to type C Summary Notification Vectors. Type C and D interrupts write 4 bits into a single summary vector in the likewise determined position. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPITCPR. Reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts. Note: Hcode should never use the offset address 0x05XX due to window conditions. Hcode should first read the pending vector into a variable, then read the summary vector from address 0x04XX, then WR_CLEAR the pending vector using the variable.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITDSV_Q_0_INST.LATC.L2(0:3) [0000]
	4:7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITDSV_Q_4_INST.LATC.L2(4:7) [0000]
	8:11	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITDSV_Q_8_INST.LATC.L2(8:11) [0000]
	12:15	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITDSV_Q_12_INST.LATC.L2(12:15) [0000]
	16:19	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITDSV_Q_16_INST.LATC.L2(16:19) [0000]
	20:23	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITDSV_Q_20_INST.LATC.L2(20:23) [0000]
	24:27	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITDSV_Q_24_INST.LATC.L2(24:27) [0000]
	28:31	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITDSV_Q_28_INST.LATC.L2(28:31) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0:3	ROX	ROX		OCB_OCI_OPITDSVRR_PCB_INTR_PAYLOAD_QUAD_0: Type D PCB Interrupt packet content(20:23) from Quad 0 READ_EFFECT { OPITDPRc.pcb_intr_type_D_pending_0=0; } // clear appropriate pending bit
4:7	ROX	ROX		OCB_OCI_OPITDSVRR_PCB_INTR_PAYLOAD_QUAD_1: Type D PCB Interrupt packet content(20:23) from Quad 1 READ_EFFECT { OPITDPRc.pcb_intr_type_D_pending_1=0; } // clear appropriate pending bit
8:11	ROX	ROX		OCB_OCI_OPITDSVRR_PCB_INTR_PAYLOAD_QUAD_2: Type D PCB Interrupt packet content(20:23) from Quad 2 READ_EFFECT { OPITDPRc.pcb_intr_type_D_pending_2=0; } // clear appropriate pending bit
12:15	ROX	ROX		OCB_OCI_OPITDSVRR_PCB_INTR_PAYLOAD_QUAD_3: Type D PCB Interrupt packet content(20:23) from Quad 3 READ_EFFECT { OPITDPRc.pcb_intr_type_D_pending_3=0; } // clear appropriate pending bit
16:19	ROX	ROX		OCB_OCI_OPITDSVRR_PCB_INTR_PAYLOAD_QUAD_4: Type D PCB Interrupt packet content(20:23) from Quad 4 READ_EFFECT { OPITDPRc.pcb_intr_type_D_pending_4=0; } // clear appropriate pending bit
20:23	ROX	ROX		OCB_OCI_OPITDSVRR_PCB_INTR_PAYLOAD_QUAD_5: Type D PCB Interrupt packet content(20:23) from Quad 5 READ_EFFECT { OPITDPRc.pcb_intr_type_D_pending_5=0; } // clear appropriate pending bit
24:27	ROX	ROX		OCB_OCI_OPITDSVRR_PCB_INTR_PAYLOAD_QUAD_6: Type D PCB Interrupt packet content(20:23) from Quad 6 READ_EFFECT { OPITDPRc.pcb_intr_type_D_pending_6=0; } // clear appropriate pending bit
28:31	ROX	ROX		OCB_OCI_OPITDSVRR_PCB_INTR_PAYLOAD_QUAD_7: Type D PCB Interrupt packet content(20:23) from Quad 7 READ_EFFECT { OPITDPRc.pcb_intr_type_D_pending_7=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCC PCB Interrupt Type E Summary Vector Reset Register
Addr:	000000000006C590 (SCOM) 00000000C0062C80 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITESVRR
Constant(s):
Comments:	This register provides access to type E Summary Notification Vectors. Type E and F interrupts write 4 bits but only if the pending bit for that position is not already set to create a "lock" mechanism of the first zero value received, and requires the pending bit cleared before another can be accepted. To clear a locked field, use the WR_CLEAR to the pending register, which allows atomic operation in case another field is written by a PIG at the same time. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPITEPR. Reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts. Note: Hcode should never use the offset address 0x05XX due to window conditions. Hcode should first read the pending vector into a variable, then read the summary vector from address 0x04XX, then WR_CLEAR the pending vector using the variable.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITESV_Q_0_INST.LATC.L2(0:3) [0000]
	4:7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITESV_Q_4_INST.LATC.L2(4:7) [0000]
	8:11	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITESV_Q_8_INST.LATC.L2(8:11) [0000]
	12:15	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITESV_Q_12_INST.LATC.L2(12:15) [0000]
	16:19	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITESV_Q_16_INST.LATC.L2(16:19) [0000]
	20:23	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITESV_Q_20_INST.LATC.L2(20:23) [0000]
	24:27	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITESV_Q_24_INST.LATC.L2(24:27) [0000]
	28:31	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITESV_Q_28_INST.LATC.L2(28:31) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0:3	ROX	ROX		OCB_OCI_OPITESVRR_PCB_INTR_PAYLOAD_QUAD_0: Type E PCB Interrupt packet content(20:23) from Quad 0 READ_EFFECT { OPITEPRd.pcb_intr_type_E_pending_0=0; } // clear appropriate pending bit
4:7	ROX	ROX		OCB_OCI_OPITESVRR_PCB_INTR_PAYLOAD_QUAD_1: Type E PCB Interrupt packet content(20:23) from Quad 1 READ_EFFECT { OPITEPRd.pcb_intr_type_E_pending_0=0; } // clear appropriate pending bit
8:11	ROX	ROX		OCB_OCI_OPITESVRR_PCB_INTR_PAYLOAD_QUAD_2: Type E PCB Interrupt packet content(20:23) from Quad 2 READ_EFFECT { OPITEPRd.pcb_intr_type_E_pending_0=0; } // clear appropriate pending bit
12:15	ROX	ROX		OCB_OCI_OPITESVRR_PCB_INTR_PAYLOAD_QUAD_3: Type E PCB Interrupt packet content(20:23) from Quad 3 READ_EFFECT { OPITEPRd.pcb_intr_type_E_pending_0=0; } // clear appropriate pending bit
16:19	ROX	ROX		OCB_OCI_OPITESVRR_PCB_INTR_PAYLOAD_QUAD_4: Type E PCB Interrupt packet content(20:23) from Quad 4 READ_EFFECT { OPITEPRd.pcb_intr_type_E_pending_0=0; } // clear appropriate pending bit
20:23	ROX	ROX		OCB_OCI_OPITESVRR_PCB_INTR_PAYLOAD_QUAD_5: Type E PCB Interrupt packet content(20:23) from Quad 5 READ_EFFECT { OPITEPRd.pcb_intr_type_E_pending_0=0; } // clear appropriate pending bit
24:27	ROX	ROX		OCB_OCI_OPITESVRR_PCB_INTR_PAYLOAD_QUAD_6: Type E PCB Interrupt packet content(20:23) from Quad 6 READ_EFFECT { OPITEPRd.pcb_intr_type_E_pending_0=0; } // clear appropriate pending bit
28:31	ROX	ROX		OCB_OCI_OPITESVRR_PCB_INTR_PAYLOAD_QUAD_7: Type E PCB Interrupt packet content(20:23) from Quad 7 READ_EFFECT { OPITEPRd.pcb_intr_type_E_pending_0=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCC PCB Interrupt Type F Summary Vector Reset Register
Addr:	000000000006C594 (SCOM) 00000000C0062CA0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITFSVRR
Constant(s):
Comments:	This register provides access to type E Summary Notification Vectors. Type E and F interrupts write 4 bits but only if the pending bit for that position is not already set to create a "lock" mechanism of the first zero value received, and requires the pending bit cleared before another can be accepted. To clear a locked field, use the WR_CLEAR to the pending register, which allows atomic operation in case another field is written by a PIG at the same time. Reading from the base 0x04XX register has no effect on the state on the associated pending bit for this core in OPITEPR. Reading from the offset address 0x05XX does reset the corresponding Pending Register bits as a side effect to allow atomic, lossless, ordered capture of all interrupts. Note: Hcode should never use the offset address 0x05XX due to window conditions. Hcode should first read the pending vector into a variable, then read the summary vector from address 0x04XX, then WR_CLEAR the pending vector using the variable.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITFSV_Q_0_INST.LATC.L2(0:3) [0000]
	4:7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITFSV_Q_4_INST.LATC.L2(4:7) [0000]
	8:11	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITFSV_Q_8_INST.LATC.L2(8:11) [0000]
	12:15	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITFSV_Q_12_INST.LATC.L2(12:15) [0000]
	16:19	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITFSV_Q_16_INST.LATC.L2(16:19) [0000]
	20:23	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITFSV_Q_20_INST.LATC.L2(20:23) [0000]
	24:27	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITFSV_Q_24_INST.LATC.L2(24:27) [0000]
	28:31	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITFSV_Q_28_INST.LATC.L2(28:31) [0000]
Bit(s)	SCOM	OCI		Dial: Description
0:3	ROX	ROX		OCB_OCI_OPITFSVRR_PCB_INTR_PAYLOAD_QUAD_0: Type F PCB Interrupt packet content(20:23) from Quad 0 READ_EFFECT { OPITFPRd.pcb_intr_type_F_pending_0=0; } // clear appropriate pending bit
4:7	ROX	ROX		OCB_OCI_OPITFSVRR_PCB_INTR_PAYLOAD_QUAD_1: Type F PCB Interrupt packet content(20:23) from Quad 1 READ_EFFECT { OPITFPRd.pcb_intr_type_F_pending_0=0; } // clear appropriate pending bit
8:11	ROX	ROX		OCB_OCI_OPITFSVRR_PCB_INTR_PAYLOAD_QUAD_2: Type F PCB Interrupt packet content(20:23) from Quad 2 READ_EFFECT { OPITFPRd.pcb_intr_type_F_pending_0=0; } // clear appropriate pending bit
12:15	ROX	ROX		OCB_OCI_OPITFSVRR_PCB_INTR_PAYLOAD_QUAD_3: Type F PCB Interrupt packet content(20:23) from Quad 3 READ_EFFECT { OPITFPRd.pcb_intr_type_F_pending_0=0; } // clear appropriate pending bit
16:19	ROX	ROX		OCB_OCI_OPITFSVRR_PCB_INTR_PAYLOAD_QUAD_4: Type F PCB Interrupt packet content(20:23) from Quad 4 READ_EFFECT { OPITFPRd.pcb_intr_type_F_pending_0=0; } // clear appropriate pending bit
20:23	ROX	ROX		OCB_OCI_OPITFSVRR_PCB_INTR_PAYLOAD_QUAD_5: Type F PCB Interrupt packet content(20:23) from Quad 5 READ_EFFECT { OPITFPRd.pcb_intr_type_F_pending_0=0; } // clear appropriate pending bit
24:27	ROX	ROX		OCB_OCI_OPITFSVRR_PCB_INTR_PAYLOAD_QUAD_6: Type F PCB Interrupt packet content(20:23) from Quad 6 READ_EFFECT { OPITFPRd.pcb_intr_type_F_pending_0=0; } // clear appropriate pending bit
28:31	ROX	ROX		OCB_OCI_OPITFSVRR_PCB_INTR_PAYLOAD_QUAD_7: Type F PCB Interrupt packet content(20:23) from Quad 7 READ_EFFECT { OPITFPRd.pcb_intr_type_F_pending_0=0; } // clear appropriate pending bit
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCC PCB Interrupt Type Injection Register
Addr:	000000000006C5C0 (SCOM) 00000000C0062E00 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITIR
Constant(s):
Comments:	This register provides a means to inject an OPIT packet into the OCB directly for local OCC complet testing. This injection is arbitrated with normal Pervasive Interrupt packets that may be received from QMEs. Users must take care that the system is a proper mode to achieve the desired testing result.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	5:7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITIRA_Q_5_INST.LATC.L2(5:7) [000]
	9:31	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITIRB_Q_9_INST.LATC.L2(9:31) [00000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:4	RO	RO		constant=0b00000
5:7	RW	RW		OCB_OCI_OPITIR_PCB_INTR_CHIPLET_ID: EC Chiplet ID (chiplet number) of emanated interrupt packet
8	RO	RO		constant=0b1
9:31	RW	RW		pcb_intr_payload
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCC PCB Interrupt Type 0 Pending a Register
Addr:	000000000006C600 (SCOM) 000000000006C601 (SCOM1) 00000000C0063000 (OCI) 00000000C0063008 (OCI1)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0PRA
Constant(s):	PU_OCB_OCI_OPIT0PRA
Comments:	This register is a bit vector that a PCB Power Management Interrupt Type 0 has been received from the respective QME (cache chiplet). The contents of the interrupt packet is accessible via the OPIT0Qq register set. These bits are ORed reduced to form OISR bit pmc_pcb_intr_type_0_pending which can be routed to any of the OCC Complex engines. Bits are cleared using WO_CLEAR with a 1 in the respective bit. Note: WOX_OR is not supported. To inject a 1 into this register, SCOM write to the corresponding QME macro to cause a new pending payload to be sent. XDEV_EFFECT { if (OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_0 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_1 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_2 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_3 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_4 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_5 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_6 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_7 ) { OCB_BASE.OISR0.pmc_pcb_intr_type0_pending = 1; } else { OCB_BASE.OISR0.pmc_pcb_intr_type0_pending = 0; } }
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT0PRA_Q_0_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT0PRA_Q_1_INST.LATC.L2(1) [0]
	2	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT0PRA_Q_2_INST.LATC.L2(2) [0]
	3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT0PRA_Q_3_INST.LATC.L2(3) [0]
	4	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT0PRA_Q_4_INST.LATC.L2(4) [0]
	5	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT0PRA_Q_5_INST.LATC.L2(5) [0]
	6	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT0PRA_Q_6_INST.LATC.L2(6) [0]
	7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT0PRA_Q_7_INST.LATC.L2(7) [0]
Bit(s)	SCOM	SCOM1	OCI	OCI1	Dial: Description
0	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_0_PENDING_0: PCB interrupt Type 0 Pending - QME 0 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
1	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_0_PENDING_1: PCB interrupt Type 0 Pending - QME 1 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
2	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_0_PENDING_2: PCB interrupt Type 0 Pending - QME 2 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
3	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_0_PENDING_3: PCB interrupt Type 0 Pending - QME 3 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
4	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_0_PENDING_4: PCB interrupt Type 0 Pending - QME 4 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
5	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_0_PENDING_5: PCB interrupt Type 0 Pending - QME 5 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
6	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_0_PENDING_6: PCB interrupt Type 0 Pending - QME 6 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
7	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_0_PENDING_7: PCB interrupt Type 0 Pending - QME 7 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
8:63	RO	RO	RO	RO	constant=0b00000000000000000000000000000000000000000000000000000000 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1

OCB_OCI OCC PCB Interrupt Type 1 Pending a Register
Addr:	000000000006C608 (SCOM) 000000000006C609 (SCOM1) 00000000C0063040 (OCI) 00000000C0063048 (OCI1)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1PRA
Constant(s):	PU_OCB_OCI_OPIT1PRA
Comments:	This register is a bit vector that a PCB Power Management Interrupt Type 0 has been received from the respective QME (cache chiplet). The contents of the interrupt packet is accessible via the OPIT0Qq register set. These bits are ORed reduced to form OISR bit pmc_pcb_intr_type_0_pending which can be routed to any of the OCC Complex engines. Bits are cleared using WO_CLEAR with a 1 in the respective bit. Note: WOX_OR is not supported. To inject a 1 into this register, SCOM write to the corresponding QME macro to cause a new pending payload to be sent. XDEV_EFFECT { if (OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_0 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_1 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_2 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_3 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_4 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_5 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_6 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_7 ) { OCB_BASE.OISR0.pmc_pcb_intr_type0_pending = 1; } else { OCB_BASE.OISR0.pmc_pcb_intr_type0_pending = 0; } }
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT1PRA_Q_0_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT1PRA_Q_1_INST.LATC.L2(1) [0]
	2	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT1PRA_Q_2_INST.LATC.L2(2) [0]
	3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT1PRA_Q_3_INST.LATC.L2(3) [0]
	4	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT1PRA_Q_4_INST.LATC.L2(4) [0]
	5	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT1PRA_Q_5_INST.LATC.L2(5) [0]
	6	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT1PRA_Q_6_INST.LATC.L2(6) [0]
	7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT1PRA_Q_7_INST.LATC.L2(7) [0]
Bit(s)	SCOM	SCOM1	OCI	OCI1	Dial: Description
0	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_1_PENDING_0: PCB interrupt Type 1 Pending - QME 0 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
1	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_1_PENDING_1: PCB interrupt Type 1 Pending - QME 1 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
2	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_1_PENDING_2: PCB interrupt Type 1 Pending - QME 2 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
3	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_1_PENDING_3: PCB interrupt Type 1 Pending - QME 3 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
4	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_1_PENDING_4: PCB interrupt Type 1 Pending - QME 4 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
5	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_1_PENDING_5: PCB interrupt Type 1 Pending - QME 5 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
6	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_1_PENDING_6: PCB interrupt Type 1 Pending - QME 6 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
7	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_1_PENDING_7: PCB interrupt Type 1 Pending - QME 7 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
8:63	RO	RO	RO	RO	constant=0b00000000000000000000000000000000000000000000000000000000 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1

OCB_OCI OCC PCB Interrupt Type 2 Pending a Register
Addr:	000000000006C610 (SCOM) 000000000006C611 (SCOM1) 00000000C0063080 (OCI) 00000000C0063088 (OCI1)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2PRA
Constant(s):	PU_OCB_OCI_OPIT2PRA
Comments:	This register is a bit vector that a PCB Power Management Interrupt Type 0 has been received from the respective QME (cache chiplet). The contents of the interrupt packet is accessible via the OPIT0Qq register set. These bits are ORed reduced to form OISR bit pmc_pcb_intr_type_0_pending which can be routed to any of the OCC Complex engines. Bits are cleared using WO_CLEAR with a 1 in the respective bit. Note: WOX_OR is not supported. To inject a 1 into this register, SCOM write to the corresponding QME macro to cause a new pending payload to be sent. XDEV_EFFECT { if (OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_0 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_1 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_2 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_3 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_4 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_5 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_6 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_7 ) { OCB_BASE.OISR0.pmc_pcb_intr_type0_pending = 1; } else { OCB_BASE.OISR0.pmc_pcb_intr_type0_pending = 0; } }
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT2PRA_Q_0_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT2PRA_Q_1_INST.LATC.L2(1) [0]
	2	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT2PRA_Q_2_INST.LATC.L2(2) [0]
	3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT2PRA_Q_3_INST.LATC.L2(3) [0]
	4	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT2PRA_Q_4_INST.LATC.L2(4) [0]
	5	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT2PRA_Q_5_INST.LATC.L2(5) [0]
	6	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT2PRA_Q_6_INST.LATC.L2(6) [0]
	7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT2PRA_Q_7_INST.LATC.L2(7) [0]
Bit(s)	SCOM	SCOM1	OCI	OCI1	Dial: Description
0	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_2_PENDING_0: PCB interrupt Type 2 Pending - QME 0 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
1	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_2_PENDING_1: PCB interrupt Type 2 Pending - QME 1 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
2	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_2_PENDING_2: PCB interrupt Type 2 Pending - QME 2 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
3	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_2_PENDING_3: PCB interrupt Type 2 Pending - QME 3 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
4	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_2_PENDING_4: PCB interrupt Type 2 Pending - QME 4 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
5	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_2_PENDING_5: PCB interrupt Type 2 Pending - QME 5 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
6	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_2_PENDING_6: PCB interrupt Type 2 Pending - QME 6 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
7	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_2_PENDING_7: PCB interrupt Type 2 Pending - QME 7 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
8:63	RO	RO	RO	RO	constant=0b00000000000000000000000000000000000000000000000000000000 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1

OCB_OCI OCC PCB Interrupt Type 3 Pending a Register
Addr:	000000000006C618 (SCOM) 000000000006C619 (SCOM1) 00000000C00630C0 (OCI) 00000000C00630C8 (OCI1)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3PRA
Constant(s):	PU_OCB_OCI_OPIT3PRA
Comments:	This register is a bit vector that a PCB Power Management Interrupt Type 0 has been received from the respective QME (cache chiplet). The contents of the interrupt packet is accessible via the OPIT0Qq register set. These bits are ORed reduced to form OISR bit pmc_pcb_intr_type_0_pending which can be routed to any of the OCC Complex engines. Bits are cleared using WO_CLEAR with a 1 in the respective bit. Note: WOX_OR is not supported. To inject a 1 into this register, SCOM write to the corresponding QME macro to cause a new pending payload to be sent. XDEV_EFFECT { if (OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_0 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_1 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_2 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_3 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_4 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_5 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_6 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_7 ) { OCB_BASE.OISR0.pmc_pcb_intr_type0_pending = 1; } else { OCB_BASE.OISR0.pmc_pcb_intr_type0_pending = 0; } }
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT3PRA_Q_0_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT3PRA_Q_1_INST.LATC.L2(1) [0]
	2	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT3PRA_Q_2_INST.LATC.L2(2) [0]
	3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT3PRA_Q_3_INST.LATC.L2(3) [0]
	4	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT3PRA_Q_4_INST.LATC.L2(4) [0]
	5	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT3PRA_Q_5_INST.LATC.L2(5) [0]
	6	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT3PRA_Q_6_INST.LATC.L2(6) [0]
	7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT3PRA_Q_7_INST.LATC.L2(7) [0]
Bit(s)	SCOM	SCOM1	OCI	OCI1	Dial: Description
0	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_3_PENDING_0: PCB interrupt Type 3 Pending - QME 0 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
1	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_3_PENDING_1: PCB interrupt Type 3 Pending - QME 1 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
2	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_3_PENDING_2: PCB interrupt Type 3 Pending - QME 2 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
3	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_3_PENDING_3: PCB interrupt Type 3 Pending - QME 3 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
4	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_3_PENDING_4: PCB interrupt Type 3 Pending - QME 4 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
5	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_3_PENDING_5: PCB interrupt Type 3 Pending - QME 5 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
6	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_3_PENDING_6: PCB interrupt Type 3 Pending - QME 6 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
7	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_3_PENDING_7: PCB interrupt Type 3 Pending - QME 7 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
8:63	RO	RO	RO	RO	constant=0b00000000000000000000000000000000000000000000000000000000 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1

OCB_OCI OCC PCB Interrupt Type 4 Pending a Register
Addr:	000000000006C620 (SCOM) 000000000006C621 (SCOM1) 00000000C0063100 (OCI) 00000000C0063108 (OCI1)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4PRA
Constant(s):	PU_OCB_OCI_OPIT4PRA
Comments:	This register is a bit vector that a PCB Power Management Interrupt Type 0 has been received from the respective QME (cache chiplet). The contents of the interrupt packet is accessible via the OPIT0Qq register set. These bits are ORed reduced to form OISR bit pmc_pcb_intr_type_0_pending which can be routed to any of the OCC Complex engines. Bits are cleared using WO_CLEAR with a 1 in the respective bit. Note: WOX_OR is not supported. To inject a 1 into this register, SCOM write to the corresponding QME macro to cause a new pending payload to be sent. XDEV_EFFECT { if (OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_0 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_1 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_2 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_3 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_4 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_5 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_6 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_7 ) { OCB_BASE.OISR0.pmc_pcb_intr_type0_pending = 1; } else { OCB_BASE.OISR0.pmc_pcb_intr_type0_pending = 0; } }
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT4PRA_Q_0_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT4PRA_Q_1_INST.LATC.L2(1) [0]
	2	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT4PRA_Q_2_INST.LATC.L2(2) [0]
	3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT4PRA_Q_3_INST.LATC.L2(3) [0]
	4	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT4PRA_Q_4_INST.LATC.L2(4) [0]
	5	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT4PRA_Q_5_INST.LATC.L2(5) [0]
	6	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT4PRA_Q_6_INST.LATC.L2(6) [0]
	7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT4PRA_Q_7_INST.LATC.L2(7) [0]
Bit(s)	SCOM	SCOM1	OCI	OCI1	Dial: Description
0	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_4_PENDING_0: PCB interrupt Type 4 Pending - QME 0 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
1	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_4_PENDING_1: PCB interrupt Type 4 Pending - QME 1 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
2	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_4_PENDING_2: PCB interrupt Type 4 Pending - QME 2 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
3	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_4_PENDING_3: PCB interrupt Type 4 Pending - QME 3 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
4	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_4_PENDING_4: PCB interrupt Type 4 Pending - QME 4 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
5	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_4_PENDING_5: PCB interrupt Type 4 Pending - QME 5 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
6	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_4_PENDING_6: PCB interrupt Type 4 Pending - QME 6 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
7	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_4_PENDING_7: PCB interrupt Type 4 Pending - QME 7 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
8:63	RO	RO	RO	RO	constant=0b00000000000000000000000000000000000000000000000000000000 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1

OCB_OCI OCC PCB Interrupt Type 5 Pending a Register
Addr:	000000000006C628 (SCOM) 000000000006C629 (SCOM1) 00000000C0063140 (OCI) 00000000C0063148 (OCI1)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5PRA
Constant(s):	PU_OCB_OCI_OPIT5PRA
Comments:	This register is a bit vector that a PCB Power Management Interrupt Type 0 has been received from the respective QME (cache chiplet). The contents of the interrupt packet is accessible via the OPIT0Qq register set. These bits are ORed reduced to form OISR bit pmc_pcb_intr_type_0_pending which can be routed to any of the OCC Complex engines. Bits are cleared using WO_CLEAR with a 1 in the respective bit. Note: WOX_OR is not supported. To inject a 1 into this register, SCOM write to the corresponding QME macro to cause a new pending payload to be sent. XDEV_EFFECT { if (OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_0 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_1 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_2 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_3 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_4 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_5 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_6 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_7 ) { OCB_BASE.OISR0.pmc_pcb_intr_type0_pending = 1; } else { OCB_BASE.OISR0.pmc_pcb_intr_type0_pending = 0; } }
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT5PRA_Q_0_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT5PRA_Q_1_INST.LATC.L2(1) [0]
	2	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT5PRA_Q_2_INST.LATC.L2(2) [0]
	3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT5PRA_Q_3_INST.LATC.L2(3) [0]
	4	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT5PRA_Q_4_INST.LATC.L2(4) [0]
	5	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT5PRA_Q_5_INST.LATC.L2(5) [0]
	6	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT5PRA_Q_6_INST.LATC.L2(6) [0]
	7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT5PRA_Q_7_INST.LATC.L2(7) [0]
Bit(s)	SCOM	SCOM1	OCI	OCI1	Dial: Description
0	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_5_PENDING_0: PCB interrupt Type 5 Pending - QME 0 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
1	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_5_PENDING_1: PCB interrupt Type 5 Pending - QME 1 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
2	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_5_PENDING_2: PCB interrupt Type 5 Pending - QME 2 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
3	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_5_PENDING_3: PCB interrupt Type 5 Pending - QME 3 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
4	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_5_PENDING_4: PCB interrupt Type 5 Pending - QME 4 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
5	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_5_PENDING_5: PCB interrupt Type 5 Pending - QME 5 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
6	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_5_PENDING_6: PCB interrupt Type 5 Pending - QME 6 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
7	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_5_PENDING_7: PCB interrupt Type 5 Pending - QME 7 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
8:63	RO	RO	RO	RO	constant=0b00000000000000000000000000000000000000000000000000000000 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1

OCB_OCI OCC PCB Interrupt Type 6 Pending a Register
Addr:	000000000006C630 (SCOM) 000000000006C631 (SCOM1) 00000000C0063180 (OCI) 00000000C0063188 (OCI1)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6PRA
Constant(s):
Comments:	This register is a bit vector that a PCB Power Management Interrupt Type 0 has been received from the respective QME (cache chiplet). The contents of the interrupt packet is accessible via the OPIT0Qq register set. These bits are ORed reduced to form OISR bit pmc_pcb_intr_type_0_pending which can be routed to any of the OCC Complex engines. Bits are cleared using WO_CLEAR with a 1 in the respective bit. Note: WOX_OR is not supported. To inject a 1 into this register, SCOM write to the corresponding QME macro to cause a new pending payload to be sent. XDEV_EFFECT { if (OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_0 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_1 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_2 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_3 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_4 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_5 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_6 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_7 ) { OCB_BASE.OISR0.pmc_pcb_intr_type0_pending = 1; } else { OCB_BASE.OISR0.pmc_pcb_intr_type0_pending = 0; } }
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT6PRA_Q_0_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT6PRA_Q_1_INST.LATC.L2(1) [0]
	2	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT6PRA_Q_2_INST.LATC.L2(2) [0]
	3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT6PRA_Q_3_INST.LATC.L2(3) [0]
	4	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT6PRA_Q_4_INST.LATC.L2(4) [0]
	5	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT6PRA_Q_5_INST.LATC.L2(5) [0]
	6	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT6PRA_Q_6_INST.LATC.L2(6) [0]
	7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT6PRA_Q_7_INST.LATC.L2(7) [0]
Bit(s)	SCOM	SCOM1	OCI	OCI1	Dial: Description
0	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT6PRA_PCB_INTR_TYPE_6_PENDING_0: PCB interrupt Type 6 Pending - QME 0 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
1	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT6PRA_PCB_INTR_TYPE_6_PENDING_1: PCB interrupt Type 6 Pending - QME 1 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
2	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT6PRA_PCB_INTR_TYPE_6_PENDING_2: PCB interrupt Type 6 Pending - QME 2 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
3	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT6PRA_PCB_INTR_TYPE_6_PENDING_3: PCB interrupt Type 6 Pending - QME 3 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
4	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT6PRA_PCB_INTR_TYPE_6_PENDING_4: PCB interrupt Type 6 Pending - QME 4 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
5	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT6PRA_PCB_INTR_TYPE_6_PENDING_5: PCB interrupt Type 6 Pending - QME 5 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
6	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT6PRA_PCB_INTR_TYPE_6_PENDING_6: PCB interrupt Type 6 Pending - QME 6 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
7	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT6PRA_PCB_INTR_TYPE_6_PENDING_7: PCB interrupt Type 6 Pending - QME 7 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
8:63	RO	RO	RO	RO	constant=0b00000000000000000000000000000000000000000000000000000000 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1

OCB_OCI OCC PCB Interrupt Type 7 Pending a Register
Addr:	000000000006C638 (SCOM) 000000000006C639 (SCOM1) 00000000C00631C0 (OCI) 00000000C00631C8 (OCI1)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7PRA
Constant(s):
Comments:	This register is a bit vector that a PCB Power Management Interrupt Type 0 has been received from the respective QME (cache chiplet). The contents of the interrupt packet is accessible via the OPIT0Qq register set. These bits are ORed reduced to form OISR bit pmc_pcb_intr_type_0_pending which can be routed to any of the OCC Complex engines. Bits are cleared using WO_CLEAR with a 1 in the respective bit. Note: WOX_OR is not supported. To inject a 1 into this register, SCOM write to the corresponding QME macro to cause a new pending payload to be sent. XDEV_EFFECT { if (OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_0 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_1 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_2 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_3 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_4 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_5 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_6 | OCB_AGEN.OPIT0PRa.pcb_intr_type_0_pending_7 ) { OCB_BASE.OISR0.pmc_pcb_intr_type0_pending = 1; } else { OCB_BASE.OISR0.pmc_pcb_intr_type0_pending = 0; } }
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT7PRA_Q_0_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT7PRA_Q_1_INST.LATC.L2(1) [0]
	2	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT7PRA_Q_2_INST.LATC.L2(2) [0]
	3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT7PRA_Q_3_INST.LATC.L2(3) [0]
	4	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT7PRA_Q_4_INST.LATC.L2(4) [0]
	5	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT7PRA_Q_5_INST.LATC.L2(5) [0]
	6	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT7PRA_Q_6_INST.LATC.L2(6) [0]
	7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT7PRA_Q_7_INST.LATC.L2(7) [0]
Bit(s)	SCOM	SCOM1	OCI	OCI1	Dial: Description
0	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT7PRA_PCB_INTR_TYPE_7_PENDING_0: PCB interrupt Type 7 Pending - QME 0 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
1	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT7PRA_PCB_INTR_TYPE_7_PENDING_1: PCB interrupt Type 7 Pending - QME 1 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
2	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT7PRA_PCB_INTR_TYPE_7_PENDING_2: PCB interrupt Type 7 Pending - QME 2 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
3	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT7PRA_PCB_INTR_TYPE_7_PENDING_3: PCB interrupt Type 7 Pending - QME 3 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
4	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT7PRA_PCB_INTR_TYPE_7_PENDING_4: PCB interrupt Type 7 Pending - QME 4 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
5	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT7PRA_PCB_INTR_TYPE_7_PENDING_5: PCB interrupt Type 7 Pending - QME 5 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
6	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT7PRA_PCB_INTR_TYPE_7_PENDING_6: PCB interrupt Type 7 Pending - QME 6 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
7	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT7PRA_PCB_INTR_TYPE_7_PENDING_7: PCB interrupt Type 7 Pending - QME 7 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
8:63	RO	RO	RO	RO	constant=0b00000000000000000000000000000000000000000000000000000000 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1

OCB_OCI OCC PCB Interrupt Type 8 Pending b Register
Addr:	000000000006C640 (SCOM) 000000000006C641 (SCOM1) 00000000C0063200 (OCI) 00000000C0063208 (OCI1)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8PRB
Constant(s):
Comments:	This register is a bit vector that a PCB Power Management Interrupt Type 8 has been received from the respective Core. The contents of the interrupt packet is accessible via the OPIT8Cc register set. These bits are ORed reduced to form OISR bit pmc_pcb_intr_type_8_pending which can be routed to any of the OCC Complex engines. Bits are cleared using WO_CLEAR with a 1 in the respective bit. Note: WOX_OR is not supported. To inject a 1 into this register, either the a write to OPITIR or a SCOM write to the corresponding QME macro to cause a new pending payload to be sent. XDEV_EFFECT { if (OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_0 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_1 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_2 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_3 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_4 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_5 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_6 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_7 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_8 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_9 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_10 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_11 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_12 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_13 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_14 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_15 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_16 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_17 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_18 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_19 || OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_20 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_21 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_22 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_23 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_24 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_25 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_26 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_27 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_28 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_29 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_30 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_31 ) { OCB_BASE.OISR0.pmc_pcb_intr_type8_pending = 1; } else { OCB_BASE.OISR0.pmc_pcb_intr_type8_pending = 0; } }
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_0_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_1_INST.LATC.L2(1) [0]
	2	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_2_INST.LATC.L2(2) [0]
	3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_3_INST.LATC.L2(3) [0]
	4	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_4_INST.LATC.L2(4) [0]
	5	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_5_INST.LATC.L2(5) [0]
	6	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_6_INST.LATC.L2(6) [0]
	7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_7_INST.LATC.L2(7) [0]
	8	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_8_INST.LATC.L2(8) [0]
	9	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_9_INST.LATC.L2(9) [0]
	10	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_10_INST.LATC.L2(10) [0]
	11	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_11_INST.LATC.L2(11) [0]
	12	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_12_INST.LATC.L2(12) [0]
	13	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_13_INST.LATC.L2(13) [0]
	14	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_14_INST.LATC.L2(14) [0]
	15	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_15_INST.LATC.L2(15) [0]
	16	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_16_INST.LATC.L2(16) [0]
	17	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_17_INST.LATC.L2(17) [0]
	18	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_18_INST.LATC.L2(18) [0]
	19	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_19_INST.LATC.L2(19) [0]
	20	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_20_INST.LATC.L2(20) [0]
	21	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_21_INST.LATC.L2(21) [0]
	22	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_22_INST.LATC.L2(22) [0]
	23	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_23_INST.LATC.L2(23) [0]
	24	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_24_INST.LATC.L2(24) [0]
	25	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_25_INST.LATC.L2(25) [0]
	26	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_26_INST.LATC.L2(26) [0]
	27	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_27_INST.LATC.L2(27) [0]
	28	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_28_INST.LATC.L2(28) [0]
	29	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_29_INST.LATC.L2(29) [0]
	30	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_30_INST.LATC.L2(30) [0]
	31	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT8PRB_Q_31_INST.LATC.L2(31) [0]
Bit(s)	SCOM	SCOM1	OCI	OCI1	Dial: Description
0	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_0: PCB interrupt Type 8 Pending - Core 0 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
1	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_1: PCB interrupt Type 8 Pending - Core 1 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
2	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_2: PCB interrupt Type 8 Pending - Core 2 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
3	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_3: PCB interrupt Type 8 Pending - Core 3 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
4	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_4: PCB interrupt Type 8 Pending - Core 4 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
5	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_5: PCB interrupt Type 8 Pending - Core 5 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
6	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_6: PCB interrupt Type 8 Pending - Core 6 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
7	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_7: PCB interrupt Type 8 Pending - Core 7 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
8	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_8: PCB interrupt Type 8 Pending - Core 8 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
9	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_9: PCB interrupt Type 8 Pending - Core 9 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
10	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_10: PCB interrupt Type 8 Pending - Core 10 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
11	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_11: PCB interrupt Type 8 Pending - Core 11 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
12	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_12: PCB interrupt Type 8 Pending - Core 12 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
13	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_13: PCB interrupt Type 8 Pending - Core 13 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
14	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_14: PCB interrupt Type 8 Pending - Core 14 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
15	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_15: PCB interrupt Type 8 Pending - Core 15 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
16	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_16: PCB interrupt Type 8 Pending - Core 16 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
17	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_17: PCB interrupt Type 8 Pending - Core 17 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
18	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_18: PCB interrupt Type 8 Pending - Core 18 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
19	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_19: PCB interrupt Type 8 Pending - Core 19 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
20	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_20: PCB interrupt Type 8 Pending - Core 20 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
21	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_21: PCB interrupt Type 8 Pending - Core 21 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
22	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_22: PCB interrupt Type 8 Pending - Core 22 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
23	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_23: PCB interrupt Type 8 Pending - Core 23 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
24	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_24: PCB interrupt Type 8 Pending - Core 24 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
25	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_25: PCB interrupt Type 8 Pending - Core 25 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
26	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_26: PCB interrupt Type 8 Pending - Core 26 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
27	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_27: PCB interrupt Type 8 Pending - Core 27 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
28	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_28: PCB interrupt Type 8 Pending - Core 28 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
29	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_29: PCB interrupt Type 8 Pending - Core 29 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
30	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_30: PCB interrupt Type 8 Pending - Core 30 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
31	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT8PRB_PCB_INTR_TYPE_8_PENDING_31: PCB interrupt Type 8 Pending - Core 31 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
32:63	RO	RO	RO	RO	constant=0b00000000000000000000000000000000 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1

OCB_OCI OCC PCB Interrupt Type 9 Pending b Register
Addr:	000000000006C660 (SCOM) 000000000006C661 (SCOM1) 00000000C0063300 (OCI) 00000000C0063308 (OCI1)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9PRB
Constant(s):
Comments:	This register is a bit vector that a PCB Power Management Interrupt Type 8 has been received from the respective Core. The contents of the interrupt packet is accessible via the OPIT8Cc register set. These bits are ORed reduced to form OISR bit pmc_pcb_intr_type_8_pending which can be routed to any of the OCC Complex engines. Bits are cleared using WO_CLEAR with a 1 in the respective bit. Note: WOX_OR is not supported. To inject a 1 into this register, either the a write to OPITIR or a SCOM write to the corresponding QME macro to cause a new pending payload to be sent. XDEV_EFFECT { if (OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_0 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_1 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_2 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_3 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_4 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_5 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_6 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_7 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_8 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_9 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_10 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_11 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_12 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_13 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_14 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_15 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_16 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_17 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_18 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_19 || OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_20 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_21 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_22 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_23 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_24 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_25 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_26 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_27 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_28 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_29 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_30 | OCB_AGEN.OPIT8PRb.pcb_intr_type_8_pending_31 ) { OCB_BASE.OISR0.pmc_pcb_intr_type8_pending = 1; } else { OCB_BASE.OISR0.pmc_pcb_intr_type8_pending = 0; } }
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_0_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_1_INST.LATC.L2(1) [0]
	2	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_2_INST.LATC.L2(2) [0]
	3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_3_INST.LATC.L2(3) [0]
	4	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_4_INST.LATC.L2(4) [0]
	5	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_5_INST.LATC.L2(5) [0]
	6	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_6_INST.LATC.L2(6) [0]
	7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_7_INST.LATC.L2(7) [0]
	8	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_8_INST.LATC.L2(8) [0]
	9	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_9_INST.LATC.L2(9) [0]
	10	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_10_INST.LATC.L2(10) [0]
	11	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_11_INST.LATC.L2(11) [0]
	12	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_12_INST.LATC.L2(12) [0]
	13	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_13_INST.LATC.L2(13) [0]
	14	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_14_INST.LATC.L2(14) [0]
	15	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_15_INST.LATC.L2(15) [0]
	16	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_16_INST.LATC.L2(16) [0]
	17	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_17_INST.LATC.L2(17) [0]
	18	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_18_INST.LATC.L2(18) [0]
	19	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_19_INST.LATC.L2(19) [0]
	20	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_20_INST.LATC.L2(20) [0]
	21	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_21_INST.LATC.L2(21) [0]
	22	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_22_INST.LATC.L2(22) [0]
	23	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_23_INST.LATC.L2(23) [0]
	24	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_24_INST.LATC.L2(24) [0]
	25	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_25_INST.LATC.L2(25) [0]
	26	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_26_INST.LATC.L2(26) [0]
	27	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_27_INST.LATC.L2(27) [0]
	28	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_28_INST.LATC.L2(28) [0]
	29	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_29_INST.LATC.L2(29) [0]
	30	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_30_INST.LATC.L2(30) [0]
	31	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPIT9PRB_Q_31_INST.LATC.L2(31) [0]
Bit(s)	SCOM	SCOM1	OCI	OCI1	Dial: Description
0	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_0: PCB interrupt Type 9 Pending - Core 0 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
1	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_1: PCB interrupt Type 9 Pending - Core 1 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
2	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_2: PCB interrupt Type 9 Pending - Core 2 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
3	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_3: PCB interrupt Type 9 Pending - Core 3 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
4	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_4: PCB interrupt Type 9 Pending - Core 4 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
5	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_5: PCB interrupt Type 9 Pending - Core 5 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
6	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_6: PCB interrupt Type 9 Pending - Core 6 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
7	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_7: PCB interrupt Type 9 Pending - Core 7 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
8	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_8: PCB interrupt Type 9 Pending - Core 8 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
9	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_9: PCB interrupt Type 9 Pending - Core 9 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
10	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_10: PCB interrupt Type 9 Pending - Core 10 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
11	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_11: PCB interrupt Type 9 Pending - Core 11 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
12	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_12: PCB interrupt Type 9 Pending - Core 12 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
13	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_13: PCB interrupt Type 9 Pending - Core 13 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
14	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_14: PCB interrupt Type 9 Pending - Core 14 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
15	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_15: PCB interrupt Type 9 Pending - Core 15 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
16	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_16: PCB interrupt Type 9 Pending - Core 16 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
17	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_17: PCB interrupt Type 9 Pending - Core 17 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
18	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_18: PCB interrupt Type 9 Pending - Core 18 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
19	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_19: PCB interrupt Type 9 Pending - Core 19 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
20	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_20: PCB interrupt Type 9 Pending - Core 20 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
21	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_21: PCB interrupt Type 9 Pending - Core 21 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
22	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_22: PCB interrupt Type 9 Pending - Core 22 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
23	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_23: PCB interrupt Type 9 Pending - Core 23 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
24	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_24: PCB interrupt Type 9 Pending - Core 24 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
25	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_25: PCB interrupt Type 9 Pending - Core 25 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
26	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_26: PCB interrupt Type 9 Pending - Core 26 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
27	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_27: PCB interrupt Type 9 Pending - Core 27 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
28	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_28: PCB interrupt Type 9 Pending - Core 28 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
29	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_29: PCB interrupt Type 9 Pending - Core 29 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
30	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_30: PCB interrupt Type 9 Pending - Core 30 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
31	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPIT9PRB_PCB_INTR_TYPE_9_PENDING_31: PCB interrupt Type 9 Pending - Core 31 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
32:63	RO	RO	RO	RO	constant=0b00000000000000000000000000000000 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1

OCB_OCI OCC PCB Interrupt Type A Pending c Register
Addr:	000000000006C680 (SCOM) 000000000006C681 (SCOM1) 00000000C0063400 (OCI) 00000000C0063408 (OCI1)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITAPRC
Constant(s):
Comments:	This register is a bit vector that a PCB Power Management Interrupt Type A has been received from the respective QME (cache chiplet). The contents of the interrupt packet is accessible via the OPITASVa (A,B), or OPITASV (C,D), register set. These bits are ORed reduced to form OISR bit pmc_pcb_intr_type_A_pending which can be routed to any of the OCC Complex engines. Bits are cleared using RO_CLEAR. To inject a 1 into this register, either the a write to OPITIR or a SCOM write to the corresponding QME macro to cause a new pending payload to be sent. XDEV_EFFECT { if (OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_0 | OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_1 | OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_2 | OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_3 | OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_4 | OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_5 | OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_6 | OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_7 ) { OCB_BASE.OISR0.pmc_pcb_intr_typeA_pending = 1; } else { OCB_BASE.OISR0.pmc_pcb_intr_typeA_pending = 0; } }
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITAPRC_Q_0_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITAPRC_Q_1_INST.LATC.L2(1) [0]
	2	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITAPRC_Q_2_INST.LATC.L2(2) [0]
	3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITAPRC_Q_3_INST.LATC.L2(3) [0]
	4	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITAPRC_Q_4_INST.LATC.L2(4) [0]
	5	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITAPRC_Q_5_INST.LATC.L2(5) [0]
	6	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITAPRC_Q_6_INST.LATC.L2(6) [0]
	7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITAPRC_Q_7_INST.LATC.L2(7) [0]
Bit(s)	SCOM	SCOM1	OCI	OCI1	Dial: Description
0	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITAPRC_PCB_INTR_TYPE_A_PENDING_0: PCB interrupt Type A Pending - QME 0 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
1	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITAPRC_PCB_INTR_TYPE_A_PENDING_1: PCB interrupt Type A Pending - QME 1 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
2	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITAPRC_PCB_INTR_TYPE_A_PENDING_2: PCB interrupt Type A Pending - QME 2 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
3	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITAPRC_PCB_INTR_TYPE_A_PENDING_3: PCB interrupt Type A Pending - QME 3 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
4	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITAPRC_PCB_INTR_TYPE_A_PENDING_4: PCB interrupt Type A Pending - QME 4 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
5	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITAPRC_PCB_INTR_TYPE_A_PENDING_5: PCB interrupt Type A Pending - QME 5 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
6	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITAPRC_PCB_INTR_TYPE_A_PENDING_6: PCB interrupt Type A Pending - QME 6 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
7	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITAPRC_PCB_INTR_TYPE_A_PENDING_7: PCB interrupt Type A Pending - QME 7 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
8:63	RO	RO	RO	RO	constant=0b00000000000000000000000000000000000000000000000000000000 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1

OCB_OCI OCC PCB Interrupt Type B Pending c Register
Addr:	000000000006C684 (SCOM) 000000000006C685 (SCOM1) 00000000C0063420 (OCI) 00000000C0063428 (OCI1)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBPRC
Constant(s):
Comments:	This register is a bit vector that a PCB Power Management Interrupt Type A has been received from the respective QME (cache chiplet). The contents of the interrupt packet is accessible via the OPITASVa (A,B), or OPITASV (C,D), register set. These bits are ORed reduced to form OISR bit pmc_pcb_intr_type_A_pending which can be routed to any of the OCC Complex engines. Bits are cleared using RO_CLEAR. To inject a 1 into this register, either the a write to OPITIR or a SCOM write to the corresponding QME macro to cause a new pending payload to be sent. XDEV_EFFECT { if (OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_0 | OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_1 | OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_2 | OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_3 | OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_4 | OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_5 | OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_6 | OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_7 ) { OCB_BASE.OISR0.pmc_pcb_intr_typeA_pending = 1; } else { OCB_BASE.OISR0.pmc_pcb_intr_typeA_pending = 0; } }
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBPRC_Q_0_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBPRC_Q_1_INST.LATC.L2(1) [0]
	2	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBPRC_Q_2_INST.LATC.L2(2) [0]
	3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBPRC_Q_3_INST.LATC.L2(3) [0]
	4	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBPRC_Q_4_INST.LATC.L2(4) [0]
	5	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBPRC_Q_5_INST.LATC.L2(5) [0]
	6	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBPRC_Q_6_INST.LATC.L2(6) [0]
	7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITBPRC_Q_7_INST.LATC.L2(7) [0]
Bit(s)	SCOM	SCOM1	OCI	OCI1	Dial: Description
0	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITBPRC_PCB_INTR_TYPE_B_PENDING_0: PCB interrupt Type B Pending - QME 0 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
1	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITBPRC_PCB_INTR_TYPE_B_PENDING_1: PCB interrupt Type B Pending - QME 1 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
2	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITBPRC_PCB_INTR_TYPE_B_PENDING_2: PCB interrupt Type B Pending - QME 2 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
3	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITBPRC_PCB_INTR_TYPE_B_PENDING_3: PCB interrupt Type B Pending - QME 3 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
4	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITBPRC_PCB_INTR_TYPE_B_PENDING_4: PCB interrupt Type B Pending - QME 4 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
5	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITBPRC_PCB_INTR_TYPE_B_PENDING_5: PCB interrupt Type B Pending - QME 5 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
6	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITBPRC_PCB_INTR_TYPE_B_PENDING_6: PCB interrupt Type B Pending - QME 6 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
7	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITBPRC_PCB_INTR_TYPE_B_PENDING_7: PCB interrupt Type B Pending - QME 7 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
8:63	RO	RO	RO	RO	constant=0b00000000000000000000000000000000000000000000000000000000 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1

OCB_OCI OCC PCB Interrupt Type C Pending c Register
Addr:	000000000006C688 (SCOM) 000000000006C689 (SCOM1) 00000000C0063440 (OCI) 00000000C0063448 (OCI1)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITCPRC
Constant(s):
Comments:	This register is a bit vector that a PCB Power Management Interrupt Type A has been received from the respective QME (cache chiplet). The contents of the interrupt packet is accessible via the OPITASVa (A,B), or OPITASV (C,D), register set. These bits are ORed reduced to form OISR bit pmc_pcb_intr_type_A_pending which can be routed to any of the OCC Complex engines. Bits are cleared using RO_CLEAR. To inject a 1 into this register, either the a write to OPITIR or a SCOM write to the corresponding QME macro to cause a new pending payload to be sent. XDEV_EFFECT { if (OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_0 | OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_1 | OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_2 | OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_3 | OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_4 | OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_5 | OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_6 | OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_7 ) { OCB_BASE.OISR0.pmc_pcb_intr_typeA_pending = 1; } else { OCB_BASE.OISR0.pmc_pcb_intr_typeA_pending = 0; } }
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITCPRC_Q_0_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITCPRC_Q_1_INST.LATC.L2(1) [0]
	2	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITCPRC_Q_2_INST.LATC.L2(2) [0]
	3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITCPRC_Q_3_INST.LATC.L2(3) [0]
	4	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITCPRC_Q_4_INST.LATC.L2(4) [0]
	5	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITCPRC_Q_5_INST.LATC.L2(5) [0]
	6	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITCPRC_Q_6_INST.LATC.L2(6) [0]
	7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITCPRC_Q_7_INST.LATC.L2(7) [0]
Bit(s)	SCOM	SCOM1	OCI	OCI1	Dial: Description
0	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITCPRC_PCB_INTR_TYPE_C_PENDING_0: PCB interrupt Type C Pending - QME 0 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
1	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITCPRC_PCB_INTR_TYPE_C_PENDING_1: PCB interrupt Type C Pending - QME 1 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
2	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITCPRC_PCB_INTR_TYPE_C_PENDING_2: PCB interrupt Type C Pending - QME 2 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
3	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITCPRC_PCB_INTR_TYPE_C_PENDING_3: PCB interrupt Type C Pending - QME 3 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
4	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITCPRC_PCB_INTR_TYPE_C_PENDING_4: PCB interrupt Type C Pending - QME 4 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
5	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITCPRC_PCB_INTR_TYPE_C_PENDING_5: PCB interrupt Type C Pending - QME 5 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
6	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITCPRC_PCB_INTR_TYPE_C_PENDING_6: PCB interrupt Type C Pending - QME 6 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
7	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITCPRC_PCB_INTR_TYPE_C_PENDING_7: PCB interrupt Type C Pending - QME 7 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
8:63	RO	RO	RO	RO	constant=0b00000000000000000000000000000000000000000000000000000000 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1

OCB_OCI OCC PCB Interrupt Type D Pending c Register
Addr:	000000000006C68C (SCOM) 000000000006C68D (SCOM1) 00000000C0063460 (OCI) 00000000C0063468 (OCI1)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITDPRC
Constant(s):
Comments:	This register is a bit vector that a PCB Power Management Interrupt Type A has been received from the respective QME (cache chiplet). The contents of the interrupt packet is accessible via the OPITASVa (A,B), or OPITASV (C,D), register set. These bits are ORed reduced to form OISR bit pmc_pcb_intr_type_A_pending which can be routed to any of the OCC Complex engines. Bits are cleared using RO_CLEAR. To inject a 1 into this register, either the a write to OPITIR or a SCOM write to the corresponding QME macro to cause a new pending payload to be sent. XDEV_EFFECT { if (OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_0 | OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_1 | OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_2 | OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_3 | OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_4 | OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_5 | OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_6 | OCB_AGEN.OPITAPRc.pcb_intr_type_A_pending_7 ) { OCB_BASE.OISR0.pmc_pcb_intr_typeA_pending = 1; } else { OCB_BASE.OISR0.pmc_pcb_intr_typeA_pending = 0; } }
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITDPRC_Q_0_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITDPRC_Q_1_INST.LATC.L2(1) [0]
	2	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITDPRC_Q_2_INST.LATC.L2(2) [0]
	3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITDPRC_Q_3_INST.LATC.L2(3) [0]
	4	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITDPRC_Q_4_INST.LATC.L2(4) [0]
	5	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITDPRC_Q_5_INST.LATC.L2(5) [0]
	6	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITDPRC_Q_6_INST.LATC.L2(6) [0]
	7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITDPRC_Q_7_INST.LATC.L2(7) [0]
Bit(s)	SCOM	SCOM1	OCI	OCI1	Dial: Description
0	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITDPRC_PCB_INTR_TYPE_D_PENDING_0: PCB interrupt Type D Pending - QME 0 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
1	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITDPRC_PCB_INTR_TYPE_D_PENDING_1: PCB interrupt Type D Pending - QME 1 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
2	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITDPRC_PCB_INTR_TYPE_D_PENDING_2: PCB interrupt Type D Pending - QME 2 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
3	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITDPRC_PCB_INTR_TYPE_D_PENDING_3: PCB interrupt Type D Pending - QME 3 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
4	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITDPRC_PCB_INTR_TYPE_D_PENDING_4: PCB interrupt Type D Pending - QME 4 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
5	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITDPRC_PCB_INTR_TYPE_D_PENDING_5: PCB interrupt Type D Pending - QME 5 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
6	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITDPRC_PCB_INTR_TYPE_D_PENDING_6: PCB interrupt Type D Pending - QME 6 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
7	ROX	ROX_CLRPART	ROX	ROX_CLRPART	OCB_OCI_OPITDPRC_PCB_INTR_TYPE_D_PENDING_7: PCB interrupt Type D Pending - QME 7 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
8:63	RO	RO	RO	RO	constant=0b00000000000000000000000000000000000000000000000000000000 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1

OCB_OCI OCC PCB Interrupt Type E Pending d Register
Addr:	000000000006C690 (SCOM) 000000000006C691 (SCOM1) 00000000C0063480 (OCI) 00000000C0063488 (OCI1)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITEPRD
Constant(s):
Comments:	This register is a bit vector that a PCB Power Management Interrupt Type E has been received from the respective Core. The contents of the interrupt packet is accessible via the OPITESV register set. These bits are ORed reduced to form OISR bit pmc_pcb_intr_type_E_pending which can be routed to any of the OCC Complex engines. Bits are cleared using WO_CLEAR with a 1 in the respective bit. Note: WOX_OR is not supported. To inject a 1 into this register, either the a write to OPITIR or a SCOM write to the corresponding QME macro to cause a new pending payload to be sent. XDEV_EFFECT { if (OCB_AGEN.OPITEPRd.pcb_intr_type_E_pending_0 | OCB_AGEN.OPITEPRd.pcb_intr_type_E_pending_1 | OCB_AGEN.OPITEPRd.pcb_intr_type_E_pending_2 | OCB_AGEN.OPITEPRd.pcb_intr_type_E_pending_3 | OCB_AGEN.OPITEPRd.pcb_intr_type_E_pending_4 | OCB_AGEN.OPITEPRd.pcb_intr_type_E_pending_5 | OCB_AGEN.OPITEPRd.pcb_intr_type_E_pending_6 | OCB_AGEN.OPITEPRd.pcb_intr_type_E_pending_7 ) { OCB_BASE.OISR0.pmc_pcb_intr_typeE_pending = 1; } else { OCB_BASE.OISR0.pmc_pcb_intr_typeE_pending = 0; } }
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITEPRD_Q_0_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITEPRD_Q_1_INST.LATC.L2(1) [0]
	2	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITEPRD_Q_2_INST.LATC.L2(2) [0]
	3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITEPRD_Q_3_INST.LATC.L2(3) [0]
	4	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITEPRD_Q_4_INST.LATC.L2(4) [0]
	5	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITEPRD_Q_5_INST.LATC.L2(5) [0]
	6	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITEPRD_Q_6_INST.LATC.L2(6) [0]
	7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITEPRD_Q_7_INST.LATC.L2(7) [0]
Bit(s)	SCOM	SCOM1	OCI	OCI1	Dial: Description
0	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPITEPRD_PCB_INTR_TYPE_E_PENDING_0: PCB interrupt Type E Pending - QME 0 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
1	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPITEPRD_PCB_INTR_TYPE_E_PENDING_1: PCB interrupt Type E Pending - QME 1 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
2	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPITEPRD_PCB_INTR_TYPE_E_PENDING_2: PCB interrupt Type E Pending - QME 2 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
3	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPITEPRD_PCB_INTR_TYPE_E_PENDING_3: PCB interrupt Type E Pending - QME 3 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
4	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPITEPRD_PCB_INTR_TYPE_E_PENDING_4: PCB interrupt Type E Pending - QME 4 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
5	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPITEPRD_PCB_INTR_TYPE_E_PENDING_5: PCB interrupt Type E Pending - QME 5 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
6	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPITEPRD_PCB_INTR_TYPE_E_PENDING_6: PCB interrupt Type E Pending - QME 6 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
7	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPITEPRD_PCB_INTR_TYPE_E_PENDING_7: PCB interrupt Type E Pending - QME 7 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
8:63	RO	RO	RO	RO	constant=0b00000000000000000000000000000000000000000000000000000000 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1

OCB_OCI OCC PCB Interrupt Type F Pending d Register
Addr:	000000000006C694 (SCOM) 000000000006C695 (SCOM1) 00000000C00634A0 (OCI) 00000000C00634A8 (OCI1)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITFPRD
Constant(s):
Comments:	This register is a bit vector that a PCB Power Management Interrupt Type E has been received from the respective Core. The contents of the interrupt packet is accessible via the OPITESV register set. These bits are ORed reduced to form OISR bit pmc_pcb_intr_type_E_pending which can be routed to any of the OCC Complex engines. Bits are cleared using WO_CLEAR with a 1 in the respective bit. Note: WOX_OR is not supported. To inject a 1 into this register, either the a write to OPITIR or a SCOM write to the corresponding QME macro to cause a new pending payload to be sent. XDEV_EFFECT { if (OCB_AGEN.OPITEPRd.pcb_intr_type_E_pending_0 | OCB_AGEN.OPITEPRd.pcb_intr_type_E_pending_1 | OCB_AGEN.OPITEPRd.pcb_intr_type_E_pending_2 | OCB_AGEN.OPITEPRd.pcb_intr_type_E_pending_3 | OCB_AGEN.OPITEPRd.pcb_intr_type_E_pending_4 | OCB_AGEN.OPITEPRd.pcb_intr_type_E_pending_5 | OCB_AGEN.OPITEPRd.pcb_intr_type_E_pending_6 | OCB_AGEN.OPITEPRd.pcb_intr_type_E_pending_7 ) { OCB_BASE.OISR0.pmc_pcb_intr_typeE_pending = 1; } else { OCB_BASE.OISR0.pmc_pcb_intr_typeE_pending = 0; } }
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITFPRD_Q_0_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITFPRD_Q_1_INST.LATC.L2(1) [0]
	2	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITFPRD_Q_2_INST.LATC.L2(2) [0]
	3	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITFPRD_Q_3_INST.LATC.L2(3) [0]
	4	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITFPRD_Q_4_INST.LATC.L2(4) [0]
	5	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITFPRD_Q_5_INST.LATC.L2(5) [0]
	6	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITFPRD_Q_6_INST.LATC.L2(6) [0]
	7	TP.TPCHIP.OCC.OCI.OCB.PMC.PCBINTR.OPITFPRD_Q_7_INST.LATC.L2(7) [0]
Bit(s)	SCOM	SCOM1	OCI	OCI1	Dial: Description
0	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPITFPRD_PCB_INTR_TYPE_F_PENDING_0: PCB interrupt Type F Pending - QME 0 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
1	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPITFPRD_PCB_INTR_TYPE_F_PENDING_1: PCB interrupt Type F Pending - QME 1 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
2	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPITFPRD_PCB_INTR_TYPE_F_PENDING_2: PCB interrupt Type F Pending - QME 2 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
3	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPITFPRD_PCB_INTR_TYPE_F_PENDING_3: PCB interrupt Type F Pending - QME 3 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
4	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPITFPRD_PCB_INTR_TYPE_F_PENDING_4: PCB interrupt Type F Pending - QME 4 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
5	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPITFPRD_PCB_INTR_TYPE_F_PENDING_5: PCB interrupt Type F Pending - QME 5 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
6	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPITFPRD_PCB_INTR_TYPE_F_PENDING_6: PCB interrupt Type F Pending - QME 6 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
7	ROX	WOX_CLEAR	ROX	WOX_CLEAR	OCB_OCI_OPITFPRD_PCB_INTR_TYPE_F_PENDING_7: PCB interrupt Type F Pending - QME 7 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1
8:63	RO	RO	RO	RO	constant=0b00000000000000000000000000000000000000000000000000000000 Dial enums: INTERRUPT_NOT_PENDING=>0b0 INTERRUPT_PENDING=>0b1

OCB_OCI OCC O2S Control First Frame 0 Register
Addr:	000000000006C700 (SCOM) 00000000C0063800 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRLF0
Constant(s):
Comments:	The O2SCTRLF0 provides the length control information for the first of the p2s frames. Note: For P10, the configuration registers are common for an interface. There is no separate control per bridge.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:23	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS0.O2SCTRLF_A_Q_0_INST.LATC.L2(0:23) [000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:5	RW	RW		OCB_OCI_O2SCTRLF0_O2S_FRAME_SIZE_0: Number of data bits per individual SPI transaction (also referred to as frame) during (virtual) chip select assertion Supported values: 0x20 (32d) (virtual) Chip Select assertion duration is O2S_FRAME_SIZE + 2
6:11	RW	RW		OCB_OCI_O2SCTRLF0_O2S_OUT_COUNT1_0: Number of bits sent out avs_mdata in frame 1 of a 2 frame set (the arbitration unit) Supported values: 0x00 to O2S_FRAME_SIZE_0. Values beyond O2S_FRAME_SIZE_0 are ignored.
12:17	RW	RW		OCB_OCI_O2SCTRLF0_O2S_IN_DELAY1_0: Number of SPI clocks to wait before capturing avs_sdata input in frame 1 Supported values: 0x00 to O2S_FRAME_SIZE_0. Values beyond O2S_FRAME_SIZE_0 result in the input never being captured
18:23	RW	RW		OCB_OCI_O2SCTRLF0_O2S_IN_COUNT1_0: Number of bits captured on avs_sdata input in frame 1 Supported values: 0x00 to O2S_FRAME_SIZE_0. The actual number of bits captured is O2S_FRAME_SIZE_0 - O2S_IN_DELAY1_0
24:63	RO	RO		constant=0b0000000000000000000000000000000000000000

OCB_OCI OCC O2S Control Second Frame 0 Register
Addr:	000000000006C701 (SCOM) 00000000C0063808 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRLS0
Constant(s):
Comments:	The O2SCTRLS0 provides the length control information for the second of the P2S frames
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:17	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS0.O2SCTRLS_A_Q_0_INST.LATC.L2(0:17) [000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:5	RW	RW		OCB_OCI_O2SCTRLS0_O2S_OUT_COUNT2_0: Number of bits sent out avs_mdata in frame 2 of a 2 frame set (the arbitration unit) Supported values: 0x00 to O2S_FRAME_SIZE_0. Values beyond O2S_FRAME_SIZE_0 are ignored.
6:11	RW	RW		OCB_OCI_O2SCTRLS0_O2S_IN_DELAY2_0: Number of SPI clocks to wait before capturing avs_sdata input in subframe 2 Supported values: 0x00 to O2S_FRAME_SIZE_0. Values beyond O2S_FRAME_SIZE_0 result in the input never being captured
12:17	RW	RW		OCB_OCI_O2SCTRLS0_O2S_IN_COUNT2_0: Number of bits captured on avs_sdata input in subframe 2 Supported values: 0x00 to O2S_FRAME_SIZE_0. The actual number of bits captured is O2S_FRAME_SIZE_0 - O2S_IN_DELAY2_0.
18:63	RO	RO		constant=0b0000000000000000000000000000000000000000000000

OCB_OCI OCC O2S Control1 0 Register
Addr:	000000000006C702 (SCOM) 00000000C0063810 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRL10
Constant(s):
Comments:	The O2SCTRL10 provides control bits for the O2S bridge interface
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS0.O2SCTRL1_A_Q_0_INST.LATC.L2(0:26) [000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	RW	RW		OCB_OCI_O2SCTRL10_O2S_BRIDGE_ENABLE_0_A: if 1 the OCI2SPI bridge A can be used to control the SPI interface If 0, the OCI2SPI is forced to the reset state. Note: if the Bridge is presently active (os2_in_progress+E147 = 1, the hard reset can truncate on- going operations and leave the SPIVID in an indeterminate state.
1	RW	RW		OCB_OCI_O2SCTRL10_O2S_BRIDGE_ENABLE_0_B: if 1 the OCI2SPI bridge B can be used to control the SPI interface If 0, the OCI2SPI is forced to the reset state. Note: if the Bridge is presently active (os2_in_progress = 1, the hard reset can truncate on-going operations and leave the SPIVID in an indeterminate state.
2:3	RW	RW		OCB_OCI_O2SCTRL10_RESERVED_2_3: Reserved bits.
4:13	RW	RW		OCB_OCI_O2SCTRL10_O2S_CLOCK_DIVIDER_0: SPI clock speed divider to divide the nest_nclk/4 mesh clock, which results in a divider = (nest_freq/ (SPI_freq*8))-1 For a 2.4GHz nest clock, this means that the SPI clk can be theoretically adjusted between 600MHz and 0.29MHz (cycle time 1.66ns...3.41us, in 1.66ns steps). However, a practical range is 0.5...25MHz.
14:16	RW	RW		OCB_OCI_O2SCTRL10_O2SCTRL10_RESERVED_14_16: Reserved for Number of Frames
17	RW	RW		OCB_OCI_O2SCTRL10_O2S_NR_OF_FRAMES_0: Specifies the number of frames sent in the frame set (# of frames before the arbitration unit rearbitrates). 0: 1 frame 1: 2 frames
18:19	RW	RW		OCB_OCI_O2SCTRL10_RESERVED_18_19: Reserved bits.
20:26	RW	RW		OCB_OCI_O2SCTRL10_SLAVE_DATA_SAMPLE_DELAY: How many clocks to wait till sampling the slave data. This delay value is based on OCC 4to1 clocks.
27:63	RO	RO		constant=0b0000000000000000000000000000000000000

OCB_OCI OCC O2S Control2 0 Register
Addr:	000000000006C703 (SCOM) 00000000C0063818 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRL20
Constant(s):
Comments:	The O2SCTRL20 provides timing information for the O2S Bridge
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS0.O2SCTRL2_A_Q_0_INST.LATC.L2(0:15) [0000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:15	RW	RW		OCB_OCI_O2SCTRL20_O2S_INTER_FRAME_DELAY_0: Delay between two frames of a two command set as measured from the end of the last bit of the first frame until the chip select of the second frame is asserted. Delay is computed as: (value * SPI clock) 0x00000: Wait 1 SPI Clock 0x00001 - 0x1FFFF: value = number of ~SPI Clocks Max. delay at the fastest SPI clock is 1.3ms.
16:63	RO	RO		constant=0b000000000000000000000000000000000000000000000000

OCC O2S STATUS 0A Register
Addr:	000000000006C706 (SCOM) 00000000C0063830 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SST0A
Constant(s):	PU_OCB_OCI_O2SST0A
Comments:	The O2SST0A displays the current status about SPI-related activities.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS0.O2SST_A_Q_0_INST.LATC.L2(0:7) [00000000]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		OCB_OCI_O2SST0A_O2S_ONGOING_0A: Indicates that a bridge transaction is in progress of being executed. This bit is set by hardware while an operation is in progress and will be be reset by hardware when the operation is complete.
1:4	RO	RO		OCB_OCI_O2SST0A_O2SST0A_RESERVED_1_4: Implemented but not used
5	ROX	ROX		OCB_OCI_O2SST0A_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_0A: Indicates that firmware attempted to perform an write to either the O2S_R/WDATA_REG while the o2s bridge is busy. This will cause undefined bridge behavior. This bit is sticky and is cleared with O2S_CLEAR_STICKY_BITS_0A.
6	RO	RO		OCB_OCI_O2SST0A_O2SST0A_RESERVED_6: Implemented but not used
7	ROX	ROX		OCB_OCI_O2SST0A_O2S_FSM_ERR_0A: Indicates a catastrophic FSM error in the OCI2SPI control FSM. This bit is sticky and is cleared with O2S_CLEAR_STICKY_BITS_0A.
8:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000

OCC O2S Command Reg 0A Register
Addr:	000000000006C707 (SCOM) 00000000C0063838 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCMD0A
Constant(s):	PU_OCB_OCI_O2SCMD0A
Comments:	The O2SCMD0A provides the means to clear the sticky bits in O2SST0A
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:1	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS0.O2SCMD_A_Q_0_INST.LATC.L2(0:1) [00]
Bit(s)	SCOM	OCI		Dial: Description
0	RW	RW		OCB_OCI_O2SCMD0A_O2SCMD0A_RESERVED_0: Implemented but not used
1	RWX	RWX		OCB_OCI_O2SCMD0A_O2S_CLEAR_STICKY_BITS_0A: if set to 1, all sticky bits in O2S_STATUS_REG_0A are cleared. WRITE_EFFECT { if (O2S_CLEAR_STICKY_BITS_0A==1) { O2SST0A.O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_0A=0; O2SST0A.O2S_FSM_ERR_0A=0; } } //
2:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000000000

OCC O2S WDATA 0A Register
Addr:	000000000006C708 (SCOM) 00000000C0063840 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SWD0A
Constant(s):	PU_OCB_OCI_O2SWD0A
Comments:	The O2SWD0A register is used for sending an AVSBus command through the o2s bridge. Note that a write to this register starts the AVSBus transaction (read or write), if enable_o2s_bridge_0{n} is set.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS0.O2SWD_A_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RW	RW		OCB_OCI_O2SWD0A_O2S_WDATA_0A: SPI send data packet WRITE_EFFECT { O2SST0A.O2S_ONGOING_0A=1; } AFTER_DELAY[large] { O2SST0A.O2S_ONGOING_0A=0; } // Set and clear ONGOING
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC O2S RDATA 0A Register
Addr:	000000000006C709 (SCOM) 00000000C0063848 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SRD0A
Constant(s):	PU_OCB_OCI_O2SRD0A
Comments:	The O2SDR0A register is used for the read data of the O2S bridge. After the o2s_ongoing bit has dropped, the read values are available in O2SDR0A.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS0.O2SRD_A_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_O2SRD0A_O2S_RDATA_0A: 8 bit SPI receive data packet, duplicated in bits 8..15 and 16..23., plus 8 bit CRC. CRC is checked in SPI master if spivid_crc_check_en = 1. If spivid_majority_vote_en = 1, bits 0..7, contain the corrected result, duplicated in bits 8..15 and 16..23.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC O2S STATUS 0B Register
Addr:	000000000006C716 (SCOM) 00000000C00638B0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SST0B
Constant(s):	PU_OCB_OCI_O2SST0B
Comments:	The O2SST0A displays the current status about SPI-related activities.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS0.O2SST_B_Q_0_INST.LATC.L2(0:7) [00000000]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		OCB_OCI_O2SST0B_O2S_ONGOING_0B: Indicates that a bridge transaction is in progress of being executed. This bit is set by hardware while an operation is in progress and will be be reset by hardware when the operation is complete.
1:4	RO	RO		OCB_OCI_O2SST0B_O2SST0B_RESERVED_1_4: Implemented but not used
5	ROX	ROX		OCB_OCI_O2SST0B_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_0B: Indicates that firmware attempted to perform an write to either the O2S_R/WDATA_REG while the o2s bridge is busy. This will cause undefined bridge behavior. This bit is sticky and is cleared with O2S_CLEAR_STICKY_BITS_0B.
6	RO	RO		OCB_OCI_O2SST0B_O2SST0B_RESERVED_6: Implemented but not used
7	ROX	ROX		OCB_OCI_O2SST0B_O2S_FSM_ERR_0B: Indicates a catastrophic FSM error in the OCI2SPI control FSM. This bit is sticky and is cleared with O2S_CLEAR_STICKY_BITS_0B.
8:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000

OCC O2S Command Reg 0B Register
Addr:	000000000006C717 (SCOM) 00000000C00638B8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCMD0B
Constant(s):	PU_OCB_OCI_O2SCMD0B
Comments:	The O2SCMD0A provides the means to clear the sticky bits in O2SST0A
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:1	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS0.O2SCMD_B_Q_0_INST.LATC.L2(0:1) [00]
Bit(s)	SCOM	OCI		Dial: Description
0	RW	RW		OCB_OCI_O2SCMD0B_O2SCMD0B_RESERVED_0: Implemented but not used
1	RWX	RWX		OCB_OCI_O2SCMD0B_O2S_CLEAR_STICKY_BITS_0B: if set to 1, all sticky bits in O2S_STATUS_REG_0B are cleared. WRITE_EFFECT { if (O2S_CLEAR_STICKY_BITS_0B==1) { O2SST0B.O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_0B=0; O2SST0B.O2S_FSM_ERR_0B=0; } } //
2:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000000000

OCC O2S WDATA 0B Register
Addr:	000000000006C718 (SCOM) 00000000C00638C0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SWD0B
Constant(s):	PU_OCB_OCI_O2SWD0B
Comments:	The O2SWD0A register is used for sending an AVSBus command through the o2s bridge. Note that a write to this register starts the AVSBus transaction (read or write), if enable_o2s_bridge_0{n} is set.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS0.O2SWD_B_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RW	RW		OCB_OCI_O2SWD0B_O2S_WDATA_0B: SPI send data packet WRITE_EFFECT { O2SST0B.O2S_ONGOING_0B=1; } AFTER_DELAY[large] { O2SST0B.O2S_ONGOING_0B=0; } // Set and clear ONGOING
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC O2S RDATA 0B Register
Addr:	000000000006C719 (SCOM) 00000000C00638C8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SRD0B
Constant(s):	PU_OCB_OCI_O2SRD0B
Comments:	The O2SDR0A register is used for the read data of the O2S bridge. After the o2s_ongoing bit has dropped, the read values are available in O2SDR0A.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS0.O2SRD_B_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_O2SRD0B_O2S_RDATA_0B: 8 bit SPI receive data packet, duplicated in bits 8..15 and 16..23., plus 8 bit CRC. CRC is checked in SPI master if spivid_crc_check_en = 1. If spivid_majority_vote_en = 1, bits 0..7, contain the corrected result, duplicated in bits 8..15 and 16..23.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCC O2S Control First Frame 1 Register
Addr:	000000000006C720 (SCOM) 00000000C0063900 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRLF1
Constant(s):
Comments:	The O2SCTRLF0 provides the length control information for the first of the p2s frames. Note: For P10, the configuration registers are common for an interface. There is no separate control per bridge.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:23	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS1.O2SCTRLF_A_Q_0_INST.LATC.L2(0:23) [000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:5	RW	RW		OCB_OCI_O2SCTRLF1_O2S_FRAME_SIZE_1: Number of data bits per individual SPI transaction (also referred to as frame) during (virtual) chip select assertion Supported values: 0x20 (32d) (virtual) Chip Select assertion duration is O2S_FRAME_SIZE + 2
6:11	RW	RW		OCB_OCI_O2SCTRLF1_O2S_OUT_COUNT1_1: Number of bits sent out avs_mdata in frame 1 of a 2 frame set (the arbitration unit) Supported values: 0x00 to O2S_FRAME_SIZE_1. Values beyond O2S_FRAME_SIZE_1 are ignored.
12:17	RW	RW		OCB_OCI_O2SCTRLF1_O2S_IN_DELAY1_1: Number of SPI clocks to wait before capturing avs_sdata input in frame 1 Supported values: 0x00 to O2S_FRAME_SIZE_1. Values beyond O2S_FRAME_SIZE_1 result in the input never being captured
18:23	RW	RW		OCB_OCI_O2SCTRLF1_O2S_IN_COUNT1_1: Number of bits captured on avs_sdata input in frame 1 Supported values: 0x00 to O2S_FRAME_SIZE_1. The actual number of bits captured is O2S_FRAME_SIZE_1 - O2S_IN_DELAY1_1
24:63	RO	RO		constant=0b0000000000000000000000000000000000000000

OCB_OCI OCC O2S Control Second Frame 1 Register
Addr:	000000000006C721 (SCOM) 00000000C0063908 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRLS1
Constant(s):
Comments:	The O2SCTRLS0 provides the length control information for the second of the P2S frames
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:17	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS1.O2SCTRLS_A_Q_0_INST.LATC.L2(0:17) [000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:5	RW	RW		OCB_OCI_O2SCTRLS1_O2S_OUT_COUNT2_1: Number of bits sent out avs_mdata in frame 2 of a 2 frame set (the arbitration unit) Supported values: 0x00 to O2S_FRAME_SIZE_1. Values beyond O2S_FRAME_SIZE_1 are ignored.
6:11	RW	RW		OCB_OCI_O2SCTRLS1_O2S_IN_DELAY2_1: Number of SPI clocks to wait before capturing avs_sdata input in subframe 2 Supported values: 0x00 to O2S_FRAME_SIZE_1. Values beyond O2S_FRAME_SIZE_1 result in the input never being captured
12:17	RW	RW		OCB_OCI_O2SCTRLS1_O2S_IN_COUNT2_1: Number of bits captured on avs_sdata input in subframe 2 Supported values: 0x00 to O2S_FRAME_SIZE_1. The actual number of bits captured is O2S_FRAME_SIZE_1 - O2S_IN_DELAY2_1.
18:63	RO	RO		constant=0b0000000000000000000000000000000000000000000000

OCB_OCI OCC O2S Control1 1 Register
Addr:	000000000006C722 (SCOM) 00000000C0063910 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRL11
Constant(s):
Comments:	The O2SCTRL10 provides control bits for the O2S bridge interface
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS1.O2SCTRL1_A_Q_0_INST.LATC.L2(0:26) [000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	RW	RW		OCB_OCI_O2SCTRL11_O2S_BRIDGE_ENABLE_1_A: if 1 the OCI2SPI bridge A can be used to control the SPI interface If 0, the OCI2SPI is forced to the reset state. Note: if the Bridge is presently active (os2_in_progress+E147 = 1, the hard reset can truncate on- going operations and leave the SPIVID in an indeterminate state.
1	RW	RW		OCB_OCI_O2SCTRL11_O2S_BRIDGE_ENABLE_1_B: if 1 the OCI2SPI bridge B can be used to control the SPI interface If 0, the OCI2SPI is forced to the reset state. Note: if the Bridge is presently active (os2_in_progress = 1, the hard reset can truncate on-going operations and leave the SPIVID in an indeterminate state.
2:3	RW	RW		OCB_OCI_O2SCTRL11_RESERVED_2_3: Reserved bits.
4:13	RW	RW		OCB_OCI_O2SCTRL11_O2S_CLOCK_DIVIDER_1: SPI clock speed divider to divide the nest_nclk/4 mesh clock, which results in a divider = (nest_freq/ (SPI_freq*8))-1 For a 2.4GHz nest clock, this means that the SPI clk can be theoretically adjusted between 600MHz and 0.29MHz (cycle time 1.66ns...3.41us, in 1.66ns steps). However, a practical range is 0.5...25MHz.
14:16	RW	RW		OCB_OCI_O2SCTRL11_O2SCTRL11_RESERVED_14_16: Reserved for Number of Frames
17	RW	RW		OCB_OCI_O2SCTRL11_O2S_NR_OF_FRAMES_1: Specifies the number of frames sent in the frame set (# of frames before the arbitration unit rearbitrates). 0: 1 frame 1: 2 frames
18:19	RW	RW		OCB_OCI_O2SCTRL11_RESERVED_18_19: Reserved bits.
20:26	RW	RW		OCB_OCI_O2SCTRL11_SLAVE_DATA_SAMPLE_DELAY: How many clocks to wait till sampling the slave data. This delay value is based on OCC 4to1 clocks.
27:63	RO	RO		constant=0b0000000000000000000000000000000000000

OCB_OCI OCC O2S Control2 1 Register
Addr:	000000000006C723 (SCOM) 00000000C0063918 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRL21
Constant(s):
Comments:	The O2SCTRL20 provides timing information for the O2S Bridge
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS1.O2SCTRL2_A_Q_0_INST.LATC.L2(0:15) [0000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:15	RW	RW		OCB_OCI_O2SCTRL21_O2S_INTER_FRAME_DELAY_1: Delay between two frames of a two command set as measured from the end of the last bit of the first frame until the chip select of the second frame is asserted. Delay is computed as: (value * SPI clock) 0x00000: Wait 1 SPI Clock 0x00001 - 0x1FFFF: value = number of ~SPI Clocks Max. delay at the fastest SPI clock is 1.3ms.
16:63	RO	RO		constant=0b000000000000000000000000000000000000000000000000

OCC O2S STATUS 1A Register
Addr:	000000000006C726 (SCOM) 00000000C0063930 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SST1A
Constant(s):	PU_OCB_OCI_O2SST1A
Comments:	The O2SST1A displays the current status about SPI-related activities.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS1.O2SST_A_Q_0_INST.LATC.L2(0:7) [00000000]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		OCB_OCI_O2SST1A_O2S_ONGOING_1A: Indicates that a bridge transaction is in progress of being executed. This bit is set by hardware while an operation is in progress and will be be reset by hardware when the operation is complete.
1:4	RO	RO		OCB_OCI_O2SST1A_O2SST1A_RESERVED_1_4: Implemented but not used
5	ROX	ROX		OCB_OCI_O2SST1A_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_1A: Indicates that firmware attempted to perform an write to either the O2S_R/WDATA_REG while the o2s bridge is busy. This will cause undefined bridge behavior. This bit is sticky and is cleared with O2S_CLEAR_STICKY_BITS_1A.
6	RO	RO		OCB_OCI_O2SST1A_O2SST1A_RESERVED_6: Implemented but not used
7	ROX	ROX		OCB_OCI_O2SST1A_O2S_FSM_ERR_1A: Indicates a catastrophic FSM error in the OCI2SPI control FSM. This bit is sticky and is cleared with O2S_CLEAR_STICKY_BITS_1A.
8:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000

OCC O2S Command Reg 1A Register
Addr:	000000000006C727 (SCOM) 00000000C0063938 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCMD1A
Constant(s):	PU_OCB_OCI_O2SCMD1A
Comments:	The O2SCMD1A provides the means to clear the sticky bits in O2SST1A
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:1	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS1.O2SCMD_A_Q_0_INST.LATC.L2(0:1) [00]
Bit(s)	SCOM	OCI		Dial: Description
0	RW	RW		OCB_OCI_O2SCMD1A_O2SCMD1A_RESERVED_0: Implemented but not used
1	RWX	RWX		OCB_OCI_O2SCMD1A_O2S_CLEAR_STICKY_BITS_1A: if set to 1, all sticky bits in O2S_STATUS_REG_1A are cleared. WRITE_EFFECT { if (O2S_CLEAR_STICKY_BITS_1A==1) { O2SST1A.O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_1A=0; O2SST1A.O2S_FSM_ERR_1A=0; } } //
2:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000000000

OCC O2S WDATA 1A Register
Addr:	000000000006C728 (SCOM) 00000000C0063940 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SWD1A
Constant(s):	PU_OCB_OCI_O2SWD1A
Comments:	The O2SWD1A register is used for sending an AVSBus command through the o2s bridge. Note that a write to this register starts the AVSBus transaction (read or write), if enable_o2s_bridge_1{n} is set.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS1.O2SWD_A_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RW	RW		OCB_OCI_O2SWD1A_O2S_WDATA_1A: SPI send data packet WRITE_EFFECT { O2SST1A.O2S_ONGOING_1A=1; } AFTER_DELAY[large] { O2SST1A.O2S_ONGOING_1A=0; } // Set and clear ONGOING
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC O2S RDATA 1A Register
Addr:	000000000006C729 (SCOM) 00000000C0063948 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SRD1A
Constant(s):	PU_OCB_OCI_O2SRD1A
Comments:	The O2SDR1A register is used for the read data of the O2S bridge. After the o2s_ongoing bit has dropped, the read values are available in O2SDR1A.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS1.O2SRD_A_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_O2SRD1A_O2S_RDATA_1A: 8 bit SPI receive data packet, duplicated in bits 8..15 and 16..23., plus 8 bit CRC. CRC is checked in SPI master if spivid_crc_check_en = 1. If spivid_majority_vote_en = 1, bits 0..7, contain the corrected result, duplicated in bits 8..15 and 16..23.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC O2S STATUS 1B Register
Addr:	000000000006C736 (SCOM) 00000000C00639B0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SST1B
Constant(s):	PU_OCB_OCI_O2SST1B
Comments:	The O2SST1A displays the current status about SPI-related activities.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS1.O2SST_B_Q_0_INST.LATC.L2(0:7) [00000000]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		OCB_OCI_O2SST1B_O2S_ONGOING_1B: Indicates that a bridge transaction is in progress of being executed. This bit is set by hardware while an operation is in progress and will be be reset by hardware when the operation is complete.
1:4	RO	RO		OCB_OCI_O2SST1B_O2SST1B_RESERVED_1_4: Implemented but not used
5	ROX	ROX		OCB_OCI_O2SST1B_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_1B: Indicates that firmware attempted to perform an write to either the O2S_R/WDATA_REG while the o2s bridge is busy. This will cause undefined bridge behavior. This bit is sticky and is cleared with O2S_CLEAR_STICKY_BITS_1B.
6	RO	RO		OCB_OCI_O2SST1B_O2SST1B_RESERVED_6: Implemented but not used
7	ROX	ROX		OCB_OCI_O2SST1B_O2S_FSM_ERR_1B: Indicates a catastrophic FSM error in the OCI2SPI control FSM. This bit is sticky and is cleared with O2S_CLEAR_STICKY_BITS_1B.
8:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000

OCC O2S Command Reg 1B Register
Addr:	000000000006C737 (SCOM) 00000000C00639B8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCMD1B
Constant(s):	PU_OCB_OCI_O2SCMD1B
Comments:	The O2SCMD1A provides the means to clear the sticky bits in O2SST1A
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:1	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS1.O2SCMD_B_Q_0_INST.LATC.L2(0:1) [00]
Bit(s)	SCOM	OCI		Dial: Description
0	RW	RW		OCB_OCI_O2SCMD1B_O2SCMD1B_RESERVED_0: Implemented but not used
1	RWX	RWX		OCB_OCI_O2SCMD1B_O2S_CLEAR_STICKY_BITS_1B: if set to 1, all sticky bits in O2S_STATUS_REG_1B are cleared. WRITE_EFFECT { if (O2S_CLEAR_STICKY_BITS_1B==1) { O2SST1B.O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_1B=0; O2SST1B.O2S_FSM_ERR_1B=0; } } //
2:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000000000

OCC O2S WDATA 1B Register
Addr:	000000000006C738 (SCOM) 00000000C00639C0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SWD1B
Constant(s):	PU_OCB_OCI_O2SWD1B
Comments:	The O2SWD1A register is used for sending an AVSBus command through the o2s bridge. Note that a write to this register starts the AVSBus transaction (read or write), if enable_o2s_bridge_1{n} is set.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS1.O2SWD_B_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RW	RW		OCB_OCI_O2SWD1B_O2S_WDATA_1B: SPI send data packet WRITE_EFFECT { O2SST1B.O2S_ONGOING_1B=1; } AFTER_DELAY[large] { O2SST1B.O2S_ONGOING_1B=0; } // Set and clear ONGOING
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC O2S RDATA 1B Register
Addr:	000000000006C739 (SCOM) 00000000C00639C8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SRD1B
Constant(s):	PU_OCB_OCI_O2SRD1B
Comments:	The O2SDR1A register is used for the read data of the O2S bridge. After the o2s_ongoing bit has dropped, the read values are available in O2SDR1A.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS1.O2SRD_B_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_O2SRD1B_O2S_RDATA_1B: 8 bit SPI receive data packet, duplicated in bits 8..15 and 16..23., plus 8 bit CRC. CRC is checked in SPI master if spivid_crc_check_en = 1. If spivid_majority_vote_en = 1, bits 0..7, contain the corrected result, duplicated in bits 8..15 and 16..23.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCC O2S Control First Frame 2 Register
Addr:	000000000006C740 (SCOM) 00000000C0063A00 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRLF2
Constant(s):
Comments:	The O2SCTRLF0 provides the length control information for the first of the p2s frames. Note: For P10, the configuration registers are common for an interface. There is no separate control per bridge.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:23	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS2.O2SCTRLF_A_Q_0_INST.LATC.L2(0:23) [000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:5	RW	RW		OCB_OCI_O2SCTRLF2_O2S_FRAME_SIZE_2: Number of data bits per individual SPI transaction (also referred to as frame) during (virtual) chip select assertion Supported values: 0x20 (32d) (virtual) Chip Select assertion duration is O2S_FRAME_SIZE + 2
6:11	RW	RW		OCB_OCI_O2SCTRLF2_O2S_OUT_COUNT1_2: Number of bits sent out avs_mdata in frame 1 of a 2 frame set (the arbitration unit) Supported values: 0x00 to O2S_FRAME_SIZE_2. Values beyond O2S_FRAME_SIZE_2 are ignored.
12:17	RW	RW		OCB_OCI_O2SCTRLF2_O2S_IN_DELAY1_2: Number of SPI clocks to wait before capturing avs_sdata input in frame 1 Supported values: 0x00 to O2S_FRAME_SIZE_2. Values beyond O2S_FRAME_SIZE_2 result in the input never being captured
18:23	RW	RW		OCB_OCI_O2SCTRLF2_O2S_IN_COUNT1_2: Number of bits captured on avs_sdata input in frame 1 Supported values: 0x00 to O2S_FRAME_SIZE_2. The actual number of bits captured is O2S_FRAME_SIZE_2 - O2S_IN_DELAY1_2
24:63	RO	RO		constant=0b0000000000000000000000000000000000000000

OCB_OCI OCC O2S Control Second Frame 2 Register
Addr:	000000000006C741 (SCOM) 00000000C0063A08 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRLS2
Constant(s):
Comments:	The O2SCTRLS0 provides the length control information for the second of the P2S frames
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:17	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS2.O2SCTRLS_A_Q_0_INST.LATC.L2(0:17) [000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:5	RW	RW		OCB_OCI_O2SCTRLS2_O2S_OUT_COUNT2_2: Number of bits sent out avs_mdata in frame 2 of a 2 frame set (the arbitration unit) Supported values: 0x00 to O2S_FRAME_SIZE_2. Values beyond O2S_FRAME_SIZE_2 are ignored.
6:11	RW	RW		OCB_OCI_O2SCTRLS2_O2S_IN_DELAY2_2: Number of SPI clocks to wait before capturing avs_sdata input in subframe 2 Supported values: 0x00 to O2S_FRAME_SIZE_2. Values beyond O2S_FRAME_SIZE_2 result in the input never being captured
12:17	RW	RW		OCB_OCI_O2SCTRLS2_O2S_IN_COUNT2_2: Number of bits captured on avs_sdata input in subframe 2 Supported values: 0x00 to O2S_FRAME_SIZE_2. The actual number of bits captured is O2S_FRAME_SIZE_2 - O2S_IN_DELAY2_2.
18:63	RO	RO		constant=0b0000000000000000000000000000000000000000000000

OCB_OCI OCC O2S Control1 2 Register
Addr:	000000000006C742 (SCOM) 00000000C0063A10 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRL12
Constant(s):
Comments:	The O2SCTRL10 provides control bits for the O2S bridge interface
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS2.O2SCTRL1_A_Q_0_INST.LATC.L2(0:26) [000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	RW	RW		OCB_OCI_O2SCTRL12_O2S_BRIDGE_ENABLE_2_A: if 1 the OCI2SPI bridge A can be used to control the SPI interface If 0, the OCI2SPI is forced to the reset state. Note: if the Bridge is presently active (os2_in_progress+E147 = 1, the hard reset can truncate on- going operations and leave the SPIVID in an indeterminate state.
1	RW	RW		OCB_OCI_O2SCTRL12_O2S_BRIDGE_ENABLE_2_B: if 1 the OCI2SPI bridge B can be used to control the SPI interface If 0, the OCI2SPI is forced to the reset state. Note: if the Bridge is presently active (os2_in_progress = 1, the hard reset can truncate on-going operations and leave the SPIVID in an indeterminate state.
2:3	RW	RW		OCB_OCI_O2SCTRL12_RESERVED_2_3: Reserved bits.
4:13	RW	RW		OCB_OCI_O2SCTRL12_O2S_CLOCK_DIVIDER_2: SPI clock speed divider to divide the nest_nclk/4 mesh clock, which results in a divider = (nest_freq/ (SPI_freq*8))-1 For a 2.4GHz nest clock, this means that the SPI clk can be theoretically adjusted between 600MHz and 0.29MHz (cycle time 1.66ns...3.41us, in 1.66ns steps). However, a practical range is 0.5...25MHz.
14:16	RW	RW		OCB_OCI_O2SCTRL12_O2SCTRL12_RESERVED_14_16: Reserved for Number of Frames
17	RW	RW		OCB_OCI_O2SCTRL12_O2S_NR_OF_FRAMES_2: Specifies the number of frames sent in the frame set (# of frames before the arbitration unit rearbitrates). 0: 1 frame 1: 2 frames
18:19	RW	RW		OCB_OCI_O2SCTRL12_RESERVED_18_19: Reserved bits.
20:26	RW	RW		OCB_OCI_O2SCTRL12_SLAVE_DATA_SAMPLE_DELAY: How many clocks to wait till sampling the slave data. This delay value is based on OCC 4to1 clocks.
27:63	RO	RO		constant=0b0000000000000000000000000000000000000

OCB_OCI OCC O2S Control2 2 Register
Addr:	000000000006C743 (SCOM) 00000000C0063A18 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRL22
Constant(s):
Comments:	The O2SCTRL20 provides timing information for the O2S Bridge
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS2.O2SCTRL2_A_Q_0_INST.LATC.L2(0:15) [0000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:15	RW	RW		OCB_OCI_O2SCTRL22_O2S_INTER_FRAME_DELAY_2: Delay between two frames of a two command set as measured from the end of the last bit of the first frame until the chip select of the second frame is asserted. Delay is computed as: (value * SPI clock) 0x00000: Wait 1 SPI Clock 0x00001 - 0x1FFFF: value = number of ~SPI Clocks Max. delay at the fastest SPI clock is 1.3ms.
16:63	RO	RO		constant=0b000000000000000000000000000000000000000000000000

OCC O2S STATUS 2A Register
Addr:	000000000006C746 (SCOM) 00000000C0063A30 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SST2A
Constant(s):
Comments:	The O2SST2A displays the current status about SPI-related activities.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS2.O2SST_A_Q_0_INST.LATC.L2(0:7) [00000000]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		OCB_OCI_O2SST2A_O2S_ONGOING_2A: Indicates that a bridge transaction is in progress of being executed. This bit is set by hardware while an operation is in progress and will be be reset by hardware when the operation is complete.
1:4	RO	RO		OCB_OCI_O2SST2A_O2SST2A_RESERVED_1_4: Implemented but not used
5	ROX	ROX		OCB_OCI_O2SST2A_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_2A: Indicates that firmware attempted to perform an write to either the O2S_R/WDATA_REG while the o2s bridge is busy. This will cause undefined bridge behavior. This bit is sticky and is cleared with O2S_CLEAR_STICKY_BITS_2A.
6	RO	RO		OCB_OCI_O2SST2A_O2SST2A_RESERVED_6: Implemented but not used
7	ROX	ROX		OCB_OCI_O2SST2A_O2S_FSM_ERR_2A: Indicates a catastrophic FSM error in the OCI2SPI control FSM. This bit is sticky and is cleared with O2S_CLEAR_STICKY_BITS_2A.
8:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000

OCC O2S Command Reg 2A Register
Addr:	000000000006C747 (SCOM) 00000000C0063A38 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCMD2A
Constant(s):
Comments:	The O2SCMD2A provides the means to clear the sticky bits in O2SST2A
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:1	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS2.O2SCMD_A_Q_0_INST.LATC.L2(0:1) [00]
Bit(s)	SCOM	OCI		Dial: Description
0	RW	RW		OCB_OCI_O2SCMD2A_O2SCMD2A_RESERVED_0: Implemented but not used
1	RWX	RWX		OCB_OCI_O2SCMD2A_O2S_CLEAR_STICKY_BITS_2A: if set to 1, all sticky bits in O2S_STATUS_REG_2A are cleared. WRITE_EFFECT { if (O2S_CLEAR_STICKY_BITS_2A==1) { O2SST2A.O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_2A=0; O2SST2A.O2S_FSM_ERR_2A=0; } } //
2:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000000000

OCC O2S WDATA 2A Register
Addr:	000000000006C748 (SCOM) 00000000C0063A40 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SWD2A
Constant(s):
Comments:	The O2SWD2A register is used for sending an AVSBus command through the o2s bridge. Note that a write to this register starts the AVSBus transaction (read or write), if enable_o2s_bridge_2{n} is set.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS2.O2SWD_A_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RW	RW		OCB_OCI_O2SWD2A_O2S_WDATA_2A: SPI send data packet WRITE_EFFECT { O2SST2A.O2S_ONGOING_2A=1; } AFTER_DELAY[large] { O2SST2A.O2S_ONGOING_2A=0; } // Set and clear ONGOING
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC O2S RDATA 2A Register
Addr:	000000000006C749 (SCOM) 00000000C0063A48 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SRD2A
Constant(s):
Comments:	The O2SDR2A register is used for the read data of the O2S bridge. After the o2s_ongoing bit has dropped, the read values are available in O2SDR2A.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS2.O2SRD_A_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_O2SRD2A_O2S_RDATA_2A: 8 bit SPI receive data packet, duplicated in bits 8..15 and 16..23., plus 8 bit CRC. CRC is checked in SPI master if spivid_crc_check_en = 1. If spivid_majority_vote_en = 1, bits 0..7, contain the corrected result, duplicated in bits 8..15 and 16..23.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC O2S STATUS 2B Register
Addr:	000000000006C756 (SCOM) 00000000C0063AB0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SST2B
Constant(s):
Comments:	The O2SST2A displays the current status about SPI-related activities.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS2.O2SST_B_Q_0_INST.LATC.L2(0:7) [00000000]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		OCB_OCI_O2SST2B_O2S_ONGOING_2B: Indicates that a bridge transaction is in progress of being executed. This bit is set by hardware while an operation is in progress and will be be reset by hardware when the operation is complete.
1:4	RO	RO		OCB_OCI_O2SST2B_O2SST2B_RESERVED_1_4: Implemented but not used
5	ROX	ROX		OCB_OCI_O2SST2B_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_2B: Indicates that firmware attempted to perform an write to either the O2S_R/WDATA_REG while the o2s bridge is busy. This will cause undefined bridge behavior. This bit is sticky and is cleared with O2S_CLEAR_STICKY_BITS_2B.
6	RO	RO		OCB_OCI_O2SST2B_O2SST2B_RESERVED_6: Implemented but not used
7	ROX	ROX		OCB_OCI_O2SST2B_O2S_FSM_ERR_2B: Indicates a catastrophic FSM error in the OCI2SPI control FSM. This bit is sticky and is cleared with O2S_CLEAR_STICKY_BITS_2B.
8:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000

OCC O2S Command Reg 2B Register
Addr:	000000000006C757 (SCOM) 00000000C0063AB8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCMD2B
Constant(s):
Comments:	The O2SCMD2A provides the means to clear the sticky bits in O2SST2A
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:1	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS2.O2SCMD_B_Q_0_INST.LATC.L2(0:1) [00]
Bit(s)	SCOM	OCI		Dial: Description
0	RW	RW		OCB_OCI_O2SCMD2B_O2SCMD2B_RESERVED_0: Implemented but not used
1	RWX	RWX		OCB_OCI_O2SCMD2B_O2S_CLEAR_STICKY_BITS_2B: if set to 1, all sticky bits in O2S_STATUS_REG_2B are cleared. WRITE_EFFECT { if (O2S_CLEAR_STICKY_BITS_2B==1) { O2SST2B.O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_2B=0; O2SST2B.O2S_FSM_ERR_2B=0; } } //
2:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000000000

OCC O2S WDATA 2B Register
Addr:	000000000006C758 (SCOM) 00000000C0063AC0 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SWD2B
Constant(s):
Comments:	The O2SWD2A register is used for sending an AVSBus command through the o2s bridge. Note that a write to this register starts the AVSBus transaction (read or write), if enable_o2s_bridge_2{n} is set.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS2.O2SWD_B_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RW	RW		OCB_OCI_O2SWD2B_O2S_WDATA_2B: SPI send data packet WRITE_EFFECT { O2SST2B.O2S_ONGOING_2B=1; } AFTER_DELAY[large] { O2SST2B.O2S_ONGOING_2B=0; } // Set and clear ONGOING
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCC O2S RDATA 2B Register
Addr:	000000000006C759 (SCOM) 00000000C0063AC8 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SRD2B
Constant(s):
Comments:	The O2SDR2A register is used for the read data of the O2S bridge. After the o2s_ongoing bit has dropped, the read values are available in O2SDR2A.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.PMC.AVSBUS2.O2SRD_B_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_O2SRD2B_O2S_RDATA_2B: 8 bit SPI receive data packet, duplicated in bits 8..15 and 16..23., plus 8 bit CRC. CRC is checked in SPI master if spivid_crc_check_en = 1. If spivid_majority_vote_en = 1, bits 0..7, contain the corrected result, duplicated in bits 8..15 and 16..23.
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI OCC WOFCntl Interchip Control Register
Addr:	000000000006C780 (SCOM) 00000000C0063C00 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_WOFICCTRL
Constant(s):
Comments:	The WOFICCTRL register provides control bits for the WOFCTRL interchip interface
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.INTER_DCM.WOFICCTRL_Q_0_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.INTER_DCM.WOFICCTRL_Q_1_INST.LATC.L2(1) [0]
	2:22	TP.TPCHIP.OCC.OCI.OCB.INTER_DCM.WOFICCTRL_Q_2_INST.LATC.L2(2:22) [000000000000000000000]
	23	TP.TPCHIP.OCC.OCI.OCB.INTER_DCM.WOFICCTRL_Q_23_INST.LATC.L2(23) [0]
Bit(s)	SCOM	OCI		Dial: Description
0	RW	RW		OCB_OCI_WOFICCTRL_INTERCHIP_LINK_ENABLE: Enable the interchip communication. When set to 1, the transmit and receive fsms are enabled.
1	WO_2P	WO_2P		OCB_OCI_WOFICCTRL_INTERCHIP_LINK_RESET: Hard reset of the send and receive FSMs back to an idle state
2	RW	RW		OCB_OCI_WOFICCTRL_INTERCHIP_CPOL: Interchip clock polarity. Should be set to CPOL=0
3	RW	RW		OCB_OCI_WOFICCTRL_INTERCHIP_CPHA: Interchip clock phase (CPHA=0 means to change/sample values of data signals on the first edge, otherwise on 2nd)
4:13	RW	RW		OCB_OCI_WOFICCTRL_INTERCHIP_CLOCK_DIVIDER: Interchip clock speed divider to divide the tpconst_gckn/4 mesh clock, which results in a interchip frequency of tpconst_gckn/(2*(clock_divider+1)). Note: Only use values > 2 For a 2.005 GHz tpconst clock, this means that the interchip clk can be theoretically adjusted between 250Mhz and 0.97MHz (cycle time 1.99ns...1.02us, in ~1ns steps). However, a practical range is 0.5...250MHz.
14	RW	RW		OCB_OCI_WOFICCTRL_RESERVED_14: Reserved
15	RW	RW		OCB_OCI_WOFICCTRL_INTERCHIP_WRAP_ENABLE: Enable wrap mode for single chip testing.
16	RW	RW		OCB_OCI_WOFICCTRL_INTERCHIP_INTERFACE_ENABLE_NORTH: Enable the tx pins on the north interface. This also selects the north rx interface for receiving data
17	RW	RW		OCB_OCI_WOFICCTRL_INTERCHIP_INTERFACE_ENABLE_SOUTH: Enable the tx pins on the south interface. This also selects the south rx interface for receiving data
18	RW	RW		OCB_OCI_WOFICCTRL_INTERCHIP_SYNC_EN: Enable Sync pin toggle on each frame (is this needed?)
19	RW	RW		OCB_OCI_WOFICCTRL_RESERVED_19: Reserved
20	RW	RW		OCB_OCI_WOFICCTRL_INTERCHIP_ECC_GEN_EN: Enable ECC generation. This will produce an 8b ECC of an assumed 64b payload using 64/72 SEC/DED encoding. If ECC generation is disabled, the contents of that byte depends on the command.
21	RW	RW		OCB_OCI_WOFICCTRL_INTERCHIP_ECC_CHECK_EN: Enable ECC checking of the 8b ECC of an assumed 64b payload using 64/72 SEC/DED encoding. If ECC generation is disabled, this check does not occur.
22	RW	RW		OCB_OCI_WOFICCTRL_RX_FSM_FREEZE_ON_UE: Freeze the rx_fsm on a detected UE to preserve the data for debug
23	WO_2P	WO_2P		OCB_OCI_WOFICCTRL_INTERCHIP_RESET_ECC_ERR: Reset the WOFICSTAT[interchip_ecc_ue] and WFINSTAT[intechip_ecc_ce] indicators
24:63	RO	RO		constant=0b0000000000000000000000000000000000000000

OCB_OCI OCC WOFCntl Interchip Ping Register
Addr:	000000000006C781 (SCOM) 00000000C0063C08 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_WOFICPING
Constant(s):
Comments:	The WOFICPING register provides control for the ping send and receive to be used for WOFCNTL interface characterization. NOTE: When interchip_ping_master or interchip_ping_slave is set, writes to the WOFICWD register do not generate a communication packet. Pings and write messages are mutually exclusive, as there is no arbitration for this interface.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.INTER_DCM.WOFICPINGA_Q_0_INST.LATC.L2(0) [0]
	5:7	TP.TPCHIP.OCC.OCI.OCB.INTER_DCM.WOFICPINGB_Q_5_INST.LATC.L2(5:7) [000]
Bit(s)	SCOM	OCI		Dial: Description
0	RWX	RWX		interchip_ping_send
1	RW	RW		interchip_ping_mode
2	RW	RW		interchip_ping_master
3	RW	RW		interchip_ping_slave
4	WO_1P	WO_1P		interchip_ping_detect_clear
5:7	RW	RW		interchip_ping_dataop
8:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000

OCB_OCI OCC WOFCntl Interchip Status Register
Addr:	000000000006C782 (SCOM) 00000000C0063C10 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_WOFICSTAT
Constant(s):
Comments:	The WOFICSTAT register provides the current status about the interchip interface
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.INTER_DCM.WOFICSTAT_Q_0_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.INTER_DCM.WOFICSTAT_Q_1_INST.LATC.L2(1) [0]
	2:3	TP.TPCHIP.OCC.OCI.OCB.INTER_DCM.WOFICSTAT_Q_2_INST.LATC.L2(2:3) [00]
	4	TP.TPCHIP.OCC.OCI.OCB.INTER_DCM.WOFICSTAT_Q_4_INST.LATC.L2(4) [0]
	5	TP.TPCHIP.OCC.OCI.OCB.INTER_DCM.WOFICSTAT_Q_5_INST.LATC.L2(5) [0]
	6	TP.TPCHIP.OCC.OCI.OCB.INTER_DCM.WOFICSTAT_Q_6_INST.LATC.L2(6) [0]
	7	TP.TPCHIP.OCC.OCI.OCB.INTER_DCM.WOFICSTAT_Q_7_INST.LATC.L2(7) [0]
	8:15	TP.TPCHIP.OCC.OCI.OCB.INTER_DCM.WOFICSTAT_Q_8_INST.LATC.L2(8:15) [00000000]
	16:23	TP.TPCHIP.OCC.OCI.OCB.INTER_DCM.WOFICSTAT_Q_16_INST.LATC.L2(16:23) [00000000]
	24:31	TP.TPCHIP.OCC.OCI.OCB.INTER_DCM.WOFICSTAT_Q_24_INST.LATC.L2(24:31) [00000000]
	32:47	TP.TPCHIP.OCC.OCI.OCB.INTER_DCM.WOFICSTAT_Q_32_INST.LATC.L2(32:47) [0000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		OCB_OCI_WOFICSTAT_INTERCHIP_ECC_UE: if this bit gets asserted, an uncorrectable ECC error was detected by the interchip interface (only valid, if interchip_ecc_check_en=1). This field is set on the first ue and remains sticky until reset by WOFICCTRL[interchip_reset_ecc_err].
1	ROX	ROX		OCB_OCI_WOFICSTAT_INTERCHIP_ECC_CE: if this bit gets asserted, an uncorrectable ECC error was detected by the interchip interface (only valid, if interchip_ecc_check_en=1). This field is set on the first ue and remains sticky until reset by WOFICCTRL[interchip_reset_ecc_err].
2:3	ROX	ROX		OCB_OCI_WOFICSTAT_RESERVED_2_3: Future error indicators
4	ROX	ROX		OCB_OCI_WOFICSTAT_INTERCHIP_TX_ONGOING: Asserted if the send_fsm is currently transmitting a packet XDEV_EFFECT { if (OCB_AGEN.OCB_OCI_WOFICSTAT.INTERCHIP_TX_ONGOING=1) OCB_BASE.OCB_OCI_OISR1.DCM_INTF_ONGOING=1; else OCB_BASE.OCB_OCI_OISR1.DCM_INTF_ONGOING= OCB_AGEN.OCB_OCI_WOFICSTAT.INTERCHIP_RX_ONGOING; }
5	ROX	ROX		OCB_OCI_WOFICSTAT_INTERCHIP_RX_ONGOING: Asserted if the rcv_fsm is currently receiving a packet XDEV_EFFECT { if (OCB_AGEN.OCB_OCI_WOFICSTAT.INTERCHIP_RX_ONGOING=1) OCB_BASE.OCB_OCI_OISR1.DCM_INTF_ONGOING=1; else OCB_BASE.OCB_OCI_OISR1.DCM_INTF_ONGOING= OCB_AGEN.OCB_OCI_WOFICSTAT.INTERCHIP_TX_ONGOING; }
6	ROX	ROX		OCB_OCI_WOFICSTAT_INTERCHIP_PING_DETECTED: if this bit gets asserted, a ping packet was detected (interchip_ping_slave=1, packet received and, if enabled, valid ECC).
7	ROX	ROX		OCB_OCI_WOFICSTAT_INTERCHIP_PING_ACK_DETECTED: if this bit gets asserted, a ping_ack packet was detected (interchip_ping_master=1, valid command decode and, if enabled, valid ECC). Note: the bit is not controlled by the setting of the interchip_mode; thus, if this bit is set when interchip_mode = 0 (slave), a firmware setup issue is probable.
8:15	ROX	ROX		OCB_OCI_WOFICSTAT_INTERCHIP_PING_DETECT_COUNT: Count the number of pick packets received This count saturates at the maximum value, and can be reset by setting interchip_ping_detect_clear. If interchip_ping_master=1, this counts the number of ping_acks detected. If interchip_ping_slave=1, this counts the number of ping packets received. This register provides characterization firmware a general count of the amoujnt of traffic that has gone over the link.
16:23	ROX	ROX		OCB_OCI_WOFICSTAT_INTERCHIP_TX_ECC: Generated ECC for the last packet sent
24:31	ROX	ROX		OCB_OCI_WOFICSTAT_INTERCHIP_RX_ECC: Captured ECC for the last packet received
32:35	ROX	ROX		OCB_OCI_WOFICSTAT_SEND_STATE_MACHINE: The current state of the send state machine
36:39	ROX	ROX		OCB_OCI_WOFICSTAT_RECV_STATE_MACHINE: The current state of the receive state machine
40:43	ROX	ROX		OCB_OCI_WOFICSTAT_PING_MST_STATE_MACHINE: The current state of the ping master state machine
44:47	ROX	ROX		OCB_OCI_WOFICSTAT_PING_SLV_STATE_MACHINE: The current state of the ping slave state machine
48:63	RO	RO		constant=0b0000000000000000

OCB_OCI OCC WOFCntl Read Data Register
Addr:	000000000006C783 (SCOM) 00000000C0063C18 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_WOFICRD
Constant(s):
Comments:	WOFICRD contains the received data packet from the WOFCntl interface
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.OCC.OCI.OCB.INTER_DCM.WOFICRD_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:63	ROX	ROX		OCB_OCI_WOFICRD_WOFCNTL_RDDATA: Data received on WOFCntl interface WRITE_EFFECT { WOFICSTAT.interchip_rx_ongoing=1; } AFTER_DELAY[large] { WOFICSTAT.Interchip_rx_ongoing=0; } // Set and clear ONGOING. This can only be written in sim environments

OCB_OCI OCC WOFCntl Write Data Register
Addr:	000000000006C784 (SCOM) 00000000C0063C20 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_WOFICWD
Constant(s):
Comments:	The WOFICWR is used to send a data packet to the neighbor chip in a DCM using the WOFCntl Interface
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.INTER_DCM.WOFICWD_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.OCC.OCI.OCB.INTER_DCM.WOFICWD_Q_32_INST.LATC.L2(32:63) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RW	RW		OCB_OCI_WOFICWD_WOCNTL_WRDATA_HIGH: Data to send on WOFCntl interface. Data will not be transmitted when only WRDATA_LOW is written,
32:63	RW	RW		OCB_OCI_WOFICWD_WOCNTL_WRDATA_LOW: Data to send on WOFCntl interface. When WRDATA_HIGH is written, the data packet will be sent on the interface. This can either be the second 32-bit write, or written as a 64 bitt write from a GPE. WRITE_EFFECT { WOFICSTAT.Interchip_tx_ongoing=1; } AFTER_DELAY[large] { WOFICSTAT.Interchip_tx_ongoing=0; } // Set and clear ONGOING

OCB_OCI OCC WOFCntl DCM Message 1 Register
Addr:	000000000006C785 (SCOM) 00000000C0063C28 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_WOFICDCM1
Constant(s):
Comments:	The WOFICDCM1 is used snapshot incoming messages if the first nibble=1
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.OCC.OCI.OCB.INTER_DCM.WOFICDCM1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:63	ROX	ROX		OCB_OCI_WOFICDCM1_DCM_MESSAGE: Snapshot of received data when the first nibble of the payload=1

OCB_OCI OCC WOFCntl DCM Message 2 Register
Addr:	000000000006C786 (SCOM) 00000000C0063C30 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_WOFICDCM2
Constant(s):
Comments:	The WOFICDCM2 is used snapshot incoming messages if the first nibble=2
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.OCC.OCI.OCB.INTER_DCM.WOFICDCM2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:63	ROX	ROX		OCB_OCI_WOFICDCM2_DCM_MESSAGE: Snapshot of received data when the first nibble of the payload=2

OCB_OCI OCC WOFCntl Interchip ECC Register
Addr:	000000000006C787 (SCOM) 00000000C0063C38 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_WOFICECC
Constant(s):
Comments:	The WOFICECC register provides ecc error injection to for link and error recovery testing
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.INTER_DCM.WOFICECC_Q_0_INST.LATC.L2(0) [0]
	1:3	TP.TPCHIP.OCC.OCI.OCB.INTER_DCM.WOFICECC_Q_1_INST.LATC.L2(1:3) [000]
Bit(s)	SCOM	OCI		Dial: Description
0	RWX	RWX		OCB_OCI_WOFICECC_INJECT_ECC_ERR: Inject an error on the next transmitted packet. If continuous mode=0, clear this bit after injecting the ecc error
1	RW	RW		OCB_OCI_WOFICECC_CONTINUOUS_INJECT: 0 - single inject 1 - continuous inject
2	RW	RW		OCB_OCI_WOFICECC_INJECT_TYPE: 0 - inject a CE (single bit flip) 1 - inject a UE (double bit flip)
3	RW	RW		OCB_OCI_WOFICECC_INJECT_DATA_OR_ECC: 0 - the error should be injected on the generated ECC 1 - the error should be injected on the data
4:63	RO	RO		constant=0b000000000000000000000000000000000000000000000000000000000000

OCB_OCI SPIPSS_ADC_CTRL_REG0
Addr:	000000000006C800 (SCOM) 00000000C0064000 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_CR0
Constant(s):
Comments:	The pmcocr0a provides the length control information for the first of the p2s frames
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:5	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_HWCTRL.HWCTRL_FRAME_SIZE_INST.LATC.L2(0:5) [000000]
	6:11	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_HWCTRL.HWCTRL_OUT_COUNT_INST.LATC.L2(0:5) [000000]
	12:17	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_HWCTRL.HWCTRL_IN_DELAY_INST.LATC.L2(0:5) [000000]
	18:23	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_HWCTRL.HWCTRL_IN_COUNT_INST.LATC.L2(0:5) [000000]
Bit(s)	SCOM	OCI		Dial: Description
0:5	RW	RW		OCB_OCI_ADC_CR0_ADC_FRAME_SIZE: Number of data bits per individual SPI transaction (also referred to as frame) during chip select assertion Supported values: 0x20 (32d) Chip Select assertion duration is adc_frame_size + 2
6:11	RW	RW		OCB_OCI_ADC_CR0_ADC_OUT_COUNT: Number of bits sent out MOSI the frame Supported values: 0x00 to spi_frame_size. Values beyond adc_frame_size are ignored.
12:17	RW	RW		OCB_OCI_ADC_CR0_ADC_IN_DELAY: Number of SPI clocks after chip select to wait before capturing MISO input Supported values: 0x00 to adc_frame_size. Values beyond adc_frame_size result in the input never being captured
18:23	RW	RW		OCB_OCI_ADC_CR0_ADC_IN_COUNT: Number of bits captured on MISO input Supported values: 0x00 to spi_frame_size. The actual number of bits captured is adc_frame_size - adc_in_delay1
24:63	RO	RO		constant=0b0000000000000000000000000000000000000000

OCB_OCI SPIPSS_ADC_CTRL_REG1
Addr:	000000000006C801 (SCOM) 00000000C0064008 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_CR1
Constant(s):
Comments:	The pmcocr1 provides control bits for the p2s bridge interface (note that this interface does not support crc)
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_HWCTRL.HWCTRL_BRIDGE_ENABLE_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_HWCTRL.HWCTRL_DEVICE_INT_INST.LATC.L2(0) [0]
	2	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_HWCTRL.HWCTRL_CLOCK_POLARITY_INST.LATC.L2(0) [0]
	3	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_HWCTRL.HWCTRL_CLOCK_PHASE_INST.LATC.L2(0) [0]
	4:13	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_HWCTRL.HWCTRL_CLOCK_DIVIDER_INST.LATC.L2(0:9) [0000000000]
	14:18	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_HWCTRL.HWCTRL_NR_OF_FRAMES_INST.LATC.L2(0:4) [00000]
	19	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_HWCTRL.HWCTRL_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN_INST.LATC.L2(0) [0]
	20:22	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_HWCTRL.BUSY_RESPONSE_CODE_INST.LATC.L2(0:2) [000]
Bit(s)	SCOM	OCI		Dial: Description
0	RWX	RWX		OCB_OCI_ADC_CR1_HWCTRL_FSM_ENABLE: if 1 the ADC FSM can be used to control the SPI interface
1	RWX	RWX		OCB_OCI_ADC_CR1_HWCTRL_DEVICE: Select the device on the SPIPSS bus to target: 0: Chip Select 0 1: Chip Select 1
2	RWX	RWX		OCB_OCI_ADC_CR1_HWCTRL_CPOL: SPI clock polarity (CPOL=0 means that clk idle is deasserted, CPOL=1 means that clk idle is asserted)
3	RWX	RWX		OCB_OCI_ADC_CR1_HWCTRL_CPHA: SPI clock phase (CPHA=0 means to change/sample values of data signals on first edge, otherwise on 2nd)
4:13	RWX	RWX		OCB_OCI_ADC_CR1_HWCTRL_CLOCK_DIVIDER: SPI clock speed divider to divide the nest_nclk/4 mesh clock, which results in a divider = (nest_freq/ (SPI_freq*8))-1 For a 2.4GHz nest clock, this means that the SPI clk can be theoretically adjusted between 600MHz and 0.29MHz (cycle time 1.66ns...3.41us, in 1.66ns steps). However, a practical range is 0.5...25MHz.
14:18	RWX	RWX		OCB_OCI_ADC_CR1_HWCTRL_NR_OF_FRAMES: Specifies the number of frames for each iteration of ADC sampling Legal values are 0, 1, ..., 31 for 1, 2, ...32 frames respectively
19	RWX	RWX		OCB_OCI_ADC_CR1_HWCTRL_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN: if this bit is 1, then a read of SPIMADC_READ_BUFFER0 causes the frame sequencer to restart ADC streaming read operation
20:22	RWX	RWX		OCB_OCI_ADC_CR1_BUSY_RESPONSE_CODE: PIB response code for the bit 19
23:63	RO	RO		constant=0b00000000000000000000000000000000000000000

OCB_OCI SPIPSS_ADC_CTRL_REG2
Addr:	000000000006C802 (SCOM) 00000000C0064010 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_CR2
Constant(s):
Comments:	The ADCCR2 provides all control bits for the spi adc interface (note that this interface does not support ecc)
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:16	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_HWCTRL.HWCTRL_INTER_FRAME_DELAY_0_INST.LATC.L2(0:16) [00000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:16	RW	RW		OCB_OCI_ADC_CR2_HWCTRL_INTER_FRAME_DELAY: Delay between two frames of a two command set as measured from the end of the last bit of the first frame until the chip select of the second frame is asserted. Delay is computed as: (value * ~100ns_hang_pulse) +0/-~100ns_hang_pulse time 0x00000: Wait 1 SPI Clock 0x00001 - 0x1FFFF: value = number of ~100ns_hang_pulses In the case of of APSS with Analog-to-Digital Converter (ADC), this delay allows for acquisition of the next reading when using a continuous acquisition mode. (TI specs indicate 325ns)
17:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000

OCB_OCI SPIPSS_ADC_STATUS_REG
Addr:	000000000006C803 (SCOM) 00000000C0064018 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_STAT
Constant(s):
Comments:	The pmcosr displays the current status about spi-related activities.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_HWCTRL.HWCTRL_STATUS_REG_OUT_0_INST.LATC.L2(0:7) [00000000]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		OCB_OCI_ADC_STAT_HWCTRL_ONGOING: Indicates that a bridge transaction is in progress of being executed. This bit is set by hardware while an operation is in progress and will be be reset by hardware when the operation is complete.
1:3	ROX	ROX		OCB_OCI_ADC_STAT_RESERVED_1_3: Reserved bits
4	ROX	ROX		OCB_OCI_ADC_STAT_HWCTRL_INVALID_NUMBER_OF_FRAMES: If this bit gets asserted, a non-supported number of frames was set in SPIPSS_ADC_CTRL_REG1. This bit is cleared upon the next enabled command that has a legal number of frames.
5	ROX	ROX		OCB_OCI_ADC_STAT_HWCTRL_WRITE_WHILE_BRIDGE_BUSY_ERR: Indicates that a bridge transaction is in progress of being executed. This bit is set by hardware while an operation is in progress and will be be reset by hardware when the operation is complete.Indicates that firmware attempted to perform an PIB Write to the SPIPSS_SPI_WDATA_REG while the ADC FSM is busy (adc_ongoing=1), which will cause undefined bridge behavior.
6	ROX	ROX		OCB_OCI_ADC_STAT_RESERVED_6: Reserved bit
7	ROX	ROX		OCB_OCI_ADC_STAT_HWCTRL_FSM_ERR: Indicates a catastrophic FSM error in the ADC control FSM
8:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000

OCB_OCI SPIPSS_ADC_COMMAND_REG
Addr:	000000000006C804 (SCOM) 00000000C0064020 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_CMD
Constant(s):
Comments:	The ADC_CMD provides the means to start the ADC bridge
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_HWCTRL.HWCTRL_START_COMMAND_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0	RWX	RWX		OCB_OCI_ADC_CMD_HWCTRL_START_SAMPLING: if set to 1 this register immediately resets itself and starts the ADC sampling
1:63	RO	RO		constant=0b000000000000000000000000000000000000000000000000000000000000000

OCB_OCI SPIPSS_ADC_RESET_REG
Addr:	000000000006C805 (SCOM) 00000000C0064028 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_RESET
Constant(s):
Comments:	Resets the ADC function in the SPIPSS interface
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:1	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_HWCTRL.HWCTRL_RESET_REG_OUT_INST.LATC.L2(0:1) [00]
Bit(s)	SCOM	OCI		Dial: Description
0:1	RWX	RWX		OCB_OCI_ADC_RESET_HWCTRL_RESET: writing value 01 on this will reset
2:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000000000

OCB_OCI SPIPSS_ADC_WDATA_REG
Addr:	000000000006C810 (SCOM) 00000000C0064080 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_WDATA
Constant(s):
Comments:	The ADC_WDATA register is used by the hardware to for the the SPI data that is shifted out for each frame to the SPIADC.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_HWCTRL.HWCTRL_WDATA_REG_OUT_INST.LATC.L2(0:15) [0000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:15	ROX	ROX		OCB_OCI_ADC_WDATA_HWCTRL_WDATA: These 16bits are shifted out of the SPI interface to the ADC every time a frame is read.
16:63	RO	RO		constant=0b000000000000000000000000000000000000000000000000

OCB_OCI SPIPSS_ADC_RDATA_REG0
Addr:	000000000006C820 (SCOM) 00000000C0064100 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_RDATA0
Constant(s):
Comments:	The ADC_RDATA0 accesses the read data for frames 0 to 3.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_HWCTRL.HWCTRL_RDATA_REG0_OUT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:15	ROX	ROX		OCB_OCI_ADC_RDATA0_HWCTRL_RDATA0: Frame 0 read data
16:31	ROX	ROX		OCB_OCI_ADC_RDATA0_HWCTRL_RDATA1: Frame 1 read data
32:47	ROX	ROX		OCB_OCI_ADC_RDATA0_HWCTRL_RDATA2: Frame 2 read data
48:63	ROX	ROX		OCB_OCI_ADC_RDATA0_HWCTRL_RDATA3: Frame 3 read data

OCB_OCI SPIPSS_ADC_RDATA_REG1
Addr:	000000000006C821 (SCOM) 00000000C0064108 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_RDATA1
Constant(s):
Comments:	The ADC_RDATA1 accesses the read data for frames 4 to 7.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_HWCTRL.HWCTRL_RDATA_REG1_OUT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:15	ROX	ROX		OCB_OCI_ADC_RDATA1_HWCTRL_RDATA4: Frame 4 read data
16:31	ROX	ROX		OCB_OCI_ADC_RDATA1_HWCTRL_RDATA5: Frame 5 read data
32:47	ROX	ROX		OCB_OCI_ADC_RDATA1_HWCTRL_RDATA6: Frame 6 read data
48:63	ROX	ROX		OCB_OCI_ADC_RDATA1_HWCTRL_RDATA7: Frame 7 read data

OCB_OCI SPIPSS_ADC_RDATA_REG2
Addr:	000000000006C822 (SCOM) 00000000C0064110 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_RDATA2
Constant(s):
Comments:	The ADC_RDATA2 accesses the read data for frames 8 to 11.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_HWCTRL.HWCTRL_RDATA_REG2_OUT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:15	ROX	ROX		OCB_OCI_ADC_RDATA2_HWCTRL_RDATA8: Frame 8 read data
16:31	ROX	ROX		OCB_OCI_ADC_RDATA2_HWCTRL_RDATA9: Frame 9 read data
32:47	ROX	ROX		OCB_OCI_ADC_RDATA2_HWCTRL_RDATA10: Frame 10 read data
48:63	ROX	ROX		OCB_OCI_ADC_RDATA2_HWCTRL_RDATA11: Frame 11 read data

OCB_OCI SPIPSS_ADC_RDATA_REG3
Addr:	000000000006C823 (SCOM) 00000000C0064118 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_RDATA3
Constant(s):
Comments:	The ADC_RDATA3 accesses the read data for frames 12 to 15.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_HWCTRL.HWCTRL_RDATA_REG3_OUT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:15	ROX	ROX		OCB_OCI_ADC_RDATA3_HWCTRL_RDATA12: Frame 12 read data
16:31	ROX	ROX		OCB_OCI_ADC_RDATA3_HWCTRL_RDATA13: Frame 13 read data
32:47	ROX	ROX		OCB_OCI_ADC_RDATA3_HWCTRL_RDATA14: Frame 14 read data
48:63	ROX	ROX		OCB_OCI_ADC_RDATA3_HWCTRL_RDATA15: Frame 15 read data

OCB_OCI SPIPSS_ADC_RDATA_REG4
Addr:	000000000006C824 (SCOM) 00000000C0064120 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_RDATA4
Constant(s):
Comments:	The ADC_RDATA4 accesses the read data for frames 16 to 19.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_HWCTRL.HWCTRL_RDATA_REG4_OUT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:15	ROX	ROX		OCB_OCI_ADC_RDATA4_HWCTRL_RDATA16: Frame 16 read data
16:31	ROX	ROX		OCB_OCI_ADC_RDATA4_HWCTRL_RDATA17: Frame 17 read data
32:47	ROX	ROX		OCB_OCI_ADC_RDATA4_HWCTRL_RDATA18: Frame 18 read data
48:63	ROX	ROX		OCB_OCI_ADC_RDATA4_HWCTRL_RDATA19: Frame 19 read data

OCB_OCI SPIPSS_ADC_RDATA_REG5
Addr:	000000000006C825 (SCOM) 00000000C0064128 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_RDATA5
Constant(s):
Comments:	The ADC_RDATA5 accesses the read data for frames 20 to 23.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_HWCTRL.HWCTRL_RDATA_REG5_OUT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:15	ROX	ROX		OCB_OCI_ADC_RDATA5_HWCTRL_RDATA20: Frame 20 read data
16:31	ROX	ROX		OCB_OCI_ADC_RDATA5_HWCTRL_RDATA21: Frame 21 read data
32:47	ROX	ROX		OCB_OCI_ADC_RDATA5_HWCTRL_RDATA22: Frame 22 read data
48:63	ROX	ROX		OCB_OCI_ADC_RDATA5_HWCTRL_RDATA23: Frame 23 read data

OCB_OCI SPIPSS_ADC_RDATA_REG6
Addr:	000000000006C826 (SCOM) 00000000C0064130 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_RDATA6
Constant(s):
Comments:	The ADC_RDATA6 accesses the read data for frames 24 to 27.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_HWCTRL.HWCTRL_RDATA_REG6_OUT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:15	ROX	ROX		OCB_OCI_ADC_RDATA6_HWCTRL_RDATA24: Frame 24 read data
16:31	ROX	ROX		OCB_OCI_ADC_RDATA6_HWCTRL_RDATA25: Frame 25 read data
32:47	ROX	ROX		OCB_OCI_ADC_RDATA6_HWCTRL_RDATA26: Frame 26 read data
48:63	ROX	ROX		OCB_OCI_ADC_RDATA6_HWCTRL_RDATA27: Frame 27 read data

OCB_OCI SPIPSS_ADC_RDATA_REG7
Addr:	000000000006C827 (SCOM) 00000000C0064138 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_RDATA7
Constant(s):
Comments:	The ADC_RDATA7 accesses the read data for frames 28 to 31.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_HWCTRL.HWCTRL_RDATA_REG7_OUT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:15	ROX	ROX		OCB_OCI_ADC_RDATA7_HWCTRL_RDATA28: Frame 28 read data
16:31	ROX	ROX		OCB_OCI_ADC_RDATA7_HWCTRL_RDATA29: Frame 29 read data
32:47	ROX	ROX		OCB_OCI_ADC_RDATA7_HWCTRL_RDATA30: Frame 30 read data
48:63	ROX	ROX		OCB_OCI_ADC_RDATA7_HWCTRL_RDATA31: Frame 31 read data

OCB_OCI SPIPSS_100NS_REG
Addr:	000000000006C828 (SCOM) 00000000C0064140 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_P2S_100NS
Constant(s):
Comments:	The P2S_100NS register defines the number of nest/4 cycles approximates 100ns as decrementer is reloaded with this value upon reaching 0. At the 0 value, a pulse is generated to represent an approximate 100ns interval.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.REG_100NS_OUT_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_P2S_100NS_P2S_100NS: Bits 0 to 31 of SPI data packet
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI SPIPSS_P2S_CTRL_REG0
Addr:	000000000006C840 (SCOM) 00000000C0064200 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_P2S_CR0
Constant(s):
Comments:	The pmcocr0a provides the length control information for the first of the p2s frames
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:5	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_P2SBRIDGE.P2S_FRAME_SIZE_INST.LATC.L2(0:5) [000000]
	6:11	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_P2SBRIDGE.P2S_OUT_COUNT1_INST.LATC.L2(0:5) [000000]
	12:17	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_P2SBRIDGE.P2S_IN_DELAY1_INST.LATC.L2(0:5) [000000]
	18:23	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_P2SBRIDGE.P2S_IN_COUNT1_INST.LATC.L2(0:5) [000000]
	24:29	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_P2SBRIDGE.P2S_OUT_COUNT2_INST.LATC.L2(0:5) [000000]
	30:35	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_P2SBRIDGE.P2S_IN_DELAY2_INST.LATC.L2(0:5) [000000]
	36:41	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_P2SBRIDGE.P2S_IN_COUNT2_INST.LATC.L2(0:5) [000000]
Bit(s)	SCOM	OCI		Dial: Description
0:5	RW	RW		OCB_OCI_P2S_CR0_P2S_FRAME_SIZE: Number of data bits per individual SPI transaction (also referred to as frame) during chip select assertion Supported values: 0x20 (32d) Chip Select assertion duration is p2s_frame_size + 2
6:11	RW	RW		OCB_OCI_P2S_CR0_P2S_OUT_COUNT1: Number of bits sent out MOSI in frame 1 of a 2 frame set (the arbitration unit) Supported values: 0x00 to spi_frame_size. Values beyond p2s_frame_size are ignored.
12:17	RW	RW		OCB_OCI_P2S_CR0_P2S_IN_DELAY1: Number of SPI clocks after chip select to wait before capturing MISO input in frame 1 Supported values: 0x00 to spi_frame_size. Values beyond p2s_frame_size result in the input never being captured
18:23	RW	RW		OCB_OCI_P2S_CR0_P2S_IN_COUNT1: Number of bits captured on MISO input in frame 1 Supported values: 0x00 to spi_frame_size. The actual number of bits captured is p2s_frame_size - p2s_in_delay1
24:29	RW	RW		OCB_OCI_P2S_CR0_P2S_OUT_COUNT2: Number of bits sent out MOSI in frame 2 of a 2 frame set (the arbitration unit) Supported values: 0x00 to p2s_frame_size. Values beyond p2s_frame_size are ignored.
30:35	RW	RW		OCB_OCI_P2S_CR0_P2S_IN_DELAY2: Number of SPI clocks after chip select to wait before capturing MISO input in frame 2 Supported values: 0x00 to p2s_frame_size. Values beyond p2s_frame_size result in the input never being captured
36:41	RW	RW		OCB_OCI_P2S_CR0_P2S_IN_COUNT2: Number of bits captured on MISO input in frame 2 Supported values: 0x00 to spi_frame_size. The actual number of bits captured is p2s_frame_size - p2s in_delay2
42:63	RO	RO		constant=0b0000000000000000000000

OCB_OCI SPIPSS_P2S_CTRL_REG1
Addr:	000000000006C841 (SCOM) 00000000C0064208 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_P2S_CR1
Constant(s):
Comments:	The pmcocr1 provides control bits for the p2s bridge interface (note that this interface does not support crc)
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_P2SBRIDGE.P2S_BRIDGE_ENABLE_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_P2SBRIDGE.P2S_DEVICE_INT_INST.LATC.L2(0) [0]
	2	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_P2SBRIDGE.P2S_CLOCK_POLARITY_INST.LATC.L2(0) [0]
	3	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_P2SBRIDGE.P2S_CLOCK_PHASE_INST.LATC.L2(0) [0]
	4:13	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_P2SBRIDGE.P2S_CLOCK_DIVIDER_INST.LATC.L2(0:9) [0000000000]
	14:16	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_P2SBRIDGE.P2S_RESERVED1_INST.LATC.L2(0:2) [000]
	17	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_P2SBRIDGE.P2S_NR_OF_FRAMES_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0	RW	RW		OCB_OCI_P2S_CR1_P2S_BRIDGE_ENABLE: if 1 the PIB2SPI bridge can be used to control the SPI interface If 0, the PIB2SPI is forced to the reset state. Note: if the Bridge is presently active (os2_in_progress = 1, the hard reset can truncate on-going operations and leave the SPIVID in an indeterminate state.
1	RW	RW		OCB_OCI_P2S_CR1_P2S_DEVICE: Select the device on the SPIPSS bus to target: 0: Chip Select 0 1: Chip Select 1
2	RW	RW		OCB_OCI_P2S_CR1_P2S_CPOL: SPI clock polarity (CPOL=0 means that clk idle is deasserted, CPOL=1 means that clk idle is asserted)
3	RW	RW		OCB_OCI_P2S_CR1_P2S_CPHA: SPI clock phase (CPHA=0 means to change/sample values of data signals on first edge, otherwise on 2nd)
4:13	RW	RW		OCB_OCI_P2S_CR1_P2S_CLOCK_DIVIDER: SPI clock speed divider to divide the nest_nclk/4 mesh clock, which results in a divider = (nest_freq/ (SPI_freq*8))-1 For a 2.4GHz nest clock, this means that the SPI clk can be theoretically adjusted between 600MHz and 0.29MHz (cycle time 1.66ns...3.41us, in 1.66ns steps). However, a practical range is 0.5...25MHz.
14:16	RW	RW		OCB_OCI_P2S_CR1_P2SCR1_RESERVED_2: Implemented but not used
17	RW	RW		OCB_OCI_P2S_CR1_P2S_NR_OF_FRAMES: Specifies the number of frames sent in the frame set (# of frames before the arbitration unit rearbitrates). 0: 1 frame 1: 2 frames
18:63	RO	RO		constant=0b0000000000000000000000000000000000000000000000

OCB_OCI SPIPSS_P2S_CTRL_REG2
Addr:	000000000006C842 (SCOM) 00000000C0064210 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_P2S_CR2
Constant(s):
Comments:	The P2SCR2 provides all control bits for the spi adc interface (note that this interface does not support ecc)
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:16	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_P2SBRIDGE.P2S_INTER_FRAME_DELAY_0_INST.LATC.L2(0:16) [00000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:16	RW	RW		OCB_OCI_P2S_CR2_P2S_INTER_FRAME_DELAY: Delay between two frames of a two command set as measured from the end of the last bit of the first frame until the chip select of the second frame is asserted. Delay is computed as: (value * ~100ns_hang_pulse) +0/-~100ns_hang_pulse time 0x00000: Wait 1 SPI Clock 0x00001 - 0x1FFFF: value = number of ~100ns_hang_pulses For values greater than 0x00000, the actual delay is 1 SPI Clock + the time delay designated by the value defined. Max. delay at 0x1FFFF: 13.1ms + 1 SPI clock cycle.
17:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000

OCB_OCI SPIPSS_P2S_STATUS_REG
Addr:	000000000006C843 (SCOM) 00000000C0064218 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_P2S_STAT
Constant(s):
Comments:	The pmcosr displays the current status about spi-related activities.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_P2SBRIDGE.P2S_STATUS_REG_OUT_0_INST.LATC.L2(0:7) [00000000]
Bit(s)	SCOM	OCI		Dial: Description
0	ROX	ROX		OCB_OCI_P2S_STAT_P2S_ONGOING: Indicates that a bridge transaction is in progress of being executed. This bit is set by hardware while an operation is in progress and will be be reset by hardware when the operation is complete.
1:4	ROX	ROX		OCB_OCI_P2S_STAT_RESERVED_1_4: Reserved bits
5	ROX	ROX		OCB_OCI_P2S_STAT_P2S_WRITE_WHILE_BRIDGE_BUSY_ERR: Indicates that a bridge transaction is in progress of being executed. This bit is set by hardware while an operation is in progress and will be be reset by hardware when the operation is complete.
6	ROX	ROX		OCB_OCI_P2S_STAT_RESERVED_6: Reserved bit
7	ROX	ROX		OCB_OCI_P2S_STAT_P2S_FSM_ERR: Indicates a catastropic FSM error in the OCI2SPI control FSM
8:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000

OCB_OCI SPIPSS_P2S_COMMAND_REG
Addr:	000000000006C844 (SCOM) 00000000C0064220 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_P2S_CMD
Constant(s):
Comments:	The P2S_CMD provides the means to start the P2S bridge
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_P2SBRIDGE.P2S_START_COMMAND_INST.LATC.L2(0) [0]
Bit(s)	SCOM	OCI		Dial: Description
0	WO_2P	WO_2P		OCB_OCI_P2S_CMD_START_P2S_COMMAND: If set to 1 and P2S_BRIDGE_ENABLE = 1, this register immediately resets itself and starts the P2S operation. If P2S_BRIDGE_ENABLE = 0, this register immediately resets itself but no operation is started.
1:63	RO	RO		constant=0b000000000000000000000000000000000000000000000000000000000000000

OCB_OCI SPIPSS_P2S_RESET_REG
Addr:	000000000006C845 (SCOM) 00000000C0064228 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_P2S_RESET
Constant(s):
Comments:	Resets the P2S function in the SPIPSS interface
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:1	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_P2SBRIDGE.P2S_RESET_REG_OUT_INST.LATC.L2(0:1) [00]
Bit(s)	SCOM	OCI		Dial: Description
0:1	RWX	RWX		OCB_OCI_P2S_RESET_P2S_RESET: writing value 01 on this will reset
2:63	RO	RO		constant=0b00000000000000000000000000000000000000000000000000000000000000

OCB_OCI SPIPSS_P2S_WDATA_REG
Addr:	000000000006C850 (SCOM) 00000000C0064280 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_P2S_WDATA
Constant(s):
Comments:	The P2S_WDATA register is used for the most significant 4B of write data through the P2S bridge. Note that a write to this register starts the SPI transaction (read or write), if the switch p2s_bridge_enable is set.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_P2SBRIDGE.P2S_WDATA_REG_OUT_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	RW	RW		OCB_OCI_P2S_WDATA_P2S_WDATA: Bits 0 to 31 of SPI data packet
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_OCI SPIPSS_P2S_RDATA_REG
Addr:	000000000006C860 (SCOM) 00000000C0064300 (OCI)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_P2S_RDATA
Constant(s):
Comments:	The P2S_RDATA register is used for the most significant 4B of read data of the P2S bridge. After the p2s_ongoing bit has dropped, the read values are available in P2S_RDATA.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.OCC_SPI.SPIPSS_P2SBRIDGE.P2S_RDATA_REG_OUT_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	OCI		Dial: Description
0:31	ROX	ROX		OCB_OCI_P2S_RDATA_P2S_RDATA: Bits 0 to 31 of SPI data packet
32:63	RO	RO		constant=0b00000000000000000000000000000000

OCB_PIB OCC Control Register
Addr:	000000000006D000 (SCOM) 000000000006D001 (SCOM1) 000000000006D002 (SCOM2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCR
Constant(s):	PU_OCB_PIB_OCR
Comments:	Register for low level control of the PPC405.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.OCC_CTRL_Q_INST.LATC.L2(0:15) [0000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCR_CORE_RESET: Controls the core_reset pin to the PPC405. Note: - the reset value puts the PPC405 into reset - a PIB slave reset may or may not set this bit as well. See bit 9 (pib_slave_reset_to_405_enable) which controls this behavior.
1	RO	WO_CLEAR	WO_OR	OCB_PIB_OCR_CHIP_RESET: Controls the chip_reset pin to the PPC405.
2	RO	WO_CLEAR	WO_OR	OCB_PIB_OCR_SYSTEM_RESET: Controls the system_reset pin to the PPC405.
3	RO	WO_CLEAR	WO_OR	OCB_PIB_OCR_OCI_ARB_RESET: Controls the reset pin to the OCI arbiter
4	RO	WO_CLEAR	WO_OR	OCB_PIB_OCR_TRACE_DISABLE: Disables the PPC405 Trace function when set
5	RO	WO_CLEAR	WO_OR	OCB_PIB_OCR_TRACE_EVENT: Asserts a trigger event to the PPC405
6	RO	WO_CLEAR	WO_OR	OCB_PIB_OCR_DBG_UNCONDITIONAL_EVENT: Asserted the unconditional debug event (UDE) and sets the UDE bit of the debug status register (DBSR) if enabled.
7	RO	WO_CLEAR	WO_OR	OCB_PIB_OCR_EXT_INTERRUPT: Asserts an external interrupt to the PPC405
8	RO	WO_CLEAR	WO_OR	OCB_PIB_OCR_CRITICAL_INTERRUPT: Asserts a critical interrupt to the PPC405
9	RO	WO_CLEAR	WO_OR	OCB_PIB_OCR_PIB_SLAVE_RESET_TO_405_ENABLE: Controls whether a PIB slave reset will put the PPC405 into reset or not. 0 - PIB slave reset will not cause PPC405 reset(default) 1 - PIB slave reset will cause PPC405 reset (sets bit 0)
10	RO	WO_CLEAR	WO_OR	OCB_PIB_OCR_OCR_DBG_HALT: Halts the PPC405 execution. This bit is ORed with OCC JTAG Configuration Register(dbg_halt) which is used by RiscWatch code for debug operations. This bit is intended to be used by OCC reset code to gracefully halt the PPC405 without colliding with RiscWatch firmware.
11:15	RO	WO_CLEAR	WO_OR	OCB_PIB_OCR_SPARE: Implemented but unused
16:63	RO	RO	RO	constant=0b000000000000000000000000000000000000000000000000

OCB_PIB OCC Debug Mode Register
Addr:	000000000006D003 (SCOM)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCDBG
Constant(s):	PU_OCB_PIB_OCDBG
Comments:	Register for debug control of OCI masters and slaves
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.OCC_DBG_Q_INST.LATC.L2(0:15) [0000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			OCB_PIB_OCDBG_MST_DIS_ABUSPAREN: Disable ADBUS_PAREN - Disable address parity generation for all GPE OCI Masters.
1	RW			OCB_PIB_OCDBG_MST_DIS_BEPAREN: Disable BE_PAREN - Disable byte enable parity generation for all GPE OCI Masters.
2	RW			OCB_PIB_OCDBG_MST_DIS_WRDBUSPAREN: Disable WRDATA_PAREN - Disable write data parity generation for all GPE OCI Masters.
3	RW			OCB_PIB_OCDBG_MST_DIS_RDDBUSPAR: Disable read data parity checking - Parity checking on read data will be disabled and data will be forwarded to unit for all GPE OCI Masters.
4	RW			OCB_PIB_OCDBG_MST_SPARE: Spare debug signal for OCI Master for all GPE OCI Masters.
5	RW			OCB_PIB_OCDBG_SLV_DIS_SACK: Disable acknowledge of secondary requests - savalid will be ignored and interface component will respond only to pavalid
6	RW			OCB_PIB_OCDBG_SLV_DIS_ABUSPAR: Disable address parity checking - Address parity error will be ignored by all GPE OCI Slaves.
7	RW			OCB_PIB_OCDBG_SLV_DIS_BEPAR: Disable byte enable parity checking - Byte enable parity error will be ignored by all GPE OCI Slaves.
8	RW			OCB_PIB_OCDBG_SLV_DIS_BE: Disable byte enable correctness checking - Invalid combinations of Byte Enable will be ignored by all GPE OCI Slaves and transfers will be allowed to progress to Unit with all 1 byte_enable.
9	RW			OCB_PIB_OCDBG_SLV_DIS_WRDBUSPAR: Disable write data parity checking - Parity checking on write data will be disabled and data will be forwarded to Unit.
10	RW			OCB_PIB_OCDBG_SLV_DIS_RDDBUSPAREN: Disable RDDBUS_PAREN - Disable read data parity generation by all GPE OCI Slaves.
11	RW			OCB_PIB_OCDBG_SLV_SPARE: Spare debug signal for all GPE OCI Slaves
12	RW			OCB_PIB_OCDBG_DISABLE_OPIT_PARITY: Disable parity checking on the OPIT interrupt bus,
13	RW			OCB_PIB_OCDBG_FREEZE_ON_FIRST_OPIT_PERR: Freeze on first OPIT parity error - will stop latching interrupt data after the first parity error. Code must clear this after a parity error to get OPIT interrupts working again.
14	RW			OCB_PIB_OCDBG_RESET_OPIT_FSM: Reset the OPIT interrupt state machine. Code must clear this to get OPIT interrupts working again.
15	RW			OCB_PIB_OCDBG_SPARE: Implemented but unused
16:63	RO			constant=0b000000000000000000000000000000000000000000000000

OCB_PIB OCC JTAG Configuration Register
Addr:	000000000006D004 (SCOM) 000000000006D005 (SCOM1) 000000000006D006 (SCOM2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OJCFG
Constant(s):
Comments:	This register contains the configuration bits for setting up to communicate with the PPC405 via JTAG
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:6	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.JTAGACC.OCC_JTAG_CFG_Q_0_INST.LATC.L2(0:6) [0000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0	RW	WO_AND	WO_OR	OCB_PIB_OJCFG_JTAG_SRC_SEL: Select source to drive the 405 JTAG pins 0 : OCC FSM 1 : FSI (toad mode)
1	RW	WO_AND	WO_OR	OCB_PIB_OJCFG_RUN_TCK: Control TCK clock (also used as act to enable all associated JTAG driver latches) 0 : off 1 : on
2:4	RW	WO_AND	WO_OR	OCB_PIB_OJCFG_TCK_WIDTH: This field is used to compute the number of clock cycles before transitioning TCK. The actual TCK width is (tck_width + 1) * 2. For example : if tck_width is "000", the actual width will be 2 clock cycles. TCK will be 1 for 2 cycles and 0 for 2 cycles and repeat... The possible values of the actual TCK width are even numbers from 2 to 16.
5	RW	WO_AND	WO_OR	OCB_PIB_OJCFG_JTAG_TRST_B: Note: this is a low active signal and the reset value puts the PPC405 JTAG logic into reset.
6	RW	WO_AND	WO_OR	OCB_PIB_OJCFG_DBG_HALT: Halts the PPC405 execution This bit is ORed with OCC Control Register(occ_dbg_halt) which is used by OCC Reset code. This bit is intended to be used by RISCWatch firmware without colliding with reset firmware.
7:63	RO	RO	RO	constant=0b000000000000000000000000000000000000000000000000000000000

OCB_PIB OCC JTAG FSM Reset Register
Addr:	000000000006D007 (SCOM)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OJFRST
Constant(s):
Comments:	Writing to this register forces the JTAG Master FSM to enter the IDLE state
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0:63	RO			constant=0b0000000000000000000000000000000000000000000000000000000000000000

OCB_PIB OCC JTAG Instruction and Control Register
Addr:	000000000006D008 (SCOM) 000000000006D009 (SCOM1) 000000000006D00A (SCOM2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OJIC
Constant(s):
Comments:	This register contains the JTAG instruction to be sent to the 405. It also contains status and control bits.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.JTAGACC.START_JTAG_CMD_Q_INST.LATC.L2(0) [0]
	1:4	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.JTAGACC.OCC_JTAG_CTRL_Q_0_INST.LATC.L2(0:3) [0000]
	12:15	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.JTAGACC.OCC_JTAG_CTRL_Q_0_INST.LATC.L2(4:7) [0000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0	WO_2P	NCX	WO_2P	OCB_PIB_OJIC_START_JTAG_CMD: Self-clearing bit. When written to a 1 will initiate the FSM to perform the specified JTAG command. Will clear to 0 on next cycle after being written.
1	RW	WO_AND	WO_OR	OCB_PIB_OJIC_DO_IR: IR control 0 : do not execute IR path 1 : execute IR path
2	RW	WO_AND	WO_OR	OCB_PIB_OJIC_DO_DR: DR control 0 : do not execute DR path 1 : execute DR path
3	RW	WO_AND	WO_OR	OCB_PIB_OJIC_DO_TAP_RESET: 405 TAP reset control 0 : do not perform TAP controller reset before IR 1 : perform TAP controller reset before IR (ie. issue TMS for 5 TCK clocks to force TAP controller state machine reset) Note: do_tap_reset is only valid when do_ir =1, otherwise its value is ignored.
4	RW	WO_AND	WO_OR	OCB_PIB_OJIC_WR_VALID: 33rd bit placed on TDI when performing a 33 bit JTAG register access
5:11	RO	RO	RO	constant=0b0000000
12:15	RW	WO_AND	WO_OR	OCB_PIB_OJIC_JTAG_INSTR: 4-bit 405 JTAG instruction
16:63	RO	RO	RO	constant=0b000000000000000000000000000000000000000000000000

OCB_PIB OCC JTAG Status Register
Addr:	000000000006D00B (SCOM)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OJSTAT
Constant(s):
Comments:	This register contains the JTAG status.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.JTAGACC.ACC_CURRENT_STATE_Q_0_INST.LATC.L2(0) [0]
	1:6	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.JTAGACC.OCC_JTAG_STAT_Q_0_INST.LATC.L2(0:5) [000000]
Bit(s)	SCOM			Dial: Description
0	ROX			OCB_PIB_OJSTAT_JTAG_INPROG: Status bit to indicate that a current JTAG operation is in progress. (ie. FSM not idle) Dial enums: OFF=>0b1 ON=>0b0
1	RWX_WCLEAR			OCB_PIB_OJSTAT_SRC_SEL_EQ1_ERR: Status to indicate that a JTAG operation was attempted, but the src_sel bit in OJCFG was set to FSI as source of JTAG instead of the JTAG accelerator.
2	RWX_WCLEAR			OCB_PIB_OJSTAT_RUN_TCK_EQ0_ERR: Status to indicate that a JTAG operation was attempted, but run_tck bit in OJCFG was set to 0. (ie. TCK is not running)
3	RWX_WCLEAR			OCB_PIB_OJSTAT_TRST_B_EQ0_ERR: Status to indicate that a JTAG operation was attempted, but the jtag_trst_b bit in OJCFG was set to 0 (ie. PPC405 JTAG is in reset)
4	RWX_WCLEAR			OCB_PIB_OJSTAT_IR_DR_EQ0_ERR: Status to indicate that a JTAG operation was attempted, but do_ir and do_dr bits in OJIC were both set to 0 (ie. no operation is selected)
5	RWX_WCLEAR			OCB_PIB_OJSTAT_INPROG_WR_ERR: Status to indicate that a PIB register write was attempted to either OJCFG, OJIC, or OJTDI while jtag_inprog = 1. (ie. JTAG operation still in progress)
6	RWX_WCLEAR			OCB_PIB_OJSTAT_FSM_ERROR: Status to indicate that the JTAG FSM went to an illegal state (ie. odd parity check on one-hot state machine bits)
7:63	RO			constant=0b000000000000000000000000000000000000000000000000000000000

OCB_PIB OCC JTAG TDI Register
Addr:	000000000006D00C (SCOM)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OJTDI
Constant(s):
Comments:	This register contains the JTAG data to be sent on TDI to the 405. This register is non-destructive and always holds the last data written to it
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.JTAGACC.OCC_JTAG_TDI_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	RW			OCB_PIB_OJTDI_JTAG_TDI: 32 bits of data to write into 405 JTAG registers
32:63	RO			constant=0b00000000000000000000000000000000

OCB_PIB OCC JTAG TDO Register
Addr:	000000000006D00D (SCOM)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OJTDO
Constant(s):
Comments:	This register contains the JTAG data received on TDO from the PPC405. It also includes readonly values of OJCFG and OJIC to reduce the register accesses for retrieving status upon a JTAG read. Note: jtag_tdo register always reflects what was shifted on TDO for the previous JTAG register operation.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.JTAGACC.TDO_SHIFT_REG_Q_0_INST.LATC.L2(1:32) [00000000000000000000000000000000]
	32:38	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.JTAGACC.OCC_JTAG_CFG_Q_0_INST.LATC.L2(0:6) [0000000]
	40	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.JTAGACC.ACC_CURRENT_STATE_Q_0_INST.LATC.L2(0) [0]
	41:46	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.JTAGACC.OCC_JTAG_STAT_Q_0_INST.LATC.L2(0:5) [000000]
	49:52	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.JTAGACC.OCC_JTAG_CTRL_Q_0_INST.LATC.L2(0:3) [0000]
	60:63	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.JTAGACC.OCC_JTAG_CTRL_Q_0_INST.LATC.L2(4:7) [0000]
Bit(s)	SCOM			Dial: Description
0:31	ROX			jtag_tdo
32	ROX			OCB_PIB_OJCFG_JTAG_SRC_SEL: Select source to drive the 405 JTAG pins 0 : OCC FSM 1 : FSI (toad mode)
33	ROX			OCB_PIB_OJCFG_RUN_TCK: Control TCK clock (also used as act to enable all associated JTAG driver latches) 0 : off 1 : on
34:36	ROX			OCB_PIB_OJCFG_TCK_WIDTH: This field is used to compute the number of clock cycles before transitioning TCK. The actual TCK width is (tck_width + 1) * 2. For example : if tck_width is "000", the actual width will be 2 clock cycles. TCK will be 1 for 2 cycles and 0 for 2 cycles and repeat... The possible values of the actual TCK width are even numbers from 2 to 16.
37	ROX			OCB_PIB_OJCFG_JTAG_TRST_B: Note: this is a low active signal and the reset value puts the PPC405 JTAG logic into reset.
38	ROX			OCB_PIB_OJCFG_DBG_HALT: Halts the PPC405 execution This bit is ORed with OCC Control Register(occ_dbg_halt) which is used by OCC Reset code. This bit is intended to be used by RISCWatch firmware without colliding with reset firmware.
39	RO			constant=0b0
40	ROX			OCB_PIB_OJSTAT_JTAG_INPROG: Status bit to indicate that a current JTAG operation is in progress. (ie. FSM not idle) Dial enums: OFF=>0b1 ON=>0b0
41	ROX			OCB_PIB_OJSTAT_SRC_SEL_EQ1_ERR: Status to indicate that a JTAG operation was attempted, but the src_sel bit in OJCFG was set to FSI as source of JTAG instead of the JTAG accelerator.
42	ROX			OCB_PIB_OJSTAT_RUN_TCK_EQ0_ERR: Status to indicate that a JTAG operation was attempted, but run_tck bit in OJCFG was set to 0. (ie. TCK is not running)
43	ROX			OCB_PIB_OJSTAT_TRST_B_EQ0_ERR: Status to indicate that a JTAG operation was attempted, but the jtag_trst_b bit in OJCFG was set to 0 (ie. PPC405 JTAG is in reset)
44	ROX			OCB_PIB_OJSTAT_IR_DR_EQ0_ERR: Status to indicate that a JTAG operation was attempted, but do_ir and do_dr bits in OJIC were both set to 0 (ie. no operation is selected)
45	ROX			OCB_PIB_OJSTAT_INPROG_WR_ERR: Status to indicate that a PIB register write was attempted to either OJCFG, OJIC, or OJTDI while jtag_inprog = 1. (ie. JTAG operation still in progress)
46	ROX			OCB_PIB_OJSTAT_FSM_ERROR: Status to indicate that the JTAG FSM went to an illegal state (ie. odd parity check on one-hot state machine bits)
47:48	RO			constant=0b00
49	ROX			OCB_PIB_OJIC_DO_IR: IR control 0 : do not execute IR path 1 : execute IR path
50	ROX			OCB_PIB_OJIC_DO_DR: DR control 0 : do not execute DR path 1 : execute DR path
51	ROX			OCB_PIB_OJIC_DO_TAP_RESET: 405 TAP reset control 0 : do not perform TAP controller reset before IR 1 : perform TAP controller reset before IR (ie. issue TMS for 5 TCK clocks to force TAP controller state machine reset) Note: do_tap_reset is only valid when do_ir =1, otherwise its value is ignored.
52	ROX			OCB_PIB_OJIC_WR_VALID: 33rd bit placed on TDI when performing a 33 bit JTAG register access
53:59	RO			constant=0b0000000
60:63	ROX			OCB_PIB_OJIC_JTAG_INSTR: 4-bit 405 JTAG instruction

OCB_PIB OCB Address 0 Register
Addr:	000000000006D010 (SCOM)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBAR0
Constant(s):	PU_OCB_PIB_OCBAR0
Comments:	This PIB accessible register captures the OCI address that is desired to be accessed.
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.ADDR_INDIR_OCI_REGION_LT_0_INST.LATC.L2(0:2) [000]
	3:28	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.ADDR_INDIR_LT_0_INST.LATC.L2(0:25) [00000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:2	RW			OCB_PIB_OCBAR0_OCI_REGION: OCI Address Space Region 0XX - Reserved 10X - PowerBus memory 110 - Register space 111 - SRAM
3:28	RW			OCB_PIB_OCBAR0_OCB_ADDRESS: Address of 8B quantity the OCI for this channel Field contents depends on accessed oci_region PowerBus 3:11 - Maskable Alignment (see PBA spec) 12:28 - Offset SRAM 3:4 - 128MB alias - bits are not compared 5:11 - 0b1111111 12:28 - Offset
29:63	RO			constant=0b00000000000000000000000000000000000

OCB_PIB OCB Control/Status 0 Register
Addr:	000000000006D011 (SCOM) 000000000006D012 (SCOM1) 000000000006D013 (SCOM2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBCSR0
Constant(s):	PU_OCB_PIB_OCBCSR0
Comments:	This PIB accessible register that controls the function of the OCB channel and provides status of it. Note that this registers base address is Read-Only and can only be written "atomically" via the WO addresses.
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.IND_CHANNEL_CREG_Q_0_INST.LATC.L2(0:15) [0000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCBCSR0_PULL_READ_UNDERFLOW: Pull Queue Read Underflow Underflow is defined as a read to the OCB Data 0 Register and the pull_empty facility is already set. This bit is cleared only by a firmware write of this bit to 1.Writes store the value. Dial enums: UNDERFLOW_NOT_DETECTED=>0b0 UNDERFLOW_DETECTED=>0b1
1	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCBCSR0_PUSH_WRITE_OVERFLOW: Push Queue Write Overflow Overflow is defined as a store to the OCB Data 0 Register and the push_full facility is already set. This bit is cleared only by a firmware write of this bit to 1. Dial enums: OVERFLOW_NOT_DETECTED=>0b0 OVERFLOW_DETECTED=>0b1
2	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR0_PULL_READ_UNDERFLOW_EN: Enable the setting of pull_read_underflow by hardware. 0 - Underflow detection disabled 1 - Underflow detection enabled This bit is set using the OR mask register and cleared using the CLEAR mask register.
3	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR0_PUSH_WRITE_OVERFLOW_EN: Enable the setting of push_write_overflow by hardware. 0 - Overflow detection disabled 1 - OVerflow detection enabled This bit is set using the OR mask register and cleared using the CLEAR mask register.
4	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR0_OCB_STREAM_MODE: Put the bridge channel in streaming mode with the behavior further defined by the setting of ocb_stream_type 0 - Stream Mode Disabled 1 - Stream Mode Enabled This bit is set using the OR mask register and cleared using the CLEAR mask register.
5	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR0_OCB_STREAM_TYPE: Type of streaming enabled by ocb_stream_mode = 1 0 - Linear 1 - Circular For Linear type, the ocb_address field is incremented by 8 with each access to the OCB Data 0 Register. In Circular type, the address manipulation via access to OCB Stream [Push/Pull] Increment registers This bit is set using the OR mask register and cleared using the CLEAR mask register.
6:7	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR0_SPARE0: Implemented but not used
8	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCBCSR0_OCB_OCI_TIMEOUT: Indicates the MnTimeout signal on the OCI for the OCB Master was asserted to flag that no OCI slave acknowledged the request. This bit is set by hardware under normal operations but can be forced using the OR mask register. This bit can be cleared using the CLEAR mask register.
9	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCBCSR0_OCB_OCI_READ_DATA_PARITY: Indicates the OCI read data parity was in error This bit is set by hardware under normal operations but can be forced using the OR mask register. This bit can be cleared using the CLEAR mask register.
10	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCBCSR0_OCB_OCI_SLAVE_ERROR: Indicates the SlvError signal on the OCI for the OCB Master was asserted. This bit is set by hardware under normal operations but can be forced using the OR mask register. This bit can be cleared using the CLEAR mask register.
11	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCBCSR0_OCB_PIB_ADDR_PARITY_ERR: Indicates the PIB address parity was in error (PIB read or write operation) This bit is set by hardware under normal operations but can be forced using the OR mask register. This bit can be cleared using the CLEAR mask register.
12	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCBCSR0_OCB_PIB_DATA_PARITY_ERR: Indicates the PIB data parity was in error for a PIB write operation This bit is set by hardware under normal operations but can be forced using the OR mask register. This bit can be cleared using the CLEAR mask register.
13	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR0_SPARE1: Implemented but not used
14	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR0_SPARE_3: mplemented but not used Used to be ocb_fsm_err
15	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR0_SPARE2: Implemented but not used Writes store the value. Reads return the last value written.
16:63	RO	RO	RO	constant=0b000000000000000000000000000000000000000000000000

OCB_PIB OCB Error Status 0 Register
Addr:	000000000006D014 (SCOM)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBESR0
Constant(s):	PU_OCB_PIB_OCBESR0
Comments:	This PIB accessible register that indicates the OCI Address of a channel operation that detected the first error. See OCB Control/Status 0 Register for the specific error(s) detected. Set and Locked by hardware, Write to clear and Unlock.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.OCB_ERROR_ADDR_LT_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	RWX_WCLRREG			OCB_PIB_OCBESR0_OCB_ERROR_ADDR: OCI address being accessed when the first channel error is detected. This register is cleared upon writing any value.
32:63	RO			constant=0b00000000000000000000000000000000

OCB_PIB OCB Data 0 Register
Addr:	000000000006D015 (SCOM)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBDR0
Constant(s):	PU_OCB_PIB_OCBDR0
Comments:	This PIB accessible register captures the PIB data to be written on the OCI or the OCI data read returned without errors from the OCI address that is desired to be accessed.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_0.DATA_INDIR_LT_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RWX			OCB_PIB_OCBDR0_OCB_DATA: Data to/from OCI for this channel

OCB_PIB OCB Address 1 Register
Addr:	000000000006D030 (SCOM)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBAR1
Constant(s):	PU_OCB_PIB_OCBAR1
Comments:	This PIB accessible register captures the OCI address that is desired to be accessed.
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.ADDR_INDIR_OCI_REGION_LT_0_INST.LATC.L2(0:2) [000]
	3:28	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.ADDR_INDIR_LT_0_INST.LATC.L2(0:25) [00000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:2	RW			OCB_PIB_OCBAR1_OCI_REGION: OCI Address Space Region 0XX - Reserved 10X - PowerBus memory 110 - Register space 111 - SRAM
3:28	RW			OCB_PIB_OCBAR1_OCB_ADDRESS: Address of 8B quantity the OCI for this channel Field contents depends on accessed oci_region PowerBus 3:11 - Maskable Alignment (see PBA spec) 12:28 - Offset SRAM 3:4 - 128MB alias - bits are not compared 5:11 - 0b1111111 12:28 - Offset
29:63	RO			constant=0b00000000000000000000000000000000000

OCB_PIB OCB Control/Status 1 Register
Addr:	000000000006D031 (SCOM) 000000000006D032 (SCOM1) 000000000006D033 (SCOM2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBCSR1
Constant(s):	PU_OCB_PIB_OCBCSR1
Comments:	This PIB accessible register that controls the function of the OCB channel and provides status of it. Note that this registers base address is Read-Only and can only be written "atomically" via the WO addresses.
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.IND_CHANNEL_CREG_Q_0_INST.LATC.L2(0:15) [0000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCBCSR1_PULL_READ_UNDERFLOW: Pull Queue Read Underflow Underflow is defined as a read to the OCB Data 1 Register and the pull_empty facility is already set. This bit is cleared only by a firmware write of this bit to 1.Writes store the value. Dial enums: UNDERFLOW_NOT_DETECTED=>0b0 UNDERFLOW_DETECTED=>0b1
1	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCBCSR1_PUSH_WRITE_OVERFLOW: Push Queue Write Overflow Overflow is defined as a store to the OCB Data 1 Register and the push_full facility is already set. This bit is cleared only by a firmware write of this bit to 1. Dial enums: OVERFLOW_NOT_DETECTED=>0b0 OVERFLOW_DETECTED=>0b1
2	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR1_PULL_READ_UNDERFLOW_EN: Enable the setting of pull_read_underflow by hardware. 0 - Underflow detection disabled 1 - Underflow detection enabled This bit is set using the OR mask register and cleared using the CLEAR mask register.
3	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR1_PUSH_WRITE_OVERFLOW_EN: Enable the setting of push_write_overflow by hardware. 0 - Overflow detection disabled 1 - OVerflow detection enabled This bit is set using the OR mask register and cleared using the CLEAR mask register.
4	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR1_OCB_STREAM_MODE: Put the bridge channel in streaming mode with the behavior further defined by the setting of ocb_stream_type 0 - Stream Mode Disabled 1 - Stream Mode Enabled This bit is set using the OR mask register and cleared using the CLEAR mask register.
5	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR1_OCB_STREAM_TYPE: Type of streaming enabled by ocb_stream_mode = 1 0 - Linear 1 - Circular For Linear type, the ocb_address field is incremented by 8 with each access to the OCB Data 1 Register. In Circular type, the address manipulation via access to OCB Stream [Push/Pull] Increment registers This bit is set using the OR mask register and cleared using the CLEAR mask register.
6:7	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR1_SPARE0: Implemented but not used
8	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCBCSR1_OCB_OCI_TIMEOUT: Indicates the MnTimeout signal on the OCI for the OCB Master was asserted to flag that no OCI slave acknowledged the request. This bit is set by hardware under normal operations but can be forced using the OR mask register. This bit can be cleared using the CLEAR mask register.
9	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCBCSR1_OCB_OCI_READ_DATA_PARITY: Indicates the OCI read data parity was in error This bit is set by hardware under normal operations but can be forced using the OR mask register. This bit can be cleared using the CLEAR mask register.
10	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCBCSR1_OCB_OCI_SLAVE_ERROR: Indicates the SlvError signal on the OCI for the OCB Master was asserted. This bit is set by hardware under normal operations but can be forced using the OR mask register. This bit can be cleared using the CLEAR mask register.
11	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCBCSR1_OCB_PIB_ADDR_PARITY_ERR: Indicates the PIB address parity was in error (PIB read or write operation) This bit is set by hardware under normal operations but can be forced using the OR mask register. This bit can be cleared using the CLEAR mask register.
12	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCBCSR1_OCB_PIB_DATA_PARITY_ERR: Indicates the PIB data parity was in error for a PIB write operation This bit is set by hardware under normal operations but can be forced using the OR mask register. This bit can be cleared using the CLEAR mask register.
13	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR1_SPARE1: Implemented but not used
14	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR1_SPARE_3: mplemented but not used Used to be ocb_fsm_err
15	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR1_SPARE2: Implemented but not used Writes store the value. Reads return the last value written.
16:63	RO	RO	RO	constant=0b000000000000000000000000000000000000000000000000

OCB_PIB OCB Error Status 1 Register
Addr:	000000000006D034 (SCOM)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBESR1
Constant(s):	PU_OCB_PIB_OCBESR1
Comments:	This PIB accessible register that indicates the OCI Address of a channel operation that detected the first error. See OCB Control/Status 0 Register for the specific error(s) detected. Set and Locked by hardware, Write to clear and Unlock.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.OCB_ERROR_ADDR_LT_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	RWX_WCLRREG			OCB_PIB_OCBESR1_OCB_ERROR_ADDR: OCI address being accessed when the first channel error is detected. This register is cleared upon writing any value.
32:63	RO			constant=0b00000000000000000000000000000000

OCB_PIB OCB Data 1 Register
Addr:	000000000006D035 (SCOM)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBDR1
Constant(s):	PU_OCB_PIB_OCBDR1
Comments:	This PIB accessible register captures the PIB data to be written on the OCI or the OCI data read returned without errors from the OCI address that is desired to be accessed.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_1.DATA_INDIR_LT_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RWX			OCB_PIB_OCBDR1_OCB_DATA: Data to/from OCI for this channel

OCB_PIB OCB Address 2 Register
Addr:	000000000006D050 (SCOM)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBAR2
Constant(s):	PU_OCB_PIB_OCBAR2
Comments:	This PIB accessible register captures the OCI address that is desired to be accessed.
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.ADDR_INDIR_OCI_REGION_LT_0_INST.LATC.L2(0:2) [000]
	3:28	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.ADDR_INDIR_LT_0_INST.LATC.L2(0:25) [00000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:2	RW			OCB_PIB_OCBAR2_OCI_REGION: OCI Address Space Region 0XX - Reserved 10X - PowerBus memory 110 - Register space 111 - SRAM
3:28	RW			OCB_PIB_OCBAR2_OCB_ADDRESS: Address of 8B quantity the OCI for this channel Field contents depends on accessed oci_region PowerBus 3:11 - Maskable Alignment (see PBA spec) 12:28 - Offset SRAM 3:4 - 128MB alias - bits are not compared 5:11 - 0b1111111 12:28 - Offset
29:63	RO			constant=0b00000000000000000000000000000000000

OCB_PIB OCB Control/Status 2 Register
Addr:	000000000006D051 (SCOM) 000000000006D052 (SCOM1) 000000000006D053 (SCOM2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBCSR2
Constant(s):	PU_OCB_PIB_OCBCSR2
Comments:	This PIB accessible register that controls the function of the OCB channel and provides status of it. Note that this registers base address is Read-Only and can only be written "atomically" via the WO addresses.
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.IND_CHANNEL_CREG_Q_0_INST.LATC.L2(0:15) [0000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCBCSR2_PULL_READ_UNDERFLOW: Pull Queue Read Underflow Underflow is defined as a read to the OCB Data 2 Register and the pull_empty facility is already set. This bit is cleared only by a firmware write of this bit to 1.Writes store the value. Dial enums: UNDERFLOW_NOT_DETECTED=>0b0 UNDERFLOW_DETECTED=>0b1
1	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCBCSR2_PUSH_WRITE_OVERFLOW: Push Queue Write Overflow Overflow is defined as a store to the OCB Data 2 Register and the push_full facility is already set. This bit is cleared only by a firmware write of this bit to 1. Dial enums: OVERFLOW_NOT_DETECTED=>0b0 OVERFLOW_DETECTED=>0b1
2	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR2_PULL_READ_UNDERFLOW_EN: Enable the setting of pull_read_underflow by hardware. 0 - Underflow detection disabled 1 - Underflow detection enabled This bit is set using the OR mask register and cleared using the CLEAR mask register.
3	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR2_PUSH_WRITE_OVERFLOW_EN: Enable the setting of push_write_overflow by hardware. 0 - Overflow detection disabled 1 - OVerflow detection enabled This bit is set using the OR mask register and cleared using the CLEAR mask register.
4	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR2_OCB_STREAM_MODE: Put the bridge channel in streaming mode with the behavior further defined by the setting of ocb_stream_type 0 - Stream Mode Disabled 1 - Stream Mode Enabled This bit is set using the OR mask register and cleared using the CLEAR mask register.
5	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR2_OCB_STREAM_TYPE: Type of streaming enabled by ocb_stream_mode = 1 0 - Linear 1 - Circular For Linear type, the ocb_address field is incremented by 8 with each access to the OCB Data 2 Register. In Circular type, the address manipulation via access to OCB Stream [Push/Pull] Increment registers This bit is set using the OR mask register and cleared using the CLEAR mask register.
6:7	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR2_SPARE0: Implemented but not used
8	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCBCSR2_OCB_OCI_TIMEOUT: Indicates the MnTimeout signal on the OCI for the OCB Master was asserted to flag that no OCI slave acknowledged the request. This bit is set by hardware under normal operations but can be forced using the OR mask register. This bit can be cleared using the CLEAR mask register.
9	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCBCSR2_OCB_OCI_READ_DATA_PARITY: Indicates the OCI read data parity was in error This bit is set by hardware under normal operations but can be forced using the OR mask register. This bit can be cleared using the CLEAR mask register.
10	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCBCSR2_OCB_OCI_SLAVE_ERROR: Indicates the SlvError signal on the OCI for the OCB Master was asserted. This bit is set by hardware under normal operations but can be forced using the OR mask register. This bit can be cleared using the CLEAR mask register.
11	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCBCSR2_OCB_PIB_ADDR_PARITY_ERR: Indicates the PIB address parity was in error (PIB read or write operation) This bit is set by hardware under normal operations but can be forced using the OR mask register. This bit can be cleared using the CLEAR mask register.
12	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCBCSR2_OCB_PIB_DATA_PARITY_ERR: Indicates the PIB data parity was in error for a PIB write operation This bit is set by hardware under normal operations but can be forced using the OR mask register. This bit can be cleared using the CLEAR mask register.
13	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR2_SPARE1: Implemented but not used
14	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR2_SPARE_3: mplemented but not used Used to be ocb_fsm_err
15	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR2_SPARE2: Implemented but not used Writes store the value. Reads return the last value written.
16:63	RO	RO	RO	constant=0b000000000000000000000000000000000000000000000000

OCB_PIB OCB Error Status 2 Register
Addr:	000000000006D054 (SCOM)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBESR2
Constant(s):	PU_OCB_PIB_OCBESR2
Comments:	This PIB accessible register that indicates the OCI Address of a channel operation that detected the first error. See OCB Control/Status 0 Register for the specific error(s) detected. Set and Locked by hardware, Write to clear and Unlock.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.OCB_ERROR_ADDR_LT_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	RWX_WCLRREG			OCB_PIB_OCBESR2_OCB_ERROR_ADDR: OCI address being accessed when the first channel error is detected. This register is cleared upon writing any value.
32:63	RO			constant=0b00000000000000000000000000000000

OCB_PIB OCB Data 2 Register
Addr:	000000000006D055 (SCOM)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBDR2
Constant(s):	PU_OCB_PIB_OCBDR2
Comments:	This PIB accessible register captures the PIB data to be written on the OCI or the OCI data read returned without errors from the OCI address that is desired to be accessed.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_2.DATA_INDIR_LT_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RWX			OCB_PIB_OCBDR2_OCB_DATA: Data to/from OCI for this channel

OCB_PIB OCB Address 3 Register
Addr:	000000000006D070 (SCOM)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBAR3
Constant(s):	PU_OCB_PIB_OCBAR3
Comments:	This PIB accessible register captures the OCI address that is desired to be accessed.
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.ADDR_INDIR_OCI_REGION_LT_0_INST.LATC.L2(0:2) [000]
	3:28	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.ADDR_INDIR_LT_0_INST.LATC.L2(0:25) [00000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:2	RW			OCB_PIB_OCBAR3_OCI_REGION: OCI Address Space Region 0XX - Reserved 10X - PowerBus memory 110 - Register space 111 - SRAM
3:28	RW			OCB_PIB_OCBAR3_OCB_ADDRESS: Address of 8B quantity the OCI for this channel Field contents depends on accessed oci_region PowerBus 3:11 - Maskable Alignment (see PBA spec) 12:28 - Offset SRAM 3:4 - 128MB alias - bits are not compared 5:11 - 0b1111111 12:28 - Offset
29:63	RO			constant=0b00000000000000000000000000000000000

OCB_PIB OCB Control/Status 3 Register
Addr:	000000000006D071 (SCOM) 000000000006D072 (SCOM1) 000000000006D073 (SCOM2)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBCSR3
Constant(s):	PU_OCB_PIB_OCBCSR3
Comments:	This PIB accessible register that controls the function of the OCB channel and provides status of it. Note that this registers base address is Read-Only and can only be written "atomically" via the WO addresses.
SelectedAttributes:	Magic=true
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.IND_CHANNEL_CREG_Q_0_INST.LATC.L2(0:15) [0000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCBCSR3_PULL_READ_UNDERFLOW: Pull Queue Read Underflow Underflow is defined as a read to the OCB Data 3 Register and the pull_empty facility is already set. This bit is cleared only by a firmware write of this bit to 1.Writes store the value. Dial enums: UNDERFLOW_NOT_DETECTED=>0b0 UNDERFLOW_DETECTED=>0b1
1	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCBCSR3_PUSH_WRITE_OVERFLOW: Push Queue Write Overflow Overflow is defined as a store to the OCB Data 3 Register and the push_full facility is already set. This bit is cleared only by a firmware write of this bit to 1. Dial enums: OVERFLOW_NOT_DETECTED=>0b0 OVERFLOW_DETECTED=>0b1
2	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR3_PULL_READ_UNDERFLOW_EN: Enable the setting of pull_read_underflow by hardware. 0 - Underflow detection disabled 1 - Underflow detection enabled This bit is set using the OR mask register and cleared using the CLEAR mask register.
3	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR3_PUSH_WRITE_OVERFLOW_EN: Enable the setting of push_write_overflow by hardware. 0 - Overflow detection disabled 1 - OVerflow detection enabled This bit is set using the OR mask register and cleared using the CLEAR mask register.
4	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR3_OCB_STREAM_MODE: Put the bridge channel in streaming mode with the behavior further defined by the setting of ocb_stream_type 0 - Stream Mode Disabled 1 - Stream Mode Enabled This bit is set using the OR mask register and cleared using the CLEAR mask register.
5	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR3_OCB_STREAM_TYPE: Type of streaming enabled by ocb_stream_mode = 1 0 - Linear 1 - Circular For Linear type, the ocb_address field is incremented by 8 with each access to the OCB Data 3 Register. In Circular type, the address manipulation via access to OCB Stream [Push/Pull] Increment registers This bit is set using the OR mask register and cleared using the CLEAR mask register.
6:7	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR3_SPARE0: Implemented but not used
8	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCBCSR3_OCB_OCI_TIMEOUT: Indicates the MnTimeout signal on the OCI for the OCB Master was asserted to flag that no OCI slave acknowledged the request. This bit is set by hardware under normal operations but can be forced using the OR mask register. This bit can be cleared using the CLEAR mask register.
9	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCBCSR3_OCB_OCI_READ_DATA_PARITY: Indicates the OCI read data parity was in error This bit is set by hardware under normal operations but can be forced using the OR mask register. This bit can be cleared using the CLEAR mask register.
10	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCBCSR3_OCB_OCI_SLAVE_ERROR: Indicates the SlvError signal on the OCI for the OCB Master was asserted. This bit is set by hardware under normal operations but can be forced using the OR mask register. This bit can be cleared using the CLEAR mask register.
11	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCBCSR3_OCB_PIB_ADDR_PARITY_ERR: Indicates the PIB address parity was in error (PIB read or write operation) This bit is set by hardware under normal operations but can be forced using the OR mask register. This bit can be cleared using the CLEAR mask register.
12	ROX	WOX_CLEAR	WOX_OR	OCB_PIB_OCBCSR3_OCB_PIB_DATA_PARITY_ERR: Indicates the PIB data parity was in error for a PIB write operation This bit is set by hardware under normal operations but can be forced using the OR mask register. This bit can be cleared using the CLEAR mask register.
13	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR3_SPARE1: Implemented but not used
14	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR3_SPARE_3: mplemented but not used Used to be ocb_fsm_err
15	RO	WO_CLEAR	WO_OR	OCB_PIB_OCBCSR3_SPARE2: Implemented but not used Writes store the value. Reads return the last value written.
16:63	RO	RO	RO	constant=0b000000000000000000000000000000000000000000000000

OCB_PIB OCB Error Status 3 Register
Addr:	000000000006D074 (SCOM)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBESR3
Constant(s):	PU_OCB_PIB_OCBESR3
Comments:	This PIB accessible register that indicates the OCI Address of a channel operation that detected the first error. See OCB Control/Status 0 Register for the specific error(s) detected. Set and Locked by hardware, Write to clear and Unlock.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.OCB_ERROR_ADDR_LT_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	RWX_WCLRREG			OCB_PIB_OCBESR3_OCB_ERROR_ADDR: OCI address being accessed when the first channel error is detected. This register is cleared upon writing any value.
32:63	RO			constant=0b00000000000000000000000000000000

OCB_PIB OCB Data 3 Register
Addr:	000000000006D075 (SCOM)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBDR3
Constant(s):	PU_OCB_PIB_OCBDR3
Comments:	This PIB accessible register captures the PIB data to be written on the OCI or the OCI data read returned without errors from the OCI address that is desired to be accessed.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.OCC.OCI.OCB.OCB_INDIRECT_3.DATA_INDIR_LT_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RWX			OCB_PIB_OCBDR3_OCB_DATA: Data to/from OCI for this channel

OCB_PIB OCC Trace Debug Control Register
Addr:	000000000006D110 (SCOM)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OTDCR
Constant(s):	PU_OCB_PIB_OTDCR
Comments:	Register to active and control trace debug and htm function
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.OCC_OTDCR_Q_INST.LATC.L2(0:7) [00000000]
Bit(s)	SCOM			Dial: Description
0	RW			OCB_PIB_OTDCR_TRACE_BUS_EN: Trace Bus Enable
1	RW			OCB_PIB_OTDCR_OCB_TRACE_MUX_SEL: OCB Trace Bus Mux_Select 0 - select OCB group 1 1 - select OCB group 2
2:3	RW			OCB_PIB_OTDCR_OCC_TRACE_MUX_SEL: OCC Trace Bus Mux Select Connects to trace_mux4 macro in occ_top 00 - Select PMC trace bus 01 - Unused 10 - Select SRAM trace bus 11 - Overview Mode : SRAM(0:11) & PMC(0:11)
4:7	RW			OCB_PIB_OTDCR_OCI_TRACE_MUX_SEL: OCC Trace Bus Mux Select 0000 - Select OCB trace bus 0001 - Select trace_mux4 trace data (SRAM) 0010 - Select PLB trace data 0011 - Select GPE0 trace data 0100 - Select GPE1 trace data 0101 - Select GPE2 trace data 0110 - Select GPE3 trace data 0111 - Select OCC Overview Mode1 trace data 1000 - Select OCC Overview Mode2 trace data 1001 - Select OCC Idle debug trace bus 1010 - Select OCC PM debug trace bus 1011 - Select OCC PCB debug trace bus 1100 - Select OCC PMC debug trace bus 1101 - Select OCC DCMSPI debug trace bus 1110:1111 - unused
8:63	RO			constant=0b00000000000000000000000000000000000000000000000000000000

OCB_PIB OCC PPC405 Cache Error Injection Control Register
Addr:	000000000006D111 (SCOM)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OPPCINJ
Constant(s):	PU_OCB_PIB_OPPCINJ
Comments:	Register to control CE and UE error injection into the PPC405 caches
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.OCC_OPPCINJ_Q_INST.LATC.L2(0:3) [0000]
Bit(s)	SCOM			Dial: Description
0	RW			OCB_PIB_OPPCINJ_OCI_ERR_INJ_DCU: Enable PPC405 data cache error injection
1	RW			OCB_PIB_OPPCINJ_OCI_ERR_INJ_ICU: Enable PPC405 instruction cache error injection
2	RW			OCB_PIB_OPPCINJ_OCI_ERR_INJ_CE_UE: Select CE or UE injection 0 : inject CE 1 : inject UE
3	RW			OCB_PIB_OPPCINJ_OCI_ERR_INJ_SINGL_CONT: Select single or continous injection 0: inject until first error is detected 1: inject continuously
4:63	RO			constant=0b000000000000000000000000000000000000000000000000000000000000

OCB_PIB OCC Special Timeout Error Address Register
Addr:	000000000006D200 (SCOM)
Name:	TP.TPCHIP.OCC.OCI.PLBTO.OCB_PIB_OSTOEAR
Constant(s):
Comments:	The OCC Special Timeout Error Address Register (OSTOEAR) is a 32-bit read-only register which contains the address of the access where the bus time-out error occurred when initiated from either the PPC405 Instruction Cache or Data Cache ports. As in the case of the OSTOESR error status fields (see "OCC Speical Timeout Error Status Register (OSTOESR)"), the OSTOEAR is locked when a timeout occurs on either cache port. Once locked, the OSTOEAR cannot be updated if any subsequent error occurs until both timeout error bits in the OSTOESR are cleared.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.PLBTO.PLBTO_V.morph_dff_alg_STO_PEAR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	RO			OCB_PIB_OSTOEAR_OCC_SPCL_TIMEOUT_ADDR: OCC Special Timeout Address from PPC405 access
32:63	RO			constant=0b00000000000000000000000000000000

OCB_PIB OCC Special Timeout Error Status Register
Addr:	000000000006D201 (SCOM)
Name:	TP.TPCHIP.OCC.OCI.PLBTO.OCB_PIB_OSTOESR
Constant(s):
Comments:	This register contains status information pertaining to the Special Timeouts associated with the PPC405 Instruction Cache or Data Cache ports accessing the OCI bus.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.OCC.OCI.PLBTO.PLBTO_V.morph_dff_alg_STO_PESR.LATC.L2(0:7) [00000000]
Bit(s)	SCOM			Dial: Description
0	RWX_WCLEAR			OCB_PIB_OSTOESR_ICU_TIMEOUT_ERROR: Indicates that a PPC405 Instruction Cache operation encountered an OCI timeout
1	RWX_WCLEAR			OCB_PIB_OSTOESR_ICU_RNW: Indicates the type of PPC405 Instruction Cache operation being performed that timed out. Dial enums: WRITE=>0b0 READ=>0b1
2:3	RW_WCLEAR			OCB_PIB_OSTOESR_RESERVED_2_3: Reserved bits
4	RWX_WCLEAR			OCB_PIB_OSTOESR_DCU_TIMEOUT_ERROR: Status bit to indicate that a PPC405 Data Cache operation encountered an OCI timeout
5	RWX_WCLEAR			OCB_PIB_OSTOESR_DCU_RNW: Indicates the type of PPC405 Data Cache operation being performed that timed out. Dial enums: WRITE=>0b0 READ=>0b1
6:7	RW_WCLEAR			OCB_PIB_OSTOESR_RESERVED_6_7: Reserved bits
8:63	RO			constant=0b00000000000000000000000000000000000000000000000000000000

OCB_PIB OCI Arbiter Revision ID (OREV)
Addr:	000000000006D202 (SCOM)
Name:	TP.TPCHIP.OCC.OCI.ARB.OCB_PIB_OREV
Constant(s):
Comments:	The OCI (PLB) Revision ID Register (OREV) is a 32-bit read-only register which contains the revision ID of the OCI (PLB) arbiter core. This is a read-only register.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.ARB.PLBARB4_V.PLB4ARB8M_ARB_TOP1.pRevData(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	RO			oci_arb_revision
32:63	RO			constant=0b00000000000000000000000000000000

OCB_PIB OCI Error Status Register
Addr:	000000000006D204 (SCOM)
Name:	TP.TPCHIP.OCC.OCI.ARB.OCB_PIB_OESR
Constant(s):
Comments:	The OCI Error Status Register (OESR) is a 32-bit register whose bits identify time-out errors on OCI bus transfers, the master initiating the transfer, and the type of transfer. Each master error status field can be locked by the master having its Mn_lockErr signal asserted for the transfer in which the time-out is encountered. Once locked, the master error status field cannot be updated if any subsequent error occurs until the FLCK bit is cleared. To clear a bit in the OESR, a "1" must be written to the bit. Writing a "0" to any bit in the OESR will not affect the status of the bit.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.ARB.PLBARB4_V.PLB4ARB8M_ARB_TOP1.morph_dff_alg_reg_PLB_pesr.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RWX_WCLEAR			OCB_PIB_OESR_OCI_M0_TIMEOUT_ERROR: Master 0 OCI timeout error status Dial enums: NO_MASTER_0_TIMEOUT_ERROR_=>0b0 MASTER_0_TIMEOUT_ERROR_=>0b1
1	RWX_WCLEAR			OCB_PIB_OESR_OCI_M0_RW_STATUS: Master 0 read/write status Dial enums: MASTER_0_ERROR_OPERATION_WAS_A_WRITE_=>0b0 MASTER_0_ERROR_OPERATION_WAS_A_READ_=>0b1
2	RWX_WCLEAR			OCB_PIB_OESR_OCI_M0_OESR_FLCK: Master 0 OESR field lock Dial enums: MASTER_0_OESR_FIELD_IS_UNLOCKED_=>0b0 MASTER_0_FIELD_IS_LOCKED=>0b1
3	RWX_WCLEAR			OCB_PIB_OESR_OCI_M0_OEAR_LOCK: Master 0 OEAR address lock Dial enums: MASTER_0_OEAR_IS_UNLOCKED_=>0b0 MASTER_0_OEAR_IS_LOCKED_=>0b1
4	RWX_WCLEAR			OCB_PIB_OESR_OCI_M1_TIMEOUT_ERROR: Master 1 OCI timeout error status Dial enums: NO_MASTER_1_TIMEOUT_ERROR_=>0b0 MASTER_1_TIMEOUT_ERROR_=>0b1
5	RWX_WCLEAR			OCB_PIB_OESR_OCI_M1_RW_STATUS: Master 1 read/write status Dial enums: MASTER_1_ERROR_OPERATION_WAS_A_WRITE_=>0b0 MASTER_1_ERROR_OPERATION_WAS_A_READ_=>0b1
6	RWX_WCLEAR			OCB_PIB_OESR_OCI_M1_OESR_FLCK: Master 1 OESR field lock Dial enums: MASTER_1_OESR_FIELD_IS_UNLOCKED_=>0b0 MASTER_1_FIELD_IS_LOCKED=>0b1
7	RWX_WCLEAR			OCB_PIB_OESR_OCI_M1_OEAR_LOCK: Master 1 OEAR address lock Dial enums: MASTER_1_OEAR_IS_UNLOCKED_=>0b0 MASTER_1_OEAR_IS_LOCKED_=>0b1
8	RWX_WCLEAR			OCB_PIB_OESR_OCI_M2_TIMEOUT_ERROR: Master 2 OCI timeout error status Dial enums: NO_MASTER_2_TIMEOUT_ERROR_=>0b0 MASTER_2_TIMEOUT_ERROR_=>0b1
9	RWX_WCLEAR			OCB_PIB_OESR_OCI_M2_RW_STATUS: Master 2 read/write status Dial enums: MASTER_2_ERROR_OPERATION_WAS_A_WRITE_=>0b0 MASTER_2_ERROR_OPERATION_WAS_A_READ_=>0b1
10	RWX_WCLEAR			OCB_PIB_OESR_OCI_M2_OESR_FLCK: Master 2 OESR field lock Dial enums: MASTER_2_OESR_FIELD_IS_UNLOCKED_=>0b0 MASTER_2_FIELD_IS_LOCKED=>0b1
11	RWX_WCLEAR			OCB_PIB_OESR_OCI_M2_OEAR_LOCK: Master 2 OEAR address lock Dial enums: MASTER_2_OEAR_IS_UNLOCKED_=>0b0 MASTER_2_OEAR_IS_LOCKED_=>0b1
12	RWX_WCLEAR			OCB_PIB_OESR_OCI_M3_TIMEOUT_ERROR: Master 3 OCI timeout error status Dial enums: NO_MASTER_3_TIMEOUT_ERROR_=>0b0 MASTER_3_TIMEOUT_ERROR_=>0b1
13	RWX_WCLEAR			OCB_PIB_OESR_OCI_M3_RW_STATUS: Master 3 read/write status Dial enums: MASTER_3_ERROR_OPERATION_WAS_A_WRITE_=>0b0 MASTER_3_ERROR_OPERATION_WAS_A_READ_=>0b1
14	RWX_WCLEAR			OCB_PIB_OESR_OCI_M3_OESR_FLCK: Master 3 OESR field lock Dial enums: MASTER_3_OESR_FIELD_IS_UNLOCKED_=>0b0 MASTER_3_FIELD_IS_LOCKED=>0b1
15	RWX_WCLEAR			OCB_PIB_OESR_OCI_M3_OEAR_LOCK: Master 3 OEAR address lock Dial enums: MASTER_3_OEAR_IS_UNLOCKED_=>0b0 MASTER_3_OEAR_IS_LOCKED_=>0b1
16	RWX_WCLEAR			OCB_PIB_OESR_OCI_M4_TIMEOUT_ERROR: Master 4 OCI timeout error status Dial enums: NO_MASTER_4_TIMEOUT_ERROR_=>0b0 MASTER_4_TIMEOUT_ERROR_=>0b1
17	RWX_WCLEAR			OCB_PIB_OESR_OCI_M4_RW_STATUS: Master 4 read/write status Dial enums: MASTER_4_ERROR_OPERATION_WAS_A_WRITE_=>0b0 MASTER_4_ERROR_OPERATION_WAS_A_READ_=>0b1
18	RWX_WCLEAR			OCB_PIB_OESR_OCI_M4_OESR_FLCK: Master 4 OESR field lock Dial enums: MASTER_4_OESR_FIELD_IS_UNLOCKED_=>0b0 MASTER_4_FIELD_IS_LOCKED=>0b1
19	RWX_WCLEAR			OCB_PIB_OESR_OCI_M4_OEAR_LOCK: Master 4 OEAR address lock Dial enums: MASTER_4_OEAR_IS_UNLOCKED_=>0b0 MASTER_4_OEAR_IS_LOCKED_=>0b1
20	RWX_WCLEAR			OCB_PIB_OESR_OCI_M5_TIMEOUT_ERROR: Master 5 OCI timeout error status Dial enums: NO_MASTER_5_TIMEOUT_ERROR_=>0b0 MASTER_5_TIMEOUT_ERROR_=>0b1
21	RWX_WCLEAR			OCB_PIB_OESR_OCI_M5_RW_STATUS: Master 5 read/write status Dial enums: MASTER_5_ERROR_OPERATION_WAS_A_WRITE_=>0b0 MASTER_5_ERROR_OPERATION_WAS_A_READ_=>0b1
22	RWX_WCLEAR			OCB_PIB_OESR_OCI_M5_OESR_FLCK: Master 5 OESR field lock Dial enums: MASTER_5_OESR_FIELD_IS_UNLOCKED_=>0b0 MASTER_5_FIELD_IS_LOCKED=>0b1
23	RWX_WCLEAR			OCB_PIB_OESR_OCI_M5_OEAR_LOCK: Master 5 OEAR address lock Dial enums: MASTER_5_OEAR_IS_UNLOCKED_=>0b0 MASTER_5_OEAR_IS_LOCKED_=>0b1
24	RWX_WCLEAR			OCB_PIB_OESR_OCI_M6_TIMEOUT_ERROR: Master 6 OCI timeout error status Dial enums: NO_MASTER_6_TIMEOUT_ERROR_=>0b0 MASTER_6_TIMEOUT_ERROR_=>0b1
25	RWX_WCLEAR			OCB_PIB_OESR_OCI_M6_RW_STATUS: Master 6 read/write status Dial enums: MASTER_6_ERROR_OPERATION_WAS_A_WRITE_=>0b0 MASTER_6_ERROR_OPERATION_WAS_A_READ_=>0b1
26	RWX_WCLEAR			OCB_PIB_OESR_OCI_M6_OESR_FLCK: Master 6 OESR field lock Dial enums: MASTER_6_OESR_FIELD_IS_UNLOCKED_=>0b0 MASTER_6_FIELD_IS_LOCKED=>0b1
27	RWX_WCLEAR			OCB_PIB_OESR_OCI_M6_OEAR_LOCK: Master 6 OEAR address lock Dial enums: MASTER_6_OEAR_IS_UNLOCKED_=>0b0 MASTER_6_OEAR_IS_LOCKED_=>0b1
28	RWX_WCLEAR			OCB_PIB_OESR_OCI_M7_TIMEOUT_ERROR: Master 7 OCI timeout error status Dial enums: NO_MASTER_7_TIMEOUT_ERROR_=>0b0 MASTER_7_TIMEOUT_ERROR_=>0b1
29	RWX_WCLEAR			OCB_PIB_OESR_OCI_M7_RW_STATUS: Master 7 read/write status Dial enums: MASTER_7_ERROR_OPERATION_WAS_A_WRITE_=>0b0 MASTER_7_ERROR_OPERATION_WAS_A_READ_=>0b1
30	RWX_WCLEAR			OCB_PIB_OESR_OCI_M7_OESR_FLCK: Master 7 OESR field lock Dial enums: MASTER_7_OESR_FIELD_IS_UNLOCKED_=>0b0 MASTER_7_FIELD_IS_LOCKED=>0b1
31	RWX_WCLEAR			OCB_PIB_OESR_OCI_M7_OEAR_LOCK: Master 7 OEAR address lock Dial enums: MASTER_7_OEAR_IS_UNLOCKED_=>0b0 MASTER_7_OEAR_IS_LOCKED_=>0b1
32:63	RO			constant=0b00000000000000000000000000000000 Dial enums: MASTER_7_OEAR_IS_UNLOCKED_=>0b0 MASTER_7_OEAR_IS_LOCKED_=>0b1

OCB_PIB OCI Error Address Register
Addr:	000000000006D206 (SCOM)
Name:	TP.TPCHIP.OCC.OCI.ARB.OCB_PIB_OEAR
Constant(s):
Comments:	The OCI Error Address Register (OEAR) is a 32-bit read-only register which contains the address of the access where the bus time-out error occurred. As in the case of the OESR master error status fields (see "OCI Error Status Register (OESR)"), the OEAR can be locked by the master having its Mn_lockErr signal asserted for the transfer. Once locked, the OEAR cannot be updated if any subsequent error occurs until all FLCK bits in the OESR are cleared.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.OCC.OCI.ARB.PLBARB4_V.PLB4ARB8M_ARB_TOP1.morph_dff_alg_reg_PLB_pearl.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	ROX			OCB_PIB_OEAR_OCI_TIMEOUT_ADDR: OCI Timeout Address
32:63	RO			constant=0b00000000000000000000000000000000

OCB_PIB OCI Arbiter Control Register
Addr:	000000000006D207 (SCOM)
Name:	TP.TPCHIP.OCC.OCI.ARB.OCB_PIB_OACR
Constant(s):
Comments:	The OCI Arbiter Control Register (OACR) is a 32-bit register which controls the modes of operation for the arbiter. The priority mode, priority order, high bus utilization, read pipeline enable, and write pipeline enable are contained in this register.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.OCC.OCI.ARB.PLBARB4_V.PLB4ARB8M_ARB_TOP1.morph_dff_alg_reg_PLB_pacr.LATC.L2(0:7) [00000000]
Bit(s)	SCOM			Dial: Description
0	RW			OCB_PIB_OACR_OCI_PRIORITY_MODE: OCI priority mode Dial enums: FIXED=>0b0 FAIR=>0b1
1:3	RWX			OCB_PIB_OACR_OCI_PRIORITY_ORDER: OCI priority order. When in Fair priority mode, this will change after each OCI transaction. 000 Masters 0, 1, 2, 3, 4, 5, 6, 7 001 Masters 1, 2, 3, 4, 5, 6, 7, 0 010 Masters 2, 3, 4, 5, 6, 7, 0, 1 011 Masters 3, 4, 5, 6, 7, 0, 1, 2 100 Masters 4, 5, 6, 7, 0, 1, 2, 3 101 Masters 5, 6, 7, 0, 1, 2, 3, 4 110 Masters 6, 7, 0, 1, 2, 3, 4, 5 111 Masters 7, 0, 1, 2, 3, 4, 5, 6
4	RW			OCB_PIB_OACR_OCI_HI_BUS_MODE: High Bus Utilization (See OCI arbiter documenation for description) Dial enums: DISABLED=>0b0 ENABLED=>0b1
5:6	RW			OCB_PIB_OACR_OCI_READ_PIPELINE_CONTROL: Read Pipeline Control 00 - read pipelining disabled 01 - 2 Deep read pipe 10 - 3 Deep read pipe 11 - 4 Deep read pipe
7	RW			OCB_PIB_OACR_OCI_WRITE_PIPELINE_CONTROL: Write Pipeline Control 0 - write pipelining disabled 1 - 2 Deep write pipe
8:63	RO			constant=0b00000000000000000000000000000000000000000000000000000000

OCB_PIB OCB Error Address Register
Addr:	000000000006D210 (SCOM)
Name:	TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBEAR
Constant(s):	PU_OCB_PIB_OCBEAR
Comments:	The OCB Error Address Register (OCBEAR) is a 32-bit register which captures the error address of a bridge operation when any of OCI Timeout, OCI Read Data Parity Error or OCI Slave Error occur. This register, used in combination with the OCI Arbiter error capture registers, allows for isolation of hardware and/or firmware issues. Note: in the case of OCI Timeout, the address may match that captured in OESR within the arbiter but this is not guaranteed. The OESR can lock on the first error and that may not necessarily be due an OCB operation. This entire register will lock when capturing any non-zero address. Any write to the OCBEAR will clear the full contents.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:39	TP.TPCHIP.OCC.OCI.OCB.ITPCTRL.OCC_OCBEAR_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	RW_WCLRPART			OCB_PIB_OCBEAR_OCB_ERROR_ADDRESS: Captured address upon OCI errors
32:34	RW_WCLRPART			OCB_PIB_OCBEAR_RESERVED_32_34: Reserved bits
35	RW_WCLRPART			OCB_PIB_OCBEAR_DIRECT_BRIDGE_SOURCE: Address was source via the Direct Bridge
36	RW_WCLRPART			OCB_PIB_OCBEAR_INDIRECT_BRIDGE_0_SOURCE: Address was source via the Indirect Bridge 0
37	RW_WCLRPART			OCB_PIB_OCBEAR_INDIRECT_BRIDGE_1_SOURCE: Address was source via the Indirect Bridge 1
38	RW_WCLRPART			OCB_PIB_OCBEAR_INDIRECT_BRIDGE_2_SOURCE: Address was source via the Indirect Bridge 2
39	RW_WCLRPART			OCB_PIB_OCBEAR_INDIRECT_BRIDGE_3_SOURCE: Address was source via the Indirect Bridge 3
40:63	RO			constant=0b000000000000000000000000

spi master error inject register
Addr:	0000000000070000 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0_ERROR_INJECT_
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0.CONFIG.ERROR_REG_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0:7	RWX			SPIMST0_ERROR_INJECT_PULSE: error inject pulse
8:15	RWX			SPIMST0_ERROR_INJECT_MASK: error inject mask
16:31	RWX			SPIMST0_ERROR_MASK: error mask
32:63	RWX			SPIMST0_ERROR_UNUSED: error unused

spi master counter configuration register
Addr:	0000000000070001 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0_COUNTER
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0.CONFIG.COUNTER_REG_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0:7	RWX			SPIMST0_COUNT_N1: counter N1 register
8:15	RWX			SPIMST0_COUNT_N2: counter N1 register
16:23	RWX			SPIMST0_COUNT_RESERVED_A: counter reserved area a register
24:31	RWX			SPIMST0_LOOPCOUNT: loop count compare register for BNEI operation
32:39	RWX			SPIMST0_LOOPCOUNT2: loop count 2 compare register for BNEI2 operation
40:47	RWX			SPIMST0_SHIFTER_FSM_CONTROL: shifter fsm control bits
48:51	RWX			SPIMST0_N1_CONTROL: shift counter N1 control bits
52:55	RWX			SPIMST0_N2_CONTROL: shift counter N2 control bits
56:63	RWX			SPIMST0_COUNT_RESERVED_B: counter reserved area b register

spi master configuration 1 register
Addr:	0000000000070002 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0_CONFIG1
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0.CONFIG.CONFIG1_REG_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0	ROX			SPIMST0_SPI_RESOURCE_LOCK: reserved
1:4	ROX			SPIMST0_PIB_MASTER_ID: PIB master id that has reserved the device
5:63	RWX			SPIMST0_CONFIG1_REG_UNUSED: reserved register space

spi master clock configuration register
Addr:	0000000000070003 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0_CLOCK_CONFIG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0.CONFIG.CLOCK_CONFIG_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0:11	RWX			SPIMST0_SCK_CLOCK_DIVIDER: SCK_clock_divider
12:19	RWX			SPIMST0_SCK_RECEIVE_DELAY: SCK_receive_delay
20	RWX			SPIMST0_ENABLE_RECEIVE_PACING: enable_receive_pacing
21	RWX			SPIMST0_SPIMST_TRACE_ENABLE: SCK clock_phase
22:23	RWX			SPIMST0_SCK_TRACE_SELECT: trace_select
24:27	RWX			SPIMST0_SCK_RESET_CONTROL: reset_control
28	RWX			SPIMST0_SCK_ECC_SPIMM_ADDR_CORR_DIS: SCK_ecc_spimm_addr_corr_dis
29:30	RWX			SPIMST0_SCK_ECC_CONTROL: ecc_control
31	RWX			SPIMST0_SCK_MMSPISM_ENABLE: mmSPIsm_enable
32:35	RWX			SPIMST0_SPI_SLAVE_RESET: hardware reset signal for spi slave
36	RWX			SPIMST0_LOOPBACK_ENABLE: loopback mode enable
37:63	RWX			SPIMST0_CLOCK_CONFIG_RESERVED: clock config reserved

spi master pattern match register
Addr:	0000000000070004 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0_MEMORY_MAPPING
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0.CONFIG.MEMORY_MAPPING_REG_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0:15	RWX			SPIMST0_MEMORY_MAPPING_BASE: memory mapping address base
16:31	RWX			SPIMST0_MEMORY_MAPPING_MASK: memory mapping address mask
32:47	RWX			SPIMST0_PATTERN_MATCH_COMPARE: serial receive pattern match compare value
48:63	RWX			SPIMST0_PATTERN_MATCH_MASK: serial receive pattern match compare value

spi master transmit data register
Addr:	0000000000070005 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0_TRANSMIT_DATA_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0.CONFIG.TRANSMIT_DATA_REG_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0:63	RWX			SPIMST0_TRANSMIT_DATA_REG_Q: spi master tranmsit data register

spi master receive data register
Addr:	0000000000070006 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0_RECEIVE_DATA_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0.CONFIG.RECEIVE_DATA_REG_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0:63	ROX			SPIMST0_RECEIVE_DATA_REG_Q: spi master receive data register

spi master sequencer operation register
Addr:	0000000000070007 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0_SEQUENCER_OP_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0.CONFIG.SEQUENCER_OP_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0:63	RWX			SPIMST0_SEQUENCER_OP_Q: spi master sequencer operation register

spi master status register
Addr:	0000000000070008 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0_STATUS_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0.CONFIG.SPI_CONFIG_FUNC_Q_INST.FSILAT.LATCH.LATC.L2(12:15) [0000]
	4:7	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0.CONFIG.SPI_CONFIG_FUNC_Q_INST.FSILAT.LATCH.LATC.L2(8:11) [0000]
	8:15	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0.SEQ.FUNC_SEQUENCER_LATCHES_Q_INST.FSILAT.LATCH.LATC.L2(16:23) [00000000]
	16:27	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0.SHIFT.FUNC_SHIFTER_LATCHES_Q_INST.FSILAT.LATCH.LATC.L2(24:35) [000000000000]
	28:31	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0.SEQ.FUNC_SEQUENCER_LATCHES_Q_INST.FSILAT.LATCH.LATC.L2(4:7) [0000]
	32:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0.CONFIG.SPI_STATUS_Q_INST.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0	RWX			SPIMST0_RDR_FULL_STATUS: indication for receive data register full
1	RWX			SPIMST0_RDR_OVER_STATUS: indication for receive data register overrun
2	RWX			SPIMST0_RDR_UNDER_STATUS: indication for receive data register underrun
3	RWX			SPIMST0_RDR_RESERVED_STATUS: indication for receive data register reserved status, unused
4	RWX			SPIMST0_TDR_FULL_STATUS: indication for transmit data register full
5	RWX			SPIMST0_TDR_OVER_STATUS: indication for transmit data register overrun
6	RWX			SPIMST0_TDR_UNDER_STATUS: indication for transmit data register underrun
7	RWX			SPIMST0_TDR_RESERVED_STATUS: indication for transmit data register reserved status, unused
8:15	ROX			SPIMST0_SEQUENCER_FSM: sequencer finit state machine bit coding
16:27	ROX			SPIMST0_SHIFTER_FSM: shifter finit state machine bit coding
28:31	ROX			SPIMST0_SEQUENCER_OP_INDEX: sequencer operation index
32	RWX			SPIMST0_COUNTER_REG_PARITY_ERRS: counter configuration register parity error
33	RWX			SPIMST0_CLOCK_REG_PARITY_ERR: clock configuration register parity error
34	RWX			SPIMST0_SEQUENCER_REG_PARITY_ERR: sequencer configuration register parity error
35	RWX			SPIMST0_SEQUENCER_FSM_PARITY_ERR: sequencer fsm parity error
36	RWX			SPIMST0_SHIFTER_FSM_PARITY_ERR: shifter fsm parity error
37	RWX			SPIMST0_PATTERN_REG_PARITY_ERR: pattern match register parity error
38	RWX			SPIMST0_TDR_REG_PARITY_ERR: transmit data register parity error
39	RWX			SPIMST0_RDR_REG_PARITY_ERR: receive data register parity error
40	RWX			SPIMST0_CONFIG_REG1_PARITY_ERR: configuration register 1 parity error
41	RWX			SPIMST0_UNUSED_PARITY_ERR: unused
42	RWX			SPIMST0_ERROR_REG_PARITY_ERR: error register parity error
43	RWX			SPIMST0_ECC_CORRECTABLE_ERR: ecc correctable error
44	RWX			SPIMST0_ECC_UNCORRECTABLE_ERR: ecc uncorrectable error
45:46	RWX			SPIMST0_ECC_STATUS: general ecc status (unsued)
47	RWX			SPIMST0_MM_ADDR_OVERLAP: memory mapped SPI address overlap
48:49	RWX			SPIMST0_ACCESS_VIOLATION: general access violation
50	RWX			SPIMST0_PORT_MULTIPLEXER_ERR: port multiplexer error
51	RWX			SPIMST0_ADDR_OUT_OF_RANGE: address range error
52	RWX			SPIMST0_MEM_MAPPING_OVERLAP: memory mapping overlap error
53	RWX			SPIMST0_SEQUENCER_SLAVE_SEL_ERR: sequencer slave select error
54	RWX			SPIMST0_SEQUENCER_FSM_ERR: sequencer fsm error
55	RWX			SPIMST0_SHIFTER_FSM_ERR: shifter fsm error
56	RWX			SPIMST0_ANY_CONFIG_PARITY_ERR: any config parity error
57	RWX			SPIMST0_SPI_PORT_MUX_INDICATOR: indication of SPI port multiplexer, must indicate zero for this SPI to run
58	RWX			SPIMST0_SPI_SEC_PIB_RETRY_RSP_INFO: indication of SPI security problem during PIB Write access
59:63	RWX			SPIMST0_UNUSED: unused

spi master error inject register
Addr:	0000000000070020 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1_ERROR_INJECT_
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1.CONFIG.ERROR_REG_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0:7	RWX			SPIMST1_ERROR_INJECT_PULSE: error inject pulse
8:15	RWX			SPIMST1_ERROR_INJECT_MASK: error inject mask
16:31	RWX			SPIMST1_ERROR_MASK: error mask
32:63	RWX			SPIMST1_ERROR_UNUSED: error unused

spi master counter configuration register
Addr:	0000000000070021 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1_COUNTER
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1.CONFIG.COUNTER_REG_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0:7	RWX			SPIMST1_COUNT_N1: counter N1 register
8:15	RWX			SPIMST1_COUNT_N2: counter N1 register
16:23	RWX			SPIMST1_COUNT_RESERVED_A: counter reserved area a register
24:31	RWX			SPIMST1_LOOPCOUNT: loop count compare register for BNEI operation
32:39	RWX			SPIMST1_LOOPCOUNT2: loop count 2 compare register for BNEI2 operation
40:47	RWX			SPIMST1_SHIFTER_FSM_CONTROL: shifter fsm control bits
48:51	RWX			SPIMST1_N1_CONTROL: shift counter N1 control bits
52:55	RWX			SPIMST1_N2_CONTROL: shift counter N2 control bits
56:63	RWX			SPIMST1_COUNT_RESERVED_B: counter reserved area b register

spi master configuration 1 register
Addr:	0000000000070022 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1_CONFIG1
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1.CONFIG.CONFIG1_REG_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0	ROX			SPIMST1_SPI_RESOURCE_LOCK: reserved
1:4	ROX			SPIMST1_PIB_MASTER_ID: PIB master id that has reserved the device
5:63	RWX			SPIMST1_CONFIG1_REG_UNUSED: reserved register space

spi master clock configuration register
Addr:	0000000000070023 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1_CLOCK_CONFIG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1.CONFIG.CLOCK_CONFIG_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0:11	RWX			SPIMST1_SCK_CLOCK_DIVIDER: SCK_clock_divider
12:19	RWX			SPIMST1_SCK_RECEIVE_DELAY: SCK_receive_delay
20	RWX			SPIMST1_ENABLE_RECEIVE_PACING: enable_receive_pacing
21	RWX			SPIMST1_SPIMST_TRACE_ENABLE: SCK clock_phase
22:23	RWX			SPIMST1_SCK_TRACE_SELECT: trace_select
24:27	RWX			SPIMST1_SCK_RESET_CONTROL: reset_control
28	RWX			SPIMST1_SCK_ECC_SPIMM_ADDR_CORR_DIS: SCK_ecc_spimm_addr_corr_dis
29:30	RWX			SPIMST1_SCK_ECC_CONTROL: ecc_control
31	RWX			SPIMST1_SCK_MMSPISM_ENABLE: mmSPIsm_enable
32:35	RWX			SPIMST1_SPI_SLAVE_RESET: hardware reset signal for spi slave
36	RWX			SPIMST1_LOOPBACK_ENABLE: loopback mode enable
37:63	RWX			SPIMST1_CLOCK_CONFIG_RESERVED: clock config reserved

spi master pattern match register
Addr:	0000000000070024 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1_MEMORY_MAPPING
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1.CONFIG.MEMORY_MAPPING_REG_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0:15	RWX			SPIMST1_MEMORY_MAPPING_BASE: memory mapping address base
16:31	RWX			SPIMST1_MEMORY_MAPPING_MASK: memory mapping address mask
32:47	RWX			SPIMST1_PATTERN_MATCH_COMPARE: serial receive pattern match compare value
48:63	RWX			SPIMST1_PATTERN_MATCH_MASK: serial receive pattern match compare value

spi master transmit data register
Addr:	0000000000070025 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1_TRANSMIT_DATA_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1.CONFIG.TRANSMIT_DATA_REG_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0:63	RWX			SPIMST1_TRANSMIT_DATA_REG_Q: spi master tranmsit data register

spi master receive data register
Addr:	0000000000070026 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1_RECEIVE_DATA_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1.CONFIG.RECEIVE_DATA_REG_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0:63	ROX			SPIMST1_RECEIVE_DATA_REG_Q: spi master receive data register

spi master sequencer operation register
Addr:	0000000000070027 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1_SEQUENCER_OP_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1.CONFIG.SEQUENCER_OP_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0:63	RWX			SPIMST1_SEQUENCER_OP_Q: spi master sequencer operation register

spi master status register
Addr:	0000000000070028 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1_STATUS_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1.CONFIG.SPI_CONFIG_FUNC_Q_INST.FSILAT.LATCH.LATC.L2(12:15) [0000]
	4:7	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1.CONFIG.SPI_CONFIG_FUNC_Q_INST.FSILAT.LATCH.LATC.L2(8:11) [0000]
	8:15	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1.SEQ.FUNC_SEQUENCER_LATCHES_Q_INST.FSILAT.LATCH.LATC.L2(16:23) [00000000]
	16:27	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1.SHIFT.FUNC_SHIFTER_LATCHES_Q_INST.FSILAT.LATCH.LATC.L2(24:35) [000000000000]
	28:31	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1.SEQ.FUNC_SEQUENCER_LATCHES_Q_INST.FSILAT.LATCH.LATC.L2(4:7) [0000]
	32:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1.CONFIG.SPI_STATUS_Q_INST.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0	RWX			SPIMST1_RDR_FULL_STATUS: indication for receive data register full
1	RWX			SPIMST1_RDR_OVER_STATUS: indication for receive data register overrun
2	RWX			SPIMST1_RDR_UNDER_STATUS: indication for receive data register underrun
3	RWX			SPIMST1_RDR_RESERVED_STATUS: indication for receive data register reserved status, unused
4	RWX			SPIMST1_TDR_FULL_STATUS: indication for transmit data register full
5	RWX			SPIMST1_TDR_OVER_STATUS: indication for transmit data register overrun
6	RWX			SPIMST1_TDR_UNDER_STATUS: indication for transmit data register underrun
7	RWX			SPIMST1_TDR_RESERVED_STATUS: indication for transmit data register reserved status, unused
8:15	ROX			SPIMST1_SEQUENCER_FSM: sequencer finit state machine bit coding
16:27	ROX			SPIMST1_SHIFTER_FSM: shifter finit state machine bit coding
28:31	ROX			SPIMST1_SEQUENCER_OP_INDEX: sequencer operation index
32	RWX			SPIMST1_COUNTER_REG_PARITY_ERRS: counter configuration register parity error
33	RWX			SPIMST1_CLOCK_REG_PARITY_ERR: clock configuration register parity error
34	RWX			SPIMST1_SEQUENCER_REG_PARITY_ERR: sequencer configuration register parity error
35	RWX			SPIMST1_SEQUENCER_FSM_PARITY_ERR: sequencer fsm parity error
36	RWX			SPIMST1_SHIFTER_FSM_PARITY_ERR: shifter fsm parity error
37	RWX			SPIMST1_PATTERN_REG_PARITY_ERR: pattern match register parity error
38	RWX			SPIMST1_TDR_REG_PARITY_ERR: transmit data register parity error
39	RWX			SPIMST1_RDR_REG_PARITY_ERR: receive data register parity error
40	RWX			SPIMST1_CONFIG_REG1_PARITY_ERR: configuration register 1 parity error
41	RWX			SPIMST1_UNUSED_PARITY_ERR: unused
42	RWX			SPIMST1_ERROR_REG_PARITY_ERR: error register parity error
43	RWX			SPIMST1_ECC_CORRECTABLE_ERR: ecc correctable error
44	RWX			SPIMST1_ECC_UNCORRECTABLE_ERR: ecc uncorrectable error
45:46	RWX			SPIMST1_ECC_STATUS: general ecc status (unsued)
47	RWX			SPIMST1_MM_ADDR_OVERLAP: memory mapped SPI address overlap
48:49	RWX			SPIMST1_ACCESS_VIOLATION: general access violation
50	RWX			SPIMST1_PORT_MULTIPLEXER_ERR: port multiplexer error
51	RWX			SPIMST1_ADDR_OUT_OF_RANGE: address range error
52	RWX			SPIMST1_MEM_MAPPING_OVERLAP: memory mapping overlap error
53	RWX			SPIMST1_SEQUENCER_SLAVE_SEL_ERR: sequencer slave select error
54	RWX			SPIMST1_SEQUENCER_FSM_ERR: sequencer fsm error
55	RWX			SPIMST1_SHIFTER_FSM_ERR: shifter fsm error
56	RWX			SPIMST1_ANY_CONFIG_PARITY_ERR: any config parity error
57	RWX			SPIMST1_SPI_PORT_MUX_INDICATOR: indication of SPI port multiplexer, must indicate zero for this SPI to run
58	RWX			SPIMST1_SPI_SEC_PIB_RETRY_RSP_INFO: indication of SPI security problem during PIB Write access
59:63	RWX			SPIMST1_UNUSED: unused

spi master error inject register
Addr:	0000000000070040 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2_ERROR_INJECT_
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2.CONFIG.ERROR_REG_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0:7	RWX			SPIMST2_ERROR_INJECT_PULSE: error inject pulse
8:15	RWX			SPIMST2_ERROR_INJECT_MASK: error inject mask
16:31	RWX			SPIMST2_ERROR_MASK: error mask
32:63	RWX			SPIMST2_ERROR_UNUSED: error unused

spi master counter configuration register
Addr:	0000000000070041 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2_COUNTER
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2.CONFIG.COUNTER_REG_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0:7	RWX			SPIMST2_COUNT_N1: counter N1 register
8:15	RWX			SPIMST2_COUNT_N2: counter N1 register
16:23	RWX			SPIMST2_COUNT_RESERVED_A: counter reserved area a register
24:31	RWX			SPIMST2_LOOPCOUNT: loop count compare register for BNEI operation
32:39	RWX			SPIMST2_LOOPCOUNT2: loop count 2 compare register for BNEI2 operation
40:47	RWX			SPIMST2_SHIFTER_FSM_CONTROL: shifter fsm control bits
48:51	RWX			SPIMST2_N1_CONTROL: shift counter N1 control bits
52:55	RWX			SPIMST2_N2_CONTROL: shift counter N2 control bits
56:63	RWX			SPIMST2_COUNT_RESERVED_B: counter reserved area b register

spi master configuration 1 register
Addr:	0000000000070042 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2_CONFIG1
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2.CONFIG.CONFIG1_REG_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0	ROX			SPIMST2_SPI_RESOURCE_LOCK: reserved
1:4	ROX			SPIMST2_PIB_MASTER_ID: PIB master id that has reserved the device
5:63	RWX			SPIMST2_CONFIG1_REG_UNUSED: reserved register space

spi master clock configuration register
Addr:	0000000000070043 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2_CLOCK_CONFIG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2.CONFIG.CLOCK_CONFIG_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0:11	RWX			SPIMST2_SCK_CLOCK_DIVIDER: SCK_clock_divider
12:19	RWX			SPIMST2_SCK_RECEIVE_DELAY: SCK_receive_delay
20	RWX			SPIMST2_ENABLE_RECEIVE_PACING: enable_receive_pacing
21	RWX			SPIMST2_SPIMST_TRACE_ENABLE: SCK clock_phase
22:23	RWX			SPIMST2_SCK_TRACE_SELECT: trace_select
24:27	RWX			SPIMST2_SCK_RESET_CONTROL: reset_control
28	RWX			SPIMST2_SCK_ECC_SPIMM_ADDR_CORR_DIS: SCK_ecc_spimm_addr_corr_dis
29:30	RWX			SPIMST2_SCK_ECC_CONTROL: ecc_control
31	RWX			SPIMST2_SCK_MMSPISM_ENABLE: mmSPIsm_enable
32:35	RWX			SPIMST2_SPI_SLAVE_RESET: hardware reset signal for spi slave
36	RWX			SPIMST2_LOOPBACK_ENABLE: loopback mode enable
37:63	RWX			SPIMST2_CLOCK_CONFIG_RESERVED: clock config reserved

spi master pattern match register
Addr:	0000000000070044 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2_MEMORY_MAPPING
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2.CONFIG.MEMORY_MAPPING_REG_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0:15	RWX			SPIMST2_MEMORY_MAPPING_BASE: memory mapping address base
16:31	RWX			SPIMST2_MEMORY_MAPPING_MASK: memory mapping address mask
32:47	RWX			SPIMST2_PATTERN_MATCH_COMPARE: serial receive pattern match compare value
48:63	RWX			SPIMST2_PATTERN_MATCH_MASK: serial receive pattern match compare value

spi master transmit data register
Addr:	0000000000070045 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2_TRANSMIT_DATA_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2.CONFIG.TRANSMIT_DATA_REG_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0:63	RWX			SPIMST2_TRANSMIT_DATA_REG_Q: spi master tranmsit data register

spi master receive data register
Addr:	0000000000070046 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2_RECEIVE_DATA_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2.CONFIG.RECEIVE_DATA_REG_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0:63	ROX			SPIMST2_RECEIVE_DATA_REG_Q: spi master receive data register

spi master sequencer operation register
Addr:	0000000000070047 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2_SEQUENCER_OP_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2.CONFIG.SEQUENCER_OP_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0:63	RWX			SPIMST2_SEQUENCER_OP_Q: spi master sequencer operation register

spi master status register
Addr:	0000000000070048 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2_STATUS_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2.CONFIG.SPI_CONFIG_FUNC_Q_INST.FSILAT.LATCH.LATC.L2(12:15) [0000]
	4:7	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2.CONFIG.SPI_CONFIG_FUNC_Q_INST.FSILAT.LATCH.LATC.L2(8:11) [0000]
	8:15	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2.SEQ.FUNC_SEQUENCER_LATCHES_Q_INST.FSILAT.LATCH.LATC.L2(16:23) [00000000]
	16:27	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2.SHIFT.FUNC_SHIFTER_LATCHES_Q_INST.FSILAT.LATCH.LATC.L2(24:35) [000000000000]
	28:31	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2.SEQ.FUNC_SEQUENCER_LATCHES_Q_INST.FSILAT.LATCH.LATC.L2(4:7) [0000]
	32:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2.CONFIG.SPI_STATUS_Q_INST.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0	RWX			SPIMST2_RDR_FULL_STATUS: indication for receive data register full
1	RWX			SPIMST2_RDR_OVER_STATUS: indication for receive data register overrun
2	RWX			SPIMST2_RDR_UNDER_STATUS: indication for receive data register underrun
3	RWX			SPIMST2_RDR_RESERVED_STATUS: indication for receive data register reserved status, unused
4	RWX			SPIMST2_TDR_FULL_STATUS: indication for transmit data register full
5	RWX			SPIMST2_TDR_OVER_STATUS: indication for transmit data register overrun
6	RWX			SPIMST2_TDR_UNDER_STATUS: indication for transmit data register underrun
7	RWX			SPIMST2_TDR_RESERVED_STATUS: indication for transmit data register reserved status, unused
8:15	ROX			SPIMST2_SEQUENCER_FSM: sequencer finit state machine bit coding
16:27	ROX			SPIMST2_SHIFTER_FSM: shifter finit state machine bit coding
28:31	ROX			SPIMST2_SEQUENCER_OP_INDEX: sequencer operation index
32	RWX			SPIMST2_COUNTER_REG_PARITY_ERRS: counter configuration register parity error
33	RWX			SPIMST2_CLOCK_REG_PARITY_ERR: clock configuration register parity error
34	RWX			SPIMST2_SEQUENCER_REG_PARITY_ERR: sequencer configuration register parity error
35	RWX			SPIMST2_SEQUENCER_FSM_PARITY_ERR: sequencer fsm parity error
36	RWX			SPIMST2_SHIFTER_FSM_PARITY_ERR: shifter fsm parity error
37	RWX			SPIMST2_PATTERN_REG_PARITY_ERR: pattern match register parity error
38	RWX			SPIMST2_TDR_REG_PARITY_ERR: transmit data register parity error
39	RWX			SPIMST2_RDR_REG_PARITY_ERR: receive data register parity error
40	RWX			SPIMST2_CONFIG_REG1_PARITY_ERR: configuration register 1 parity error
41	RWX			SPIMST2_UNUSED_PARITY_ERR: unused
42	RWX			SPIMST2_ERROR_REG_PARITY_ERR: error register parity error
43	RWX			SPIMST2_ECC_CORRECTABLE_ERR: ecc correctable error
44	RWX			SPIMST2_ECC_UNCORRECTABLE_ERR: ecc uncorrectable error
45:46	RWX			SPIMST2_ECC_STATUS: general ecc status (unsued)
47	RWX			SPIMST2_MM_ADDR_OVERLAP: memory mapped SPI address overlap
48:49	RWX			SPIMST2_ACCESS_VIOLATION: general access violation
50	RWX			SPIMST2_PORT_MULTIPLEXER_ERR: port multiplexer error
51	RWX			SPIMST2_ADDR_OUT_OF_RANGE: address range error
52	RWX			SPIMST2_MEM_MAPPING_OVERLAP: memory mapping overlap error
53	RWX			SPIMST2_SEQUENCER_SLAVE_SEL_ERR: sequencer slave select error
54	RWX			SPIMST2_SEQUENCER_FSM_ERR: sequencer fsm error
55	RWX			SPIMST2_SHIFTER_FSM_ERR: shifter fsm error
56	RWX			SPIMST2_ANY_CONFIG_PARITY_ERR: any config parity error
57	RWX			SPIMST2_SPI_PORT_MUX_INDICATOR: indication of SPI port multiplexer, must indicate zero for this SPI to run
58	RWX			SPIMST2_SPI_SEC_PIB_RETRY_RSP_INFO: indication of SPI security problem during PIB Write access
59:63	RWX			SPIMST2_UNUSED: unused

spi master error inject register
Addr:	0000000000070060 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3_ERROR_INJECT_
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3.CONFIG.ERROR_REG_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0:7	RWX			SPIMST3_ERROR_INJECT_PULSE: error inject pulse
8:15	RWX			SPIMST3_ERROR_INJECT_MASK: error inject mask
16:31	RWX			SPIMST3_ERROR_MASK: error mask
32:63	RWX			SPIMST3_ERROR_UNUSED: error unused

spi master counter configuration register
Addr:	0000000000070061 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3_COUNTER
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3.CONFIG.COUNTER_REG_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0:7	RWX			SPIMST3_COUNT_N1: counter N1 register
8:15	RWX			SPIMST3_COUNT_N2: counter N1 register
16:23	RWX			SPIMST3_COUNT_RESERVED_A: counter reserved area a register
24:31	RWX			SPIMST3_LOOPCOUNT: loop count compare register for BNEI operation
32:39	RWX			SPIMST3_LOOPCOUNT2: loop count 2 compare register for BNEI2 operation
40:47	RWX			SPIMST3_SHIFTER_FSM_CONTROL: shifter fsm control bits
48:51	RWX			SPIMST3_N1_CONTROL: shift counter N1 control bits
52:55	RWX			SPIMST3_N2_CONTROL: shift counter N2 control bits
56:63	RWX			SPIMST3_COUNT_RESERVED_B: counter reserved area b register

spi master configuration 1 register
Addr:	0000000000070062 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3_CONFIG1
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3.CONFIG.CONFIG1_REG_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0	ROX			SPIMST3_SPI_RESOURCE_LOCK: reserved
1:4	ROX			SPIMST3_PIB_MASTER_ID: PIB master id that has reserved the device
5:63	RWX			SPIMST3_CONFIG1_REG_UNUSED: reserved register space

spi master clock configuration register
Addr:	0000000000070063 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3_CLOCK_CONFIG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3.CONFIG.CLOCK_CONFIG_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0:11	RWX			SPIMST3_SCK_CLOCK_DIVIDER: SCK_clock_divider
12:19	RWX			SPIMST3_SCK_RECEIVE_DELAY: SCK_receive_delay
20	RWX			SPIMST3_ENABLE_RECEIVE_PACING: enable_receive_pacing
21	RWX			SPIMST3_SPIMST_TRACE_ENABLE: SCK clock_phase
22:23	RWX			SPIMST3_SCK_TRACE_SELECT: trace_select
24:27	RWX			SPIMST3_SCK_RESET_CONTROL: reset_control
28	RWX			SPIMST3_SCK_ECC_SPIMM_ADDR_CORR_DIS: SCK_ecc_spimm_addr_corr_dis
29:30	RWX			SPIMST3_SCK_ECC_CONTROL: ecc_control
31	RWX			SPIMST3_SCK_MMSPISM_ENABLE: mmSPIsm_enable
32:35	RWX			SPIMST3_SPI_SLAVE_RESET: hardware reset signal for spi slave
36	RWX			SPIMST3_LOOPBACK_ENABLE: loopback mode enable
37:63	RWX			SPIMST3_CLOCK_CONFIG_RESERVED: clock config reserved

spi master pattern match register
Addr:	0000000000070064 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3_MEMORY_MAPPING
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3.CONFIG.MEMORY_MAPPING_REG_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0:15	RWX			SPIMST3_MEMORY_MAPPING_BASE: memory mapping address base
16:31	RWX			SPIMST3_MEMORY_MAPPING_MASK: memory mapping address mask
32:47	RWX			SPIMST3_PATTERN_MATCH_COMPARE: serial receive pattern match compare value
48:63	RWX			SPIMST3_PATTERN_MATCH_MASK: serial receive pattern match compare value

spi master transmit data register
Addr:	0000000000070065 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3_TRANSMIT_DATA_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3.CONFIG.TRANSMIT_DATA_REG_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0:63	RWX			SPIMST3_TRANSMIT_DATA_REG_Q: spi master tranmsit data register

spi master receive data register
Addr:	0000000000070066 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3_RECEIVE_DATA_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3.CONFIG.RECEIVE_DATA_REG_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0:63	ROX			SPIMST3_RECEIVE_DATA_REG_Q: spi master receive data register

spi master sequencer operation register
Addr:	0000000000070067 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3_SEQUENCER_OP_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3.CONFIG.SEQUENCER_OP_Q_INST.FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0:63	RWX			SPIMST3_SEQUENCER_OP_Q: spi master sequencer operation register

spi master status register
Addr:	0000000000070068 (FSISPI)
Name:	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3_STATUS_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3.CONFIG.SPI_CONFIG_FUNC_Q_INST.FSILAT.LATCH.LATC.L2(12:15) [0000]
	4:7	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3.CONFIG.SPI_CONFIG_FUNC_Q_INST.FSILAT.LATCH.LATC.L2(8:11) [0000]
	8:15	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3.SEQ.FUNC_SEQUENCER_LATCHES_Q_INST.FSILAT.LATCH.LATC.L2(16:23) [00000000]
	16:27	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3.SHIFT.FUNC_SHIFTER_LATCHES_Q_INST.FSILAT.LATCH.LATC.L2(24:35) [000000000000]
	28:31	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3.SEQ.FUNC_SEQUENCER_LATCHES_Q_INST.FSILAT.LATCH.LATC.L2(4:7) [0000]
	32:63	TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3.CONFIG.SPI_STATUS_Q_INST.FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	FSISPI			Dial: Description
0	RWX			SPIMST3_RDR_FULL_STATUS: indication for receive data register full
1	RWX			SPIMST3_RDR_OVER_STATUS: indication for receive data register overrun
2	RWX			SPIMST3_RDR_UNDER_STATUS: indication for receive data register underrun
3	RWX			SPIMST3_RDR_RESERVED_STATUS: indication for receive data register reserved status, unused
4	RWX			SPIMST3_TDR_FULL_STATUS: indication for transmit data register full
5	RWX			SPIMST3_TDR_OVER_STATUS: indication for transmit data register overrun
6	RWX			SPIMST3_TDR_UNDER_STATUS: indication for transmit data register underrun
7	RWX			SPIMST3_TDR_RESERVED_STATUS: indication for transmit data register reserved status, unused
8:15	ROX			SPIMST3_SEQUENCER_FSM: sequencer finit state machine bit coding
16:27	ROX			SPIMST3_SHIFTER_FSM: shifter finit state machine bit coding
28:31	ROX			SPIMST3_SEQUENCER_OP_INDEX: sequencer operation index
32	RWX			SPIMST3_COUNTER_REG_PARITY_ERRS: counter configuration register parity error
33	RWX			SPIMST3_CLOCK_REG_PARITY_ERR: clock configuration register parity error
34	RWX			SPIMST3_SEQUENCER_REG_PARITY_ERR: sequencer configuration register parity error
35	RWX			SPIMST3_SEQUENCER_FSM_PARITY_ERR: sequencer fsm parity error
36	RWX			SPIMST3_SHIFTER_FSM_PARITY_ERR: shifter fsm parity error
37	RWX			SPIMST3_PATTERN_REG_PARITY_ERR: pattern match register parity error
38	RWX			SPIMST3_TDR_REG_PARITY_ERR: transmit data register parity error
39	RWX			SPIMST3_RDR_REG_PARITY_ERR: receive data register parity error
40	RWX			SPIMST3_CONFIG_REG1_PARITY_ERR: configuration register 1 parity error
41	RWX			SPIMST3_UNUSED_PARITY_ERR: unused
42	RWX			SPIMST3_ERROR_REG_PARITY_ERR: error register parity error
43	RWX			SPIMST3_ECC_CORRECTABLE_ERR: ecc correctable error
44	RWX			SPIMST3_ECC_UNCORRECTABLE_ERR: ecc uncorrectable error
45:46	RWX			SPIMST3_ECC_STATUS: general ecc status (unsued)
47	RWX			SPIMST3_MM_ADDR_OVERLAP: memory mapped SPI address overlap
48:49	RWX			SPIMST3_ACCESS_VIOLATION: general access violation
50	RWX			SPIMST3_PORT_MULTIPLEXER_ERR: port multiplexer error
51	RWX			SPIMST3_ADDR_OUT_OF_RANGE: address range error
52	RWX			SPIMST3_MEM_MAPPING_OVERLAP: memory mapping overlap error
53	RWX			SPIMST3_SEQUENCER_SLAVE_SEL_ERR: sequencer slave select error
54	RWX			SPIMST3_SEQUENCER_FSM_ERR: sequencer fsm error
55	RWX			SPIMST3_SHIFTER_FSM_ERR: shifter fsm error
56	RWX			SPIMST3_ANY_CONFIG_PARITY_ERR: any config parity error
57	RWX			SPIMST3_SPI_PORT_MUX_INDICATOR: indication of SPI port multiplexer, must indicate zero for this SPI to run
58	RWX			SPIMST3_SPI_SEC_PIB_RETRY_RSP_INFO: indication of SPI security problem during PIB Write access
59:63	RWX			SPIMST3_UNUSED: unused

Provides the controlablity in handling the auto increment/decrment address pointer in indirect mode from both access
Addr:	000000000008FFF0 (SCOM)
Name:	TP.TPCHIP.PIBMEM.PIBMEM.CTRL_MAC.PIBMEM_CONTROL_REGISTER
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:1	TP.TPCHIP.PIBMEM.PIBMEM.CTRL_MAC.CTRL_WRAP.ENABLE_FACESS.CTRL_COMP.CONTROL_REG_0_INST.LATC.L2(0:1) [00]
	2:5	TP.TPCHIP.PIBMEM.PIBMEM.CTRL_MAC.CTRL_WRAP.ENABLE_FACESS.CTRL_COMP.CONTROL_REG_2_INST.LATC.L2(2:5) [0000]
Bit(s)	SCOM			Dial: Description
0	RWX			AUTO_PRE_INCREMENT_PIB: If this bit is 1 : when Auto_increment_register is read/written from pib side, data will be read/written into array after the address pointer is incremented. If this bit is 0 : when Auto_increment_register is read/written, data will be read/written into array before address pointer is incremented. Default_value : 0
1	RWX			AUTO_POST_DECREMENT_PIB: If this bit is 1 : when Auto_decrement_register is read/written from pib side, data will be read/written into array before the address pointer is decremented. If this bit is 0 : when Auto_decrement_register is read/written, data will be read/written into array after address pointer is decremented. Default_value:0
2	RWX			DISABLE_ECC: If this bit is 1 : disables the ECC checking and calculating If this bit is 0 : sends ECC and checks the ECC for the array data
3	RWX			AUTO_PRE_INCREMENT_FACES: If this bit is 1 : when Auto_increment_register is read/written from fastacess side, data will be read/written into array after the address pointer is incremented. If this bit is 0 : when Auto_increment_register is read/written, data will be read/written into array before address pointer is incremented. Default_value : 0
4	RWX			AUTO_POST_DECREMENT_FACES: If this bit is 1 : when Auto_decrement_register is read/written from fastacess side, data will be read/written into array before the address pointer is decremented. If this bit is 0 : when Auto_decrement_register is read/written, data will be read/written into array after address pointer is decremented. Default_value:0
5	RW			FENCE_ABIST_CMP_FAR: Fence abist_start_test to PIBMEM Abist Engine, CMP and FAR

Indirect address pointer
Addr:	000000000008FFF1 (SCOM)
Name:	TP.TPCHIP.PIBMEM.PIBMEM.CTRL_MAC.PIBMEM_ADDRESS_REGISTER
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	48:63	TP.TPCHIP.PIBMEM.PIBMEM.CTRL_MAC.CTRL_WRAP.ENABLE_FACESS.CTRL_COMP.ADDRESS_REG_0_INST.LATC.L2(0:15) [0000000000000000]
Bit(s)	SCOM			Dial: Description
0:47	RO			constant=0b000000000000000000000000000000000000000000000000
48:63	RWX			ADDRESS_POINTER: If the value on this is 0x0000 ? accesses 0th location of the array 0x0001 ? accesses 1st location of the array

Status of PIBMEM controller
Addr:	000000000008FFF5 (SCOM)
Name:	TP.TPCHIP.PIBMEM.PIBMEM.CTRL_MAC.PIBMEM_STATUS_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.PIBMEM.PIBMEM.CTRL_MAC.CTRL_WRAP.ENABLE_FACESS.CTRL_COMP.STATUS_REG_0_INST.LATC.L2(0:7) [00000000]
	19:26	TP.TPCHIP.PIBMEM.PIBMEM.CTRL_MAC.CTRL_WRAP.ENABLE_FACESS.CTRL_COMP.STATUS_REG_0_INST.LATC.L2(8:15) [00000000]
	32:47	TP.TPCHIP.PIBMEM.PIBMEM.CTRL_MAC.CTRL_WRAP.ENABLE_FACESS.CTRL_COMP.RST_INTR_ADDR_PIB_LT_INST.LATC.L2(0:15) [0000000000000000]
	48:63	TP.TPCHIP.PIBMEM.PIBMEM.CTRL_MAC.CTRL_WRAP.ENABLE_FACESS.CTRL_COMP.RST_INTR_ADDR_FACES_LT_INST.LATC.L2(0:15) [0000000000000000]
Bit(s)	SCOM			Dial: Description
0	ROX			ADDR_INVALID_PIB: Address which PIB is trying to access in PIBMEM is not valid one in PIBMEM
1	ROX			WRITE_INVALID_PIB: Address for which PIB is trying to write is not writable
2	ROX			READ_INVALID_PIB: Address for which PIB is trying to read is not readable
3	ROX			ECC_UNCORRECTED_ERROR_PIB: Uncorrectable error occurred while PIB memory read . This also go out as FIR error
4	ROX			ECC_CORRECTED_ERROR_PIB: Corrected error in PIB mem read . Data can still be considered as good. This is an error o/p of ECC_CHECK_CORRECTION block
5	ROX			bad_array_address_pib
6	ROX			WRITE_RST_INTERRUPT_PIB: This bit gets set, when a reset occurred during write operation to PIBMEM from PIB side. It is sticky status bit.
7	ROX			READ_RST_INTERRUPT_PIB: This bit gets set, when a reset occurred during read operation to PIBMEM from PIB side. It is sticky status bit.
8:18	RO			constant=0b00000000000
19	ROX			ADDR_INVALID_FACES: Address which is given by Fast acesss interface, to access in PIBMEM is not valid one in PIBMEM
20	ROX			WRITE_INVALID_FACES: Address which is given by Fast acesss interface, to access in PIBMEM is not valid one in PIBMEM or not writable
21	ROX			READ_INVALID_FACES: Address which is given by Fast acesss interface, to access is not readable
22	ROX			ECC_UNCORRECTED_ERROR_FACES: Uncorrectable error occurred while fast acess interface read
23	ROX			ECC_CORRECTED_ERROR_FACES: Corrected error in fast acess read operation . Data can still be considered as good. This is an error o/p of ECC_CHECK_CORRECTION block
24	ROX			BAD_ARRAY_ADDRESS_FACES: Wrong address accessd in indirect mode of operation from fast acess interface . It is sticky status bit.
25	ROX			WRITE_RST_INTERRUPT_FACES: This bit gets set, when a reset occurred during write operation to PIBMEM from fast acess side. It is sticky status bit.
26	ROX			READ_RST_INTERRUPT_FACES: This bit gets set, when a reset occurred during read operation to PIBMEM from fast acess side. It is sticky status bit.
27:31	RO			constant=0b00000
32:47	ROX			ADDR_RESET_INTR_PIB: Address information of reset interrupted transaction from PIB side.
48:63	ROX			ADDR_RESET_INTR_FACES: Address information of reset interrupted transaction from FAST ACESS side.

Write into this register with proper value will reset complete PIBMEM controller except array
Addr:	000000000008FFF6 (SCOM)
Name:	TP.TPCHIP.PIBMEM.PIBMEM.CTRL_MAC.PIBMEM_RESET_REGISTER
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:1	TP.TPCHIP.PIBMEM.PIBMEM.CTRL_MAC.CTRL_WRAP.ENABLE_FACESS.CTRL_COMP.RESET_REG_0_INST.LATC.L2(0:1) [00]
Bit(s)	SCOM			Dial: Description
0:1	RW			RESET: writing value 10 on this will reset PIBMEM

Indirect address pointer
Addr:	000000000008FFF7 (SCOM)
Name:	TP.TPCHIP.PIBMEM.PIBMEM.CTRL_MAC.PIBMEM_ADDRESS_REGISTER_FA
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	48:63	TP.TPCHIP.PIBMEM.PIBMEM.CTRL_MAC.CTRL_WRAP.ENABLE_FACESS.CTRL_COMP.FACES_ADDRESS_REG_0_INST.LATC.L2(0:15) [0000000000000000]
Bit(s)	SCOM			Dial: Description
0:47	RO			constant=0b000000000000000000000000000000000000000000000000
48:63	RWX			ADDRESS_POINTER_FA: If the value on this is 0x0000 ? accesses 0th location of the array 0x0001 ? accesses 1st location of the array

FIR Error Mask register
Addr:	000000000008FFF8 (SCOM)
Name:	TP.TPCHIP.PIBMEM.PIBMEM.CTRL_MAC.FIR_MASK_REGISTER
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	3	TP.TPCHIP.PIBMEM.PIBMEM.CTRL_MAC.CTRL_WRAP.ENABLE_FACESS.CTRL_COMP.FIR_MASK_REG_3_INST.LATC.L2(3) [0]
	5:7	TP.TPCHIP.PIBMEM.PIBMEM.CTRL_MAC.CTRL_WRAP.ENABLE_FACESS.CTRL_COMP.FIR_MASK_REG_5_INST.LATC.L2(5:7) [000]
	22	TP.TPCHIP.PIBMEM.PIBMEM.CTRL_MAC.CTRL_WRAP.ENABLE_FACESS.CTRL_COMP.FIR_MASK_REG_22_INST.LATC.L2(22) [0]
	24:26	TP.TPCHIP.PIBMEM.PIBMEM.CTRL_MAC.CTRL_WRAP.ENABLE_FACESS.CTRL_COMP.FIR_MASK_REG_24_INST.LATC.L2(24:26) [000]
Bit(s)	SCOM			Dial: Description
0:2	RO			constant=0b000
3	RWX			MASK_ECC_UNCORRECTED_ERR_PIB: Bit allows to mask ecc uncorrected error for pib transaction in generation of FIR error
4	RO			constant=0b0
5	RWX			MASK_BAD_ARRAY_ADDR_PIB: Bit allows to mask bad array address error for pib transaction in generation of FIR error
6	RWX			MASK_WRT_RST_INTRPT_PIB: Bit allows to mask write reset interrupt for pib transaction in generation of FIR error
7	RWX			MASK_RD_RST_INTRPT_PIB: Bit allows to mask read reset interrupt for pib transaction in generation of FIR error
8:21	RO			constant=0b00000000000000
22	RWX			MASK_ECC_UNCORRECTED_ERR_FACES: Bit allows to mask ecc uncorrected error for fast access transaction in generation of FIR error
23	RO			constant=0b0
24	RWX			MASK_BAD_ARRAY_ADDR_FACES: Bit allows to mask bad array address error for fast access transaction in generation of FIR error
25	RWX			MASK_WRT_RST_INTRPT_FACES: Bit allows to mask write reset interrupt error for fast access transaction in generation of FIR error
26	RWX			MASK_RD_RST_INTRPT_FACES: Bit allows to mask read reset interrupt error for fast access transaction in generation of FIR error
27	RO			constant=0b0

Reports first uncorrectable/correctable error unless cleared by writing to this register
Addr:	000000000008FFFB (SCOM)
Name:	TP.TPCHIP.PIBMEM.PIBMEM.CTRL_MAC.ECC_CAPTURE_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:24	TP.TPCHIP.PIBMEM.PIBMEM.CTRL_MAC.CTRL_WRAP.ENABLE_FACESS.CTRL_COMP.ECC_CAPTURE_REG_0_INST.LATC.L2(0:24) [0000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RWX_WCLRPART			ECC_CORRECTED_ERROR: Reports that ECC Corrected Error occured first unless cleared by writing to this register
1	RWX_WCLRPART			ECC_UNCORRECTED_ERROR: Reports that ECC Uncorrected Error occured first unless cleared by writing to this register
2:17	RWX_WCLRPART			ECC_ARRAY_ADDRESS: Holds address for ECC Corrected/Uncorrected Error
18:24	RWX_WCLRPART			ECC_BIT_LOCATION: Holds corrupted bit location in case of correctable error and is invalid in case of uncorrectable error

Alter/Display Control Register
Addr:	0000000000090000 (SCOM)
Name:	TP.TPBR.AD.ALTD_ADDR_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	8	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#8.L.LAT.LATC.L2(8) [0]
	9	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#9.L.LAT.LATC.L2(9) [0]
	10	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#10.L.LAT.LATC.L2(10) [0]
	11	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#11.L.LAT.LATC.L2(11) [0]
	12	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#12.L.LAT.LATC.L2(12) [0]
	13	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#13.L.LAT.LATC.L2(13) [0]
	14	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#14.L.LAT.LATC.L2(14) [0]
	15	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#15.L.LAT.LATC.L2(15) [0]
	16	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#16.L.LAT.LATC.L2(16) [0]
	17	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#17.L.LAT.LATC.L2(17) [0]
	18	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#18.L.LAT.LATC.L2(18) [0]
	19	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#19.L.LAT.LATC.L2(19) [0]
	20	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#20.L.LAT.LATC.L2(20) [0]
	21	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#21.L.LAT.LATC.L2(21) [0]
	22	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#22.L.LAT.LATC.L2(22) [0]
	23	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#23.L.LAT.LATC.L2(23) [0]
	24	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#24.L.LAT.LATC.L2(24) [0]
	25	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#25.L.LAT.LATC.L2(25) [0]
	26	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#26.L.LAT.LATC.L2(26) [0]
	27	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#27.L.LAT.LATC.L2(27) [0]
	28	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#28.L.LAT.LATC.L2(28) [0]
	29	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#29.L.LAT.LATC.L2(29) [0]
	30	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#30.L.LAT.LATC.L2(30) [0]
	31	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#31.L.LAT.LATC.L2(31) [0]
	32	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#32.L.LAT.LATC.L2(32) [0]
	33	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#33.L.LAT.LATC.L2(33) [0]
	34	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#34.L.LAT.LATC.L2(34) [0]
	35	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#35.L.LAT.LATC.L2(35) [0]
	36	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#36.L.LAT.LATC.L2(36) [0]
	37	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#37.L.LAT.LATC.L2(37) [0]
	38	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#38.L.LAT.LATC.L2(38) [0]
	39	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#39.L.LAT.LATC.L2(39) [0]
	40	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#40.L.LAT.LATC.L2(40) [0]
	41	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#41.L.LAT.LATC.L2(41) [0]
	42	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#42.L.LAT.LATC.L2(42) [0]
	43	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#43.L.LAT.LATC.L2(43) [0]
	44	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#44.L.LAT.LATC.L2(44) [0]
	45	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#45.L.LAT.LATC.L2(45) [0]
	46	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#46.L.LAT.LATC.L2(46) [0]
	47	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#47.L.LAT.LATC.L2(47) [0]
	48	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#48.L.LAT.LATC.L2(48) [0]
	49	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#49.L.LAT.LATC.L2(49) [0]
	50	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#50.L.LAT.LATC.L2(50) [0]
	51	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#51.L.LAT.LATC.L2(51) [0]
	52	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#52.L.LAT.LATC.L2(52) [0]
	53	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#53.L.LAT.LATC.L2(53) [0]
	54	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#54.L.LAT.LATC.L2(54) [0]
	55	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#55.L.LAT.LATC.L2(55) [0]
	56	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#56.L.LAT.LATC.L2(56) [0]
	57	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#57.L.LAT.LATC.L2(57) [0]
	58	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#58.L.LAT.LATC.L2(58) [0]
	59	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#59.L.LAT.LATC.L2(59) [0]
	60	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#60.L.LAT.LATC.L2(60) [0]
	61	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#61.L.LAT.LATC.L2(61) [0]
	62	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#62.L.LAT.LATC.L2(62) [0]
	63	TP.TPBR.AD.PBADR.ALTD_ADDR_REG.READ_WRITE.INT_CG.BITS#63.L.LAT.LATC.L2(63) [0]
Bit(s)	SCOM			Dial: Description
0:7	RO			constant=0b00000000
8:63	RWX			FBC_ALTD_ADDRESS: The Address bits 8:63 to use with the Alter/Display command

Alter/Display Command Register
Addr:	0000000000090001 (SCOM)
Name:	TP.TPBR.AD.ALTD_CMD_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	2	TP.TPBR.AD.ALTDSM.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#2.L.LAT.LATC.L2(2) [0]
	3	TP.TPBR.AD.ALTDSM.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#3.L.LAT.LATC.L2(3) [0]
	4	TP.TPBR.AD.ALTDSM.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#4.L.LAT.LATC.L2(4) [0]
	5	TP.TPBR.AD.ALTDSM.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#5.L.LAT.LATC.L2(5) [0]
	6	TP.TPBR.AD.ALTDSM.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#6.L.LAT.LATC.L2(6) [0]
	7	TP.TPBR.AD.PBADR.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#7.L.LAT.LATC.L2(7) [0]
	11	TP.TPBR.AD.PIB.ALTD_CMD_REG.READ_WRITE.EXTERNAL_CG.BITS#11.L.LAT.LATC.L2(11) [0]
	12	TP.TPBR.AD.PIB.ALTD_CMD_REG.READ_WRITE.EXTERNAL_CG.BITS#12.L.LAT.LATC.L2(12) [0]
	13	TP.TPBR.AD.PIB.ALTD_CMD_REG.READ_WRITE.EXTERNAL_CG.BITS#13.L.LAT.LATC.L2(13) [0]
	14	TP.TPBR.AD.PIB.ALTD_CMD_REG.READ_WRITE.EXTERNAL_CG.BITS#14.L.LAT.LATC.L2(14) [0]
	15	TP.TPBR.AD.PIB.ALTD_CMD_REG.READ_WRITE.EXTERNAL_CG.BITS#15.L.LAT.LATC.L2(15) [0]
	16	TP.TPBR.AD.PBADR.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#16.L.LAT.LATC.L2(16) [0]
	17	TP.TPBR.AD.PBADR.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#17.L.LAT.LATC.L2(17) [0]
	18	TP.TPBR.AD.PBADR.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#18.L.LAT.LATC.L2(18) [0]
	19	TP.TPBR.AD.ALTDSM.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#19.L.LAT.LATC.L2(19) [0]
	20	TP.TPBR.AD.PBADR.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#20.L.LAT.LATC.L2(20) [0]
	21	TP.TPBR.AD.PBADR.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#21.L.LAT.LATC.L2(21) [0]
	22	TP.TPBR.AD.ALTDSM.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#22.L.LAT.LATC.L2(22) [0]
	23	TP.TPBR.AD.ALTDSM.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#23.L.LAT.LATC.L2(23) [0]
	24	TP.TPBR.AD.ALTDSM.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#24.L.LAT.LATC.L2(24) [0]
	25	TP.TPBR.AD.PBADR.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#25.L.LAT.LATC.L2(25) [0]
	26	TP.TPBR.AD.PBADR.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#26.L.LAT.LATC.L2(26) [0]
	27	TP.TPBR.AD.PBADR.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#27.L.LAT.LATC.L2(27) [0]
	28	TP.TPBR.AD.PBADR.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#28.L.LAT.LATC.L2(28) [0]
	29	TP.TPBR.AD.PBADR.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#29.L.LAT.LATC.L2(29) [0]
	30	TP.TPBR.AD.PBADR.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#30.L.LAT.LATC.L2(30) [0]
	31	TP.TPBR.AD.PBADR.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#31.L.LAT.LATC.L2(31) [0]
	32	TP.TPBR.AD.PBADR.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#32.L.LAT.LATC.L2(32) [0]
	33	TP.TPBR.AD.PBADR.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#33.L.LAT.LATC.L2(33) [0]
	34	TP.TPBR.AD.PBADR.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#34.L.LAT.LATC.L2(34) [0]
	35	TP.TPBR.AD.PBADR.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#35.L.LAT.LATC.L2(35) [0]
	36	TP.TPBR.AD.PBADR.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#36.L.LAT.LATC.L2(36) [0]
	37	TP.TPBR.AD.PBADR.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#37.L.LAT.LATC.L2(37) [0]
	38	TP.TPBR.AD.PBADR.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#38.L.LAT.LATC.L2(38) [0]
	39	TP.TPBR.AD.PBADR.ALTD_CMD_REG.READ_WRITE.INT_CG.BITS#39.L.LAT.LATC.L2(39) [0]
Bit(s)	SCOM			Dial: Description
0:1	RO			constant=0b00
2	NCX			FBC_ALTD_START_OP: Start the Fabric Alter/Display Operation (latch resets after arbitration passed)
3	NCX			FBC_ALTD_CLEAR_STATUS: Clear the Fabric Alter/Display Status Register
4	NCX			FBC_ALTD_RESET_FSM: Reset the Fabric Alter/Display State Machine and Status Registers - exceptional use only
5	RW			FBC_ALTD_RNW: The Read or Write control for the Fabric Alter/Display command. Read = 1; Write = 0; setting must match FBC_altd_ttype Dial enums: READ=>0b1 WRITE=>0b0
6	RWX			FBC_ALTD_AXTYPE: Address Only type command no data transfer will be done
7	RW			FBC_ALTD_DATA_ONLY: Skip the cmd-cresp part and only send a data packet with FBC_altd_address(0:13) as ttag. The Address bits 57:59 are send to the HT-Data ramp, too
8:9	RO			constant=0b00
10	NCX			FBC_lock_pick
11	RWX			FBC_LOCKED: set when the locked the ALTD_CMD_REG, ALTD_ADDRESS_REG and ALTD_DATA_REG
12:15	ROX			FBC_LOCK_ID: Reading current lock owner (only valid when locked). Writing current owner when overwrite the lock
16:18	RWX			FBC_ALTD_SCOPE: The broadcast scope of the command Dial enums: LN=>0b000 NN=>0b010 G=>0b011 RN=>0b100 VG=>0b101 AUTO=>0b111
19	RW			FBC_ALTD_AUTO_INC: The Fabric Alter/Display will Auto Increment the address and issue the next command Auto Increment = 1; Address will increment by 8 and next command will be issued after current command is completed Regular = 0; Alter/Display will issue one command and stop Dial enums: AUTO_INC=>0b1 REGULAR=>0b0
20	RWX			FBC_ALTD_DROP_PRIORITY: Initial command drop priority: specifying which commands are dropped due to PB congestion first Dial enums: LOW=>0b0 HIGH=>0b1
21	RW			FBC_ALTD_DROP_PRIORITY_MAX: Maximal value the Command drop priority can increase to (if not already bigger) Dial enums: LOW=>0b0 HIGH=>0b1
22	RW			FBC_ALTD_OVERWRITE_PBINIT: start this command even when pbinit is low
23	RW			FBC_ALTD_PIB_DIRECT: copy ALTD_ADRESS_REG to PIB_DIRECT_CMD and ALTD_DATA_REG to PIB_DIRECT_DATA register inst. MUST NOT USE XSCOM OF THIS ADU UNTIL DONE
24	RW			FBC_ALTD_WITH_TM_QUIESCE: Set and wait for the local token manager quiesce before the powerbus quiesce or altd command
25:31	RW			FBC_ALTD_TTYPE: The TTYPE used in the Alter/Display command Official Supported values: CI Partial Write DMA Partial Write CI Partial Read DMA Read PB Operation (axtype) Dial enums: CI_PARTIAL_WRITE=>0b0110111 CI_PARTIAL_OOO_WRITE=>0b0110110 DMA_PARTIAL_WRITE=>0b0100110 CI_PARTIAL_READ=>0b0110100 DMA_READ=>0b0000110 PBOPERATION=>0b0111111
32:39	RW			FBC_ALTD_TSIZE: The Tsize used in the Alter/Display command Supported values: 1, 2, 4 and 8 bytes. WATCH OUT: The encoding of this is the PowerBus "secondary encode" and so it is defined different for each ttype

Alter/Display Special Option Register - all bits reset when used
Addr:	0000000000090002 (SCOM)
Name:	TP.TPBR.AD.ALTD_OPTION_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	22	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#22.L.LAT.LATC.L2(22) [0]
	23	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#23.L.LAT.LATC.L2(23) [0]
	28	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#28.L.LAT.LATC.L2(28) [0]
	29	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#29.L.LAT.LATC.L2(29) [0]
	30	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#30.L.LAT.LATC.L2(30) [0]
	31	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#31.L.LAT.LATC.L2(31) [0]
	32	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#32.L.LAT.LATC.L2(32) [0]
	33	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#33.L.LAT.LATC.L2(33) [0]
	34	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#34.L.LAT.LATC.L2(34) [0]
	35	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#35.L.LAT.LATC.L2(35) [0]
	36	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#36.L.LAT.LATC.L2(36) [0]
	37	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#37.L.LAT.LATC.L2(37) [0]
	38	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#38.L.LAT.LATC.L2(38) [0]
	39	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#39.L.LAT.LATC.L2(39) [0]
	40	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#40.L.LAT.LATC.L2(40) [0]
	41	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#41.L.LAT.LATC.L2(41) [0]
	42	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#42.L.LAT.LATC.L2(42) [0]
	43	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#43.L.LAT.LATC.L2(43) [0]
	44	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#44.L.LAT.LATC.L2(44) [0]
	45	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#45.L.LAT.LATC.L2(45) [0]
	46	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#46.L.LAT.LATC.L2(46) [0]
	47	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#47.L.LAT.LATC.L2(47) [0]
	51	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#51.L.LAT.LATC.L2(51) [0]
	52	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#52.L.LAT.LATC.L2(52) [0]
	54	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#54.L.LAT.LATC.L2(54) [0]
	55	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#55.L.LAT.LATC.L2(55) [0]
	56	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#56.L.LAT.LATC.L2(56) [0]
	57	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#57.L.LAT.LATC.L2(57) [0]
	58	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#58.L.LAT.LATC.L2(58) [0]
	59	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#59.L.LAT.LATC.L2(59) [0]
	60	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#60.L.LAT.LATC.L2(60) [0]
	61	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#61.L.LAT.LATC.L2(61) [0]
	62	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#62.L.LAT.LATC.L2(62) [0]
	63	TP.TPBR.AD.ALTDSM.ALTD_OPTION_REG.READ_WRITE.INT_CG.BITS#63.L.LAT.LATC.L2(63) [0]
Bit(s)	SCOM			Dial: Description
0:21	RO			constant=0b0000000000000000000000
22	RWX			FBC_ALTD_WITH_PBINIT_LOW_WAIT: Wait for the pbinit signal to be dropped before continuing
23	RWX			FBC_ALTD_WITH_PRE_QUIESCE: Sent out a powerbus quiesce command before executing the altd command
24:27	RO			constant=0b0000
28:47	RWX			FBC_ALTD_AFTER_QUIESCE_WAIT_COUNT: time to wait between quiesce and altd command
48:50	RO			constant=0b000
51	RWX			FBC_ALTD_WITH_POST_INIT: Sent out a powerbus init command after executing the command
52	RWX			FBC_ALTD_WITH_FAST_PATH: Enables Fast Path during Powerbus init
53	RO			constant=0b0
54:63	RWX			FBC_ALTD_BEFORE_INIT_WAIT_COUNT: time to wait between altd command and init

Alter/Display Status Register
Addr:	0000000000090003 (SCOM)
Name:	TP.TPBR.AD.ALTD_STATUS_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.AD.ALTDSM.ALTD_STATUS_REG.Q_INT(0) [0]
	1	TP.TPBR.AD.ALTDSM.ALTD_SM_L2_INST.LATC.L2(1) [0]
	2	TP.TPBR.AD.ALTDSM.ALTD_ADDR_DONE_L2_INST.LATC.L2(0) [0]
	3	TP.TPBR.AD.ALTDSM.ALTD_DATA_DONE_L2_INST.LATC.L2(0) [0]
	4	TP.TPBR.AD.ALTDSM.ALTD_WAIT_RESP_L2_INST.LATC.L2(0) [0]
	5	TP.TPBR.AD.ALTDSM.ALTD_STATUS_ERR.EXTERNAL_CG.BITS#5.L.LAT.LATC.L2(5) [0]
	6	TP.TPBR.AD.PBADR.ALTD_STATUS_ERR.EXTERNAL_CG.BITS#6.L.LAT.LATC.L2(6) [0]
	7	TP.TPBR.AD.ALTDSM.ALTD_STATUS_ERR.EXTERNAL_CG.BITS#7.L.LAT.LATC.L2(7) [0]
	8	TP.TPBR.AD.ALTDSM.ALTD_STATUS_ERR.EXTERNAL_CG.BITS#8.L.LAT.LATC.L2(8) [0]
	9	TP.TPBR.AD.ALTDSM.ALTD_STATUS_ERR.EXTERNAL_CG.BITS#9.L.LAT.LATC.L2(9) [0]
	10	TP.TPBR.AD.ALTDSM.ALTD_STATUS_ERR.EXTERNAL_CG.BITS#10.L.LAT.LATC.L2(10) [0]
	11	TP.TPBR.AD.ALTDSM.ALTD_STATUS_ERR.EXTERNAL_CG.BITS#11.L.LAT.LATC.L2(11) [0]
	12	TP.TPBR.AD.ALTDSM.ALTD_STATUS_ERR.EXTERNAL_CG.BITS#12.L.LAT.LATC.L2(12) [0]
	15	TP.TPBR.AD.ALTDSM.ALTD_PBINIT_MISSING_L2_INST.LATC.L2(0) [0]
	16	TP.TPBR.AD.ALTDSM.ALTD_SM_L2_INST.LATC.L2(13) [0]
	17	TP.TPBR.AD.ALTDSM.PIB_DIRECT_DONE_L2_INST.LATC.L2(0) [0]
	18	TP.TPBR.AD.ALTDSM.ALTD_PBINIT_MISSING_L2_INST.LATC.L2(0) [0]
	33	TP.TPBR.AD.PIB.ALTD_STATUS_REG.READ_WRITE.EXTERNAL_CG.BITS#33.L.LAT.LATC.L2(33) [0]
	34	TP.TPBR.AD.PIB.ALTD_STATUS_REG.READ_WRITE.EXTERNAL_CG.BITS#34.L.LAT.LATC.L2(34) [0]
	35	TP.TPBR.AD.PIB.ALTD_STATUS_REG.READ_WRITE.EXTERNAL_CG.BITS#35.L.LAT.LATC.L2(35) [0]
	36	TP.TPBR.AD.PIB.ALTD_STATUS_REG.READ_WRITE.EXTERNAL_CG.BITS#36.L.LAT.LATC.L2(36) [0]
	37	TP.TPBR.AD.PIB.ALTD_STATUS_REG.READ_WRITE.EXTERNAL_CG.BITS#37.L.LAT.LATC.L2(37) [0]
	48	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_STATUS_ERR.EXTERNAL_CG.BITS#48.L.LAT.LATC.L2(48) [0]
	49	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_STATUS_ERR.EXTERNAL_CG.BITS#49.L.LAT.LATC.L2(49) [0]
	50	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_STATUS_ERR.EXTERNAL_CG.BITS#50.L.LAT.LATC.L2(50) [0]
	59	TP.TPBR.AD.PBADR.ALTD_STATUS_REG.READ_WRITE.EXTERNAL_CG.BITS#59.L.LAT.LATC.L2(59) [0]
	60	TP.TPBR.AD.PBADR.ALTD_STATUS_REG.READ_WRITE.EXTERNAL_CG.BITS#60.L.LAT.LATC.L2(60) [0]
	61	TP.TPBR.AD.PBADR.ALTD_STATUS_REG.READ_WRITE.EXTERNAL_CG.BITS#61.L.LAT.LATC.L2(61) [0]
	62	TP.TPBR.AD.PBADR.ALTD_STATUS_REG.READ_WRITE.EXTERNAL_CG.BITS#62.L.LAT.LATC.L2(62) [0]
	63	TP.TPBR.AD.PBADR.ALTD_STATUS_REG.READ_WRITE.EXTERNAL_CG.BITS#63.L.LAT.LATC.L2(63) [0]
Bit(s)	SCOM			Dial: Description
0	ROX			FBC_altd_busy
1	ROX			FBC_ALTD_WAIT_CMD_ARBIT: Waiting for arbiter to send the command out
2	ROX			FBC_ALTD_ADDR_DONE: The Address portion of the Fabric Alter/Display Operation is complete
3	ROX			FBC_ALTD_DATA_DONE: The Data portion of the Fabric Alter/Display Operation is complete
4	ROX			FBC_ALTD_WAIT_RESP: Waiting on a Clean Combined Resp
5	RWX_WCLRREG			FBC_ALTD_OVERRUN_ERROR: Overrun Error indicates new data was written before the previous data was used or a read was performed without new data arrived
6	RWX_WCLRREG			FBC_ALTD_AUTOINC_ERROR: AutoInc Error indicates internal address counter rolled over the 0.5M boundary
7	RWX_WCLRREG			FBC_ALTD_COMMAND_ERROR: Command Error indicates new command was issued before the previous one finished
8	RWX_WCLRREG			FBC_ALTD_ADDRESS_ERROR: Invalid Adress Error: PB respond with Adress Errror cresp
9	RWX_WCLRREG			FBC_ALTD_PB_OP_HANG_ERR: PB Timeout while waiting for cresp
10	RWX_WCLRREG			FBC_ALTD_PB_DATA_HANG_ERR: PB Timeout while waiting for data
11	RWX_WCLRREG			FBC_ALTD_PB_UNEXPECT_CRESP_ERR: Combined responce from PB received at a time it is not expected by FSM
12	RWX_WCLRREG			FBC_ALTD_PB_UNEXPECT_DATA_ERR: Data from PB received at a time it is not expected by FSM
13:14	RO			constant=0b00
15	ROX			FBC_ALTD_PBINIT_MISSING: attempt to start a command without pb_init active, it stays blocked until pb_init is set or overriden, a reset or clear will both abort the pending operation
16	ROX			FBC_ALTD_WAIT_PIB_DIRECT: waiting on xscom statemachine to complete direct pib (write) command
17	ROX			FBC_ALTD_PIB_DIRECT_DONE: completed a direct to pib (write) command
18	ROX			FBC_ALTD_PBINIT_MISSING: attempt to start a command without pb_init active, it stays blocked until pb_init is set or overriden, a reset or clear will both abort the pending operation
19:32	RO			constant=0b00000000000000
33:37	ROX			FBC_ALTD_PIB_ERROR: PIB Slave Error indicates what kind of PIB slave error occured
38:47	RO			constant=0b0000000000
48	RWX_WCLRREG			FBC_ALTD_ECC_CE: correctable ecc error detected and corrected during FBC_altd transaction (read)
49	RWX_WCLRREG			FBC_ALTD_ECC_UE: uncorrectable ecc error detected during FBC_altd transaction (read)
50	RWX_WCLRREG			FBC_ALTD_ECC_SUE: special uncorrectable ecc error detected during FBC_altd transaction (read)
51:58	RO			constant=0b00000000
59:63	ROX			FBC_ALTD_CRESP_VALUE: The cresp value (not cleared - may contain old or invalid value until cresp arrived)

Alter/Display Data Register
Addr:	0000000000090004 (SCOM)
Name:	TP.TPBR.AD.ALTD_DATA_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#0.L.LAT.LATC.L2(0) [0]
	1	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#1.L.LAT.LATC.L2(1) [0]
	2	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#2.L.LAT.LATC.L2(2) [0]
	3	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#3.L.LAT.LATC.L2(3) [0]
	4	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#4.L.LAT.LATC.L2(4) [0]
	5	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#5.L.LAT.LATC.L2(5) [0]
	6	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#6.L.LAT.LATC.L2(6) [0]
	7	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#7.L.LAT.LATC.L2(7) [0]
	8	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#8.L.LAT.LATC.L2(8) [0]
	9	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#9.L.LAT.LATC.L2(9) [0]
	10	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#10.L.LAT.LATC.L2(10) [0]
	11	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#11.L.LAT.LATC.L2(11) [0]
	12	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#12.L.LAT.LATC.L2(12) [0]
	13	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#13.L.LAT.LATC.L2(13) [0]
	14	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#14.L.LAT.LATC.L2(14) [0]
	15	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#15.L.LAT.LATC.L2(15) [0]
	16	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#16.L.LAT.LATC.L2(16) [0]
	17	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#17.L.LAT.LATC.L2(17) [0]
	18	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#18.L.LAT.LATC.L2(18) [0]
	19	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#19.L.LAT.LATC.L2(19) [0]
	20	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#20.L.LAT.LATC.L2(20) [0]
	21	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#21.L.LAT.LATC.L2(21) [0]
	22	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#22.L.LAT.LATC.L2(22) [0]
	23	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#23.L.LAT.LATC.L2(23) [0]
	24	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#24.L.LAT.LATC.L2(24) [0]
	25	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#25.L.LAT.LATC.L2(25) [0]
	26	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#26.L.LAT.LATC.L2(26) [0]
	27	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#27.L.LAT.LATC.L2(27) [0]
	28	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#28.L.LAT.LATC.L2(28) [0]
	29	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#29.L.LAT.LATC.L2(29) [0]
	30	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#30.L.LAT.LATC.L2(30) [0]
	31	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#31.L.LAT.LATC.L2(31) [0]
	32	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#32.L.LAT.LATC.L2(32) [0]
	33	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#33.L.LAT.LATC.L2(33) [0]
	34	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#34.L.LAT.LATC.L2(34) [0]
	35	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#35.L.LAT.LATC.L2(35) [0]
	36	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#36.L.LAT.LATC.L2(36) [0]
	37	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#37.L.LAT.LATC.L2(37) [0]
	38	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#38.L.LAT.LATC.L2(38) [0]
	39	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#39.L.LAT.LATC.L2(39) [0]
	40	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#40.L.LAT.LATC.L2(40) [0]
	41	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#41.L.LAT.LATC.L2(41) [0]
	42	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#42.L.LAT.LATC.L2(42) [0]
	43	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#43.L.LAT.LATC.L2(43) [0]
	44	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#44.L.LAT.LATC.L2(44) [0]
	45	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#45.L.LAT.LATC.L2(45) [0]
	46	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#46.L.LAT.LATC.L2(46) [0]
	47	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#47.L.LAT.LATC.L2(47) [0]
	48	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#48.L.LAT.LATC.L2(48) [0]
	49	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#49.L.LAT.LATC.L2(49) [0]
	50	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#50.L.LAT.LATC.L2(50) [0]
	51	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#51.L.LAT.LATC.L2(51) [0]
	52	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#52.L.LAT.LATC.L2(52) [0]
	53	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#53.L.LAT.LATC.L2(53) [0]
	54	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#54.L.LAT.LATC.L2(54) [0]
	55	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#55.L.LAT.LATC.L2(55) [0]
	56	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#56.L.LAT.LATC.L2(56) [0]
	57	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#57.L.LAT.LATC.L2(57) [0]
	58	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#58.L.LAT.LATC.L2(58) [0]
	59	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#59.L.LAT.LATC.L2(59) [0]
	60	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#60.L.LAT.LATC.L2(60) [0]
	61	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#61.L.LAT.LATC.L2(61) [0]
	62	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#62.L.LAT.LATC.L2(62) [0]
63	TP.TPBR.AD.PBDAT.ADS_REGS.ALTD_DATA_REG.READ_WRITE.INT_CG.BITS#63.L.LAT.LATC.L2(63) [0]
Bit(s)	SCOM			Dial: Description
0:63	RWX			FBC_ALTD_DATA: The Data to use with the Alter/Display command

Force ECC Register
Addr:	000000000009000D (SCOM)
Name:	TP.TPBR.AD.FORCE_ECC_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.AD.PBDAT.ADS_REGS.OVERWRITE_ECC.READ_WRITE.INT_CG.BITS#0.L.LAT.LATC.L2(0) [0]
	1	TP.TPBR.AD.PBDAT.ADS_REGS.OVERWRITE_ECC.READ_WRITE.INT_CG.BITS#1.L.LAT.LATC.L2(1) [0]
	2	TP.TPBR.AD.PBDAT.ADS_REGS.OVERWRITE_ECC.READ_WRITE.INT_CG.BITS#2.L.LAT.LATC.L2(2) [0]
	3	TP.TPBR.AD.PBDAT.ADS_REGS.OVERWRITE_ECC.READ_WRITE.INT_CG.BITS#3.L.LAT.LATC.L2(3) [0]
	4	TP.TPBR.AD.PBDAT.ADS_REGS.OVERWRITE_ECC.READ_WRITE.INT_CG.BITS#4.L.LAT.LATC.L2(4) [0]
	5	TP.TPBR.AD.PBDAT.ADS_REGS.OVERWRITE_ECC.READ_WRITE.INT_CG.BITS#5.L.LAT.LATC.L2(5) [0]
	6	TP.TPBR.AD.PBDAT.ADS_REGS.OVERWRITE_ECC.READ_WRITE.INT_CG.BITS#6.L.LAT.LATC.L2(6) [0]
	7	TP.TPBR.AD.PBDAT.ADS_REGS.OVERWRITE_ECC.READ_WRITE.INT_CG.BITS#7.L.LAT.LATC.L2(7) [0]
	8	TP.TPBR.AD.PBDAT.ADS_REGS.OVERWRITE_ECC.READ_WRITE.INT_CG.BITS#8.L.LAT.LATC.L2(8) [0]
	9	TP.TPBR.AD.PBDAT.ADS_REGS.OVERWRITE_ECC.READ_WRITE.INT_CG.BITS#9.L.LAT.LATC.L2(9) [0]
	10	TP.TPBR.AD.PBDAT.ADS_REGS.OVERWRITE_ECC.READ_WRITE.INT_CG.BITS#10.L.LAT.LATC.L2(10) [0]
	11	TP.TPBR.AD.PBDAT.ADS_REGS.OVERWRITE_ECC.READ_WRITE.INT_CG.BITS#11.L.LAT.LATC.L2(11) [0]
	12	TP.TPBR.AD.PBDAT.ADS_REGS.OVERWRITE_ECC.READ_WRITE.INT_CG.BITS#12.L.LAT.LATC.L2(12) [0]
	13	TP.TPBR.AD.PBDAT.ADS_REGS.OVERWRITE_ECC.READ_WRITE.INT_CG.BITS#13.L.LAT.LATC.L2(13) [0]
	14	TP.TPBR.AD.PBDAT.ADS_REGS.OVERWRITE_ECC.READ_WRITE.INT_CG.BITS#14.L.LAT.LATC.L2(14) [0]
	15	TP.TPBR.AD.PBDAT.ADS_REGS.OVERWRITE_ECC.READ_WRITE.INT_CG.BITS#15.L.LAT.LATC.L2(15) [0]
	16	TP.TPBR.AD.PBDAT.ADS_REGS.OVERWRITE_ECC.READ_WRITE.INT_CG.BITS#16.L.LAT.LATC.L2(16) [0]
	17	TP.TPBR.AD.PBDAT.ADS_REGS.OVERWRITE_ECC.READ_WRITE.INT_CG.BITS#17.L.LAT.LATC.L2(17) [0]
Bit(s)	SCOM			Dial: Description
0	RWX			ALTD_DATA_ITAG: 64th Bit the itag of a fabric alter/display operation
1:16	RWX			ALTD_DATA_TX_ECC: The two ECC values of a pcb/xscom/lpc -> pb data transfer
17	RWX			ALTD_DATA_TX_ECC_OVERWRITE: Override(=supress update of) ECC value of a pcb -> pb operationdata transfer. Be careful! There MUST BE NO xscom neither lpc data read data transfer. In Example a XSCOM read will modify the ECC value

Alter/Display XSCOM Base Address Register
Addr:	0000000000090010 (SCOM)
Name:	TP.TPBR.AD.XSCOM_BASE_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	8	TP.TPBR.AD.PBADR.XSCOM_BASE_REG.READ_WRITE.INT_CG.BITS#8.L.LAT.LATC.L2(8) [0]
	9	TP.TPBR.AD.PBADR.XSCOM_BASE_REG.READ_WRITE.INT_CG.BITS#9.L.LAT.LATC.L2(9) [0]
	10	TP.TPBR.AD.PBADR.XSCOM_BASE_REG.READ_WRITE.INT_CG.BITS#10.L.LAT.LATC.L2(10) [0]
	11	TP.TPBR.AD.PBADR.XSCOM_BASE_REG.READ_WRITE.INT_CG.BITS#11.L.LAT.LATC.L2(11) [0]
	12	TP.TPBR.AD.PBADR.XSCOM_BASE_REG.READ_WRITE.INT_CG.BITS#12.L.LAT.LATC.L2(12) [0]
	13	TP.TPBR.AD.PBADR.XSCOM_BASE_REG.READ_WRITE.INT_CG.BITS#13.L.LAT.LATC.L2(13) [0]
	14	TP.TPBR.AD.PBADR.XSCOM_BASE_REG.READ_WRITE.INT_CG.BITS#14.L.LAT.LATC.L2(14) [0]
	15	TP.TPBR.AD.PBADR.XSCOM_BASE_REG.READ_WRITE.INT_CG.BITS#15.L.LAT.LATC.L2(15) [0]
	16	TP.TPBR.AD.PBADR.XSCOM_BASE_REG.READ_WRITE.INT_CG.BITS#16.L.LAT.LATC.L2(16) [0]
	17	TP.TPBR.AD.PBADR.XSCOM_BASE_REG.READ_WRITE.INT_CG.BITS#17.L.LAT.LATC.L2(17) [0]
	18	TP.TPBR.AD.PBADR.XSCOM_BASE_REG.READ_WRITE.INT_CG.BITS#18.L.LAT.LATC.L2(18) [0]
	19	TP.TPBR.AD.PBADR.XSCOM_BASE_REG.READ_WRITE.INT_CG.BITS#19.L.LAT.LATC.L2(19) [0]
	20	TP.TPBR.AD.PBADR.XSCOM_BASE_REG.READ_WRITE.INT_CG.BITS#20.L.LAT.LATC.L2(20) [0]
	21	TP.TPBR.AD.PBADR.XSCOM_BASE_REG.READ_WRITE.INT_CG.BITS#21.L.LAT.LATC.L2(21) [0]
	22	TP.TPBR.AD.PBADR.XSCOM_BASE_REG.READ_WRITE.INT_CG.BITS#22.L.LAT.LATC.L2(22) [0]
	23	TP.TPBR.AD.PBADR.XSCOM_BASE_REG.READ_WRITE.INT_CG.BITS#23.L.LAT.LATC.L2(23) [0]
	24	TP.TPBR.AD.PBADR.XSCOM_BASE_REG.READ_WRITE.INT_CG.BITS#24.L.LAT.LATC.L2(24) [0]
	25	TP.TPBR.AD.PBADR.XSCOM_BASE_REG.READ_WRITE.INT_CG.BITS#25.L.LAT.LATC.L2(25) [0]
	26	TP.TPBR.AD.PBADR.XSCOM_BASE_REG.READ_WRITE.INT_CG.BITS#26.L.LAT.LATC.L2(26) [0]
	27	TP.TPBR.AD.PBADR.XSCOM_BASE_REG.READ_WRITE.INT_CG.BITS#27.L.LAT.LATC.L2(27) [0]
	28	TP.TPBR.AD.PBADR.XSCOM_BASE_REG.READ_WRITE.INT_CG.BITS#28.L.LAT.LATC.L2(28) [0]
	29	TP.TPBR.AD.PBADR.XSCOM_BASE_REG.READ_WRITE.INT_CG.BITS#29.L.LAT.LATC.L2(29) [0]
	61	TP.TPBR.AD.PBADR.XSCOM_BASE_REG.READ_WRITE.INT_CG.BITS#61.L.LAT.LATC.L2(61) [0]
	62	TP.TPBR.AD.PBADR.XSCOM_BASE_REG.READ_WRITE.INT_CG.BITS#62.L.LAT.LATC.L2(62) [0]
	63	TP.TPBR.AD.PBADR.XSCOM_BASE_REG.READ_WRITE.INT_CG.BITS#63.L.LAT.LATC.L2(63) [0]
Bit(s)	SCOM			Dial: Description
0:7	RO			constant=0b00000000
8:29	RW			FBC_XSCOM_BASE: Base Address for XSCOM logic in Alter/Display
30:60	RO			constant=0b0000000000000000000000000000000
61	RW			FBC_XSCOM_DISABLE_LOCAL_SHORTCUT: Used to disable the shortcut for local ADU internal registers
62	WOX			FBC_XSCOM_RESET: Used to reset the XSCOM State Machine logic in Alter/Display
63	RW			FBC_XSCOM_DISABLE: Used to disable the XSCOM State Machine logic in Alter/Display

XSCOM Mode Register
Addr:	0000000000090011 (SCOM)
Name:	TP.TPBR.AD.XSCOM_MODE_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_MODE.READ_WRITE.INT_CG.BITS#0.L.LAT.LATC.L2(0) [0]
	1	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_MODE.READ_WRITE.INT_CG.BITS#1.L.LAT.LATC.L2(1) [0]
	2	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_MODE.READ_WRITE.INT_CG.BITS#2.L.LAT.LATC.L2(2) [0]
	3	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_MODE.READ_WRITE.INT_CG.BITS#3.L.LAT.LATC.L2(3) [0]
	4	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_MODE.READ_WRITE.INT_CG.BITS#4.L.LAT.LATC.L2(4) [0]
	5	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_MODE.READ_WRITE.INT_CG.BITS#5.L.LAT.LATC.L2(5) [0]
	6	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_MODE.READ_WRITE.INT_CG.BITS#6.L.LAT.LATC.L2(6) [0]
	7	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_MODE.READ_WRITE.INT_CG.BITS#7.L.LAT.LATC.L2(7) [0]
	8	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_MODE.READ_WRITE.INT_CG.BITS#8.L.LAT.LATC.L2(8) [0]
	9	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_MODE.READ_WRITE.INT_CG.BITS#9.L.LAT.LATC.L2(9) [0]
	10	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_MODE.READ_WRITE.INT_CG.BITS#10.L.LAT.LATC.L2(10) [0]
	11	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_MODE.READ_WRITE.INT_CG.BITS#11.L.LAT.LATC.L2(11) [0]
	12	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_MODE.READ_WRITE.INT_CG.BITS#12.L.LAT.LATC.L2(12) [0]
	13	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_MODE.READ_WRITE.INT_CG.BITS#13.L.LAT.LATC.L2(13) [0]
	14	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_MODE.READ_WRITE.INT_CG.BITS#14.L.LAT.LATC.L2(14) [0]
	15	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_MODE.READ_WRITE.INT_CG.BITS#15.L.LAT.LATC.L2(15) [0]
	16	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_MODE.READ_WRITE.INT_CG.BITS#16.L.LAT.LATC.L2(16) [0]
	17	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_MODE.READ_WRITE.INT_CG.BITS#17.L.LAT.LATC.L2(17) [0]
	18	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_MODE.READ_WRITE.INT_CG.BITS#18.L.LAT.LATC.L2(18) [0]
	19	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_MODE.READ_WRITE.INT_CG.BITS#19.L.LAT.LATC.L2(19) [0]
	20	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_MODE.READ_WRITE.INT_CG.BITS#20.L.LAT.LATC.L2(20) [0]
Bit(s)	SCOM			Dial: Description
0:3	RW			XSCOM_MODE_SPARE: spare
4	RW			XSCOM_MODE_BAR_PIB_ON_ERROR1: Prohibit xscom through pib after an error 001. Accessing ADU registers and the PIB register is still allowed.
5	RW			XSCOM_MODE_BAR_PIB_ON_ERROR2: Prohibit xscom through pib after an error 010. Accessing ADU registers and the PIB register is still allowed.
6	RW			XSCOM_MODE_BAR_PIB_ON_ERROR3: Prohibit xscom through pib after an error 011. Accessing ADU registers and the PIB register is still allowed.
7	RW			XSCOM_MODE_BAR_PIB_ON_ERROR4: Prohibit xscom through pib after an error 100. Accessing ADU registers and the PIB register is still allowed.
8	RW			XSCOM_MODE_BAR_PIB_ON_ERROR5: Prohibit xscom through pib after an error 101. Accessing ADU registers and the PIB register is still allowed.
9	RW			XSCOM_MODE_BAR_PIB_ON_ERROR6: Prohibit xscom through pib after an error 110. Accessing ADU registers and the PIB register is still allowed.
10	RW			XSCOM_MODE_BAR_PIB_ON_ERROR7: Prohibit xscom through pib after an error 111. Accessing ADU registers and the PIB register is still allowed.
11	RW			XSCOM_MODE_HANG_PIB_RESET: Reset XSCOM State Machine when a pib hang was detected
12	RW			XSCOM_MODE_HANG_RESET: Reset XSCOM State Machine when another a hang was detected
13	RW			XSCOM_MODE_RESET_ON_PARITY: Reset XSCOM State Machine when a parity error was detected
14	RW			XSCOM_MODE_FREEZE_LOG_ON_ERROR1: Freeze xscom log register after an error 001.
15	RW			XSCOM_MODE_FREEZE_LOG_ON_ERROR2: Freeze xscom log register after an error 010.
16	RW			XSCOM_MODE_FREEZE_LOG_ON_ERROR3: Freeze xscom log register after an error 011.
17	RW			XSCOM_MODE_FREEZE_LOG_ON_ERROR4: Freeze xscom log register after an error 100.
18	RW			XSCOM_MODE_FREEZE_LOG_ON_ERROR5: Freeze xscom log register after an error 101.
19	RW			XSCOM_MODE_FREEZE_LOG_ON_ERROR6: Freeze xscom log register after an error 110.
20	RW			XSCOM_MODE_FREEZE_LOG_ON_ERROR7: Freeze xscom log register after an error 111.

XSCOM Status Log Register
Addr:	0000000000090012 (SCOM)
Name:	TP.TPBR.AD.XSCOM_LOG_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.AD.PBADR.XSCOM_SM_IP_L2_INST.LATC.L2(0) [0]
	1	TP.TPBR.AD.XCSM.ADS_REGS.ERROR_LOG.READ_WRITE.EXTERNAL_CG.BITS#1.L.LAT.LATC.L2(1) [0]
	2	TP.TPBR.AD.XCSM.ADS_REGS.ERROR_LOG.READ_WRITE.EXTERNAL_CG.BITS#2.L.LAT.LATC.L2(2) [0]
	3	TP.TPBR.AD.XCSM.ADS_REGS.ERROR_LOG.READ_WRITE.EXTERNAL_CG.BITS#3.L.LAT.LATC.L2(3) [0]
	4	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#4.L.LAT.LATC.L2(4) [0]
	5	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#5.L.LAT.LATC.L2(5) [0]
	6	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#6.L.LAT.LATC.L2(6) [0]
	7	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#7.L.LAT.LATC.L2(7) [0]
	8	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#8.L.LAT.LATC.L2(8) [0]
	9	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#9.L.LAT.LATC.L2(9) [0]
	10	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#10.L.LAT.LATC.L2(10) [0]
	11	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#11.L.LAT.LATC.L2(11) [0]
	12	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#12.L.LAT.LATC.L2(12) [0]
	13	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#13.L.LAT.LATC.L2(13) [0]
	14	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#14.L.LAT.LATC.L2(14) [0]
	15	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#15.L.LAT.LATC.L2(15) [0]
	16	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#16.L.LAT.LATC.L2(16) [0]
	17	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#17.L.LAT.LATC.L2(17) [0]
	18	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#18.L.LAT.LATC.L2(18) [0]
	19	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#19.L.LAT.LATC.L2(19) [0]
	20	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#20.L.LAT.LATC.L2(20) [0]
	21	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#21.L.LAT.LATC.L2(21) [0]
	22	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#22.L.LAT.LATC.L2(22) [0]
	23	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#23.L.LAT.LATC.L2(23) [0]
	24	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#24.L.LAT.LATC.L2(24) [0]
	27	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#27.L.LAT.LATC.L2(27) [0]
	28	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#28.L.LAT.LATC.L2(28) [0]
	29	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#29.L.LAT.LATC.L2(29) [0]
	31	TP.TPBR.AD.PIB.XSCOM_LOG_REG.READ_WRITE.EXTERNAL_CG.BITS#31.L.LAT.LATC.L2(31) [0]
	33	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#33.L.LAT.LATC.L2(33) [0]
	34	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#34.L.LAT.LATC.L2(34) [0]
	35	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#35.L.LAT.LATC.L2(35) [0]
	36	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#36.L.LAT.LATC.L2(36) [0]
	37	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#37.L.LAT.LATC.L2(37) [0]
	38	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#38.L.LAT.LATC.L2(38) [0]
	39	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#39.L.LAT.LATC.L2(39) [0]
	40	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#40.L.LAT.LATC.L2(40) [0]
	41	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#41.L.LAT.LATC.L2(41) [0]
	42	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#42.L.LAT.LATC.L2(42) [0]
	43	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#43.L.LAT.LATC.L2(43) [0]
	44	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#44.L.LAT.LATC.L2(44) [0]
	45	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#45.L.LAT.LATC.L2(45) [0]
	46	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#46.L.LAT.LATC.L2(46) [0]
	47	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#47.L.LAT.LATC.L2(47) [0]
	48	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#48.L.LAT.LATC.L2(48) [0]
	49	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#49.L.LAT.LATC.L2(49) [0]
	50	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#50.L.LAT.LATC.L2(50) [0]
	51	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#51.L.LAT.LATC.L2(51) [0]
	52	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#52.L.LAT.LATC.L2(52) [0]
	53	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#53.L.LAT.LATC.L2(53) [0]
	54	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#54.L.LAT.LATC.L2(54) [0]
	55	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#55.L.LAT.LATC.L2(55) [0]
	56	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#56.L.LAT.LATC.L2(56) [0]
	57	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#57.L.LAT.LATC.L2(57) [0]
	58	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#58.L.LAT.LATC.L2(58) [0]
	59	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#59.L.LAT.LATC.L2(59) [0]
	60	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#60.L.LAT.LATC.L2(60) [0]
	61	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#61.L.LAT.LATC.L2(61) [0]
	62	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#62.L.LAT.LATC.L2(62) [0]
	63	TP.TPBR.AD.PBADR.ERROR_LOG.READ_WRITE.INT_CG.BITS#63.L.LAT.LATC.L2(63) [0]
Bit(s)	SCOM			Dial: Description
0	ROX			XSCOM_CMD_IN_PROG: XSCOM Command In Progress (read only status bit does not freeze on error)
1:3	RWX_WCLRREG			XSCOM_CMD_STATUS: XSCOM Command Returned Status
4	RWX_WCLRREG			XSCOM_WRITE_CMD: XSCOM was a Write Command
5:24	RWX_WCLRREG			XSCOM_ADDR_TAG: XSCOM Command Fabric Address Tag, indicates master of command
25:26	RO			constant=0b00
27:29	RWX_WCLRREG			XSCOM_THR_ID: XSCOM Command Fabric Thread ID, indicates master thread of command
30	RO			constant=0b0
31	ROX			XSCOM_PIB_COMPONENT_BUSY: PIB transaction ongoing, if set
32	RO			constant=0b0
33:63	RWX_WCLRREG			XSCOM_PIB_ADDR: XSCOM PIB Address of Failing Command

XSCOM Error Register
Addr:	0000000000090013 (SCOM)
Name:	TP.TPBR.AD.XSCOM_ERR_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.AD.PBADR.XSCOM_STATUS_ERR.EXTERNAL_CG.BITS#0.L.LAT.LATC.L2(0) [0]
	1	TP.TPBR.AD.PBADR.XSCOM_STATUS_ERR.EXTERNAL_CG.BITS#1.L.LAT.LATC.L2(1) [0]
	2	TP.TPBR.AD.PBADR.XSCOM_STATUS_ERR.EXTERNAL_CG.BITS#2.L.LAT.LATC.L2(2) [0]
	3	TP.TPBR.AD.PBADR.XSCOM_STATUS_ERR.EXTERNAL_CG.BITS#3.L.LAT.LATC.L2(3) [0]
	4	TP.TPBR.AD.PBADR.XSCOM_STATUS_ERR.EXTERNAL_CG.BITS#4.L.LAT.LATC.L2(4) [0]
	5	TP.TPBR.AD.PBADR.XSCOM_STATUS_ERR.EXTERNAL_CG.BITS#5.L.LAT.LATC.L2(5) [0]
	8	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_STATUS_ERR.EXTERNAL_CG.BITS#8.L.LAT.LATC.L2(8) [0]
	9	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_STATUS_ERR.EXTERNAL_CG.BITS#9.L.LAT.LATC.L2(9) [0]
	10	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_STATUS_ERR.EXTERNAL_CG.BITS#10.L.LAT.LATC.L2(10) [0]
	11	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_STATUS_ERR.EXTERNAL_CG.BITS#11.L.LAT.LATC.L2(11) [0]
	12	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_STATUS_ERR.INT_CG.BITS#12.L.LAT.LATC.L2(12) [0]
	13	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_STATUS_ERR.INT_CG.BITS#13.L.LAT.LATC.L2(13) [0]
	14	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_STATUS_ERR.INT_CG.BITS#14.L.LAT.LATC.L2(14) [0]
	15	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_STATUS_ERR.INT_CG.BITS#15.L.LAT.LATC.L2(15) [0]
	16	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_STATUS_ERR.INT_CG.BITS#16.L.LAT.LATC.L2(16) [0]
	17	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_STATUS_ERR.INT_CG.BITS#17.L.LAT.LATC.L2(17) [0]
	18	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_STATUS_ERR.INT_CG.BITS#18.L.LAT.LATC.L2(18) [0]
	19	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_STATUS_ERR.INT_CG.BITS#19.L.LAT.LATC.L2(19) [0]
	20	TP.TPBR.AD.XCSM.ADS_REGS.XSCOM_STATUS_ERR.INT_CG.BITS#20.L.LAT.LATC.L2(20) [0]
Bit(s)	SCOM			Dial: Description
0	RWX_WCLRREG			XSCOM_ADDRESS_ERR: XSCOM Command Error: invalid address
1	RWX_WCLRREG			XSCOM_TSIZE_ERR: XSCOM Command Error: invalid tsize
2	RWX_WCLRREG			XSCOM_RC_TTAG_PAR_ERR: PowerBus Reflected Command ttag Parity Error
3	RWX_WCLRREG			XSCOM_CR_TTAG_PAR_ERR: PowerBus Combined responce ttag Parity Error
4	RWX_WCLRREG			XSCOM_CR_ATAG_PAR_ERR: PowerBus Combined responce atag Parity Error
5	RWX_WCLRREG			XSCOM_RC_ADDR_PAR_ERR: PowerBus Reflected Command addr Parity Error
6:7	RO			constant=0b00
8	RWX_WCLRREG			PB_ECC_CE_ERR: pb received correctable ecc error
9	RWX_WCLRREG			PB_ECC_UE_ERR: pb received uncorrectable ecc error
10	RWX_WCLRREG			PB_ECC_SUE_ERR: pb received special uncorrectable ecc error
11	RWX_WCLRREG			RTAG_PARITY_ERR: Error: the data received came with an rtag that has an parity error, so it could also be not XSCOM related
12	RWX_WCLRREG			CRESP_HANG_ERR: Hang Detected waiting for cResp
13	RWX_WCLRREG			PIB_HANG_ERR: Hang Detected waiting for PIB
14	RWX_WCLRREG			PBDATA_HANG_ERR: Hang Detected waiting for Data from PB
15	RWX_WCLRREG			ADS_HANG_ERR: Hang Detected waiting for internal ADU bus to complete
16	RWX_WCLRREG			XSCOM_FSM_PERR: XSCOM Command State Machine Parity Error
17	RWX_WCLRREG			SPARE0_ERR: a spare latch was set - should never happen - this spare is just a placeholder
18	RWX_WCLRREG			SPARE1_ERR: a spare latch was set - should never happen - this spare is just a placeholder
19	RWX_WCLRREG			UNEXPECT_DATA_ERR: Unexpected PB Data Error: state machine was idle while data arrived
20	RWX_WCLRREG			ILL_CRESP_ERR: Error Illegal Combined Responce Reveiced
21:63	RO			constant=0b0000000000000000000000000000000000000000000

XSCOM Received Remote Status pMisc and Source Register
Addr:	0000000000090018 (SCOM)
Name:	TP.TPBR.AD.XSCOM_RCVED_STAT_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.AD.RCV.ADS_REGS.XSCOM_STAT.READ_WRITE.INT_CG.BITS#0.L.LAT.LATC.L2(0) [0]
	1	TP.TPBR.AD.RCV.ADS_REGS.XSCOM_STAT.READ_WRITE.INT_CG.BITS#1.L.LAT.LATC.L2(1) [0]
	2	TP.TPBR.AD.RCV.ADS_REGS.XSCOM_STAT.READ_WRITE.INT_CG.BITS#2.L.LAT.LATC.L2(2) [0]
	3	TP.TPBR.AD.RCV.ADS_REGS.XSCOM_STAT.READ_WRITE.INT_CG.BITS#3.L.LAT.LATC.L2(3) [0]
	4	TP.TPBR.AD.RCV.ADS_REGS.XSCOM_STAT.READ_WRITE.INT_CG.BITS#4.L.LAT.LATC.L2(4) [0]
	5	TP.TPBR.AD.RCV.ADS_REGS.XSCOM_STAT.READ_WRITE.INT_CG.BITS#5.L.LAT.LATC.L2(5) [0]
	6	TP.TPBR.AD.RCV.ADS_REGS.XSCOM_STAT.READ_WRITE.INT_CG.BITS#6.L.LAT.LATC.L2(6) [0]
	7	TP.TPBR.AD.RCV.ADS_REGS.XSCOM_STAT.READ_WRITE.INT_CG.BITS#7.L.LAT.LATC.L2(7) [0]
	8	TP.TPBR.AD.RCV.ADS_REGS.XSCOM_STAT.READ_WRITE.INT_CG.BITS#8.L.LAT.LATC.L2(8) [0]
	9	TP.TPBR.AD.RCV.ADS_REGS.XSCOM_STAT.READ_WRITE.INT_CG.BITS#9.L.LAT.LATC.L2(9) [0]
	10	TP.TPBR.AD.RCV.ADS_REGS.XSCOM_STAT.READ_WRITE.INT_CG.BITS#10.L.LAT.LATC.L2(10) [0]
	11	TP.TPBR.AD.RCV.ADS_REGS.XSCOM_STAT.READ_WRITE.INT_CG.BITS#11.L.LAT.LATC.L2(11) [0]
	12	TP.TPBR.AD.RCV.ADS_REGS.XSCOM_STAT.READ_WRITE.INT_CG.BITS#12.L.LAT.LATC.L2(12) [0]
	13	TP.TPBR.AD.RCV.ADS_REGS.XSCOM_STAT.READ_WRITE.INT_CG.BITS#13.L.LAT.LATC.L2(13) [0]
	14	TP.TPBR.AD.RCV.ADS_REGS.XSCOM_STAT.READ_WRITE.INT_CG.BITS#14.L.LAT.LATC.L2(14) [0]
	15	TP.TPBR.AD.RCV.ADS_REGS.XSCOM_STAT.READ_WRITE.INT_CG.BITS#15.L.LAT.LATC.L2(15) [0]
	16	TP.TPBR.AD.RCV.ADS_REGS.XSCOM_STAT.READ_WRITE.INT_CG.BITS#16.L.LAT.LATC.L2(16) [0]
	17	TP.TPBR.AD.RCV.ADS_REGS.XSCOM_STAT.READ_WRITE.INT_CG.BITS#17.L.LAT.LATC.L2(17) [0]
	18	TP.TPBR.AD.RCV.ADS_REGS.XSCOM_STAT.READ_WRITE.INT_CG.BITS#18.L.LAT.LATC.L2(18) [0]
	19	TP.TPBR.AD.RCV.ADS_REGS.XSCOM_STAT.READ_WRITE.INT_CG.BITS#19.L.LAT.LATC.L2(19) [0]
Bit(s)	SCOM			Dial: Description
0	RWX_WCLRREG			XSCOM_DONE: XSCOM Command Done - an xscom command sourced from this chip has completed This bit needs to be cleared before an XSCOM operation to be accurate
1:3	RWX_WCLRREG			XSCOM_RESULT: XSCOM Result code - "000":ok "001":need-retry other:error
4	RWX_WCLRREG
5:9	RWX_WCLRREG			XSCOM_COREID: UnitId of the command source (which ncu started this operation)
10:12	RWX_WCLRREG			XSCOM_STAT_THRID: ThreadId of the command source (which thread started this operation)
13:16	RWX_WCLRREG			DEST_TOPOLOGY_ID: Thread Id of XSCOM command destination (pointing to the ADU that executed the command)
17:19	RWX_WCLRREG

XSCOM Access Address Register (ADU Internal command transfer use only)
Addr:	000000000009001C (SCOM)
Name:	TP.TPBR.AD.ADS_XSCOM_CMD_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#0.L.LAT.LATC.L2(0) [0]
	5	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#5.L.LAT.LATC.L2(5) [0]
	6	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#6.L.LAT.LATC.L2(6) [0]
	7	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#7.L.LAT.LATC.L2(7) [0]
	8	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#8.L.LAT.LATC.L2(8) [0]
	9	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#9.L.LAT.LATC.L2(9) [0]
	10	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#10.L.LAT.LATC.L2(10) [0]
	11	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#11.L.LAT.LATC.L2(11) [0]
	30	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#30.L.LAT.LATC.L2(30) [0]
	31	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#31.L.LAT.LATC.L2(31) [0]
	32	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#32.L.LAT.LATC.L2(32) [0]
	33	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#33.L.LAT.LATC.L2(33) [0]
	34	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#34.L.LAT.LATC.L2(34) [0]
	35	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#35.L.LAT.LATC.L2(35) [0]
	36	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#36.L.LAT.LATC.L2(36) [0]
	37	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#37.L.LAT.LATC.L2(37) [0]
	38	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#38.L.LAT.LATC.L2(38) [0]
	39	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#39.L.LAT.LATC.L2(39) [0]
	40	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#40.L.LAT.LATC.L2(40) [0]
	41	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#41.L.LAT.LATC.L2(41) [0]
	42	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#42.L.LAT.LATC.L2(42) [0]
	43	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#43.L.LAT.LATC.L2(43) [0]
	44	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#44.L.LAT.LATC.L2(44) [0]
	45	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#45.L.LAT.LATC.L2(45) [0]
	46	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#46.L.LAT.LATC.L2(46) [0]
	47	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#47.L.LAT.LATC.L2(47) [0]
	48	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#48.L.LAT.LATC.L2(48) [0]
	49	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#49.L.LAT.LATC.L2(49) [0]
	50	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#50.L.LAT.LATC.L2(50) [0]
	51	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#51.L.LAT.LATC.L2(51) [0]
	52	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#52.L.LAT.LATC.L2(52) [0]
	53	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#53.L.LAT.LATC.L2(53) [0]
	54	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#54.L.LAT.LATC.L2(54) [0]
	55	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#55.L.LAT.LATC.L2(55) [0]
	56	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#56.L.LAT.LATC.L2(56) [0]
	57	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#57.L.LAT.LATC.L2(57) [0]
	58	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#58.L.LAT.LATC.L2(58) [0]
	59	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#59.L.LAT.LATC.L2(59) [0]
	60	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#60.L.LAT.LATC.L2(60) [0]
	61	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#61.L.LAT.LATC.L2(61) [0]
	62	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#62.L.LAT.LATC.L2(62) [0]
	63	TP.TPBR.AD.PBADR.XSCOM_CMD_REG.READ_WRITE.INT_CG.BITS#63.L.LAT.LATC.L2(63) [0]
Bit(s)	SCOM			Dial: Description
0	ROX			ADS_XSCOM_CMD_REG_RNW: INTERNAL REGISTER, indicate read operation of current xscom/lpc access (else it is a write)
1:4	RO			constant=0b0000
5:11	ROX			ADS_XSCOM_CMD_REG_SIZE: INTERNAL REGISTER, size of current xscom/lpc access
12:29	RO			constant=0b000000000000000000
30:63	ROX			ADS_XSCOM_CMD_REG_ADR: INTERNAL REGISTER, byte address of current xscom/lpc access

XSCOM Data Ramp Register (Internal use only)
Addr:	000000000009001E (SCOM)
Name:	TP.TPBR.AD.XSCOM_DAT0_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#0.L.LAT.LATC.L2(0) [0]
	1	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#1.L.LAT.LATC.L2(1) [0]
	2	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#2.L.LAT.LATC.L2(2) [0]
	3	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#3.L.LAT.LATC.L2(3) [0]
	4	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#4.L.LAT.LATC.L2(4) [0]
	5	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#5.L.LAT.LATC.L2(5) [0]
	6	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#6.L.LAT.LATC.L2(6) [0]
	7	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#7.L.LAT.LATC.L2(7) [0]
	8	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#8.L.LAT.LATC.L2(8) [0]
	9	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#9.L.LAT.LATC.L2(9) [0]
	10	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#10.L.LAT.LATC.L2(10) [0]
	11	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#11.L.LAT.LATC.L2(11) [0]
	12	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#12.L.LAT.LATC.L2(12) [0]
	13	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#13.L.LAT.LATC.L2(13) [0]
	14	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#14.L.LAT.LATC.L2(14) [0]
	15	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#15.L.LAT.LATC.L2(15) [0]
	16	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#16.L.LAT.LATC.L2(16) [0]
	17	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#17.L.LAT.LATC.L2(17) [0]
	18	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#18.L.LAT.LATC.L2(18) [0]
	19	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#19.L.LAT.LATC.L2(19) [0]
	20	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#20.L.LAT.LATC.L2(20) [0]
	21	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#21.L.LAT.LATC.L2(21) [0]
	22	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#22.L.LAT.LATC.L2(22) [0]
	23	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#23.L.LAT.LATC.L2(23) [0]
	24	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#24.L.LAT.LATC.L2(24) [0]
	25	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#25.L.LAT.LATC.L2(25) [0]
	26	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#26.L.LAT.LATC.L2(26) [0]
	27	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#27.L.LAT.LATC.L2(27) [0]
	28	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#28.L.LAT.LATC.L2(28) [0]
	29	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#29.L.LAT.LATC.L2(29) [0]
	30	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#30.L.LAT.LATC.L2(30) [0]
	31	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#31.L.LAT.LATC.L2(31) [0]
	32	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#32.L.LAT.LATC.L2(32) [0]
	33	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#33.L.LAT.LATC.L2(33) [0]
	34	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#34.L.LAT.LATC.L2(34) [0]
	35	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#35.L.LAT.LATC.L2(35) [0]
	36	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#36.L.LAT.LATC.L2(36) [0]
	37	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#37.L.LAT.LATC.L2(37) [0]
	38	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#38.L.LAT.LATC.L2(38) [0]
	39	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#39.L.LAT.LATC.L2(39) [0]
	40	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#40.L.LAT.LATC.L2(40) [0]
	41	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#41.L.LAT.LATC.L2(41) [0]
	42	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#42.L.LAT.LATC.L2(42) [0]
	43	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#43.L.LAT.LATC.L2(43) [0]
	44	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#44.L.LAT.LATC.L2(44) [0]
	45	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#45.L.LAT.LATC.L2(45) [0]
	46	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#46.L.LAT.LATC.L2(46) [0]
	47	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#47.L.LAT.LATC.L2(47) [0]
	48	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#48.L.LAT.LATC.L2(48) [0]
	49	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#49.L.LAT.LATC.L2(49) [0]
	50	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#50.L.LAT.LATC.L2(50) [0]
	51	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#51.L.LAT.LATC.L2(51) [0]
	52	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#52.L.LAT.LATC.L2(52) [0]
	53	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#53.L.LAT.LATC.L2(53) [0]
	54	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#54.L.LAT.LATC.L2(54) [0]
	55	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#55.L.LAT.LATC.L2(55) [0]
	56	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#56.L.LAT.LATC.L2(56) [0]
	57	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#57.L.LAT.LATC.L2(57) [0]
	58	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#58.L.LAT.LATC.L2(58) [0]
	59	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#59.L.LAT.LATC.L2(59) [0]
	60	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#60.L.LAT.LATC.L2(60) [0]
	61	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#61.L.LAT.LATC.L2(61) [0]
	62	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#62.L.LAT.LATC.L2(62) [0]
63	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA0.READ_WRITE.INT_CG.BITS#63.L.LAT.LATC.L2(63) [0]
Bit(s)	SCOM			Dial: Description
0:63	RWX			XSCOM_DAT0: INTERNAL REGISTER, left data in the Dataramp (to be transfered to/from PIB/LPC)

XSCOM Data Ramp Register (Internal use only)
Addr:	000000000009001F (SCOM)
Name:	TP.TPBR.AD.XSCOM_DAT1_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#0.L.LAT.LATC.L2(0) [0]
	1	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#1.L.LAT.LATC.L2(1) [0]
	2	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#2.L.LAT.LATC.L2(2) [0]
	3	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#3.L.LAT.LATC.L2(3) [0]
	4	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#4.L.LAT.LATC.L2(4) [0]
	5	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#5.L.LAT.LATC.L2(5) [0]
	6	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#6.L.LAT.LATC.L2(6) [0]
	7	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#7.L.LAT.LATC.L2(7) [0]
	8	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#8.L.LAT.LATC.L2(8) [0]
	9	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#9.L.LAT.LATC.L2(9) [0]
	10	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#10.L.LAT.LATC.L2(10) [0]
	11	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#11.L.LAT.LATC.L2(11) [0]
	12	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#12.L.LAT.LATC.L2(12) [0]
	13	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#13.L.LAT.LATC.L2(13) [0]
	14	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#14.L.LAT.LATC.L2(14) [0]
	15	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#15.L.LAT.LATC.L2(15) [0]
	16	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#16.L.LAT.LATC.L2(16) [0]
	17	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#17.L.LAT.LATC.L2(17) [0]
	18	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#18.L.LAT.LATC.L2(18) [0]
	19	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#19.L.LAT.LATC.L2(19) [0]
	20	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#20.L.LAT.LATC.L2(20) [0]
	21	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#21.L.LAT.LATC.L2(21) [0]
	22	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#22.L.LAT.LATC.L2(22) [0]
	23	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#23.L.LAT.LATC.L2(23) [0]
	24	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#24.L.LAT.LATC.L2(24) [0]
	25	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#25.L.LAT.LATC.L2(25) [0]
	26	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#26.L.LAT.LATC.L2(26) [0]
	27	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#27.L.LAT.LATC.L2(27) [0]
	28	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#28.L.LAT.LATC.L2(28) [0]
	29	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#29.L.LAT.LATC.L2(29) [0]
	30	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#30.L.LAT.LATC.L2(30) [0]
	31	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#31.L.LAT.LATC.L2(31) [0]
	32	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#32.L.LAT.LATC.L2(32) [0]
	33	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#33.L.LAT.LATC.L2(33) [0]
	34	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#34.L.LAT.LATC.L2(34) [0]
	35	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#35.L.LAT.LATC.L2(35) [0]
	36	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#36.L.LAT.LATC.L2(36) [0]
	37	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#37.L.LAT.LATC.L2(37) [0]
	38	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#38.L.LAT.LATC.L2(38) [0]
	39	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#39.L.LAT.LATC.L2(39) [0]
	40	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#40.L.LAT.LATC.L2(40) [0]
	41	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#41.L.LAT.LATC.L2(41) [0]
	42	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#42.L.LAT.LATC.L2(42) [0]
	43	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#43.L.LAT.LATC.L2(43) [0]
	44	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#44.L.LAT.LATC.L2(44) [0]
	45	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#45.L.LAT.LATC.L2(45) [0]
	46	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#46.L.LAT.LATC.L2(46) [0]
	47	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#47.L.LAT.LATC.L2(47) [0]
	48	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#48.L.LAT.LATC.L2(48) [0]
	49	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#49.L.LAT.LATC.L2(49) [0]
	50	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#50.L.LAT.LATC.L2(50) [0]
	51	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#51.L.LAT.LATC.L2(51) [0]
	52	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#52.L.LAT.LATC.L2(52) [0]
	53	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#53.L.LAT.LATC.L2(53) [0]
	54	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#54.L.LAT.LATC.L2(54) [0]
	55	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#55.L.LAT.LATC.L2(55) [0]
	56	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#56.L.LAT.LATC.L2(56) [0]
	57	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#57.L.LAT.LATC.L2(57) [0]
	58	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#58.L.LAT.LATC.L2(58) [0]
	59	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#59.L.LAT.LATC.L2(59) [0]
	60	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#60.L.LAT.LATC.L2(60) [0]
	61	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#61.L.LAT.LATC.L2(61) [0]
	62	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#62.L.LAT.LATC.L2(62) [0]
63	TP.TPBR.AD.PBDAT.ADS_REGS.XSCOM_DATA1.READ_WRITE.INT_CG.BITS#63.L.LAT.LATC.L2(63) [0]
Bit(s)	SCOM			Dial: Description
0:63	RWX			XSCOM_DAT1: INTERNAL REGISTER, right data in the Dataramp (to be transfered to/from PIB/LPC)

pMisc Status Register
Addr:	0000000000090020 (SCOM)
Name:	TP.TPBR.AD.SND_STAT_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.AD.SND.ADS_REGS.SND_STAT_ERR.EXTERNAL_CG.BITS#0.L.LAT.LATC.L2(0) [0]
	1	TP.TPBR.AD.SND.ADS_REGS.SND_STAT_ERR.EXTERNAL_CG.BITS#1.L.LAT.LATC.L2(1) [0]
	2	TP.TPBR.AD.SND.ADS_REGS.SND_STAT_ERR.EXTERNAL_CG.BITS#2.L.LAT.LATC.L2(2) [0]
	3	TP.TPBR.AD.SND.ADS_REGS.SND_STAT_ERR.EXTERNAL_CG.BITS#3.L.LAT.LATC.L2(3) [0]
	4	TP.TPBR.AD.SND.ADS_REGS.SND_STAT_ERR.EXTERNAL_CG.BITS#4.L.LAT.LATC.L2(4) [0]
	5	TP.TPBR.AD.SND.ADS_REGS.SND_STAT_ERR.EXTERNAL_CG.BITS#5.L.LAT.LATC.L2(5) [0]
	6	TP.TPBR.AD.SND.ADS_REGS.SND_STAT_ERR.EXTERNAL_CG.BITS#6.L.LAT.LATC.L2(6) [0]
	16	TP.TPBR.AD.PBADR.SND_STAT_ERR.EXTERNAL_CG.BITS#16.L.LAT.LATC.L2(16) [0]
	32	TP.TPBR.AD.RCV.ADS_REGS.SND_STAT_ERR.EXTERNAL_CG.BITS#32.L.LAT.LATC.L2(32) [0]
	33	TP.TPBR.AD.RCV.ADS_REGS.SND_STAT_ERR.EXTERNAL_CG.BITS#33.L.LAT.LATC.L2(33) [0]
	34	TP.TPBR.AD.RCV.ADS_REGS.SND_STAT_ERR.EXTERNAL_CG.BITS#34.L.LAT.LATC.L2(34) [0]
	48	TP.TPBR.AD.RCV.ADS_REGS.SND_STAT.READ_WRITE.EXTERNAL_CG.BITS#48.L.LAT.LATC.L2(48) [0]
	49	TP.TPBR.AD.RCV.ADS_REGS.SND_STAT.READ_WRITE.EXTERNAL_CG.BITS#49.L.LAT.LATC.L2(49) [0]
	50	TP.TPBR.AD.RCV.ADS_REGS.SND_STAT.READ_WRITE.EXTERNAL_CG.BITS#50.L.LAT.LATC.L2(50) [0]
	51	TP.TPBR.AD.RCV.ADS_REGS.SND_STAT.READ_WRITE.EXTERNAL_CG.BITS#51.L.LAT.LATC.L2(51) [0]
Bit(s)	SCOM			Dial: Description
0	RWX_WCLRREG			ERR_CMD_OVERRUN: Error Command dropped due to queue overrun
1	RWX_WCLRREG			TRC_CMD_OVERRUN: Trace Command dropped due to queue overrun
2	RWX_WCLRREG			XSC_CMD_OVERRUN: XSCOM Status Command dropped due to queue overrun
3	RWX_WCLRREG			HTM_CMD_OVERRUN: HTM Command dropped due to queue overrun
4	RWX_WCLRREG			TOD_CMD_OVERRUN: TOD Command dropped due to queue overrun
5	RWX_WCLRREG			CMD_COUNT_ERR: attempt to send but too much commands at a time (causes short stall to prevent tag reuse)
6	RWX_WCLRREG			SND_PB_OP_HANG_ERR: pmisc snd waiting for outstanding cresp much to long
7:15	RO			constant=0b000000000
16	RWX_WCLRREG			SND_INVALID_CRESP_ERR: pmisc send received a invalid combined responce
17:31	RO			constant=0b000000000000000
32	RWX_WCLRREG			RCV_TTAG_PARITY_ERR: parity error of ttag in rcv macro
33	RWX_WCLRREG			RCV_PB_OP_HANG_ERR: pmisc rcv waiting for outstanding cresp much to long
34	RWX_WCLRREG			TOD_HANG_ERR: pmisc rcv waiting for second tod packet much to long
35:47	RO			constant=0b0000000000000
48:51	ROX			RCV_TOD_STATE: Reflects what parts of a pMisc TOD package has been received. CRESPAB means all but waiting for XCSM doing the PIB operation. Dial enums: IDLE=>0b0000 RCMDA=>0b1000 RCMDB=>0b0100 CRESPA=>0b0010 RCMDB_CRESPA=>0b0110 CRESPB=>0b0001 RCMDA_CRESPB=>0b1001 RCMDAB=>0b1100 CRESPAB=>0b0011
52:60	RO			constant=0b000000000 Dial enums: IDLE=>0b0000 RCMDA=>0b1000 RCMDB=>0b0100 CRESPA=>0b0010 RCMDB_CRESPA=>0b0110 CRESPB=>0b0001 RCMDA_CRESPB=>0b1001 RCMDAB=>0b1100 CRESPAB=>0b0011

pMisc Mode Register
Addr:	0000000000090021 (SCOM)
Name:	TP.TPBR.AD.SND_MODE_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.AD.SND.ADS_REGS.SND_RCV_MODE.READ_WRITE.INT_CG.BITS#0.L.LAT.LATC.L2(0) [0]
	1	TP.TPBR.AD.SND.ADS_REGS.SND_RCV_MODE.READ_WRITE.INT_CG.BITS#1.L.LAT.LATC.L2(1) [0]
	2	TP.TPBR.AD.SND.ADS_REGS.SND_RCV_MODE.READ_WRITE.INT_CG.BITS#2.L.LAT.LATC.L2(2) [0]
	3	TP.TPBR.AD.SND.ADS_REGS.SND_RCV_MODE.READ_WRITE.INT_CG.BITS#3.L.LAT.LATC.L2(3) [0]
	4	TP.TPBR.AD.SND.ADS_REGS.SND_RCV_MODE.READ_WRITE.INT_CG.BITS#4.L.LAT.LATC.L2(4) [0]
	5	TP.TPBR.AD.SND.ADS_REGS.SND_RCV_MODE.READ_WRITE.INT_CG.BITS#5.L.LAT.LATC.L2(5) [0]
	6	TP.TPBR.AD.SND.ADS_REGS.SND_RCV_MODE.READ_WRITE.INT_CG.BITS#6.L.LAT.LATC.L2(6) [0]
	7	TP.TPBR.AD.SND.ADS_REGS.SND_RCV_MODE.READ_WRITE.INT_CG.BITS#7.L.LAT.LATC.L2(7) [0]
	8	TP.TPBR.AD.SND.ADS_REGS.SND_RCV_MODE.READ_WRITE.INT_CG.BITS#8.L.LAT.LATC.L2(8) [0]
	9	TP.TPBR.AD.SND.ADS_REGS.SND_RCV_MODE.READ_WRITE.INT_CG.BITS#9.L.LAT.LATC.L2(9) [0]
	10	TP.TPBR.AD.SND.ADS_REGS.SND_RCV_MODE.READ_WRITE.INT_CG.BITS#10.L.LAT.LATC.L2(10) [0]
	11	TP.TPBR.AD.SND.ADS_REGS.SND_RCV_MODE.READ_WRITE.INT_CG.BITS#11.L.LAT.LATC.L2(11) [0]
	12	TP.TPBR.AD.SND.ADS_REGS.SND_RCV_MODE.READ_WRITE.INT_CG.BITS#12.L.LAT.LATC.L2(12) [0]
	13	TP.TPBR.AD.SND.ADS_REGS.SND_RCV_MODE.READ_WRITE.INT_CG.BITS#13.L.LAT.LATC.L2(13) [0]
	14	TP.TPBR.AD.SND.ADS_REGS.SND_RCV_MODE.READ_WRITE.INT_CG.BITS#14.L.LAT.LATC.L2(14) [0]
	15	TP.TPBR.AD.SND.ADS_REGS.SND_RCV_MODE.READ_WRITE.INT_CG.BITS#15.L.LAT.LATC.L2(15) [0]
	16	TP.TPBR.AD.SND.ADS_REGS.SND_RCV_MODE.READ_WRITE.INT_CG.BITS#16.L.LAT.LATC.L2(16) [0]
	17	TP.TPBR.AD.SND.ADS_REGS.SND_RCV_MODE.READ_WRITE.INT_CG.BITS#17.L.LAT.LATC.L2(17) [0]
	18	TP.TPBR.AD.SND.ADS_REGS.SND_RCV_MODE.READ_WRITE.INT_CG.BITS#18.L.LAT.LATC.L2(18) [0]
	19	TP.TPBR.AD.SND.ADS_REGS.SND_RCV_MODE.READ_WRITE.INT_CG.BITS#19.L.LAT.LATC.L2(19) [0]
	20	TP.TPBR.AD.SND.ADS_REGS.SND_RCV_MODE.READ_WRITE.INT_CG.BITS#20.L.LAT.LATC.L2(20) [0]
	21	TP.TPBR.AD.SND.ADS_REGS.SND_RCV_MODE.READ_WRITE.INT_CG.BITS#21.L.LAT.LATC.L2(21) [0]
	22	TP.TPBR.AD.SND.ADS_REGS.SND_RCV_MODE.READ_WRITE.INT_CG.BITS#22.L.LAT.LATC.L2(22) [0]
	25	TP.TPBR.AD.RCV.ADS_REGS.SND_RCV_MODE.READ_WRITE.EXTERNAL_CG.BITS#25.L.LAT.LATC.L2(25) [0]
	26	TP.TPBR.AD.RCV.ADS_REGS.SND_RCV_MODE.READ_WRITE.EXTERNAL_CG.BITS#26.L.LAT.LATC.L2(26) [0]
	27	TP.TPBR.AD.RCV.ADS_REGS.SND_RCV_MODE.READ_WRITE.EXTERNAL_CG.BITS#27.L.LAT.LATC.L2(27) [0]
	28	TP.TPBR.AD.RCV.ADS_REGS.SND_RCV_MODE.READ_WRITE.EXTERNAL_CG.BITS#28.L.LAT.LATC.L2(28) [0]
	29	TP.TPBR.AD.RCV.ADS_REGS.SND_RCV_MODE.READ_WRITE.EXTERNAL_CG.BITS#29.L.LAT.LATC.L2(29) [0]
	30	TP.TPBR.AD.RCV.ADS_REGS.SND_RCV_MODE.READ_WRITE.EXTERNAL_CG.BITS#30.L.LAT.LATC.L2(30) [0]
	31	TP.TPBR.AD.RCV.ADS_REGS.SND_RCV_MODE.READ_WRITE.EXTERNAL_CG.BITS#31.L.LAT.LATC.L2(31) [0]
Bit(s)	SCOM			Dial: Description
0	RW			ENABLE_TRC_GLB_TRIG0: Enable broadcast of Trace Global Trigger 0
1	RW			ENABLE_TRC_GLB_TRIG1: Enable broadcast of Trace Global Trigger 1
2	RW			ENABLE_GLB_PULSE_MODE: On rising edge, send a Trace Global Trigger toggle cmd.
3	RW			SINGLE_OUTSTANDING_CMD: Wait for the clean cresp on every command befor the next can be posted. This can cause big delays if a command gets retried for a long time. DO NOT use TOGETHER with ENABLE_RECEIVE_OWN_TOD to prevent DEADLOCK. This is because the receive part depends on xscom-result-pmisc going out, befor xcsm accepts the next TOD command. The deadlock would be tod retrying for ever and xscom fsm can not finish sending the result pmisc.
4:7	RW			PROG_REQ_DELAY: Program amount of delay between Fabric address requests Matchs 4 MSB of 12 bit counter, allows delay from 0 cycles to 3840 cycles in steps of 256 cycles. Defaulted to no delay (0000) in design.
8	RW			DISABLE_ERR_CMD: Block error commands from being broadcast (malf rising edge only)
9	RW			DISABLE_HTM_CMD: Block htm commands from being broadcast
10	RW			DISABLE_TRACE_CMD: Block trace commands from being broadcast
11	RW			DISABLE_TOD_CMD: Block freqchng commands from being broadcast
12	RW			DISABLE_XSCOM_CMD: Block XSCOM commands from being broadcast
13	RW			ENABLE_CLR_ERR_CMD: Enable sending of err reset when a malf goes away EXPERIMENTAL - DO NOT USE (sequence odering can not be guaranteed)
14	RW			OVERRIDE_PBINIT_ERR_CMD: Allow error commands to being broadcast on quiesced PB
15	RW			OVERRIDE_PBINIT_HTM_CMD: Allow htm commands to being broadcast on quiesced PB
16	RW			OVERRIDE_PBINIT_TRACE_CMD: Allow trace commands to being broadcast on quiesced PB
17	RW			OVERRIDE_PBINIT_TOD_CMD: Allow freqchng commands to being broadcast on quiesced PB
18	RW			OVERRIDE_PBINIT_XSCOM_CMD: Allow XSCOM commands to being broadcast on quiesced PB
19	RW			DISABLE_CHECKSTOP: Disable forwarding checkstop to stop PowerBus
20	WOX			MANUAL_SET_PB_STOP: Manual set and overwrite state of stop the Power Bus Signal (requires disabling forwarding first)
21	WOX			MANUAL_CLR_PB_STOP: Manual clr and overwrite state of stop the Power Bus Signal (requires disabling forwarding first)
22	ROX			PB_STOP: state of the Power Bus pb_stop Signal
23:24	RO			constant=0b00
25	WOX			MANUAL_PB_SWITCH_ABCD: force a local (not broadcasted) PowerBus AB or CD Register switch
26:27	RW			ENABLE_RECEIVE_OWN_TRIGGER: enables receiving debug trigger pmisc from same adu (with same nodeid,chipid)
28	RW			ENABLE_RECEIVE_OWN_TOD: enables receiving tod pmisc from same adu (with same nodeid,chipid) DO NOT use TOGETHER with SINGLE_OUTSTANDING_CMD to prevent DEADLOCK (see there for reason why)
29	WOX			RESET_TOD_STATE: reset state machine of incomplete tod pmisc receive
30	RW			ENABLE_PB_SWITCH_AB: enable generation of a PowerBus AB Register Switch event pulse
31	RW			ENABLE_PB_SWITCH_CD: enable generation of a PowerBus CD Register Switch event pulse

pMisc Receive Malfunction Alert Register (first)
Addr:	0000000000090022 (SCOM)
Name:	TP.TPBR.AD.RCV_ERRLOG0_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.AD.RCV.ADS_REGS.ERRLOG0_REG.READ_WRITE.INT_CG.BITS#0.L.LAT.LATC.L2(0) [0]
	1	TP.TPBR.AD.RCV.ADS_REGS.ERRLOG0_REG.READ_WRITE.INT_CG.BITS#1.L.LAT.LATC.L2(1) [0]
	2	TP.TPBR.AD.RCV.ADS_REGS.ERRLOG0_REG.READ_WRITE.INT_CG.BITS#2.L.LAT.LATC.L2(2) [0]
	3	TP.TPBR.AD.RCV.ADS_REGS.ERRLOG0_REG.READ_WRITE.INT_CG.BITS#3.L.LAT.LATC.L2(3) [0]
	4	TP.TPBR.AD.RCV.ADS_REGS.ERRLOG0_REG.READ_WRITE.INT_CG.BITS#4.L.LAT.LATC.L2(4) [0]
	5	TP.TPBR.AD.RCV.ADS_REGS.ERRLOG0_REG.READ_WRITE.INT_CG.BITS#5.L.LAT.LATC.L2(5) [0]
	6	TP.TPBR.AD.RCV.ADS_REGS.ERRLOG0_REG.READ_WRITE.INT_CG.BITS#6.L.LAT.LATC.L2(6) [0]
	7	TP.TPBR.AD.RCV.ADS_REGS.ERRLOG0_REG.READ_WRITE.INT_CG.BITS#7.L.LAT.LATC.L2(7) [0]
	8	TP.TPBR.AD.RCV.ADS_REGS.ERRLOG0_REG.READ_WRITE.INT_CG.BITS#8.L.LAT.LATC.L2(8) [0]
	9	TP.TPBR.AD.RCV.ADS_REGS.ERRLOG0_REG.READ_WRITE.INT_CG.BITS#9.L.LAT.LATC.L2(9) [0]
	10	TP.TPBR.AD.RCV.ADS_REGS.ERRLOG0_REG.READ_WRITE.INT_CG.BITS#10.L.LAT.LATC.L2(10) [0]
	11	TP.TPBR.AD.RCV.ADS_REGS.ERRLOG0_REG.READ_WRITE.INT_CG.BITS#11.L.LAT.LATC.L2(11) [0]
	12	TP.TPBR.AD.RCV.ADS_REGS.ERRLOG0_REG.READ_WRITE.INT_CG.BITS#12.L.LAT.LATC.L2(12) [0]
	13	TP.TPBR.AD.RCV.ADS_REGS.ERRLOG0_REG.READ_WRITE.INT_CG.BITS#13.L.LAT.LATC.L2(13) [0]
	14	TP.TPBR.AD.RCV.ADS_REGS.ERRLOG0_REG.READ_WRITE.INT_CG.BITS#14.L.LAT.LATC.L2(14) [0]
	15	TP.TPBR.AD.RCV.ADS_REGS.ERRLOG0_REG.READ_WRITE.INT_CG.BITS#15.L.LAT.LATC.L2(15) [0]
Bit(s)	SCOM			Dial: Description
0	RW_WAND			malf_err_from_topology_id_00
1	RW_WAND			malf_err_from_topology_id_01
2	RW_WAND			malf_err_from_topology_id_02
3	RW_WAND			malf_err_from_topology_id_03
4	RW_WAND			malf_err_from_topology_id_04
5	RW_WAND			malf_err_from_topology_id_05
6	RW_WAND			malf_err_from_topology_id_06
7	RW_WAND			malf_err_from_topology_id_07
8	RW_WAND			malf_err_from_topology_id_08
9	RW_WAND			malf_err_from_topology_id_09
10	RW_WAND			malf_err_from_topology_id_10
11	RW_WAND			malf_err_from_topology_id_11
12	RW_WAND			malf_err_from_topology_id_12
13	RW_WAND			malf_err_from_topology_id_13
14	RW_WAND			malf_err_from_topology_id_14
15	RW_WAND			malf_err_from_topology_id_15

TOD pMisc Data Send Register
Addr:	0000000000090028 (SCOM)
Name:	TP.TPBR.AD.TOD_DATA_SND_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#0.L.LAT.LATC.L2(0) [0]
	1	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#1.L.LAT.LATC.L2(1) [0]
	2	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#2.L.LAT.LATC.L2(2) [0]
	3	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#3.L.LAT.LATC.L2(3) [0]
	4	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#4.L.LAT.LATC.L2(4) [0]
	5	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#5.L.LAT.LATC.L2(5) [0]
	6	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#6.L.LAT.LATC.L2(6) [0]
	7	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#7.L.LAT.LATC.L2(7) [0]
	8	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#8.L.LAT.LATC.L2(8) [0]
	9	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#9.L.LAT.LATC.L2(9) [0]
	10	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#10.L.LAT.LATC.L2(10) [0]
	11	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#11.L.LAT.LATC.L2(11) [0]
	12	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#12.L.LAT.LATC.L2(12) [0]
	13	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#13.L.LAT.LATC.L2(13) [0]
	14	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#14.L.LAT.LATC.L2(14) [0]
	15	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#15.L.LAT.LATC.L2(15) [0]
	16	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#16.L.LAT.LATC.L2(16) [0]
	17	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#17.L.LAT.LATC.L2(17) [0]
	18	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#18.L.LAT.LATC.L2(18) [0]
	19	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#19.L.LAT.LATC.L2(19) [0]
	20	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#20.L.LAT.LATC.L2(20) [0]
	21	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#21.L.LAT.LATC.L2(21) [0]
	22	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#22.L.LAT.LATC.L2(22) [0]
	23	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#23.L.LAT.LATC.L2(23) [0]
	24	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#24.L.LAT.LATC.L2(24) [0]
	25	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#25.L.LAT.LATC.L2(25) [0]
	26	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#26.L.LAT.LATC.L2(26) [0]
	27	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#27.L.LAT.LATC.L2(27) [0]
	28	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#28.L.LAT.LATC.L2(28) [0]
	29	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#29.L.LAT.LATC.L2(29) [0]
	30	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#30.L.LAT.LATC.L2(30) [0]
	31	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#31.L.LAT.LATC.L2(31) [0]
	32	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#32.L.LAT.LATC.L2(32) [0]
	33	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#33.L.LAT.LATC.L2(33) [0]
	34	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#34.L.LAT.LATC.L2(34) [0]
	35	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#35.L.LAT.LATC.L2(35) [0]
	36	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#36.L.LAT.LATC.L2(36) [0]
	37	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#37.L.LAT.LATC.L2(37) [0]
	38	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#38.L.LAT.LATC.L2(38) [0]
	39	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#39.L.LAT.LATC.L2(39) [0]
	40	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#40.L.LAT.LATC.L2(40) [0]
	41	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#41.L.LAT.LATC.L2(41) [0]
	42	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#42.L.LAT.LATC.L2(42) [0]
	43	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#43.L.LAT.LATC.L2(43) [0]
	44	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#44.L.LAT.LATC.L2(44) [0]
	45	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#45.L.LAT.LATC.L2(45) [0]
	46	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#46.L.LAT.LATC.L2(46) [0]
	47	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#47.L.LAT.LATC.L2(47) [0]
	48	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#48.L.LAT.LATC.L2(48) [0]
	49	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#49.L.LAT.LATC.L2(49) [0]
	50	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#50.L.LAT.LATC.L2(50) [0]
	51	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#51.L.LAT.LATC.L2(51) [0]
	52	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#52.L.LAT.LATC.L2(52) [0]
	53	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#53.L.LAT.LATC.L2(53) [0]
	54	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#54.L.LAT.LATC.L2(54) [0]
	55	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#55.L.LAT.LATC.L2(55) [0]
	56	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#56.L.LAT.LATC.L2(56) [0]
	57	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#57.L.LAT.LATC.L2(57) [0]
	58	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#58.L.LAT.LATC.L2(58) [0]
	59	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#59.L.LAT.LATC.L2(59) [0]
	60	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#60.L.LAT.LATC.L2(60) [0]
	61	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#61.L.LAT.LATC.L2(61) [0]
	62	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#62.L.LAT.LATC.L2(62) [0]
63	TP.TPBR.AD.SND.ADS_REGS.TOD_DATA.READ_WRITE.INT_CG.BITS#63.L.LAT.LATC.L2(63) [0]
Bit(s)	SCOM			Dial: Description
0:63	RW			PCB_TOD_DATA_SND: TOD command value to be sent

TOD pMisc Data Receive Register
Addr:	0000000000090029 (SCOM)
Name:	TP.TPBR.AD.TOD_DATA_RCV_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#0.L.LAT.LATC.L2(0) [0]
	1	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#1.L.LAT.LATC.L2(1) [0]
	2	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#2.L.LAT.LATC.L2(2) [0]
	3	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#3.L.LAT.LATC.L2(3) [0]
	4	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#4.L.LAT.LATC.L2(4) [0]
	5	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#5.L.LAT.LATC.L2(5) [0]
	6	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#6.L.LAT.LATC.L2(6) [0]
	7	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#7.L.LAT.LATC.L2(7) [0]
	8	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#8.L.LAT.LATC.L2(8) [0]
	9	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#9.L.LAT.LATC.L2(9) [0]
	10	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#10.L.LAT.LATC.L2(10) [0]
	11	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#11.L.LAT.LATC.L2(11) [0]
	12	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#12.L.LAT.LATC.L2(12) [0]
	13	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#13.L.LAT.LATC.L2(13) [0]
	14	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#14.L.LAT.LATC.L2(14) [0]
	15	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#15.L.LAT.LATC.L2(15) [0]
	16	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#16.L.LAT.LATC.L2(16) [0]
	17	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#17.L.LAT.LATC.L2(17) [0]
	18	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#18.L.LAT.LATC.L2(18) [0]
	19	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#19.L.LAT.LATC.L2(19) [0]
	20	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#20.L.LAT.LATC.L2(20) [0]
	21	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#21.L.LAT.LATC.L2(21) [0]
	22	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#22.L.LAT.LATC.L2(22) [0]
	23	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#23.L.LAT.LATC.L2(23) [0]
	24	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#24.L.LAT.LATC.L2(24) [0]
	25	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#25.L.LAT.LATC.L2(25) [0]
	26	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#26.L.LAT.LATC.L2(26) [0]
	27	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#27.L.LAT.LATC.L2(27) [0]
	28	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#28.L.LAT.LATC.L2(28) [0]
	29	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#29.L.LAT.LATC.L2(29) [0]
	30	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#30.L.LAT.LATC.L2(30) [0]
	31	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_A.READ_WRITE.INT_CG.BITS#31.L.LAT.LATC.L2(31) [0]
	32	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#32.L.LAT.LATC.L2(32) [0]
	33	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#33.L.LAT.LATC.L2(33) [0]
	34	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#34.L.LAT.LATC.L2(34) [0]
	35	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#35.L.LAT.LATC.L2(35) [0]
	36	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#36.L.LAT.LATC.L2(36) [0]
	37	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#37.L.LAT.LATC.L2(37) [0]
	38	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#38.L.LAT.LATC.L2(38) [0]
	39	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#39.L.LAT.LATC.L2(39) [0]
	40	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#40.L.LAT.LATC.L2(40) [0]
	41	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#41.L.LAT.LATC.L2(41) [0]
	42	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#42.L.LAT.LATC.L2(42) [0]
	43	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#43.L.LAT.LATC.L2(43) [0]
	44	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#44.L.LAT.LATC.L2(44) [0]
	45	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#45.L.LAT.LATC.L2(45) [0]
	46	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#46.L.LAT.LATC.L2(46) [0]
	47	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#47.L.LAT.LATC.L2(47) [0]
	48	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#48.L.LAT.LATC.L2(48) [0]
	49	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#49.L.LAT.LATC.L2(49) [0]
	50	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#50.L.LAT.LATC.L2(50) [0]
	51	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#51.L.LAT.LATC.L2(51) [0]
	52	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#52.L.LAT.LATC.L2(52) [0]
	53	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#53.L.LAT.LATC.L2(53) [0]
	54	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#54.L.LAT.LATC.L2(54) [0]
	55	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#55.L.LAT.LATC.L2(55) [0]
	56	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#56.L.LAT.LATC.L2(56) [0]
	57	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#57.L.LAT.LATC.L2(57) [0]
	58	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#58.L.LAT.LATC.L2(58) [0]
	59	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#59.L.LAT.LATC.L2(59) [0]
	60	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#60.L.LAT.LATC.L2(60) [0]
	61	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#61.L.LAT.LATC.L2(61) [0]
	62	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#62.L.LAT.LATC.L2(62) [0]
63	TP.TPBR.AD.RCV.ADS_REGS.TOD_DATA_B.READ_WRITE.INT_CG.BITS#63.L.LAT.LATC.L2(63) [0]
Bit(s)	SCOM			Dial: Description
0:63	ROX			PCB_TOD_DATA_RCV: TOD command value received before forewarded to pib

TOD Command Receive PIB Address Register
Addr:	000000000009002A (SCOM)
Name:	TP.TPBR.AD.TOD_CMD_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	30	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#30.L.LAT.LATC.L2(30) [0]
	31	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#31.L.LAT.LATC.L2(31) [0]
	32	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#32.L.LAT.LATC.L2(32) [0]
	33	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#33.L.LAT.LATC.L2(33) [0]
	34	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#34.L.LAT.LATC.L2(34) [0]
	35	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#35.L.LAT.LATC.L2(35) [0]
	36	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#36.L.LAT.LATC.L2(36) [0]
	37	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#37.L.LAT.LATC.L2(37) [0]
	38	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#38.L.LAT.LATC.L2(38) [0]
	39	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#39.L.LAT.LATC.L2(39) [0]
	40	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#40.L.LAT.LATC.L2(40) [0]
	41	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#41.L.LAT.LATC.L2(41) [0]
	42	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#42.L.LAT.LATC.L2(42) [0]
	43	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#43.L.LAT.LATC.L2(43) [0]
	44	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#44.L.LAT.LATC.L2(44) [0]
	45	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#45.L.LAT.LATC.L2(45) [0]
	46	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#46.L.LAT.LATC.L2(46) [0]
	47	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#47.L.LAT.LATC.L2(47) [0]
	48	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#48.L.LAT.LATC.L2(48) [0]
	49	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#49.L.LAT.LATC.L2(49) [0]
	50	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#50.L.LAT.LATC.L2(50) [0]
	51	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#51.L.LAT.LATC.L2(51) [0]
	52	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#52.L.LAT.LATC.L2(52) [0]
	53	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#53.L.LAT.LATC.L2(53) [0]
	54	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#54.L.LAT.LATC.L2(54) [0]
	55	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#55.L.LAT.LATC.L2(55) [0]
	56	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#56.L.LAT.LATC.L2(56) [0]
	57	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#57.L.LAT.LATC.L2(57) [0]
	58	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#58.L.LAT.LATC.L2(58) [0]
	59	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#59.L.LAT.LATC.L2(59) [0]
	60	TP.TPBR.AD.RCV.ADS_REGS.TOD_CMD_REG.READ_WRITE.INT_CG.BITS#60.L.LAT.LATC.L2(60) [0]
Bit(s)	SCOM			Dial: Description
0:29	RO			constant=0b000000001000000000000000000000
30:60	RW			TOD_CMD_REG_ADR: The constant PIB Address of a TOD register to store received TOD cmd in: 0x00040029
61:63	RO			constant=0b000

PIB Slave Data Register (internal use only)
Addr:	0000000000090030 (SCOM)
Name:	TP.TPBR.AD.IO_DATA_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#0.L.LAT.LATC.L2(0) [0]
	1	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#1.L.LAT.LATC.L2(1) [0]
	2	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#2.L.LAT.LATC.L2(2) [0]
	3	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#3.L.LAT.LATC.L2(3) [0]
	4	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#4.L.LAT.LATC.L2(4) [0]
	5	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#5.L.LAT.LATC.L2(5) [0]
	6	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#6.L.LAT.LATC.L2(6) [0]
	7	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#7.L.LAT.LATC.L2(7) [0]
	8	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#8.L.LAT.LATC.L2(8) [0]
	9	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#9.L.LAT.LATC.L2(9) [0]
	10	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#10.L.LAT.LATC.L2(10) [0]
	11	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#11.L.LAT.LATC.L2(11) [0]
	12	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#12.L.LAT.LATC.L2(12) [0]
	13	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#13.L.LAT.LATC.L2(13) [0]
	14	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#14.L.LAT.LATC.L2(14) [0]
	15	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#15.L.LAT.LATC.L2(15) [0]
	16	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#16.L.LAT.LATC.L2(16) [0]
	17	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#17.L.LAT.LATC.L2(17) [0]
	18	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#18.L.LAT.LATC.L2(18) [0]
	19	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#19.L.LAT.LATC.L2(19) [0]
	20	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#20.L.LAT.LATC.L2(20) [0]
	21	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#21.L.LAT.LATC.L2(21) [0]
	22	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#22.L.LAT.LATC.L2(22) [0]
	23	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#23.L.LAT.LATC.L2(23) [0]
	24	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#24.L.LAT.LATC.L2(24) [0]
	25	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#25.L.LAT.LATC.L2(25) [0]
	26	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#26.L.LAT.LATC.L2(26) [0]
	27	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#27.L.LAT.LATC.L2(27) [0]
	28	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#28.L.LAT.LATC.L2(28) [0]
	29	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#29.L.LAT.LATC.L2(29) [0]
	30	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#30.L.LAT.LATC.L2(30) [0]
	31	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#31.L.LAT.LATC.L2(31) [0]
	32	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#32.L.LAT.LATC.L2(32) [0]
	33	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#33.L.LAT.LATC.L2(33) [0]
	34	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#34.L.LAT.LATC.L2(34) [0]
	35	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#35.L.LAT.LATC.L2(35) [0]
	36	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#36.L.LAT.LATC.L2(36) [0]
	37	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#37.L.LAT.LATC.L2(37) [0]
	38	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#38.L.LAT.LATC.L2(38) [0]
	39	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#39.L.LAT.LATC.L2(39) [0]
	40	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#40.L.LAT.LATC.L2(40) [0]
	41	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#41.L.LAT.LATC.L2(41) [0]
	42	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#42.L.LAT.LATC.L2(42) [0]
	43	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#43.L.LAT.LATC.L2(43) [0]
	44	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#44.L.LAT.LATC.L2(44) [0]
	45	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#45.L.LAT.LATC.L2(45) [0]
	46	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#46.L.LAT.LATC.L2(46) [0]
	47	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#47.L.LAT.LATC.L2(47) [0]
	48	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#48.L.LAT.LATC.L2(48) [0]
	49	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#49.L.LAT.LATC.L2(49) [0]
	50	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#50.L.LAT.LATC.L2(50) [0]
	51	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#51.L.LAT.LATC.L2(51) [0]
	52	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#52.L.LAT.LATC.L2(52) [0]
	53	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#53.L.LAT.LATC.L2(53) [0]
	54	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#54.L.LAT.LATC.L2(54) [0]
	55	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#55.L.LAT.LATC.L2(55) [0]
	56	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#56.L.LAT.LATC.L2(56) [0]
	57	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#57.L.LAT.LATC.L2(57) [0]
	58	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#58.L.LAT.LATC.L2(58) [0]
	59	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#59.L.LAT.LATC.L2(59) [0]
	60	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#60.L.LAT.LATC.L2(60) [0]
	61	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#61.L.LAT.LATC.L2(61) [0]
	62	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#62.L.LAT.LATC.L2(62) [0]
63	TP.TPBR.AD.PIB.PIB_IO_REG.READ_WRITE.INT_CG.BITS#63.L.LAT.LATC.L2(63) [0]
Bit(s)	SCOM			Dial: Description
0:63	ROX			PCB_IO_TMP_DATA: INTERNAL ONLY data to be transfered between ads and pib

Data for access to PIB from XSCOM
Addr:	0000000000090031 (SCOM)
Name:	TP.TPBR.AD.PIB_CMD_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#0.L.LAT.LATC.L2(0) [0]
	30	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#30.L.LAT.LATC.L2(30) [0]
	31	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#31.L.LAT.LATC.L2(31) [0]
	32	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#32.L.LAT.LATC.L2(32) [0]
	33	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#33.L.LAT.LATC.L2(33) [0]
	34	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#34.L.LAT.LATC.L2(34) [0]
	35	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#35.L.LAT.LATC.L2(35) [0]
	36	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#36.L.LAT.LATC.L2(36) [0]
	37	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#37.L.LAT.LATC.L2(37) [0]
	38	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#38.L.LAT.LATC.L2(38) [0]
	39	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#39.L.LAT.LATC.L2(39) [0]
	40	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#40.L.LAT.LATC.L2(40) [0]
	41	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#41.L.LAT.LATC.L2(41) [0]
	42	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#42.L.LAT.LATC.L2(42) [0]
	43	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#43.L.LAT.LATC.L2(43) [0]
	44	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#44.L.LAT.LATC.L2(44) [0]
	45	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#45.L.LAT.LATC.L2(45) [0]
	46	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#46.L.LAT.LATC.L2(46) [0]
	47	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#47.L.LAT.LATC.L2(47) [0]
	48	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#48.L.LAT.LATC.L2(48) [0]
	49	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#49.L.LAT.LATC.L2(49) [0]
	50	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#50.L.LAT.LATC.L2(50) [0]
	51	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#51.L.LAT.LATC.L2(51) [0]
	52	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#52.L.LAT.LATC.L2(52) [0]
	53	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#53.L.LAT.LATC.L2(53) [0]
	54	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#54.L.LAT.LATC.L2(54) [0]
	55	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#55.L.LAT.LATC.L2(55) [0]
	56	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#56.L.LAT.LATC.L2(56) [0]
	57	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#57.L.LAT.LATC.L2(57) [0]
	58	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#58.L.LAT.LATC.L2(58) [0]
	59	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#59.L.LAT.LATC.L2(59) [0]
	60	TP.TPBR.AD.PIB.PIB_CMD_REG.READ_WRITE.INT_CG.BITS#60.L.LAT.LATC.L2(60) [0]
Bit(s)	SCOM			Dial: Description
0	ROX			PIB_CMD_REG_RNW: INTERNAL REGISTER, setting this bit cause a PIB read and resulting data stored in PIB_DATA_REG
1:29	RO			constant=0b00000000000000000000000000000
30:60	ROX			PIB_CMD_REG_ADR: INTERNAL REGISTER, pib address
61:63	RO			constant=0b000

Data for access to PIB from Alt-Displ. Writing this register with pib_read_not_write=0 causes a PIB write
Addr:	0000000000090032 (SCOM)
Name:	TP.TPBR.AD.PIB_DATA_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#0.L.LAT.LATC.L2(0) [0]
	1	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#1.L.LAT.LATC.L2(1) [0]
	2	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#2.L.LAT.LATC.L2(2) [0]
	3	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#3.L.LAT.LATC.L2(3) [0]
	4	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#4.L.LAT.LATC.L2(4) [0]
	5	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#5.L.LAT.LATC.L2(5) [0]
	6	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#6.L.LAT.LATC.L2(6) [0]
	7	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#7.L.LAT.LATC.L2(7) [0]
	8	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#8.L.LAT.LATC.L2(8) [0]
	9	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#9.L.LAT.LATC.L2(9) [0]
	10	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#10.L.LAT.LATC.L2(10) [0]
	11	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#11.L.LAT.LATC.L2(11) [0]
	12	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#12.L.LAT.LATC.L2(12) [0]
	13	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#13.L.LAT.LATC.L2(13) [0]
	14	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#14.L.LAT.LATC.L2(14) [0]
	15	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#15.L.LAT.LATC.L2(15) [0]
	16	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#16.L.LAT.LATC.L2(16) [0]
	17	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#17.L.LAT.LATC.L2(17) [0]
	18	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#18.L.LAT.LATC.L2(18) [0]
	19	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#19.L.LAT.LATC.L2(19) [0]
	20	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#20.L.LAT.LATC.L2(20) [0]
	21	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#21.L.LAT.LATC.L2(21) [0]
	22	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#22.L.LAT.LATC.L2(22) [0]
	23	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#23.L.LAT.LATC.L2(23) [0]
	24	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#24.L.LAT.LATC.L2(24) [0]
	25	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#25.L.LAT.LATC.L2(25) [0]
	26	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#26.L.LAT.LATC.L2(26) [0]
	27	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#27.L.LAT.LATC.L2(27) [0]
	28	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#28.L.LAT.LATC.L2(28) [0]
	29	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#29.L.LAT.LATC.L2(29) [0]
	30	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#30.L.LAT.LATC.L2(30) [0]
	31	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#31.L.LAT.LATC.L2(31) [0]
	32	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#32.L.LAT.LATC.L2(32) [0]
	33	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#33.L.LAT.LATC.L2(33) [0]
	34	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#34.L.LAT.LATC.L2(34) [0]
	35	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#35.L.LAT.LATC.L2(35) [0]
	36	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#36.L.LAT.LATC.L2(36) [0]
	37	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#37.L.LAT.LATC.L2(37) [0]
	38	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#38.L.LAT.LATC.L2(38) [0]
	39	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#39.L.LAT.LATC.L2(39) [0]
	40	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#40.L.LAT.LATC.L2(40) [0]
	41	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#41.L.LAT.LATC.L2(41) [0]
	42	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#42.L.LAT.LATC.L2(42) [0]
	43	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#43.L.LAT.LATC.L2(43) [0]
	44	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#44.L.LAT.LATC.L2(44) [0]
	45	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#45.L.LAT.LATC.L2(45) [0]
	46	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#46.L.LAT.LATC.L2(46) [0]
	47	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#47.L.LAT.LATC.L2(47) [0]
	48	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#48.L.LAT.LATC.L2(48) [0]
	49	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#49.L.LAT.LATC.L2(49) [0]
	50	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#50.L.LAT.LATC.L2(50) [0]
	51	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#51.L.LAT.LATC.L2(51) [0]
	52	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#52.L.LAT.LATC.L2(52) [0]
	53	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#53.L.LAT.LATC.L2(53) [0]
	54	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#54.L.LAT.LATC.L2(54) [0]
	55	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#55.L.LAT.LATC.L2(55) [0]
	56	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#56.L.LAT.LATC.L2(56) [0]
	57	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#57.L.LAT.LATC.L2(57) [0]
	58	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#58.L.LAT.LATC.L2(58) [0]
	59	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#59.L.LAT.LATC.L2(59) [0]
	60	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#60.L.LAT.LATC.L2(60) [0]
	61	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#61.L.LAT.LATC.L2(61) [0]
	62	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#62.L.LAT.LATC.L2(62) [0]
63	TP.TPBR.AD.PIB.PIB_DATA_REG.READ_WRITE.INT_CG.BITS#63.L.LAT.LATC.L2(63) [0]
Bit(s)	SCOM			Dial: Description
0:63	ROX			PIB_DATA: Data from and to PIB

Reset pulse for PIB
Addr:	0000000000090033 (SCOM)
Name:	TP.TPBR.AD.PIB_RESET_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.AD.PIB.PIB_RESET_REG.READ_WRITE.EXTERNAL_CG.BITS#0.L.LAT.LATC.L2(0) [0]
	1	TP.TPBR.AD.PIB.PIB_RESET_REG.READ_WRITE.EXTERNAL_CG.BITS#1.L.LAT.LATC.L2(1) [0]
	2	TP.TPBR.AD.PIB.PIB_RESET_REG.READ_WRITE.EXTERNAL_CG.BITS#2.L.LAT.LATC.L2(2) [0]
Bit(s)	SCOM			Dial: Description
0	WOX			PIB_RESET: writing this to 1 cause a PIB reset - this should not be used as it is not connected to PIB Arbiter in P10
1	ROX			PIB_RESET_STATE: PIB reset state
2	RWX_WAND			PIB_RESET_ABORTED_CMD: a former PIB reset aborted a command of this master

LPC Base Address Register
Addr:	0000000000090040 (SCOM)
Name:	TP.TPBR.AD.LPC_BASE_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	8	TP.TPBR.AD.PBADR.LPC_BASE_REG.READ_WRITE.INT_CG.BITS#8.L.LAT.LATC.L2(8) [0]
	9	TP.TPBR.AD.PBADR.LPC_BASE_REG.READ_WRITE.INT_CG.BITS#9.L.LAT.LATC.L2(9) [0]
	10	TP.TPBR.AD.PBADR.LPC_BASE_REG.READ_WRITE.INT_CG.BITS#10.L.LAT.LATC.L2(10) [0]
	11	TP.TPBR.AD.PBADR.LPC_BASE_REG.READ_WRITE.INT_CG.BITS#11.L.LAT.LATC.L2(11) [0]
	12	TP.TPBR.AD.PBADR.LPC_BASE_REG.READ_WRITE.INT_CG.BITS#12.L.LAT.LATC.L2(12) [0]
	13	TP.TPBR.AD.PBADR.LPC_BASE_REG.READ_WRITE.INT_CG.BITS#13.L.LAT.LATC.L2(13) [0]
	14	TP.TPBR.AD.PBADR.LPC_BASE_REG.READ_WRITE.INT_CG.BITS#14.L.LAT.LATC.L2(14) [0]
	15	TP.TPBR.AD.PBADR.LPC_BASE_REG.READ_WRITE.INT_CG.BITS#15.L.LAT.LATC.L2(15) [0]
	16	TP.TPBR.AD.PBADR.LPC_BASE_REG.READ_WRITE.INT_CG.BITS#16.L.LAT.LATC.L2(16) [0]
	17	TP.TPBR.AD.PBADR.LPC_BASE_REG.READ_WRITE.INT_CG.BITS#17.L.LAT.LATC.L2(17) [0]
	18	TP.TPBR.AD.PBADR.LPC_BASE_REG.READ_WRITE.INT_CG.BITS#18.L.LAT.LATC.L2(18) [0]
	19	TP.TPBR.AD.PBADR.LPC_BASE_REG.READ_WRITE.INT_CG.BITS#19.L.LAT.LATC.L2(19) [0]
	20	TP.TPBR.AD.PBADR.LPC_BASE_REG.READ_WRITE.INT_CG.BITS#20.L.LAT.LATC.L2(20) [0]
	21	TP.TPBR.AD.PBADR.LPC_BASE_REG.READ_WRITE.INT_CG.BITS#21.L.LAT.LATC.L2(21) [0]
	22	TP.TPBR.AD.PBADR.LPC_BASE_REG.READ_WRITE.INT_CG.BITS#22.L.LAT.LATC.L2(22) [0]
	23	TP.TPBR.AD.PBADR.LPC_BASE_REG.READ_WRITE.INT_CG.BITS#23.L.LAT.LATC.L2(23) [0]
	24	TP.TPBR.AD.PBADR.LPC_BASE_REG.READ_WRITE.INT_CG.BITS#24.L.LAT.LATC.L2(24) [0]
	25	TP.TPBR.AD.PBADR.LPC_BASE_REG.READ_WRITE.INT_CG.BITS#25.L.LAT.LATC.L2(25) [0]
	26	TP.TPBR.AD.PBADR.LPC_BASE_REG.READ_WRITE.INT_CG.BITS#26.L.LAT.LATC.L2(26) [0]
	27	TP.TPBR.AD.PBADR.LPC_BASE_REG.READ_WRITE.INT_CG.BITS#27.L.LAT.LATC.L2(27) [0]
	28	TP.TPBR.AD.PBADR.LPC_BASE_REG.READ_WRITE.INT_CG.BITS#28.L.LAT.LATC.L2(28) [0]
	29	TP.TPBR.AD.PBADR.LPC_BASE_REG.READ_WRITE.INT_CG.BITS#29.L.LAT.LATC.L2(29) [0]
	30	TP.TPBR.AD.PBADR.LPC_BASE_REG.READ_WRITE.INT_CG.BITS#30.L.LAT.LATC.L2(30) [0]
	31	TP.TPBR.AD.PBADR.LPC_BASE_REG.READ_WRITE.INT_CG.BITS#31.L.LAT.LATC.L2(31) [0]
	63	TP.TPBR.AD.PBADR.LPC_BASE_REG.READ_WRITE.INT_CG.BITS#63.L.LAT.LATC.L2(63) [0]
Bit(s)	SCOM			Dial: Description
0:7	RO			constant=0b00000000
8:31	RW			LPC_BASE: Base Address for LPC unit
32:62	RO			constant=0b0000000000000000000000000000000
63	RW			LPC_DISABLE: Used to disable the LPC

Data for access to LPC from XSCOM
Addr:	0000000000090041 (SCOM)
Name:	TP.TPBR.AD.LPC_CMD_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#0.L.LAT.LATC.L2(0) [0]
	5	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#5.L.LAT.LATC.L2(5) [0]
	6	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#6.L.LAT.LATC.L2(6) [0]
	7	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#7.L.LAT.LATC.L2(7) [0]
	8	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#8.L.LAT.LATC.L2(8) [0]
	9	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#9.L.LAT.LATC.L2(9) [0]
	10	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#10.L.LAT.LATC.L2(10) [0]
	11	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#11.L.LAT.LATC.L2(11) [0]
	32	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#32.L.LAT.LATC.L2(32) [0]
	33	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#33.L.LAT.LATC.L2(33) [0]
	34	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#34.L.LAT.LATC.L2(34) [0]
	35	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#35.L.LAT.LATC.L2(35) [0]
	36	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#36.L.LAT.LATC.L2(36) [0]
	37	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#37.L.LAT.LATC.L2(37) [0]
	38	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#38.L.LAT.LATC.L2(38) [0]
	39	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#39.L.LAT.LATC.L2(39) [0]
	40	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#40.L.LAT.LATC.L2(40) [0]
	41	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#41.L.LAT.LATC.L2(41) [0]
	42	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#42.L.LAT.LATC.L2(42) [0]
	43	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#43.L.LAT.LATC.L2(43) [0]
	44	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#44.L.LAT.LATC.L2(44) [0]
	45	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#45.L.LAT.LATC.L2(45) [0]
	46	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#46.L.LAT.LATC.L2(46) [0]
	47	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#47.L.LAT.LATC.L2(47) [0]
	48	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#48.L.LAT.LATC.L2(48) [0]
	49	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#49.L.LAT.LATC.L2(49) [0]
	50	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#50.L.LAT.LATC.L2(50) [0]
	51	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#51.L.LAT.LATC.L2(51) [0]
	52	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#52.L.LAT.LATC.L2(52) [0]
	53	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#53.L.LAT.LATC.L2(53) [0]
	54	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#54.L.LAT.LATC.L2(54) [0]
	55	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#55.L.LAT.LATC.L2(55) [0]
	56	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#56.L.LAT.LATC.L2(56) [0]
	57	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#57.L.LAT.LATC.L2(57) [0]
	58	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#58.L.LAT.LATC.L2(58) [0]
	59	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#59.L.LAT.LATC.L2(59) [0]
	60	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#60.L.LAT.LATC.L2(60) [0]
	61	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#61.L.LAT.LATC.L2(61) [0]
	62	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#62.L.LAT.LATC.L2(62) [0]
	63	TP.TPBR.AD.LPC.LPC_CMD_REG.READ_WRITE.INT_CG.BITS#63.L.LAT.LATC.L2(63) [0]
Bit(s)	SCOM			Dial: Description
0	RW			LPC_CMD_REG_RNW: INTERNAL REGISTER, setting this bit cause a LPC read and resulting data stored in LPC_DATA_REG
1:4	RO			constant=0b0000
5:11	RWX			LPC_CMD_REG_SIZE: INTERNAL REGISTER, size of current xscom/lpc access
12:31	RO			constant=0b00000000000000000000
32:63	RWX			LPC_CMD_REG_ADR: INTERNAL REGISTER, lpc address, Please Note: This field is updated after execution

Data for access to LPC from Alt-Displ. Writing this register with lpc_read_not_write=0 causes a LPC write
Addr:	0000000000090042 (SCOM)
Name:	TP.TPBR.AD.LPC_DATA_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#0.L.LAT.LATC.L2(0) [0]
	1	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#1.L.LAT.LATC.L2(1) [0]
	2	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#2.L.LAT.LATC.L2(2) [0]
	3	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#3.L.LAT.LATC.L2(3) [0]
	4	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#4.L.LAT.LATC.L2(4) [0]
	5	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#5.L.LAT.LATC.L2(5) [0]
	6	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#6.L.LAT.LATC.L2(6) [0]
	7	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#7.L.LAT.LATC.L2(7) [0]
	8	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#8.L.LAT.LATC.L2(8) [0]
	9	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#9.L.LAT.LATC.L2(9) [0]
	10	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#10.L.LAT.LATC.L2(10) [0]
	11	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#11.L.LAT.LATC.L2(11) [0]
	12	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#12.L.LAT.LATC.L2(12) [0]
	13	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#13.L.LAT.LATC.L2(13) [0]
	14	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#14.L.LAT.LATC.L2(14) [0]
	15	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#15.L.LAT.LATC.L2(15) [0]
	16	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#16.L.LAT.LATC.L2(16) [0]
	17	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#17.L.LAT.LATC.L2(17) [0]
	18	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#18.L.LAT.LATC.L2(18) [0]
	19	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#19.L.LAT.LATC.L2(19) [0]
	20	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#20.L.LAT.LATC.L2(20) [0]
	21	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#21.L.LAT.LATC.L2(21) [0]
	22	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#22.L.LAT.LATC.L2(22) [0]
	23	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#23.L.LAT.LATC.L2(23) [0]
	24	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#24.L.LAT.LATC.L2(24) [0]
	25	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#25.L.LAT.LATC.L2(25) [0]
	26	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#26.L.LAT.LATC.L2(26) [0]
	27	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#27.L.LAT.LATC.L2(27) [0]
	28	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#28.L.LAT.LATC.L2(28) [0]
	29	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#29.L.LAT.LATC.L2(29) [0]
	30	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#30.L.LAT.LATC.L2(30) [0]
	31	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#31.L.LAT.LATC.L2(31) [0]
	32	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#32.L.LAT.LATC.L2(32) [0]
	33	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#33.L.LAT.LATC.L2(33) [0]
	34	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#34.L.LAT.LATC.L2(34) [0]
	35	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#35.L.LAT.LATC.L2(35) [0]
	36	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#36.L.LAT.LATC.L2(36) [0]
	37	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#37.L.LAT.LATC.L2(37) [0]
	38	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#38.L.LAT.LATC.L2(38) [0]
	39	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#39.L.LAT.LATC.L2(39) [0]
	40	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#40.L.LAT.LATC.L2(40) [0]
	41	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#41.L.LAT.LATC.L2(41) [0]
	42	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#42.L.LAT.LATC.L2(42) [0]
	43	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#43.L.LAT.LATC.L2(43) [0]
	44	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#44.L.LAT.LATC.L2(44) [0]
	45	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#45.L.LAT.LATC.L2(45) [0]
	46	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#46.L.LAT.LATC.L2(46) [0]
	47	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#47.L.LAT.LATC.L2(47) [0]
	48	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#48.L.LAT.LATC.L2(48) [0]
	49	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#49.L.LAT.LATC.L2(49) [0]
	50	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#50.L.LAT.LATC.L2(50) [0]
	51	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#51.L.LAT.LATC.L2(51) [0]
	52	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#52.L.LAT.LATC.L2(52) [0]
	53	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#53.L.LAT.LATC.L2(53) [0]
	54	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#54.L.LAT.LATC.L2(54) [0]
	55	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#55.L.LAT.LATC.L2(55) [0]
	56	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#56.L.LAT.LATC.L2(56) [0]
	57	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#57.L.LAT.LATC.L2(57) [0]
	58	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#58.L.LAT.LATC.L2(58) [0]
	59	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#59.L.LAT.LATC.L2(59) [0]
	60	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#60.L.LAT.LATC.L2(60) [0]
	61	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#61.L.LAT.LATC.L2(61) [0]
	62	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#62.L.LAT.LATC.L2(62) [0]
63	TP.TPBR.AD.LPC.LPC_DAT_REG.READ_WRITE.INT_CG.BITS#63.L.LAT.LATC.L2(63) [0]
Bit(s)	SCOM			Dial: Description
0:63	RWX			LPC_DATA: Data from and to LPC

Status/Debug register for lpc operation
Addr:	0000000000090043 (SCOM)
Name:	TP.TPBR.AD.LPC_STATUS_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.AD.LPC.LPC_STATUS_REG.READ_WRITE.INT_CG.BITS#0.L.LAT.LATC.L2(0) [0]
	10	TP.TPBR.AD.LPC.LPC_STATUS_REG.READ_WRITE.INT_CG.BITS#10.L.LAT.LATC.L2(10) [0]
	11	TP.TPBR.AD.LPC.LPC_STATUS_REG.READ_WRITE.INT_CG.BITS#11.L.LAT.LATC.L2(11) [0]
Bit(s)	SCOM			Dial: Description
0	ROX			LPC_DONE_STATUS: STAUTS OF LPC TRANSACTION
1:9	RO			constant=0b000000000
10	ROX			LPC_VALID_STATUS: STAUTS OF LPC HANDSHAKE- STATE OF LP_OPB_VALID
11	ROX			LPC_ACK_STATUS: STAUTS OF LPC HANDSHAKE- STATE OF LP_OPB_ACK
12:63	RO			constant=0b0000000000000000000000000000000000000000000000000000

Divider values for ADU PowerBus Hang
Addr:	0000000000090050 (SCOM)
Name:	TP.TPBR.AD.ADU_HANG_DIV_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.AD.PBADR.ADU_HANG_DIV_REG.READ_WRITE.INT_CG.BITS#0.L.LAT.LATC.L2(0) [0]
	1	TP.TPBR.AD.PBADR.ADU_HANG_DIV_REG.READ_WRITE.INT_CG.BITS#1.L.LAT.LATC.L2(1) [0]
	2	TP.TPBR.AD.PBADR.ADU_HANG_DIV_REG.READ_WRITE.INT_CG.BITS#2.L.LAT.LATC.L2(2) [0]
	3	TP.TPBR.AD.PBADR.ADU_HANG_DIV_REG.READ_WRITE.INT_CG.BITS#3.L.LAT.LATC.L2(3) [0]
	4	TP.TPBR.AD.PBADR.ADU_HANG_DIV_REG.READ_WRITE.INT_CG.BITS#4.L.LAT.LATC.L2(4) [0]
	5	TP.TPBR.AD.PBADR.ADU_HANG_DIV_REG.READ_WRITE.INT_CG.BITS#5.L.LAT.LATC.L2(5) [0]
	6	TP.TPBR.AD.PBADR.ADU_HANG_DIV_REG.READ_WRITE.INT_CG.BITS#6.L.LAT.LATC.L2(6) [0]
	7	TP.TPBR.AD.PBADR.ADU_HANG_DIV_REG.READ_WRITE.INT_CG.BITS#7.L.LAT.LATC.L2(7) [0]
	8	TP.TPBR.AD.PBADR.ADU_HANG_DIV_REG.READ_WRITE.INT_CG.BITS#8.L.LAT.LATC.L2(8) [0]
	9	TP.TPBR.AD.PBADR.ADU_HANG_DIV_REG.READ_WRITE.INT_CG.BITS#9.L.LAT.LATC.L2(9) [0]
Bit(s)	SCOM			Dial: Description
0:4	RW			ADU_DATA_HANG_DIV: Divider value for ADU PowerBus Data Hang
5:9	RW			ADU_OPER_HANG_DIV: Divider value for ADU PowerBus Operational Hang
10:63	RO			constant=0b000000000000000000000000000000000000000000000000000000

Topology ID Translation Table 0
Addr:	0000000000090051 (SCOM)
Name:	TP.TPBR.AD.TOPOID_XLAT_TBL0
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#0.L.LAT.LATC.L2(0) [0]
	1	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#1.L.LAT.LATC.L2(1) [0]
	2	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#2.L.LAT.LATC.L2(2) [0]
	3	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#3.L.LAT.LATC.L2(3) [0]
	4	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#4.L.LAT.LATC.L2(4) [0]
	5	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#5.L.LAT.LATC.L2(5) [0]
	6	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#6.L.LAT.LATC.L2(6) [0]
	7	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#7.L.LAT.LATC.L2(7) [0]
	8	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#8.L.LAT.LATC.L2(8) [0]
	9	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#9.L.LAT.LATC.L2(9) [0]
	10	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#10.L.LAT.LATC.L2(10) [0]
	11	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#11.L.LAT.LATC.L2(11) [0]
	12	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#12.L.LAT.LATC.L2(12) [0]
	13	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#13.L.LAT.LATC.L2(13) [0]
	14	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#14.L.LAT.LATC.L2(14) [0]
	15	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#15.L.LAT.LATC.L2(15) [0]
	16	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#16.L.LAT.LATC.L2(16) [0]
	17	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#17.L.LAT.LATC.L2(17) [0]
	18	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#18.L.LAT.LATC.L2(18) [0]
	19	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#19.L.LAT.LATC.L2(19) [0]
	20	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#20.L.LAT.LATC.L2(20) [0]
	21	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#21.L.LAT.LATC.L2(21) [0]
	22	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#22.L.LAT.LATC.L2(22) [0]
	23	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#23.L.LAT.LATC.L2(23) [0]
	24	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#24.L.LAT.LATC.L2(24) [0]
	25	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#25.L.LAT.LATC.L2(25) [0]
	26	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#26.L.LAT.LATC.L2(26) [0]
	27	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#27.L.LAT.LATC.L2(27) [0]
	28	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#28.L.LAT.LATC.L2(28) [0]
	29	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#29.L.LAT.LATC.L2(29) [0]
	30	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#30.L.LAT.LATC.L2(30) [0]
	31	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#31.L.LAT.LATC.L2(31) [0]
	32	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#32.L.LAT.LATC.L2(32) [0]
	33	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#33.L.LAT.LATC.L2(33) [0]
	34	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#34.L.LAT.LATC.L2(34) [0]
	35	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#35.L.LAT.LATC.L2(35) [0]
	36	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#36.L.LAT.LATC.L2(36) [0]
	37	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#37.L.LAT.LATC.L2(37) [0]
	38	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#38.L.LAT.LATC.L2(38) [0]
	39	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL0.READ_WRITE.INT_CG.BITS#39.L.LAT.LATC.L2(39) [0]
Bit(s)	SCOM			Dial: Description
0	RW			TOPOID_0_VALID: valid bit for topology id 0
1	RW			TOPOID_1_VALID: valid bit for topology id 1
2	RW			TOPOID_2_VALID: valid bit for topology id 2
3	RW			TOPOID_3_VALID: valid bit for topology id 3
4	RW			TOPOID_4_VALID: valid bit for topology id 4
5	RW			TOPOID_5_VALID: valid bit for topology id 5
6	RW			TOPOID_6_VALID: valid bit for topology id 6
7	RW			TOPOID_7_VALID: valid bit for topology id 7
8:11	RW			TOPOID_0: Topology id 0
12:15	RW			TOPOID_1: Topology id 1
16:19	RW			TOPOID_2: Topology id 2
20:23	RW			TOPOID_3: Topology id 3
24:27	RW			TOPOID_4: Topology id 4
28:31	RW			TOPOID_5: Topology id 5
32:35	RW			TOPOID_6: Topology id 6
36:39	RW			TOPOID_7: Topology id 7
40:63	RO			constant=0b000000000000000000000000

Topology ID Translation Table 1
Addr:	0000000000090052 (SCOM)
Name:	TP.TPBR.AD.TOPOID_XLAT_TBL1
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#0.L.LAT.LATC.L2(0) [0]
	1	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#1.L.LAT.LATC.L2(1) [0]
	2	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#2.L.LAT.LATC.L2(2) [0]
	3	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#3.L.LAT.LATC.L2(3) [0]
	4	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#4.L.LAT.LATC.L2(4) [0]
	5	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#5.L.LAT.LATC.L2(5) [0]
	6	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#6.L.LAT.LATC.L2(6) [0]
	7	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#7.L.LAT.LATC.L2(7) [0]
	8	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#8.L.LAT.LATC.L2(8) [0]
	9	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#9.L.LAT.LATC.L2(9) [0]
	10	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#10.L.LAT.LATC.L2(10) [0]
	11	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#11.L.LAT.LATC.L2(11) [0]
	12	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#12.L.LAT.LATC.L2(12) [0]
	13	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#13.L.LAT.LATC.L2(13) [0]
	14	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#14.L.LAT.LATC.L2(14) [0]
	15	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#15.L.LAT.LATC.L2(15) [0]
	16	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#16.L.LAT.LATC.L2(16) [0]
	17	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#17.L.LAT.LATC.L2(17) [0]
	18	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#18.L.LAT.LATC.L2(18) [0]
	19	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#19.L.LAT.LATC.L2(19) [0]
	20	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#20.L.LAT.LATC.L2(20) [0]
	21	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#21.L.LAT.LATC.L2(21) [0]
	22	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#22.L.LAT.LATC.L2(22) [0]
	23	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#23.L.LAT.LATC.L2(23) [0]
	24	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#24.L.LAT.LATC.L2(24) [0]
	25	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#25.L.LAT.LATC.L2(25) [0]
	26	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#26.L.LAT.LATC.L2(26) [0]
	27	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#27.L.LAT.LATC.L2(27) [0]
	28	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#28.L.LAT.LATC.L2(28) [0]
	29	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#29.L.LAT.LATC.L2(29) [0]
	30	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#30.L.LAT.LATC.L2(30) [0]
	31	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#31.L.LAT.LATC.L2(31) [0]
	32	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#32.L.LAT.LATC.L2(32) [0]
	33	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#33.L.LAT.LATC.L2(33) [0]
	34	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#34.L.LAT.LATC.L2(34) [0]
	35	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#35.L.LAT.LATC.L2(35) [0]
	36	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#36.L.LAT.LATC.L2(36) [0]
	37	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#37.L.LAT.LATC.L2(37) [0]
	38	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#38.L.LAT.LATC.L2(38) [0]
	39	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL1.READ_WRITE.INT_CG.BITS#39.L.LAT.LATC.L2(39) [0]
Bit(s)	SCOM			Dial: Description
0	RW			TOPOID_8_VALID: valid bit for topology id 8
1	RW			TOPOID_9_VALID: valid bit for topology id 9
2	RW			TOPOID_10_VALID: valid bit for topology id 10
3	RW			TOPOID_11_VALID: valid bit for topology id 11
4	RW			TOPOID_12_VALID: valid bit for topology id 12
5	RW			TOPOID_13_VALID: valid bit for topology id 13
6	RW			TOPOID_14_VALID: valid bit for topology id 14
7	RW			TOPOID_15_VALID: valid bit for topology id 15
8:11	RW			TOPOID_8_: Topology id 8
12:15	RW			TOPOID_9_: Topology id 9
16:19	RW			TOPOID_10: Topology id 10
20:23	RW			TOPOID_11: Topology id 11
24:27	RW			TOPOID_12: Topology id 12
28:31	RW			TOPOID_13: Topology id 13
32:35	RW			TOPOID_14: Topology id 14
36:39	RW			TOPOID_15: Topology id 15
40:63	RO			constant=0b000000000000000000000000

Topology ID Translation Table 2
Addr:	0000000000090053 (SCOM)
Name:	TP.TPBR.AD.TOPOID_XLAT_TBL2
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#0.L.LAT.LATC.L2(0) [0]
	1	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#1.L.LAT.LATC.L2(1) [0]
	2	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#2.L.LAT.LATC.L2(2) [0]
	3	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#3.L.LAT.LATC.L2(3) [0]
	4	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#4.L.LAT.LATC.L2(4) [0]
	5	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#5.L.LAT.LATC.L2(5) [0]
	6	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#6.L.LAT.LATC.L2(6) [0]
	7	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#7.L.LAT.LATC.L2(7) [0]
	8	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#8.L.LAT.LATC.L2(8) [0]
	9	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#9.L.LAT.LATC.L2(9) [0]
	10	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#10.L.LAT.LATC.L2(10) [0]
	11	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#11.L.LAT.LATC.L2(11) [0]
	12	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#12.L.LAT.LATC.L2(12) [0]
	13	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#13.L.LAT.LATC.L2(13) [0]
	14	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#14.L.LAT.LATC.L2(14) [0]
	15	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#15.L.LAT.LATC.L2(15) [0]
	16	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#16.L.LAT.LATC.L2(16) [0]
	17	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#17.L.LAT.LATC.L2(17) [0]
	18	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#18.L.LAT.LATC.L2(18) [0]
	19	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#19.L.LAT.LATC.L2(19) [0]
	20	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#20.L.LAT.LATC.L2(20) [0]
	21	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#21.L.LAT.LATC.L2(21) [0]
	22	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#22.L.LAT.LATC.L2(22) [0]
	23	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#23.L.LAT.LATC.L2(23) [0]
	24	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#24.L.LAT.LATC.L2(24) [0]
	25	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#25.L.LAT.LATC.L2(25) [0]
	26	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#26.L.LAT.LATC.L2(26) [0]
	27	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#27.L.LAT.LATC.L2(27) [0]
	28	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#28.L.LAT.LATC.L2(28) [0]
	29	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#29.L.LAT.LATC.L2(29) [0]
	30	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#30.L.LAT.LATC.L2(30) [0]
	31	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#31.L.LAT.LATC.L2(31) [0]
	32	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#32.L.LAT.LATC.L2(32) [0]
	33	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#33.L.LAT.LATC.L2(33) [0]
	34	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#34.L.LAT.LATC.L2(34) [0]
	35	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#35.L.LAT.LATC.L2(35) [0]
	36	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#36.L.LAT.LATC.L2(36) [0]
	37	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#37.L.LAT.LATC.L2(37) [0]
	38	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#38.L.LAT.LATC.L2(38) [0]
	39	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL2.READ_WRITE.INT_CG.BITS#39.L.LAT.LATC.L2(39) [0]
Bit(s)	SCOM			Dial: Description
0	RW			TOPOID_16_VALID: valid bit for topology id 16
1	RW			TOPOID_17_VALID: valid bit for topology id 17
2	RW			TOPOID_18_VALID: valid bit for topology id 18
3	RW			TOPOID_19_VALID: valid bit for topology id 19
4	RW			TOPOID_20_VALID: valid bit for topology id 20
5	RW			TOPOID_21_VALID: valid bit for topology id 21
6	RW			TOPOID_22_VALID: valid bit for topology id 22
7	RW			TOPOID_23_VALID: valid bit for topology id 23
8:11	RW			TOPOID_16: Topology id 16
12:15	RW			TOPOID_17: Topology id 17
16:19	RW			TOPOID_18: Topology id 18
20:23	RW			TOPOID_19: Topology id 19
24:27	RW			TOPOID_20: Topology id 20
28:31	RW			TOPOID_21: Topology id 21
32:35	RW			TOPOID_22: Topology id 22
36:39	RW			TOPOID_23: Topology id 23
40:63	RO			constant=0b000000000000000000000000

Topology ID Translation Table 3
Addr:	0000000000090054 (SCOM)
Name:	TP.TPBR.AD.TOPOID_XLAT_TBL3
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#0.L.LAT.LATC.L2(0) [0]
	1	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#1.L.LAT.LATC.L2(1) [0]
	2	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#2.L.LAT.LATC.L2(2) [0]
	3	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#3.L.LAT.LATC.L2(3) [0]
	4	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#4.L.LAT.LATC.L2(4) [0]
	5	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#5.L.LAT.LATC.L2(5) [0]
	6	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#6.L.LAT.LATC.L2(6) [0]
	7	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#7.L.LAT.LATC.L2(7) [0]
	8	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#8.L.LAT.LATC.L2(8) [0]
	9	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#9.L.LAT.LATC.L2(9) [0]
	10	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#10.L.LAT.LATC.L2(10) [0]
	11	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#11.L.LAT.LATC.L2(11) [0]
	12	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#12.L.LAT.LATC.L2(12) [0]
	13	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#13.L.LAT.LATC.L2(13) [0]
	14	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#14.L.LAT.LATC.L2(14) [0]
	15	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#15.L.LAT.LATC.L2(15) [0]
	16	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#16.L.LAT.LATC.L2(16) [0]
	17	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#17.L.LAT.LATC.L2(17) [0]
	18	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#18.L.LAT.LATC.L2(18) [0]
	19	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#19.L.LAT.LATC.L2(19) [0]
	20	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#20.L.LAT.LATC.L2(20) [0]
	21	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#21.L.LAT.LATC.L2(21) [0]
	22	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#22.L.LAT.LATC.L2(22) [0]
	23	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#23.L.LAT.LATC.L2(23) [0]
	24	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#24.L.LAT.LATC.L2(24) [0]
	25	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#25.L.LAT.LATC.L2(25) [0]
	26	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#26.L.LAT.LATC.L2(26) [0]
	27	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#27.L.LAT.LATC.L2(27) [0]
	28	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#28.L.LAT.LATC.L2(28) [0]
	29	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#29.L.LAT.LATC.L2(29) [0]
	30	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#30.L.LAT.LATC.L2(30) [0]
	31	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#31.L.LAT.LATC.L2(31) [0]
	32	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#32.L.LAT.LATC.L2(32) [0]
	33	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#33.L.LAT.LATC.L2(33) [0]
	34	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#34.L.LAT.LATC.L2(34) [0]
	35	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#35.L.LAT.LATC.L2(35) [0]
	36	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#36.L.LAT.LATC.L2(36) [0]
	37	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#37.L.LAT.LATC.L2(37) [0]
	38	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#38.L.LAT.LATC.L2(38) [0]
	39	TP.TPBR.AD.PBADR.TOPOID_XLAT_TBL3.READ_WRITE.INT_CG.BITS#39.L.LAT.LATC.L2(39) [0]
Bit(s)	SCOM			Dial: Description
0	RW			TOPOID_24_VALID: valid bit for topology id 24
1	RW			TOPOID_25_VALID: valid bit for topology id 25
2	RW			TOPOID_26_VALID: valid bit for topology id 26
3	RW			TOPOID_27_VALID: valid bit for topology id 27
4	RW			TOPOID_28_VALID: valid bit for topology id 28
5	RW			TOPOID_29_VALID: valid bit for topology id 29
6	RW			TOPOID_30_VALID: valid bit for topology id 30
7	RW			TOPOID_31_VALID: valid bit for topology id 31
8:11	RW			TOPOID_24: Topology id 24
12:15	RW			TOPOID_25: Topology id 25
16:19	RW			TOPOID_26: Topology id 26
20:23	RW			TOPOID_27: Topology id 27
24:27	RW			TOPOID_28: Topology id 28
28:31	RW			TOPOID_29: Topology id 29
32:35	RW			TOPOID_30: Topology id 30
36:39	RW			TOPOID_31: Topology id 31
40:63	RO			constant=0b000000000000000000000000

CONTROl REGISTER_FAST_MODE_B(Read data is not reliable)
Addr:	00000000000A0000 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.CONTROL_REGISTER_B
Constant(s):	PU_CONTROL_REGISTER_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_CNTR_REG_OUT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RWX			PIB_CNTR_REG_BIT_WITHSTART_000: for command register of i2c engine
1	RWX			PIB_CNTR_REG_BIT_WITHADDR_000: for command register of i2c engine
2	RWX			PIB_CNTR_REG_BIT_READCONT_000: for command register of i2c engine
3	RWX			PIB_CNTR_REG_BIT_WITHSTOP_000: for command register of i2c engine
4:7	RWX			PIB_CNTR_REG_LENGTH_000: Maximum_write = 4 , Maximum_read = 8
8:14	RWX			PIB_CNTR_REG_ADDR_000: for command register of i2c engine
15	RWX			PIB_CNTR_REG_BIT_RNW_000: for command register of i2c engine
16:17	RWX			PIB_CNTR_REG_SPEED_000: Bit_rate_divisor value is 00= No change 01= 0x177 10= 0x5E 11= 0x0B
18:22	RWX			PIB_CNTR_REG_PORT_NUMBER_000: for mode register of i2c engine
23:25	RWX			REG_ADDR_LEN_000:  00= No register address in FIFO 01= 1 Byte of FIFO's data is Register address 10= 2 Byte of FIFO's data are Register address 11= 3 Byte of FIFO's data are Register address
26	RWX			ENH_MODE_000: Enable enhanced mode in mode register of I2C engine
27	RWX			ECC_ENABLE_000: Enables ECC for the current operation
28	RWX			ECCCHK_DISABLE_000: Disables ECC checking for Read operation when ECC is enabled
29	RWX			CNTR_UNUSED_000: reserved not used
30:31	RWX			FAST_MODE_INTERRUPT_STERRING_BITS_000: decides which master should see the done interrupt of fast_mode
32:39	RWX			PIB_CNTR_REG_DATA_1_000: data for i2c FIFO
40:47	RWX			PIB_CNTR_REG_DATA_2_000: data for i2c FIFO
48:55	RWX			PIB_CNTR_REG_DATA_3_000: data for i2c FIFO
56:63	RWX			PIB_CNTR_REG_DATA_4_000: data for i2c FIFO

DATA8to15_REGISTER_READ_ONLY_FAST_MODE
Addr:	00000000000A0001 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.DATA8TO15_REGISTER_B
Constant(s):	PU_DATA8TO15_REGISTER_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_DATA_REG_OUT_0_INST.LATC.L2(64:127) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	ROX			PIB_DATA8TO15_000: last 8 bytes of data for read and it is not available for Write operation

RESET REGISTER_FAST_MODE
Addr:	00000000000A0001 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.RESET_REGISTER_B
Constant(s):	PU_RESET_REGISTER_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.OVERALL_RESET_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	WOX			overall_reset_000 one bit register resets all registers and I2C ENGINE

STATUS REGISTER_FAST_MODE
Addr:	00000000000A0002 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.STATUS_REGISTER_B
Constant(s):	PU_STATUS_REGISTER_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_STATUS_REG_OUT_0_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_STATUS_REG_OUT_1_INST.LATC.L2(1) [0]
	2	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_STATUS_REG_OUT_2_INST.LATC.L2(2) [0]
	3	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_STATUS_REG_OUT_3_INST.LATC.L2(3) [0]
	4	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_STATUS_REG_OUT_4_INST.LATC.L2(4) [0]
	5	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_STATUS_REG_OUT_5_INST.LATC.L2(5) [0]
	6:37	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_DATA_REG_OUT_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_STATUS_REG_OUT_26_INST.LATC.L2(26) [0]
	41	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.ECC_CORRECTED_ERROR_LT_INST.LATC.L2(0) [0]
	42	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.ECC_UNCORRECTED_ERROR_LT_INST.LATC.L2(0) [0]
	43	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.ECC_CONFIG_ERR_LT_INST.LATC.L2(0) [0]
	44	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_STATUS_REG_OUT_6_INST.LATC.L2(6) [0]
	45	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_STATUS_REG_OUT_7_INST.LATC.L2(7) [0]
	46	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_STATUS_REG_OUT_8_INST.LATC.L2(8) [0]
	47	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_STATUS_REG_OUT_9_INST.LATC.L2(9) [0]
	48	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_STATUS_REG_OUT_10_INST.LATC.L2(10) [0]
	49	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_STATUS_REG_OUT_11_INST.LATC.L2(11) [0]
	50	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_STATUS_REG_OUT_12_INST.LATC.L2(12) [0]
	51	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_STATUS_REG_OUT_13_INST.LATC.L2(13) [0]
	52	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_STATUS_REG_OUT_14_INST.LATC.L2(14) [0]
	53	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_STATUS_REG_OUT_15_INST.LATC.L2(15) [0]
	54	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_STATUS_REG_OUT_16_INST.LATC.L2(16) [0]
	55	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_STATUS_REG_OUT_17_INST.LATC.L2(17) [0]
	56:59	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_STATUS_REG_OUT_18_INST.LATC.L2(18:21) [0000]
	60:63	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_STATUS_REG_OUT_22_INST.LATC.L2(22:25) [0000]
Bit(s)	SCOM			Dial: Description
0	ROX			BUS_STATUS_ADDR_NVLD_000: address invalid
1	ROX			BUS_STATUS_WRITE_NVLD_000: write invalid
2	ROX			BUS_STATUS_READ_NVLD_000: read invalid
3	ROX			BUS_STATUS_ADDR_P_ERR_000: address parity error
4	ROX			BUS_STATUS_PAR_ERR_000: data parity error
5	ROX			BUS_STATUS_LB_PARITY_ERROR_000: local bus parity error
6:37	ROX			PIB_DATA0TO7_000: 1st 8 bytes of data for read and for write 5ht byte to 12th byte
38:39	RO			constant=0b00
40	ROX			BUS_STATUS_WAITING_IN_I2C_QUEUE_000: operation queue status
41	ROX			ECC_CORRECTED_ERROR_000: This is a warning indicates that one bit flip was there in data and been corrected.
42	ROX			ECC_UNCORRECTED_ERROR_000: This is the error indicating that there are 2 bit flips in read data which cannot be corrected
43	ROX			ECC_CONFIG_ERROR_000: This the error indicating that control register is ecc_enabled for data_length not equal to 8. OR ECC is enabled for the engine where ECC block is not at all instantiated
44	ROX			BUS_STATUS_BUSY_000: local bus busy
45	ROX			BUS_STATUS_INVALID_COMMAND_000: invalid command
46	ROX			BUS_STATUS_PARITY_ERROR_000: parity error
47	ROX			BUS_STATUS_BACK_END_OVERRUN_ERROR_000: back end overrun error
48	ROX			BUS_STATUS_BACK_END_ACCESS_ERROR_000: back end access error
49	ROX			BUS_STATUS_ARBITRATION_LOST_ERROR_000: arbitration lost error
50	ROX			BUS_STATUS_NACK_RECEIVED_ERROR_000: nack receieved error
51	ROX			BUS_STATUS_DATA_REQUEST_000: data request
52	ROX			BUS_STATUS_COMMAND_COMPLETE_000: command complete
53	ROX			BUS_STATUS_STOP_ERROR_000: stop error
54	ROX			BUS_STATUS_I2C_PORT_BUSY_000: i2c port busy
55	ROX			BUS_STATUS_I2C_INTERFACE_BUSY_000: i2c interface busy
56:59	ROX			BUS_STATUS_FIFO_ENTRY_COUNT_000: fifo entry count
60:63	ROX			PCBIF_ERRS_000: PCBIF errors

DATA0to7_REGISTER_FAST_MODE
Addr:	00000000000A0003 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.DATA0TO7_REGISTER_B
Constant(s):	PU_DATA0TO7_REGISTER_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_DATA_REG_OUT_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RWX			PIB_DATA0TO7_000: 1st 8 bytes of data for read and for write 5ht byte to 12th byte

FIFO1_REGISTER_READ_B
Addr:	00000000000A0004 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.FIFO1_REGISTER_READ_B
Constant(s):	PU_FIFO1_REGISTER_READ_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.FIFO_BITS_OUT_INST.NO_FSILAT.LATCH.LATC.L2(0:7) [00000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:7	ROX			FIFO_BITS_READ0_000: As FIFO is not a normal register, cannot be completely verified in regchk . So this is a dummy register to maintain address in HTML fifo data byte 0 .Should be able to read/write 1 bytes
8:31	RO			constant=0b000000000000000000000000
32:39	ROX			PEEK_DATA1_000: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state
40	ROX			LBUS_PARITY_ERR1_000: local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

COMMAND_REGISTER_B
Addr:	00000000000A0005 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.COMMAND_REGISTER_B
Constant(s):	PU_COMMAND_REGISTER_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.CMD_REG_INST.NO_FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0	RWX			WITH_START_000: Decides start command to be issued or not during the beginiing of the operation Decides start command to be issued or not during the beginiing of the operation
1	RWX			WITH_ADDRESS_000: Decides Device address to be send or not during the beginning of the operation Decides Device address to be send or not during the beginning of the operation
2	RWX			READ_CONTINUE_000: Decides Next read operation is continuation of present operation or not Decides Next read operation is continuation of present operation or not
3	RWX			WITH_STOP_000: Decides stop command to be issued or not during the end of the operation Decides stop command to be issued or not during the end of the operation
4:7	RWX			NOT_USED_000: not used not used
8:14	RWX			DEVICE_ADDRESS_000: Device address of Slave on the I2C Bus Device address of Slave on the I2C Bus
15	RWX			READ_NOT_WRITE_000: I2C read or write I2C read or write
16:31	RWX			LENGTH_IN_BYTES_000: Length of Bytes to be accessed through the I2C Bus Length of Bytes to be accessed through the I2C Bus
32:39	ROX			PEEK_DATA1_000: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_000: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

MODE_REGISTER_B
Addr:	00000000000A0006 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.MODE_REGISTER_B
Constant(s):	PU_MODE_REGISTER_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.BIT_RATE_DIVISOR_INST.NO_FSILAT.LATCH.LATC.L2(0:15) [0000000000000000]
	16:21	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.MODE_REG_INST.NO_FSILAT.LATCH.LATC.L2(0:5) [000000]
	28:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.MODE_REG_INST.NO_FSILAT.LATCH.LATC.L2(6:9) [0000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:15	RWX			BIT_RATE_DIVISOR_000: Decides the speed on the I2C bus
16:21	RWX			PORT_NUMBER_000: port number
22:27	RO			constant=0b000000
28	RWX			FGAT_MODE_000: fgat mode
29	RWX			DIAG_MODE_000: diag mode
30	RWX			PACING_ALLOW_MODE_000: pacing allow mode
31	RWX			WRAP_MODE_000: wrap_mode
32:39	ROX			PEEK_DATA1_000: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state
40	ROX			LBUS_PARITY_ERR1_000: local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

WATER_MARK_REGISTER_B
Addr:	00000000000A0007 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.WATER_MARK_REGISTER_B
Constant(s):	PU_WATER_MARK_REGISTER_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	16:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.WATERMARK_REG_16_INST.NO_FSILAT.LATCH.LATC.L2(16:31) [0000000000000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:15	RO			constant=0b0000000000000000
16:31	RWX			WATERMARK_REG_000: water mark register water mark register
32:39	ROX			PEEK_DATA1_000: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_000: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

INTERRUPT_MASK_REGISTER_B
Addr:	00000000000A0008 (SCOM) 00000000000A0009 (SCOM1) 00000000000A000A (SCOM2)
Name:	TP.TPCHIP.PIB.I2CM.INTERRUPT_MASK_REGISTER_B
Constant(s):	PU_INTERRUPT_MASK_REGISTER_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	16:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.INT_MASK_16_INST.NO_FSILAT.LATCH.LATC.L2(16:31) [0000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0:15	RO	RO	RO	constant=0b0000000000000000
16:31	WOX	WOX_OR	WOX_AND	INT_MASK_000: interrupt mask register interrupt mask register
32:63	RO	RO	RO	constant=0b00000000000000000000000000000000

INTERRUPT_MASK_REGISTER_read_B
Addr:	00000000000A0008 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.INTERRUPT_MASK_REGISTER_READ_B
Constant(s):	PU_INTERRUPT_MASK_REGISTER_READ_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	16:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.INT_MASK_16_INST.NO_FSILAT.LATCH.LATC.L2(16:31) [0000000000000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:15	RO			constant=0b0000000000000000
16:31	ROX			INT_MASK_000: interrupt mask register interrupt mask register
32:39	ROX			PEEK_DATA1_000: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_000: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

INTERRUPT_CONDITION_B
Addr:	00000000000A0009 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.INTERRUPT_COND_B
Constant(s):	PU_INTERRUPT_COND_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	16:21	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(17:22) [000000]
	22	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(11) [0]
	23	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.INT_CONDS(23) [0]
	24	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(23) [0]
	25:26	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.INT_CONDS(25:26) [00]
	28:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.INT_CONDS(28:31) [0000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:15	RO			constant=0b0000000000000000 intterupt conditions
16	ROX			INVALID_CMD_000: invalid command : new command given when old command is not yet completed intterupt conditions
17	ROX			LBUS_PARITY_ERROR_000: local bus parity error intterupt conditions
18	ROX			BE_OV_ERROR_000: back end overrun error : Writing/reading into full/empty fifo resply intterupt conditions
19	ROX			BE_ACC_ERROR_000: back end access error : Writing/Reading more data than requested intterupt conditions
20	ROX			ARBITRATION_LOST_ERROR_000: arbitration lost error: I2C bus is held by someother master when trying to access intterupt conditions
21	ROX			NACK_RECEIVED_ERROR_000: nack receieved error: Slave is not responding back with the ACK. intterupt conditions
22	ROX			DATA_REQUEST_000: data request: FIFO needs to be accesssed some more times to full fill the expectation intterupt conditions
23	ROX			int_conds_cmd_complete_000 intterupt conditions
24	ROX			STOP_ERROR_000: stop error: Didnot able to send the stop condition on the BUS intterupt conditions
25	ROX			int_conds_i2c_busy_000 intterupt conditions
26	ROX			int_conds_not_i2c_busy_000 intterupt conditions
27	RO			constant=0b0 intterupt conditions
28	ROX			int_conds_scl_eq_1_000 intterupt conditions
29	ROX			int_conds_scl_eq_000_000 intterupt conditions
30	ROX			int_conds_sda_eq_1_000 intterupt conditions
31	ROX			int_conds_sda_eq_000_000 intterupt conditions
32:39	ROX			PEEK_DATA1_000: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_000: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

INTERRUPTS_REGISTER_B
Addr:	00000000000A000A (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.INTERRUPTS_B
Constant(s):	PU_INTERRUPTS_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.INTS(0:31) [00000000000000000000000000000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:31	ROX			ints_000 interrupts
32:39	ROX			PEEK_DATA1_000: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_000: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

IMM_RESET_I2C_B
Addr:	00000000000A000B (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.IMM_RESET_I2C_B
Constant(s):	PU_IMM_RESET_I2C_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_reset_i2c_000 resets command,mode,watermark,interrupt mask,status registers

STATUS_REGISTER_ENGINE_B
Addr:	00000000000A000B (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.STATUS_REGISTER_ENGINE_B
Constant(s):	PU_STATUS_REGISTER_ENGINE_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:5	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(17:22) [000000]
	8	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(23) [0]
	20	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.SCL_SYN(0) [0]
	23	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(37) [0]
	28:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.FIFO_LVL.DOUT_INST.NO_FSILAT.LATCH.LATC.L2(0:3) [0000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
	44:47	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.I2CM_PIBM_INTERRUPT_INT_0_INST.LATC.L2(0:3) [0000]
	48:53	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.EXTERNAL_STATUS(0:5) [000000]
Bit(s)	SCOM			Dial: Description
0	ROX			INVALID_CMD_000: invalid command : new command given when old command is not yet completed invalid command : new command given when old command is not yet completed
1	ROX			LBUS_PARITY_ERROR_000: local bus parity error local bus parity error
2	ROX			BE_OV_ERROR_000: back end overrun error : Writing/reading into full/empty fifo resply back end overrun error
3	ROX			BE_ACC_ERROR_000: back end access error : Writing/Reading more data than requested back end access error
4	ROX			ARBITRATION_LOST_ERROR_000: arbitration lost error: I2C bus is held by someother master when trying to access arbitration lost error
5	ROX			NACK_RECEIVED_ERROR_000: nack receieved error: Slave is not responding back with the ACK. nack receieved error
6	ROX			DATA_REQUEST_000: data request: FIFO needs to be accesssed some more times to full fill the expectation data request
7	ROX			cmd_complete_000 command complete : Indicates the completion of command
8	ROX			STOP_ERROR_000: stop error: Didnot able to send the stop condition on the BUS stop error
9:15	ROX			max_num_of_ports_000 maximum number of ports defined for this Engine
16	ROX			any_i2c_int_000 any_i2c_int
17	ROX			waiting_for_i2c_busy_000
18	RO			constant=0b0
19	ROX			i2c_port_history_busy_000 i2c_port_history_busy_000
20	ROX			scl_syn_000 scl_syn
21	ROX			sda_syn_000 sda_syn
22	ROX			i2c_busy_000 i2c busy: I2C bus is occupied
23	ROX			SELF_BUSY_000: self busy: I2C bus is occupied by itself self busy: I2C bus is occupied by itself
24:27	RO			constant=0b0000
28:31	ROX			FIFO_ENTRY_COUNT_000: fifo_entry count : Number of bytes present in the FIFO fifo_entry count : Number of bytes present in the FIFO
32:39	ROX			PEEK_DATA1_000: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_000: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:43	RO			constant=0b000
44:47	ROX			I2CM_STEERED_INTERRUPTS_000: Steered i2cm_interrupt either for fast mode or legacy mode
48:53	ROX			external_status_000
54:63	RO			constant=0b0000000000

EXTENDED_STATUS_B
Addr:	00000000000A000C (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.EXTENDED_STATUS_B
Constant(s):	PU_EXTENDED_STATUS_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.FIFO_SIZE(0:7) [00000000]
	11:15	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(39:43) [00000]
	16	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.SCL_SYN(0) [0]
	17	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.SDA_SYN(0) [0]
	18:19	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(46:47) [00]
	20	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(38) [0]
	25	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(37) [0]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:7	ROX			fifo_size_000 total fifo size
8:10	RO			constant=0b000
11:15	ROX			MSM_CURR_STATE_000: current state current state
16	ROX			scl_syn_ext_000 scl_syn
17	ROX			sda_syn_ext_000 sda_syn
18	ROX			s_scl_000 s_scl : clock input for wrap mode
19	ROX			s_sda_000 s_sda : Data input for wrap mode
20	ROX			m_scl_000 m_scl : clock output for wrap mode
21	ROX			m_sda_000 m_sda : data output for wrap mode
22	ROX			high_water_000 high water mark : FIFO reached higest water level
23	ROX			low_water_000 low water mark : FIFO reached lowest water level
24	ROX			i2c_busy_ext_000 i2c busy : I2C bus is busy
25	ROX			SELF_BUSY_000: self busy: I2C bus is occupied by itself self busy : I2C bus is held busy by itself
26:31	RO			constant=0b011001
32:39	ROX			PEEK_DATA1_000: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_000: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

IMM_RESET_ERR_B
Addr:	00000000000A000C (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.IMM_RESET_ERR_B
Constant(s):	PU_IMM_RESET_ERR_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_reset_errors_000 resets fifo ,some status bits and state machine

IMM_SET_S_SCL_B
Addr:	00000000000A000D (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.IMM_SET_S_SCL_B
Constant(s):	PU_IMM_SET_S_SCL_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_set_s_scl_000 sets output s_scl

RESIDUAL_FRONT_END_BACK_END_LENGTH_B
Addr:	00000000000A000D (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.RESIDUAL_FRONT_END_BACK_END_LENGTH_B
Constant(s):	PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.RESID_FE_LEN_INST.NO_FSILAT.LATCH.LATC.L2(0:15) [0000000000000000]
	16:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.RESID_BE_LEN(0:15) [0000000000000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:15	ROX			RESID_FE_LEN_000: residual front end length register residual front end length register
16:31	ROX			resid_be_len_000 residual back end length register
32:39	ROX			PEEK_DATA1_000: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_000: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

I2C_BUSY_REGISTER_B
Addr:	00000000000A000E (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.I2C_BUSY_REGISTER_B
Constant(s):	PU_I2C_BUSY_REGISTER_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:13	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.I2C_BUSY_ALL_0_INST.NO_FSILAT.LATCH.LATC.L2(0:13) [00000000000000]
	14:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.I2C_BUSY_REG(14:31) [000000000000000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:31	ROX			port_busy_000 corresponding port is busy if it is '1' no one should access . If '0' can be accessed. Port busy/I2C register will get reset with SCOM write with a data pattern which has bit 0 - 1 and bit 1 -0 and rest of the bits can be any value. For more details please refere documentation.
32:39	ROX			PEEK_DATA1_000: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_000: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

IMM_RESET_S_SCL_B
Addr:	00000000000A000F (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.IMM_RESET_S_SCL_B
Constant(s):	PU_IMM_RESET_S_SCL_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_reset_s_scl_000 resets output s_scl

IMM_SET_S_SDA_B
Addr:	00000000000A0010 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.IMM_SET_S_SDA_B
Constant(s):	PU_IMM_SET_S_SDA_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_set_s_sda_000 sets output s_sda

IMM_RESET_S_SDA_B
Addr:	00000000000A0011 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.IMM_RESET_S_SDA_B
Constant(s):	PU_IMM_RESET_S_SDA_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_reset_s_sda_000 resets output s_sda

FIFO4_REGISTER_READ_000
Addr:	00000000000A0012 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.FIFO4_REGISTER_READ_B
Constant(s):	PU_FIFO4_REGISTER_READ_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.FIFO_BITS_OUT_INST.NO_FSILAT.LATCH.LATC.L2(0:7) [00000000]
	8:15	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.FIFO_BITS_OUT_INST.NO_FSILAT.LATCH.LATC.L2(9:16) [00000000]
	16:23	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.FIFO_BITS_OUT_INST.NO_FSILAT.LATCH.LATC.L2(18:25) [00000000]
	24:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.TP_I2CM_COMP.FIFO_BITS_OUT_INST.NO_FSILAT.LATCH.LATC.L2(27:34) [00000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:7	ROX			FIFO_BITS_READ0_000: As FIFO is not a normal register, cannot be completely verified in regchk . So this is a dummy register to maintain address in HTML fifo data byte 0 .Should be able to read/write 1 bytes
8:15	ROX			fifo_bits_read2_000
16:23	ROX			fifo_bits_read3_000
24:31	ROX			fifo_bits_read4_000
32:39	ROX			PEEK_DATA1_000: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state
40	ROX			LBUS_PARITY_ERR1_000: local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

CC Protect Mode Register
Addr:	00000000000A03FE (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.PIBI2CM_PROTECT_MODE_REG_B
Constant(s):	PU_PIBI2CM_PROTECT_MODE_REG_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.PCBIF_COMP.PROTECT_MODE.RD_PROTECT_ENA_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.PCBIF_COMP.PROTECT_MODE.WR_PROTECT_ENA_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	RW			CC_READ_PROTECT_ENABLE_000: Enable read protection
1	RW			CC_WRITE_PROTECT_ENABLE_000: Enable write protection

Atomic Lock Register
Addr:	00000000000A03FF (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.PIBI2CM_ATOMIC_LOCK_REG_B
Constant(s):	PU_PIBI2CM_ATOMIC_LOCK_REG_B
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.PCBIF_COMP.ATOMIC_LOCK.ATOMIC_LOCK_ENA_INST.LATC.L2(0) [0]
	1:4	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.PCBIF_COMP.ATOMIC_LOCK.ATOMIC_ID_Q_INST.LATC.L2(0:3) [0000]
	8:15	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#0.PCBIF_COMP.ATOMIC_LOCK.ATOMIC_LOCK_ACTIVITY_Q_INST.LATC.L2(0:7) [00000000]
Bit(s)	SCOM			Dial: Description
0	RW			CC_ATOMIC_LOCK_ENABLE_000: Enable atomic lock
1:4	ROX			CC_ATOMIC_ID_000: Atomic ID
5:7	RO			constant=0b000
8:15	ROX			CC_ATOMIC_ACTIVITY_000: Atomic lock counter

CONTROl REGISTER_FAST_MODE_C(Read data is not reliable)
Addr:	00000000000A1000 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.CONTROL_REGISTER_C
Constant(s):	PU_CONTROL_REGISTER_C
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_CNTR_REG_OUT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RWX			PIB_CNTR_REG_BIT_WITHSTART_001: for command register of i2c engine
1	RWX			PIB_CNTR_REG_BIT_WITHADDR_001: for command register of i2c engine
2	RWX			PIB_CNTR_REG_BIT_READCONT_001: for command register of i2c engine
3	RWX			PIB_CNTR_REG_BIT_WITHSTOP_001: for command register of i2c engine
4:7	RWX			PIB_CNTR_REG_LENGTH_001: Maximum_write = 4 , Maximum_read = 8
8:14	RWX			PIB_CNTR_REG_ADDR_001: for command register of i2c engine
15	RWX			PIB_CNTR_REG_BIT_RNW_001: for command register of i2c engine
16:17	RWX			PIB_CNTR_REG_SPEED_001: Bit_rate_divisor value is 00= No change 01= 0x177 10= 0x5E 11= 0x0B
18:22	RWX			PIB_CNTR_REG_PORT_NUMBER_001: for mode register of i2c engine
23:25	RWX			REG_ADDR_LEN_001:  00= No register address in FIFO 01= 1 Byte of FIFO's data is Register address 10= 2 Byte of FIFO's data are Register address 11= 3 Byte of FIFO's data are Register address
26	RWX			ENH_MODE_001: Enable enhanced mode in mode register of I2C engine
27	RWX			ECC_ENABLE_001: Enables ECC for the current operation
28	RWX			ECCCHK_DISABLE_001: Disables ECC checking for Read operation when ECC is enabled
29	RWX			CNTR_UNUSED_001: reserved not used
30:31	RWX			FAST_MODE_INTERRUPT_STERRING_BITS_001: decides which master should see the done interrupt of fast_mode
32:39	RWX			PIB_CNTR_REG_DATA_1_001: data for i2c FIFO
40:47	RWX			PIB_CNTR_REG_DATA_2_001: data for i2c FIFO
48:55	RWX			PIB_CNTR_REG_DATA_3_001: data for i2c FIFO
56:63	RWX			PIB_CNTR_REG_DATA_4_001: data for i2c FIFO

DATA8to15_REGISTER_READ_ONLY_FAST_MODE
Addr:	00000000000A1001 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.DATA8TO15_REGISTER_C
Constant(s):	PU_DATA8TO15_REGISTER_C
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_DATA_REG_OUT_0_INST.LATC.L2(64:127) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	ROX			PIB_DATA8TO15_001: last 8 bytes of data for read and it is not available for Write operation

RESET REGISTER_FAST_MODE
Addr:	00000000000A1001 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.RESET_REGISTER_C
Constant(s):	PU_RESET_REGISTER_C
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.OVERALL_RESET_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	WOX			overall_reset_001 one bit register resets all registers and I2C ENGINE

STATUS REGISTER_FAST_MODE
Addr:	00000000000A1002 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.STATUS_REGISTER_C
Constant(s):	PU_STATUS_REGISTER_C
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_STATUS_REG_OUT_0_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_STATUS_REG_OUT_1_INST.LATC.L2(1) [0]
	2	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_STATUS_REG_OUT_2_INST.LATC.L2(2) [0]
	3	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_STATUS_REG_OUT_3_INST.LATC.L2(3) [0]
	4	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_STATUS_REG_OUT_4_INST.LATC.L2(4) [0]
	5	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_STATUS_REG_OUT_5_INST.LATC.L2(5) [0]
	6:37	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_DATA_REG_OUT_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_STATUS_REG_OUT_26_INST.LATC.L2(26) [0]
	41	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.ECC_CORRECTED_ERROR_LT_INST.LATC.L2(0) [0]
	42	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.ECC_UNCORRECTED_ERROR_LT_INST.LATC.L2(0) [0]
	43	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.ECC_CONFIG_ERR_LT_INST.LATC.L2(0) [0]
	44	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_STATUS_REG_OUT_6_INST.LATC.L2(6) [0]
	45	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_STATUS_REG_OUT_7_INST.LATC.L2(7) [0]
	46	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_STATUS_REG_OUT_8_INST.LATC.L2(8) [0]
	47	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_STATUS_REG_OUT_9_INST.LATC.L2(9) [0]
	48	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_STATUS_REG_OUT_10_INST.LATC.L2(10) [0]
	49	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_STATUS_REG_OUT_11_INST.LATC.L2(11) [0]
	50	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_STATUS_REG_OUT_12_INST.LATC.L2(12) [0]
	51	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_STATUS_REG_OUT_13_INST.LATC.L2(13) [0]
	52	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_STATUS_REG_OUT_14_INST.LATC.L2(14) [0]
	53	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_STATUS_REG_OUT_15_INST.LATC.L2(15) [0]
	54	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_STATUS_REG_OUT_16_INST.LATC.L2(16) [0]
	55	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_STATUS_REG_OUT_17_INST.LATC.L2(17) [0]
	56:59	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_STATUS_REG_OUT_18_INST.LATC.L2(18:21) [0000]
	60:63	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_STATUS_REG_OUT_22_INST.LATC.L2(22:25) [0000]
Bit(s)	SCOM			Dial: Description
0	ROX			BUS_STATUS_ADDR_NVLD_001: address invalid
1	ROX			BUS_STATUS_WRITE_NVLD_001: write invalid
2	ROX			BUS_STATUS_READ_NVLD_001: read invalid
3	ROX			BUS_STATUS_ADDR_P_ERR_001: address parity error
4	ROX			BUS_STATUS_PAR_ERR_001: data parity error
5	ROX			BUS_STATUS_LB_PARITY_ERROR_001: local bus parity error
6:37	ROX			PIB_DATA0TO7_001: 1st 8 bytes of data for read and for write 5ht byte to 12th byte
38:39	RO			constant=0b00
40	ROX			BUS_STATUS_WAITING_IN_I2C_QUEUE_001: operation queue status
41	ROX			ECC_CORRECTED_ERROR_001: This is a warning indicates that one bit flip was there in data and been corrected.
42	ROX			ECC_UNCORRECTED_ERROR_001: This is the error indicating that there are 2 bit flips in read data which cannot be corrected
43	ROX			ECC_CONFIG_ERROR_001: This the error indicating that control register is ecc_enabled for data_length not equal to 8. OR ECC is enabled for the engine where ECC block is not at all instantiated
44	ROX			BUS_STATUS_BUSY_001: local bus busy
45	ROX			BUS_STATUS_INVALID_COMMAND_001: invalid command
46	ROX			BUS_STATUS_PARITY_ERROR_001: parity error
47	ROX			BUS_STATUS_BACK_END_OVERRUN_ERROR_001: back end overrun error
48	ROX			BUS_STATUS_BACK_END_ACCESS_ERROR_001: back end access error
49	ROX			BUS_STATUS_ARBITRATION_LOST_ERROR_001: arbitration lost error
50	ROX			BUS_STATUS_NACK_RECEIVED_ERROR_001: nack receieved error
51	ROX			BUS_STATUS_DATA_REQUEST_001: data request
52	ROX			BUS_STATUS_COMMAND_COMPLETE_001: command complete
53	ROX			BUS_STATUS_STOP_ERROR_001: stop error
54	ROX			BUS_STATUS_I2C_PORT_BUSY_001: i2c port busy
55	ROX			BUS_STATUS_I2C_INTERFACE_BUSY_001: i2c interface busy
56:59	ROX			BUS_STATUS_FIFO_ENTRY_COUNT_001: fifo entry count
60:63	ROX			PCBIF_ERRS_001: PCBIF errors

DATA0to7_REGISTER_FAST_MODE
Addr:	00000000000A1003 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.DATA0TO7_REGISTER_C
Constant(s):	PU_DATA0TO7_REGISTER_C
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_DATA_REG_OUT_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RWX			PIB_DATA0TO7_001: 1st 8 bytes of data for read and for write 5ht byte to 12th byte

FIFO1_REGISTER_READ_C
Addr:	00000000000A1004 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.FIFO1_REGISTER_READ_C
Constant(s):	PU_FIFO1_REGISTER_READ_C
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.FIFO_BITS_OUT_INST.NO_FSILAT.LATCH.LATC.L2(0:7) [00000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:7	ROX			FIFO_BITS_READ0_001: As FIFO is not a normal register, cannot be completely verified in regchk . So this is a dummy register to maintain address in HTML fifo data byte 0 .Should be able to read/write 1 bytes
8:31	RO			constant=0b000000000000000000000000
32:39	ROX			PEEK_DATA1_001: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state
40	ROX			LBUS_PARITY_ERR1_001: local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

COMMAND_REGISTER_C
Addr:	00000000000A1005 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.COMMAND_REGISTER_C
Constant(s):	PU_COMMAND_REGISTER_C
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.CMD_REG_INST.NO_FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0	RWX			WITH_START_001: Decides start command to be issued or not during the beginiing of the operation Decides start command to be issued or not during the beginiing of the operation
1	RWX			WITH_ADDRESS_001: Decides Device address to be send or not during the beginning of the operation Decides Device address to be send or not during the beginning of the operation
2	RWX			READ_CONTINUE_001: Decides Next read operation is continuation of present operation or not Decides Next read operation is continuation of present operation or not
3	RWX			WITH_STOP_001: Decides stop command to be issued or not during the end of the operation Decides stop command to be issued or not during the end of the operation
4:7	RWX			NOT_USED_001: not used not used
8:14	RWX			DEVICE_ADDRESS_001: Device address of Slave on the I2C Bus Device address of Slave on the I2C Bus
15	RWX			READ_NOT_WRITE_001: I2C read or write I2C read or write
16:31	RWX			LENGTH_IN_BYTES_001: Length of Bytes to be accessed through the I2C Bus Length of Bytes to be accessed through the I2C Bus
32:39	ROX			PEEK_DATA1_001: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_001: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

MODE_REGISTER_C
Addr:	00000000000A1006 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.MODE_REGISTER_C
Constant(s):	PU_MODE_REGISTER_C
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.BIT_RATE_DIVISOR_INST.NO_FSILAT.LATCH.LATC.L2(0:15) [0000000000000000]
	16:21	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.MODE_REG_INST.NO_FSILAT.LATCH.LATC.L2(0:5) [000000]
	28:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.MODE_REG_INST.NO_FSILAT.LATCH.LATC.L2(6:9) [0000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:15	RWX			BIT_RATE_DIVISOR_001: Decides the speed on the I2C bus
16:21	RWX			PORT_NUMBER_001: port number
22:27	RO			constant=0b000000
28	RWX			FGAT_MODE_001: fgat mode
29	RWX			DIAG_MODE_001: diag mode
30	RWX			PACING_ALLOW_MODE_001: pacing allow mode
31	RWX			WRAP_MODE_001: wrap_mode
32:39	ROX			PEEK_DATA1_001: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state
40	ROX			LBUS_PARITY_ERR1_001: local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

WATER_MARK_REGISTER_C
Addr:	00000000000A1007 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.WATER_MARK_REGISTER_C
Constant(s):	PU_WATER_MARK_REGISTER_C
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	16:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.WATERMARK_REG_16_INST.NO_FSILAT.LATCH.LATC.L2(16:31) [0000000000000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:15	RO			constant=0b0000000000000000
16:31	RWX			WATERMARK_REG_001: water mark register water mark register
32:39	ROX			PEEK_DATA1_001: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_001: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

INTERRUPT_MASK_REGISTER_C
Addr:	00000000000A1008 (SCOM) 00000000000A1009 (SCOM1) 00000000000A100A (SCOM2)
Name:	TP.TPCHIP.PIB.I2CM.INTERRUPT_MASK_REGISTER_C
Constant(s):	PU_INTERRUPT_MASK_REGISTER_C
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	16:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.INT_MASK_16_INST.NO_FSILAT.LATCH.LATC.L2(16:31) [0000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0:15	RO	RO	RO	constant=0b0000000000000000
16:31	WOX	WOX_OR	WOX_AND	INT_MASK_001: interrupt mask register interrupt mask register
32:63	RO	RO	RO	constant=0b00000000000000000000000000000000

INTERRUPT_MASK_REGISTER_read_C
Addr:	00000000000A1008 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.INTERRUPT_MASK_REGISTER_READ_C
Constant(s):	PU_INTERRUPT_MASK_REGISTER_READ_C
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	16:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.INT_MASK_16_INST.NO_FSILAT.LATCH.LATC.L2(16:31) [0000000000000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:15	RO			constant=0b0000000000000000
16:31	ROX			INT_MASK_001: interrupt mask register interrupt mask register
32:39	ROX			PEEK_DATA1_001: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_001: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

INTERRUPT_CONDITION_B
Addr:	00000000000A1009 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.INTERRUPT_COND_C
Constant(s):	PU_INTERRUPT_COND_C
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	16:21	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(17:22) [000000]
	22	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(11) [0]
	23	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.INT_CONDS(23) [0]
	24	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(23) [0]
	25:26	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.INT_CONDS(25:26) [00]
	28:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.INT_CONDS(28:31) [0000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:15	RO			constant=0b0000000000000000 intterupt conditions
16	ROX			INVALID_CMD_001: invalid command : new command given when old command is not yet completed intterupt conditions
17	ROX			LBUS_PARITY_ERROR_001: local bus parity error intterupt conditions
18	ROX			BE_OV_ERROR_001: back end overrun error : Writing/reading into full/empty fifo resply intterupt conditions
19	ROX			BE_ACC_ERROR_001: back end access error : Writing/Reading more data than requested intterupt conditions
20	ROX			ARBITRATION_LOST_ERROR_001: arbitration lost error: I2C bus is held by someother master when trying to access intterupt conditions
21	ROX			NACK_RECEIVED_ERROR_001: nack receieved error: Slave is not responding back with the ACK. intterupt conditions
22	ROX			DATA_REQUEST_001: data request: FIFO needs to be accesssed some more times to full fill the expectation intterupt conditions
23	ROX			int_conds_cmd_complete_001 intterupt conditions
24	ROX			STOP_ERROR_001: stop error: Didnot able to send the stop condition on the BUS intterupt conditions
25	ROX			int_conds_i2c_busy_001 intterupt conditions
26	ROX			int_conds_not_i2c_busy_001 intterupt conditions
27	RO			constant=0b0 intterupt conditions
28	ROX			int_conds_scl_eq_1_001 intterupt conditions
29	ROX			int_conds_scl_eq_001_001 intterupt conditions
30	ROX			int_conds_sda_eq_1_001 intterupt conditions
31	ROX			int_conds_sda_eq_001_001 intterupt conditions
32:39	ROX			PEEK_DATA1_001: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_001: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

INTERRUPTS_REGISTER_C
Addr:	00000000000A100A (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.INTERRUPTS_C
Constant(s):	PU_INTERRUPTS_C
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.INTS(0:31) [00000000000000000000000000000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:31	ROX			ints_001 interrupts
32:39	ROX			PEEK_DATA1_001: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_001: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

IMM_RESET_I2C_C
Addr:	00000000000A100B (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.IMM_RESET_I2C_C
Constant(s):	PU_IMM_RESET_I2C_C
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_reset_i2c_001 resets command,mode,watermark,interrupt mask,status registers

STATUS_REGISTER_ENGINE_C
Addr:	00000000000A100B (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.STATUS_REGISTER_ENGINE_C
Constant(s):	PU_STATUS_REGISTER_ENGINE_C
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:5	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(17:22) [000000]
	8	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(23) [0]
	20	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.SCL_SYN(0) [0]
	23	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(37) [0]
	28:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.FIFO_LVL.DOUT_INST.NO_FSILAT.LATCH.LATC.L2(0:3) [0000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
	44:47	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.I2CM_PIBM_INTERRUPT_INT_0_INST.LATC.L2(0:3) [0000]
	48:53	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.EXTERNAL_STATUS(6:11) [000000]
Bit(s)	SCOM			Dial: Description
0	ROX			INVALID_CMD_001: invalid command : new command given when old command is not yet completed invalid command : new command given when old command is not yet completed
1	ROX			LBUS_PARITY_ERROR_001: local bus parity error local bus parity error
2	ROX			BE_OV_ERROR_001: back end overrun error : Writing/reading into full/empty fifo resply back end overrun error
3	ROX			BE_ACC_ERROR_001: back end access error : Writing/Reading more data than requested back end access error
4	ROX			ARBITRATION_LOST_ERROR_001: arbitration lost error: I2C bus is held by someother master when trying to access arbitration lost error
5	ROX			NACK_RECEIVED_ERROR_001: nack receieved error: Slave is not responding back with the ACK. nack receieved error
6	ROX			DATA_REQUEST_001: data request: FIFO needs to be accesssed some more times to full fill the expectation data request
7	ROX			cmd_complete_001 command complete : Indicates the completion of command
8	ROX			STOP_ERROR_001: stop error: Didnot able to send the stop condition on the BUS stop error
9:15	ROX			max_num_of_ports_001 maximum number of ports defined for this Engine
16	ROX			any_i2c_int_001 any_i2c_int
17	ROX			waiting_for_i2c_busy_001
18	RO			constant=0b0
19	ROX			i2c_port_history_busy_001 i2c_port_history_busy_001
20	ROX			scl_syn_001 scl_syn
21	ROX			sda_syn_001 sda_syn
22	ROX			i2c_busy_001 i2c busy: I2C bus is occupied
23	ROX			SELF_BUSY_001: self busy: I2C bus is occupied by itself self busy: I2C bus is occupied by itself
24:27	RO			constant=0b0000
28:31	ROX			FIFO_ENTRY_COUNT_001: fifo_entry count : Number of bytes present in the FIFO fifo_entry count : Number of bytes present in the FIFO
32:39	ROX			PEEK_DATA1_001: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_001: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:43	RO			constant=0b000
44:47	ROX			I2CM_STEERED_INTERRUPTS_001: Steered i2cm_interrupt either for fast mode or legacy mode
48:53	ROX			external_status_001
54:63	RO			constant=0b0000000000

EXTENDED_STATUS_C
Addr:	00000000000A100C (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.EXTENDED_STATUS_C
Constant(s):	PU_EXTENDED_STATUS_C
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.FIFO_SIZE(0:7) [00000000]
	11:15	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(39:43) [00000]
	16	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.SCL_SYN(0) [0]
	17	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.SDA_SYN(0) [0]
	18:19	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(46:47) [00]
	20	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(38) [0]
	25	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(37) [0]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:7	ROX			fifo_size_001 total fifo size
8:10	RO			constant=0b000
11:15	ROX			MSM_CURR_STATE_001: current state current state
16	ROX			scl_syn_ext_001 scl_syn
17	ROX			sda_syn_ext_001 sda_syn
18	ROX			s_scl_001 s_scl : clock input for wrap mode
19	ROX			s_sda_001 s_sda : Data input for wrap mode
20	ROX			m_scl_001 m_scl : clock output for wrap mode
21	ROX			m_sda_001 m_sda : data output for wrap mode
22	ROX			high_water_001 high water mark : FIFO reached higest water level
23	ROX			low_water_001 low water mark : FIFO reached lowest water level
24	ROX			i2c_busy_ext_001 i2c busy : I2C bus is busy
25	ROX			SELF_BUSY_001: self busy: I2C bus is occupied by itself self busy : I2C bus is held busy by itself
26:31	RO			constant=0b011001
32:39	ROX			PEEK_DATA1_001: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_001: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

IMM_RESET_ERR_B
Addr:	00000000000A100C (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.IMM_RESET_ERR_C
Constant(s):	PU_IMM_RESET_ERR_C
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_reset_errors_001 resets fifo ,some status bits and state machine

IMM_SET_S_SCL_C
Addr:	00000000000A100D (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.IMM_SET_S_SCL_C
Constant(s):	PU_IMM_SET_S_SCL_C
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_set_s_scl_001 sets output s_scl

RESIDUAL_FRONT_END_BACK_END_LENGTH_C
Addr:	00000000000A100D (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.RESIDUAL_FRONT_END_BACK_END_LENGTH_C
Constant(s):	PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.RESID_FE_LEN_INST.NO_FSILAT.LATCH.LATC.L2(0:15) [0000000000000000]
	16:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.RESID_BE_LEN(0:15) [0000000000000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:15	ROX			RESID_FE_LEN_001: residual front end length register residual front end length register
16:31	ROX			resid_be_len_001 residual back end length register
32:39	ROX			PEEK_DATA1_001: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_001: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

I2C_BUSY_REGISTER_C
Addr:	00000000000A100E (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.I2C_BUSY_REGISTER_C
Constant(s):	PU_I2C_BUSY_REGISTER_C
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:13	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.I2C_BUSY_ALL_0_INST.NO_FSILAT.LATCH.LATC.L2(0:13) [00000000000000]
	14:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.I2C_BUSY_REG(14:31) [000000000000000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:31	ROX			port_busy_001 corresponding port is busy if it is '1' no one should access . If '0' can be accessed. Port/I2C busy register will get reset with SCOM write with a data pattern which has bit 0 - 1 and bit 1 -0 and rest of the bits can be any value. For more details please refere documentation.
32:39	ROX			PEEK_DATA1_001: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_001: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

IMM_RESET_S_SCL_C
Addr:	00000000000A100F (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.IMM_RESET_S_SCL_C
Constant(s):	PU_IMM_RESET_S_SCL_C
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_reset_s_scl_001 resets output s_scl

IMM_SET_S_SDA_C
Addr:	00000000000A1010 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.IMM_SET_S_SDA_C
Constant(s):	PU_IMM_SET_S_SDA_C
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_set_s_sda_001 sets output s_sda

IMM_RESET_S_SDA_C
Addr:	00000000000A1011 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.IMM_RESET_S_SDA_C
Constant(s):	PU_IMM_RESET_S_SDA_C
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_reset_s_sda_001 resets output s_sda

FIFO4_REGISTER_READ_001
Addr:	00000000000A1012 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.FIFO4_REGISTER_READ_C
Constant(s):	PU_FIFO4_REGISTER_READ_C
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.FIFO_BITS_OUT_INST.NO_FSILAT.LATCH.LATC.L2(0:7) [00000000]
	8:15	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.FIFO_BITS_OUT_INST.NO_FSILAT.LATCH.LATC.L2(9:16) [00000000]
	16:23	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.FIFO_BITS_OUT_INST.NO_FSILAT.LATCH.LATC.L2(18:25) [00000000]
	24:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.TP_I2CM_COMP.FIFO_BITS_OUT_INST.NO_FSILAT.LATCH.LATC.L2(27:34) [00000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:7	ROX			FIFO_BITS_READ0_001: As FIFO is not a normal register, cannot be completely verified in regchk . So this is a dummy register to maintain address in HTML fifo data byte 0 .Should be able to read/write 1 bytes
8:15	ROX			fifo_bits_read2_001
16:23	ROX			fifo_bits_read3_001
24:31	ROX			fifo_bits_read4_001
32:39	ROX			PEEK_DATA1_001: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state
40	ROX			LBUS_PARITY_ERR1_001: local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

CC Protect Mode Register
Addr:	00000000000A13FE (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.PIBI2CM_PROTECT_MODE_REG_C
Constant(s):	PU_PIBI2CM_PROTECT_MODE_REG_C
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.PCBIF_COMP.PROTECT_MODE.RD_PROTECT_ENA_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.PCBIF_COMP.PROTECT_MODE.WR_PROTECT_ENA_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	RW			CC_READ_PROTECT_ENABLE_001: Enable read protection
1	RW			CC_WRITE_PROTECT_ENABLE_001: Enable write protection

Atomic Lock Register
Addr:	00000000000A13FF (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.PIBI2CM_ATOMIC_LOCK_REG_C
Constant(s):	PU_PIBI2CM_ATOMIC_LOCK_REG_C
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.PCBIF_COMP.ATOMIC_LOCK.ATOMIC_LOCK_ENA_INST.LATC.L2(0) [0]
	1:4	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.PCBIF_COMP.ATOMIC_LOCK.ATOMIC_ID_Q_INST.LATC.L2(0:3) [0000]
	8:15	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#1.PCBIF_COMP.ATOMIC_LOCK.ATOMIC_LOCK_ACTIVITY_Q_INST.LATC.L2(0:7) [00000000]
Bit(s)	SCOM			Dial: Description
0	RW			CC_ATOMIC_LOCK_ENABLE_001: Enable atomic lock
1:4	ROX			CC_ATOMIC_ID_001: Atomic ID
5:7	RO			constant=0b000
8:15	ROX			CC_ATOMIC_ACTIVITY_001: Atomic lock counter

CONTROl REGISTER_FAST_MODE(Read data is not reliable)
Addr:	00000000000A2000 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.CONTROL_REGISTER_D
Constant(s):	PU_CONTROL_REGISTER_D
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_CNTR_REG_OUT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RWX			PIB_CNTR_REG_BIT_WITHSTART_002: for command register of i2c engine
1	RWX			PIB_CNTR_REG_BIT_WITHADDR_002: for command register of i2c engine
2	RWX			PIB_CNTR_REG_BIT_READCONT_002: for command register of i2c engine
3	RWX			PIB_CNTR_REG_BIT_WITHSTOP_002: for command register of i2c engine
4:7	RWX			PIB_CNTR_REG_LENGTH_002: Maximum_write = 4 , Maximum_read = 8
8:14	RWX			PIB_CNTR_REG_ADDR_002: for command register of i2c engine
15	RWX			PIB_CNTR_REG_BIT_RNW_002: for command register of i2c engine
16:17	RWX			PIB_CNTR_REG_SPEED_002: Bit_rate_divisor value is 00= No change 01= 0x177 10= 0x5E 11= 0x0B
18:22	RWX			PIB_CNTR_REG_PORT_NUMBER_002: for mode register of i2c engine
23:25	RWX			REG_ADDR_LEN_002:  00= No register address in FIFO 01= 1 Byte of FIFO's data is Register address 10= 2 Byte of FIFO's data are Register address 11= 3 Byte of FIFO's data are Register address
26	RWX			ENH_MODE_002: Enable enhanced mode in mode register of I2C engine
27	RWX			ECC_ENABLE_002: Enables ECC for the current operation
28	RWX			ECCCHK_DISABLE_002: Disables ECC checking for Read operation when ECC is enabled
29	RWX			CNTR_UNUSED_002: reserved not used
30:31	RWX			FAST_MODE_INTERRUPT_STERRING_BITS_002: decides which master should see the done interrupt of fast_mode
32:39	RWX			PIB_CNTR_REG_DATA_1_002: data for i2c FIFO
40:47	RWX			PIB_CNTR_REG_DATA_2_002: data for i2c FIFO
48:55	RWX			PIB_CNTR_REG_DATA_3_002: data for i2c FIFO
56:63	RWX			PIB_CNTR_REG_DATA_4_002: data for i2c FIFO

DATA8to15_REGISTER_READ_ONLY_FAST_MODE
Addr:	00000000000A2001 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.DATA8TO15_REGISTER_D
Constant(s):	PU_DATA8TO15_REGISTER_D
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_DATA_REG_OUT_0_INST.LATC.L2(64:127) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	ROX			PIB_DATA8TO15_002: last 8 bytes of data for read and it is not available for Write operation

RESET REGISTER_FAST_MODE
Addr:	00000000000A2001 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.RESET_REGISTER_D
Constant(s):	PU_RESET_REGISTER_D
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.OVERALL_RESET_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	WOX			overall_reset_002 one bit register resets all registers and I2C ENGINE

STATUS REGISTER_FAST_MODE
Addr:	00000000000A2002 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.STATUS_REGISTER_D
Constant(s):	PU_STATUS_REGISTER_D
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_STATUS_REG_OUT_0_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_STATUS_REG_OUT_1_INST.LATC.L2(1) [0]
	2	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_STATUS_REG_OUT_2_INST.LATC.L2(2) [0]
	3	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_STATUS_REG_OUT_3_INST.LATC.L2(3) [0]
	4	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_STATUS_REG_OUT_4_INST.LATC.L2(4) [0]
	5	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_STATUS_REG_OUT_5_INST.LATC.L2(5) [0]
	6:37	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_DATA_REG_OUT_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_STATUS_REG_OUT_26_INST.LATC.L2(26) [0]
	41	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.ECC_CORRECTED_ERROR_LT_INST.LATC.L2(0) [0]
	42	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.ECC_UNCORRECTED_ERROR_LT_INST.LATC.L2(0) [0]
	43	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.ECC_CONFIG_ERR_LT_INST.LATC.L2(0) [0]
	44	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_STATUS_REG_OUT_6_INST.LATC.L2(6) [0]
	45	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_STATUS_REG_OUT_7_INST.LATC.L2(7) [0]
	46	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_STATUS_REG_OUT_8_INST.LATC.L2(8) [0]
	47	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_STATUS_REG_OUT_9_INST.LATC.L2(9) [0]
	48	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_STATUS_REG_OUT_10_INST.LATC.L2(10) [0]
	49	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_STATUS_REG_OUT_11_INST.LATC.L2(11) [0]
	50	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_STATUS_REG_OUT_12_INST.LATC.L2(12) [0]
	51	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_STATUS_REG_OUT_13_INST.LATC.L2(13) [0]
	52	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_STATUS_REG_OUT_14_INST.LATC.L2(14) [0]
	53	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_STATUS_REG_OUT_15_INST.LATC.L2(15) [0]
	54	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_STATUS_REG_OUT_16_INST.LATC.L2(16) [0]
	55	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_STATUS_REG_OUT_17_INST.LATC.L2(17) [0]
	56:59	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_STATUS_REG_OUT_18_INST.LATC.L2(18:21) [0000]
	60:63	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_STATUS_REG_OUT_22_INST.LATC.L2(22:25) [0000]
Bit(s)	SCOM			Dial: Description
0	ROX			BUS_STATUS_ADDR_NVLD_002: address invalid
1	ROX			BUS_STATUS_WRITE_NVLD_002: write invalid
2	ROX			BUS_STATUS_READ_NVLD_002: read invalid
3	ROX			BUS_STATUS_ADDR_P_ERR_002: address parity error
4	ROX			BUS_STATUS_PAR_ERR_002: data parity error
5	ROX			BUS_STATUS_LB_PARITY_ERROR_002: local bus parity error
6:37	ROX			PIB_DATA0TO7_002: 1st 8 bytes of data for read and for write 5ht byte to 12th byte
38:39	RO			constant=0b00
40	ROX			BUS_STATUS_WAITING_IN_I2C_QUEUE_002: operation queue status
41	ROX			ECC_CORRECTED_ERROR_002: This is a warning indicates that one bit flip was there in data and been corrected.
42	ROX			ECC_UNCORRECTED_ERROR_002: This is the error indicating that there are 2 bit flips in read data which cannot be corrected
43	ROX			ECC_CONFIG_ERROR_002: This the error indicating that control register is ecc_enabled for data_length not equal to 8. OR ECC is enabled for the engine where ECC block is not at all instantiated
44	ROX			BUS_STATUS_BUSY_002: local bus busy
45	ROX			BUS_STATUS_INVALID_COMMAND_002: invalid command
46	ROX			BUS_STATUS_PARITY_ERROR_002: parity error
47	ROX			BUS_STATUS_BACK_END_OVERRUN_ERROR_002: back end overrun error
48	ROX			BUS_STATUS_BACK_END_ACCESS_ERROR_002: back end access error
49	ROX			BUS_STATUS_ARBITRATION_LOST_ERROR_002: arbitration lost error
50	ROX			BUS_STATUS_NACK_RECEIVED_ERROR_002: nack receieved error
51	ROX			BUS_STATUS_DATA_REQUEST_002: data request
52	ROX			BUS_STATUS_COMMAND_COMPLETE_002: command complete
53	ROX			BUS_STATUS_STOP_ERROR_002: stop error
54	ROX			BUS_STATUS_I2C_PORT_BUSY_002: i2c port busy
55	ROX			BUS_STATUS_I2C_INTERFACE_BUSY_002: i2c interface busy
56:59	ROX			BUS_STATUS_FIFO_ENTRY_COUNT_002: fifo entry count
60:63	ROX			PCBIF_ERRS_002: PCBIF errors

DATA0to7_REGISTER_FAST_MODE
Addr:	00000000000A2003 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.DATA0TO7_REGISTER_D
Constant(s):	PU_DATA0TO7_REGISTER_D
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_DATA_REG_OUT_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RWX			PIB_DATA0TO7_002: 1st 8 bytes of data for read and for write 5ht byte to 12th byte

FIFO1_REGISTER_READ_B
Addr:	00000000000A2004 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.FIFO1_REGISTER_READ_D
Constant(s):	PU_FIFO1_REGISTER_READ_D
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.FIFO_BITS_OUT_INST.NO_FSILAT.LATCH.LATC.L2(0:7) [00000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:7	ROX			FIFO_BITS_READ0_002: As FIFO is not a normal register, cannot be completely verified in regchk . So this is a dummy register to maintain address in HTML fifo data byte 0 .Should be able to read/write 1 bytes
8:31	RO			constant=0b000000000000000000000000
32:39	ROX			PEEK_DATA1_002: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state
40	ROX			LBUS_PARITY_ERR1_002: local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

COMMAND_REGISTER_D
Addr:	00000000000A2005 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.COMMAND_REGISTER_D
Constant(s):	PU_COMMAND_REGISTER_D
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.CMD_REG_INST.NO_FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0	RWX			WITH_START_002: Decides start command to be issued or not during the beginiing of the operation Decides start command to be issued or not during the beginiing of the operation
1	RWX			WITH_ADDRESS_002: Decides Device address to be send or not during the beginning of the operation Decides Device address to be send or not during the beginning of the operation
2	RWX			READ_CONTINUE_002: Decides Next read operation is continuation of present operation or not Decides Next read operation is continuation of present operation or not
3	RWX			WITH_STOP_002: Decides stop command to be issued or not during the end of the operation Decides stop command to be issued or not during the end of the operation
4:7	RWX			NOT_USED_002: not used not used
8:14	RWX			DEVICE_ADDRESS_002: Device address of Slave on the I2C Bus Device address of Slave on the I2C Bus
15	RWX			READ_NOT_WRITE_002: I2C read or write I2C read or write
16:31	RWX			LENGTH_IN_BYTES_002: Length of Bytes to be accessed through the I2C Bus Length of Bytes to be accessed through the I2C Bus
32:39	ROX			PEEK_DATA1_002: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_002: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

MODE_REGISTER_D
Addr:	00000000000A2006 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.MODE_REGISTER_D
Constant(s):	PU_MODE_REGISTER_D
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.BIT_RATE_DIVISOR_INST.NO_FSILAT.LATCH.LATC.L2(0:15) [0000000000000000]
	16:21	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.MODE_REG_INST.NO_FSILAT.LATCH.LATC.L2(0:5) [000000]
	28:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.MODE_REG_INST.NO_FSILAT.LATCH.LATC.L2(6:9) [0000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:15	RWX			BIT_RATE_DIVISOR_002: Decides the speed on the I2C bus
16:21	RWX			PORT_NUMBER_002: port number
22:27	RO			constant=0b000000
28	RWX			FGAT_MODE_002: fgat mode
29	RWX			DIAG_MODE_002: diag mode
30	RWX			PACING_ALLOW_MODE_002: pacing allow mode
31	RWX			WRAP_MODE_002: wrap_mode
32:39	ROX			PEEK_DATA1_002: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state
40	ROX			LBUS_PARITY_ERR1_002: local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

WATER_MARK_REGISTER_D
Addr:	00000000000A2007 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.WATER_MARK_REGISTER_D
Constant(s):	PU_WATER_MARK_REGISTER_D
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	16:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.WATERMARK_REG_16_INST.NO_FSILAT.LATCH.LATC.L2(16:31) [0000000000000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:15	RO			constant=0b0000000000000000
16:31	RWX			WATERMARK_REG_002: water mark register water mark register
32:39	ROX			PEEK_DATA1_002: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_002: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

INTERRUPT_MASK_REGISTER_D
Addr:	00000000000A2008 (SCOM) 00000000000A2009 (SCOM1) 00000000000A200A (SCOM2)
Name:	TP.TPCHIP.PIB.I2CM.INTERRUPT_MASK_REGISTER_D
Constant(s):	PU_INTERRUPT_MASK_REGISTER_D
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	16:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.INT_MASK_16_INST.NO_FSILAT.LATCH.LATC.L2(16:31) [0000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0:15	RO	RO	RO	constant=0b0000000000000000
16:31	WOX	WOX_OR	WOX_AND	INT_MASK_002: interrupt mask register interrupt mask register
32:63	RO	RO	RO	constant=0b00000000000000000000000000000000

INTERRUPT_MASK_REGISTER_read_D
Addr:	00000000000A2008 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.INTERRUPT_MASK_REGISTER_READ_D
Constant(s):	PU_INTERRUPT_MASK_REGISTER_READ_D
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	16:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.INT_MASK_16_INST.NO_FSILAT.LATCH.LATC.L2(16:31) [0000000000000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:15	RO			constant=0b0000000000000000
16:31	ROX			INT_MASK_002: interrupt mask register interrupt mask register
32:39	ROX			PEEK_DATA1_002: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_002: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

INTERRUPT_CONDITION_D
Addr:	00000000000A2009 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.INTERRUPT_COND_D
Constant(s):	PU_INTERRUPT_COND_D
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	16:21	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(17:22) [000000]
	22	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(11) [0]
	23	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.INT_CONDS(23) [0]
	24	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(23) [0]
	25:26	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.INT_CONDS(25:26) [00]
	28:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.INT_CONDS(28:31) [0000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:15	RO			constant=0b0000000000000000 intterupt conditions
16	ROX			INVALID_CMD_002: invalid command : new command given when old command is not yet completed intterupt conditions
17	ROX			LBUS_PARITY_ERROR_002: local bus parity error intterupt conditions
18	ROX			BE_OV_ERROR_002: back end overrun error : Writing/reading into full/empty fifo resply intterupt conditions
19	ROX			BE_ACC_ERROR_002: back end access error : Writing/Reading more data than requested intterupt conditions
20	ROX			ARBITRATION_LOST_ERROR_002: arbitration lost error: I2C bus is held by someother master when trying to access intterupt conditions
21	ROX			NACK_RECEIVED_ERROR_002: nack receieved error: Slave is not responding back with the ACK. intterupt conditions
22	ROX			DATA_REQUEST_002: data request: FIFO needs to be accesssed some more times to full fill the expectation intterupt conditions
23	ROX			int_conds_cmd_complete_002 intterupt conditions
24	ROX			STOP_ERROR_002: stop error: Didnot able to send the stop condition on the BUS intterupt conditions
25	ROX			int_conds_i2c_busy_002 intterupt conditions
26	ROX			int_conds_not_i2c_busy_002 intterupt conditions
27	RO			constant=0b0 intterupt conditions
28	ROX			int_conds_scl_eq_1_002 intterupt conditions
29	ROX			int_conds_scl_eq_002_002 intterupt conditions
30	ROX			int_conds_sda_eq_1_002 intterupt conditions
31	ROX			int_conds_sda_eq_002_002 intterupt conditions
32:39	ROX			PEEK_DATA1_002: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_002: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

INTERRUPTS_REGISTER_D
Addr:	00000000000A200A (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.INTERRUPTS_D
Constant(s):	PU_INTERRUPTS_D
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.INTS(0:31) [00000000000000000000000000000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:31	ROX			ints_002 interrupts
32:39	ROX			PEEK_DATA1_002: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_002: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

IMM_RESET_I2C_D
Addr:	00000000000A200B (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.IMM_RESET_I2C_D
Constant(s):	PU_IMM_RESET_I2C_D
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_reset_i2c_002 resets command,mode,watermark,interrupt mask,status registers

STATUS_REGISTER_ENGINE_D
Addr:	00000000000A200B (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.STATUS_REGISTER_ENGINE_D
Constant(s):	PU_STATUS_REGISTER_ENGINE_D
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:5	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(17:22) [000000]
	8	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(23) [0]
	20	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.SCL_SYN(0) [0]
	23	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(37) [0]
	28:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.FIFO_LVL.DOUT_INST.NO_FSILAT.LATCH.LATC.L2(0:3) [0000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
	44:47	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.I2CM_PIBM_INTERRUPT_INT_0_INST.LATC.L2(0:3) [0000]
	48:53	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.EXTERNAL_STATUS(12:17) [000000]
Bit(s)	SCOM			Dial: Description
0	ROX			INVALID_CMD_002: invalid command : new command given when old command is not yet completed invalid command : new command given when old command is not yet completed
1	ROX			LBUS_PARITY_ERROR_002: local bus parity error local bus parity error
2	ROX			BE_OV_ERROR_002: back end overrun error : Writing/reading into full/empty fifo resply back end overrun error
3	ROX			BE_ACC_ERROR_002: back end access error : Writing/Reading more data than requested back end access error
4	ROX			ARBITRATION_LOST_ERROR_002: arbitration lost error: I2C bus is held by someother master when trying to access arbitration lost error
5	ROX			NACK_RECEIVED_ERROR_002: nack receieved error: Slave is not responding back with the ACK. nack receieved error
6	ROX			DATA_REQUEST_002: data request: FIFO needs to be accesssed some more times to full fill the expectation data request
7	ROX			cmd_complete_002 command complete : Indicates the completion of command
8	ROX			STOP_ERROR_002: stop error: Didnot able to send the stop condition on the BUS stop error
9:15	ROX			max_num_of_ports_002 maximum number of ports defined for this Engine
16	ROX			any_i2c_int_002 any_i2c_int
17	ROX			waiting_for_i2c_busy_002
18	RO			constant=0b0
19	ROX			i2c_port_history_busy_002 i2c_port_history_busy_002
20	ROX			scl_syn_002 scl_syn
21	ROX			sda_syn_002 sda_syn
22	ROX			i2c_busy_002 i2c busy: I2C bus is occupied
23	ROX			SELF_BUSY_002: self busy: I2C bus is occupied by itself self busy: I2C bus is occupied by itself
24:27	RO			constant=0b0000
28:31	ROX			FIFO_ENTRY_COUNT_002: fifo_entry count : Number of bytes present in the FIFO fifo_entry count : Number of bytes present in the FIFO
32:39	ROX			PEEK_DATA1_002: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_002: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:43	RO			constant=0b000
44:47	ROX			I2CM_STEERED_INTERRUPTS_002: Steered i2cm_interrupt either for fast mode or legacy mode
48:53	ROX			external_status_002
54:63	RO			constant=0b0000000000

EXTENDED_STATUS_B
Addr:	00000000000A200C (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.EXTENDED_STATUS_D
Constant(s):	PU_EXTENDED_STATUS_D
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.FIFO_SIZE(0:7) [00000000]
	11:15	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(39:43) [00000]
	16	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.SCL_SYN(0) [0]
	17	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.SDA_SYN(0) [0]
	18:19	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(46:47) [00]
	20	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(38) [0]
	25	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(37) [0]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:7	ROX			fifo_size_002 total fifo size
8:10	RO			constant=0b000
11:15	ROX			MSM_CURR_STATE_002: current state current state
16	ROX			scl_syn_ext_002 scl_syn
17	ROX			sda_syn_ext_002 sda_syn
18	ROX			s_scl_002 s_scl : clock input for wrap mode
19	ROX			s_sda_002 s_sda : Data input for wrap mode
20	ROX			m_scl_002 m_scl : clock output for wrap mode
21	ROX			m_sda_002 m_sda : data output for wrap mode
22	ROX			high_water_002 high water mark : FIFO reached higest water level
23	ROX			low_water_002 low water mark : FIFO reached lowest water level
24	ROX			i2c_busy_ext_002 i2c busy : I2C bus is busy
25	ROX			SELF_BUSY_002: self busy: I2C bus is occupied by itself self busy : I2C bus is held busy by itself
26:31	RO			constant=0b011001
32:39	ROX			PEEK_DATA1_002: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_002: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

IMM_RESET_ERR_D
Addr:	00000000000A200C (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.IMM_RESET_ERR_D
Constant(s):	PU_IMM_RESET_ERR_D
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_reset_errors_002 resets fifo ,some status bits and state machine

IMM_SET_S_SCL_D
Addr:	00000000000A200D (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.IMM_SET_S_SCL_D
Constant(s):	PU_IMM_SET_S_SCL_D
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_set_s_scl_002 sets output s_scl

RESIDUAL_FRONT_END_BACK_END_LENGTH_D
Addr:	00000000000A200D (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.RESIDUAL_FRONT_END_BACK_END_LENGTH_D
Constant(s):	PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.RESID_FE_LEN_INST.NO_FSILAT.LATCH.LATC.L2(0:15) [0000000000000000]
	16:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.RESID_BE_LEN(0:15) [0000000000000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:15	ROX			RESID_FE_LEN_002: residual front end length register residual front end length register
16:31	ROX			resid_be_len_002 residual back end length register
32:39	ROX			PEEK_DATA1_002: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_002: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

I2C_BUSY_REGISTER_D
Addr:	00000000000A200E (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.I2C_BUSY_REGISTER_D
Constant(s):	PU_I2C_BUSY_REGISTER_D
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:1	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.I2C_BUSY_ALL_0_INST.NO_FSILAT.LATCH.LATC.L2(0:1) [00]
	2:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.I2C_BUSY_REG(2:31) [000000000000000000000000000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:31	ROX			port_busy_002 corresponding port is busy if it is '1' no one should access . If '0' can be accessed. Port/I2C busy register will get reset with SCOM write with a data pattern which has bit 0 - 1 and bit 1 -0 and rest of the bits can be any value. For more details please refere documentation.
32:39	ROX			PEEK_DATA1_002: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_002: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

IMM_RESET_S_SCL_D
Addr:	00000000000A200F (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.IMM_RESET_S_SCL_D
Constant(s):	PU_IMM_RESET_S_SCL_D
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_reset_s_scl_002 resets output s_scl

IMM_SET_S_SDA_D
Addr:	00000000000A2010 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.IMM_SET_S_SDA_D
Constant(s):	PU_IMM_SET_S_SDA_D
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_set_s_sda_002 sets output s_sda

IMM_RESET_S_SDA_D
Addr:	00000000000A2011 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.IMM_RESET_S_SDA_D
Constant(s):	PU_IMM_RESET_S_SDA_D
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_reset_s_sda_002 resets output s_sda

FIFO4_REGISTER_READ_002
Addr:	00000000000A2012 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.FIFO4_REGISTER_READ_D
Constant(s):	PU_FIFO4_REGISTER_READ_D
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.FIFO_BITS_OUT_INST.NO_FSILAT.LATCH.LATC.L2(0:7) [00000000]
	8:15	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.FIFO_BITS_OUT_INST.NO_FSILAT.LATCH.LATC.L2(9:16) [00000000]
	16:23	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.FIFO_BITS_OUT_INST.NO_FSILAT.LATCH.LATC.L2(18:25) [00000000]
	24:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.TP_I2CM_COMP.FIFO_BITS_OUT_INST.NO_FSILAT.LATCH.LATC.L2(27:34) [00000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:7	ROX			FIFO_BITS_READ0_002: As FIFO is not a normal register, cannot be completely verified in regchk . So this is a dummy register to maintain address in HTML fifo data byte 0 .Should be able to read/write 1 bytes
8:15	ROX			fifo_bits_read2_002
16:23	ROX			fifo_bits_read3_002
24:31	ROX			fifo_bits_read4_002
32:39	ROX			PEEK_DATA1_002: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state
40	ROX			LBUS_PARITY_ERR1_002: local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

CC Protect Mode Register
Addr:	00000000000A23FE (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.PIBI2CM_PROTECT_MODE_REG_D
Constant(s):	PU_PIBI2CM_PROTECT_MODE_REG_D
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.PCBIF_COMP.PROTECT_MODE.RD_PROTECT_ENA_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.PCBIF_COMP.PROTECT_MODE.WR_PROTECT_ENA_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	RW			CC_READ_PROTECT_ENABLE_002: Enable read protection
1	RW			CC_WRITE_PROTECT_ENABLE_002: Enable write protection

Atomic Lock Register
Addr:	00000000000A23FF (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.PIBI2CM_ATOMIC_LOCK_REG_D
Constant(s):	PU_PIBI2CM_ATOMIC_LOCK_REG_D
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.PCBIF_COMP.ATOMIC_LOCK.ATOMIC_LOCK_ENA_INST.LATC.L2(0) [0]
	1:4	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.PCBIF_COMP.ATOMIC_LOCK.ATOMIC_ID_Q_INST.LATC.L2(0:3) [0000]
	8:15	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#2.PCBIF_COMP.ATOMIC_LOCK.ATOMIC_LOCK_ACTIVITY_Q_INST.LATC.L2(0:7) [00000000]
Bit(s)	SCOM			Dial: Description
0	RW			CC_ATOMIC_LOCK_ENABLE_002: Enable atomic lock
1:4	ROX			CC_ATOMIC_ID_002: Atomic ID
5:7	RO			constant=0b000
8:15	ROX			CC_ATOMIC_ACTIVITY_002: Atomic lock counter

CONTROl REGISTER_FAST_MODE(Read data is not reliable)
Addr:	00000000000A3000 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.CONTROL_REGISTER_E
Constant(s):	PU_CONTROL_REGISTER_E
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_CNTR_REG_OUT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RWX			PIB_CNTR_REG_BIT_WITHSTART_003: for command register of i2c engine
1	RWX			PIB_CNTR_REG_BIT_WITHADDR_003: for command register of i2c engine
2	RWX			PIB_CNTR_REG_BIT_READCONT_003: for command register of i2c engine
3	RWX			PIB_CNTR_REG_BIT_WITHSTOP_003: for command register of i2c engine
4:7	RWX			PIB_CNTR_REG_LENGTH_003: Maximum_write = 4 , Maximum_read = 8
8:14	RWX			PIB_CNTR_REG_ADDR_003: for command register of i2c engine
15	RWX			PIB_CNTR_REG_BIT_RNW_003: for command register of i2c engine
16:17	RWX			PIB_CNTR_REG_SPEED_003: Bit_rate_divisor value is 00= No change 01= 0x177 10= 0x5E 11= 0x0B
18:22	RWX			PIB_CNTR_REG_PORT_NUMBER_003: for mode register of i2c engine
23:25	RWX			REG_ADDR_LEN_003:  00= No register address in FIFO 01= 1 Byte of FIFO's data is Register address 10= 2 Byte of FIFO's data are Register address 11= 3 Byte of FIFO's data are Register address
26	RWX			ENH_MODE_003: Enable enhanced mode in mode register of I2C engine
27	RWX			ECC_ENABLE_003: Enables ECC for the current operation
28	RWX			ECCCHK_DISABLE_003: Disables ECC checking for Read operation when ECC is enabled
29	RWX			CNTR_UNUSED_003: reserved not used
30:31	RWX			FAST_MODE_INTERRUPT_STERRING_BITS_003: decides which master should see the done interrupt of fast_mode
32:39	RWX			PIB_CNTR_REG_DATA_1_003: data for i2c FIFO
40:47	RWX			PIB_CNTR_REG_DATA_2_003: data for i2c FIFO
48:55	RWX			PIB_CNTR_REG_DATA_3_003: data for i2c FIFO
56:63	RWX			PIB_CNTR_REG_DATA_4_003: data for i2c FIFO

DATA8to15_REGISTER_READ_ONLY_FAST_MODE
Addr:	00000000000A3001 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.DATA8TO15_REGISTER_E
Constant(s):	PU_DATA8TO15_REGISTER_E
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_DATA_REG_OUT_0_INST.LATC.L2(64:127) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	ROX			PIB_DATA8TO15_003: last 8 bytes of data for read and it is not available for Write operation

RESET REGISTER_FAST_MODE
Addr:	00000000000A3001 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.RESET_REGISTER_E
Constant(s):	PU_RESET_REGISTER_E
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.OVERALL_RESET_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	WOX			overall_reset_003 one bit register resets all registers and I2C ENGINE

STATUS REGISTER_FAST_MODE
Addr:	00000000000A3002 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.STATUS_REGISTER_E
Constant(s):	PU_STATUS_REGISTER_E
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_STATUS_REG_OUT_0_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_STATUS_REG_OUT_1_INST.LATC.L2(1) [0]
	2	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_STATUS_REG_OUT_2_INST.LATC.L2(2) [0]
	3	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_STATUS_REG_OUT_3_INST.LATC.L2(3) [0]
	4	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_STATUS_REG_OUT_4_INST.LATC.L2(4) [0]
	5	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_STATUS_REG_OUT_5_INST.LATC.L2(5) [0]
	6:37	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_DATA_REG_OUT_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_STATUS_REG_OUT_26_INST.LATC.L2(26) [0]
	41	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.ECC_CORRECTED_ERROR_LT_INST.LATC.L2(0) [0]
	42	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.ECC_UNCORRECTED_ERROR_LT_INST.LATC.L2(0) [0]
	43	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.ECC_CONFIG_ERR_LT_INST.LATC.L2(0) [0]
	44	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_STATUS_REG_OUT_6_INST.LATC.L2(6) [0]
	45	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_STATUS_REG_OUT_7_INST.LATC.L2(7) [0]
	46	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_STATUS_REG_OUT_8_INST.LATC.L2(8) [0]
	47	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_STATUS_REG_OUT_9_INST.LATC.L2(9) [0]
	48	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_STATUS_REG_OUT_10_INST.LATC.L2(10) [0]
	49	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_STATUS_REG_OUT_11_INST.LATC.L2(11) [0]
	50	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_STATUS_REG_OUT_12_INST.LATC.L2(12) [0]
	51	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_STATUS_REG_OUT_13_INST.LATC.L2(13) [0]
	52	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_STATUS_REG_OUT_14_INST.LATC.L2(14) [0]
	53	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_STATUS_REG_OUT_15_INST.LATC.L2(15) [0]
	54	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_STATUS_REG_OUT_16_INST.LATC.L2(16) [0]
	55	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_STATUS_REG_OUT_17_INST.LATC.L2(17) [0]
	56:59	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_STATUS_REG_OUT_18_INST.LATC.L2(18:21) [0000]
	60:63	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_STATUS_REG_OUT_22_INST.LATC.L2(22:25) [0000]
Bit(s)	SCOM			Dial: Description
0	ROX			BUS_STATUS_ADDR_NVLD_003: address invalid
1	ROX			BUS_STATUS_WRITE_NVLD_003: write invalid
2	ROX			BUS_STATUS_READ_NVLD_003: read invalid
3	ROX			BUS_STATUS_ADDR_P_ERR_003: address parity error
4	ROX			BUS_STATUS_PAR_ERR_003: data parity error
5	ROX			BUS_STATUS_LB_PARITY_ERROR_003: local bus parity error
6:37	ROX			PIB_DATA0TO7_003: 1st 8 bytes of data for read and for write 5ht byte to 12th byte
38:39	RO			constant=0b00
40	ROX			BUS_STATUS_WAITING_IN_I2C_QUEUE_003: operation queue status
41	ROX			ECC_CORRECTED_ERROR_003: This is a warning indicates that one bit flip was there in data and been corrected.
42	ROX			ECC_UNCORRECTED_ERROR_003: This is the error indicating that there are 2 bit flips in read data which cannot be corrected
43	ROX			ECC_CONFIG_ERROR_003: This the error indicating that control register is ecc_enabled for data_length not equal to 8. OR ECC is enabled for the engine where ECC block is not at all instantiated
44	ROX			BUS_STATUS_BUSY_003: local bus busy
45	ROX			BUS_STATUS_INVALID_COMMAND_003: invalid command
46	ROX			BUS_STATUS_PARITY_ERROR_003: parity error
47	ROX			BUS_STATUS_BACK_END_OVERRUN_ERROR_003: back end overrun error
48	ROX			BUS_STATUS_BACK_END_ACCESS_ERROR_003: back end access error
49	ROX			BUS_STATUS_ARBITRATION_LOST_ERROR_003: arbitration lost error
50	ROX			BUS_STATUS_NACK_RECEIVED_ERROR_003: nack receieved error
51	ROX			BUS_STATUS_DATA_REQUEST_003: data request
52	ROX			BUS_STATUS_COMMAND_COMPLETE_003: command complete
53	ROX			BUS_STATUS_STOP_ERROR_003: stop error
54	ROX			BUS_STATUS_I2C_PORT_BUSY_003: i2c port busy
55	ROX			BUS_STATUS_I2C_INTERFACE_BUSY_003: i2c interface busy
56:59	ROX			BUS_STATUS_FIFO_ENTRY_COUNT_003: fifo entry count
60:63	ROX			PCBIF_ERRS_003: PCBIF errors

DATA0to7_REGISTER_FAST_MODE
Addr:	00000000000A3003 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.DATA0TO7_REGISTER_E
Constant(s):	PU_DATA0TO7_REGISTER_E
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_DATA_REG_OUT_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RWX			PIB_DATA0TO7_003: 1st 8 bytes of data for read and for write 5ht byte to 12th byte

FIFO1_REGISTER_READ_E
Addr:	00000000000A3004 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.FIFO1_REGISTER_READ_E
Constant(s):	PU_FIFO1_REGISTER_READ_E
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.FIFO_BITS_OUT_INST.NO_FSILAT.LATCH.LATC.L2(0:7) [00000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:7	ROX			FIFO_BITS_READ0_003: As FIFO is not a normal register, cannot be completely verified in regchk . So this is a dummy register to maintain address in HTML fifo data byte 0 .Should be able to read/write 1 bytes
8:31	RO			constant=0b000000000000000000000000
32:39	ROX			PEEK_DATA1_003: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state
40	ROX			LBUS_PARITY_ERR1_003: local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

COMMAND_REGISTER_B
Addr:	00000000000A3005 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.COMMAND_REGISTER_E
Constant(s):	PU_COMMAND_REGISTER_E
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.CMD_REG_INST.NO_FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0	RWX			WITH_START_003: Decides start command to be issued or not during the beginiing of the operation Decides start command to be issued or not during the beginiing of the operation
1	RWX			WITH_ADDRESS_003: Decides Device address to be send or not during the beginning of the operation Decides Device address to be send or not during the beginning of the operation
2	RWX			READ_CONTINUE_003: Decides Next read operation is continuation of present operation or not Decides Next read operation is continuation of present operation or not
3	RWX			WITH_STOP_003: Decides stop command to be issued or not during the end of the operation Decides stop command to be issued or not during the end of the operation
4:7	RWX			NOT_USED_003: not used not used
8:14	RWX			DEVICE_ADDRESS_003: Device address of Slave on the I2C Bus Device address of Slave on the I2C Bus
15	RWX			READ_NOT_WRITE_003: I2C read or write I2C read or write
16:31	RWX			LENGTH_IN_BYTES_003: Length of Bytes to be accessed through the I2C Bus Length of Bytes to be accessed through the I2C Bus
32:39	ROX			PEEK_DATA1_003: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_003: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

MODE_REGISTER_E
Addr:	00000000000A3006 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.MODE_REGISTER_E
Constant(s):	PU_MODE_REGISTER_E
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.BIT_RATE_DIVISOR_INST.NO_FSILAT.LATCH.LATC.L2(0:15) [0000000000000000]
	16:21	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.MODE_REG_INST.NO_FSILAT.LATCH.LATC.L2(0:5) [000000]
	28:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.MODE_REG_INST.NO_FSILAT.LATCH.LATC.L2(6:9) [0000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:15	RWX			BIT_RATE_DIVISOR_003: Decides the speed on the I2C bus
16:21	RWX			PORT_NUMBER_003: port number
22:27	RO			constant=0b000000
28	RWX			FGAT_MODE_003: fgat mode
29	RWX			DIAG_MODE_003: diag mode
30	RWX			PACING_ALLOW_MODE_003: pacing allow mode
31	RWX			WRAP_MODE_003: wrap_mode
32:39	ROX			PEEK_DATA1_003: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state
40	ROX			LBUS_PARITY_ERR1_003: local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

WATER_MARK_REGISTER_E
Addr:	00000000000A3007 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.WATER_MARK_REGISTER_E
Constant(s):	PU_WATER_MARK_REGISTER_E
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	16:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.WATERMARK_REG_16_INST.NO_FSILAT.LATCH.LATC.L2(16:31) [0000000000000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:15	RO			constant=0b0000000000000000
16:31	RWX			WATERMARK_REG_003: water mark register water mark register
32:39	ROX			PEEK_DATA1_003: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_003: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

INTERRUPT_MASK_REGISTER_E
Addr:	00000000000A3008 (SCOM) 00000000000A3009 (SCOM1) 00000000000A300A (SCOM2)
Name:	TP.TPCHIP.PIB.I2CM.INTERRUPT_MASK_REGISTER_E
Constant(s):	PU_INTERRUPT_MASK_REGISTER_E
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	16:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.INT_MASK_16_INST.NO_FSILAT.LATCH.LATC.L2(16:31) [0000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0:15	RO	RO	RO	constant=0b0000000000000000
16:31	WOX	WOX_OR	WOX_AND	INT_MASK_003: interrupt mask register interrupt mask register
32:63	RO	RO	RO	constant=0b00000000000000000000000000000000

INTERRUPT_MASK_REGISTER_read_E
Addr:	00000000000A3008 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.INTERRUPT_MASK_REGISTER_READ_E
Constant(s):	PU_INTERRUPT_MASK_REGISTER_READ_E
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	16:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.INT_MASK_16_INST.NO_FSILAT.LATCH.LATC.L2(16:31) [0000000000000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:15	RO			constant=0b0000000000000000
16:31	ROX			INT_MASK_003: interrupt mask register interrupt mask register
32:39	ROX			PEEK_DATA1_003: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_003: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

INTERRUPT_CONDITION_E
Addr:	00000000000A3009 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.INTERRUPT_COND_E
Constant(s):	PU_INTERRUPT_COND_E
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	16:21	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(17:22) [000000]
	22	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(11) [0]
	23	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.INT_CONDS(23) [0]
	24	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(23) [0]
	25:26	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.INT_CONDS(25:26) [00]
	28:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.INT_CONDS(28:31) [0000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:15	RO			constant=0b0000000000000000 intterupt conditions
16	ROX			INVALID_CMD_003: invalid command : new command given when old command is not yet completed intterupt conditions
17	ROX			LBUS_PARITY_ERROR_003: local bus parity error intterupt conditions
18	ROX			BE_OV_ERROR_003: back end overrun error : Writing/reading into full/empty fifo resply intterupt conditions
19	ROX			BE_ACC_ERROR_003: back end access error : Writing/Reading more data than requested intterupt conditions
20	ROX			ARBITRATION_LOST_ERROR_003: arbitration lost error: I2C bus is held by someother master when trying to access intterupt conditions
21	ROX			NACK_RECEIVED_ERROR_003: nack receieved error: Slave is not responding back with the ACK. intterupt conditions
22	ROX			DATA_REQUEST_003: data request: FIFO needs to be accesssed some more times to full fill the expectation intterupt conditions
23	ROX			int_conds_cmd_complete_003 intterupt conditions
24	ROX			STOP_ERROR_003: stop error: Didnot able to send the stop condition on the BUS intterupt conditions
25	ROX			int_conds_i2c_busy_003 intterupt conditions
26	ROX			int_conds_not_i2c_busy_003 intterupt conditions
27	RO			constant=0b0 intterupt conditions
28	ROX			int_conds_scl_eq_1_003 intterupt conditions
29	ROX			int_conds_scl_eq_003_003 intterupt conditions
30	ROX			int_conds_sda_eq_1_003 intterupt conditions
31	ROX			int_conds_sda_eq_003_003 intterupt conditions
32:39	ROX			PEEK_DATA1_003: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_003: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

INTERRUPTS_REGISTER_E
Addr:	00000000000A300A (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.INTERRUPTS_E
Constant(s):	PU_INTERRUPTS_E
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.INTS(0:31) [00000000000000000000000000000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:31	ROX			ints_003 interrupts
32:39	ROX			PEEK_DATA1_003: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_003: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

IMM_RESET_I2C_E
Addr:	00000000000A300B (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.IMM_RESET_I2C_E
Constant(s):	PU_IMM_RESET_I2C_E
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_reset_i2c_003 resets command,mode,watermark,interrupt mask,status registers

STATUS_REGISTER_ENGINE_B
Addr:	00000000000A300B (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.STATUS_REGISTER_ENGINE_E
Constant(s):	PU_STATUS_REGISTER_ENGINE_E
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:5	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(17:22) [000000]
	8	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(23) [0]
	20	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.SCL_SYN(0) [0]
	23	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(37) [0]
	28:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.FIFO_LVL.DOUT_INST.NO_FSILAT.LATCH.LATC.L2(0:3) [0000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
	44:47	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.I2CM_PIBM_INTERRUPT_INT_0_INST.LATC.L2(0:3) [0000]
	48:51	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.SECURE_PIBMID_I2C_ACCESS#3.SECURE_PIBMID_I2C_HW_ENABLE.LOCK_PIBMID.LATC.L2(0:3) [0000]
	52:53	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.SECURE_PIBMID_I2C_ACCESS#3.SECURE_PIBMID_I2C_HW_ENABLE.LOCK_PIBMID_STATUS.LATC.L2(0:1) [00]
Bit(s)	SCOM			Dial: Description
0	ROX			INVALID_CMD_003: invalid command : new command given when old command is not yet completed invalid command : new command given when old command is not yet completed
1	ROX			LBUS_PARITY_ERROR_003: local bus parity error local bus parity error
2	ROX			BE_OV_ERROR_003: back end overrun error : Writing/reading into full/empty fifo resply back end overrun error
3	ROX			BE_ACC_ERROR_003: back end access error : Writing/Reading more data than requested back end access error
4	ROX			ARBITRATION_LOST_ERROR_003: arbitration lost error: I2C bus is held by someother master when trying to access arbitration lost error
5	ROX			NACK_RECEIVED_ERROR_003: nack receieved error: Slave is not responding back with the ACK. nack receieved error
6	ROX			DATA_REQUEST_003: data request: FIFO needs to be accesssed some more times to full fill the expectation data request
7	ROX			cmd_complete_003 command complete : Indicates the completion of command
8	ROX			STOP_ERROR_003: stop error: Didnot able to send the stop condition on the BUS stop error
9:15	ROX			max_num_of_ports_003 maximum number of ports defined for this Engine
16	ROX			any_i2c_int_003 any_i2c_int
17	ROX			waiting_for_i2c_busy_003
18	RO			constant=0b0
19	ROX			i2c_port_history_busy_003 i2c_port_history_busy_003
20	ROX			scl_syn_003 scl_syn
21	ROX			sda_syn_003 sda_syn
22	ROX			i2c_busy_003 i2c busy: I2C bus is occupied
23	ROX			SELF_BUSY_003: self busy: I2C bus is occupied by itself self busy: I2C bus is occupied by itself
24:27	RO			constant=0b0000
28:31	ROX			FIFO_ENTRY_COUNT_003: fifo_entry count : Number of bytes present in the FIFO fifo_entry count : Number of bytes present in the FIFO
32:39	ROX			PEEK_DATA1_003: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_003: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:43	RO			constant=0b000
44:47	ROX			I2CM_STEERED_INTERRUPTS_003: Steered i2cm_interrupt either for fast mode or legacy mode
48:53	ROX			EXTERNAL_STATUS_003: status on secured locked master id and status
54:63	RO			constant=0b0000000000

EXTENDED_STATUS_B
Addr:	00000000000A300C (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.EXTENDED_STATUS_E
Constant(s):	PU_EXTENDED_STATUS_E
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.FIFO_SIZE(0:7) [00000000]
	11:15	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(39:43) [00000]
	16	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.SCL_SYN(0) [0]
	17	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.SDA_SYN(0) [0]
	18:19	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(46:47) [00]
	20	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(38) [0]
	25	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.FREE_RUNNING_LATCHES_INST.NO_FSILAT.LATCH.LATC.L2(37) [0]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:7	ROX			fifo_size_003 total fifo size
8:10	RO			constant=0b000
11:15	ROX			MSM_CURR_STATE_003: current state current state
16	ROX			scl_syn_ext_003 scl_syn
17	ROX			sda_syn_ext_003 sda_syn
18	ROX			s_scl_003 s_scl : clock input for wrap mode
19	ROX			s_sda_003 s_sda : Data input for wrap mode
20	ROX			m_scl_003 m_scl : clock output for wrap mode
21	ROX			m_sda_003 m_sda : data output for wrap mode
22	ROX			high_water_003 high water mark : FIFO reached higest water level
23	ROX			low_water_003 low water mark : FIFO reached lowest water level
24	ROX			i2c_busy_ext_003 i2c busy : I2C bus is busy
25	ROX			SELF_BUSY_003: self busy: I2C bus is occupied by itself self busy : I2C bus is held busy by itself
26:31	RO			constant=0b011001
32:39	ROX			PEEK_DATA1_003: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_003: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

IMM_RESET_ERR_E
Addr:	00000000000A300C (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.IMM_RESET_ERR_E
Constant(s):	PU_IMM_RESET_ERR_E
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_reset_errors_003 resets fifo ,some status bits and state machine

IMM_SET_S_SCL_E
Addr:	00000000000A300D (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.IMM_SET_S_SCL_E
Constant(s):	PU_IMM_SET_S_SCL_E
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_set_s_scl_003 sets output s_scl

RESIDUAL_FRONT_END_BACK_END_LENGTH_E
Addr:	00000000000A300D (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.RESIDUAL_FRONT_END_BACK_END_LENGTH_E
Constant(s):	PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.RESID_FE_LEN_INST.NO_FSILAT.LATCH.LATC.L2(0:15) [0000000000000000]
	16:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.RESID_BE_LEN(0:15) [0000000000000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:15	ROX			RESID_FE_LEN_003: residual front end length register residual front end length register
16:31	ROX			resid_be_len_003 residual back end length register
32:39	ROX			PEEK_DATA1_003: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_003: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

I2C_BUSY_REGISTER_E
Addr:	00000000000A300E (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.I2C_BUSY_REGISTER_E
Constant(s):	PU_I2C_BUSY_REGISTER_E
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.I2C_BUSY_ALL_0_INST.NO_FSILAT.LATCH.LATC.L2(0:15) [0000000000000000]
	16:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.I2C_BUSY_REG(16:31) [0000000000000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:31	ROX			port_busy_003 corresponding port is busy if it is '1' no one should access . If '0' can be accessed. Port/I2C busy register will get reset with SCOM write with a data pattern which has bit 0 - 1 and bit 1 -0 and rest of the bits can be any value. For more details please refere documentation.
32:39	ROX			PEEK_DATA1_003: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state ' 0 : invalid command' '1: parity error' '2: back end overrun error' '3: back end access error' '4: arbitration lost error' '5: nack receieved error' '6: data request' '7: state m/c idle '
40	ROX			LBUS_PARITY_ERR1_003: local bus parity error from the local bus to glue logic local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

IMM_RESET_S_SCL_E
Addr:	00000000000A300F (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.IMM_RESET_S_SCL_E
Constant(s):	PU_IMM_RESET_S_SCL_E
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_reset_s_scl_003 resets output s_scl

IMM_SET_S_SDA_E
Addr:	00000000000A3010 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.IMM_SET_S_SDA_E
Constant(s):	PU_IMM_SET_S_SDA_E
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_set_s_sda_003 sets output s_sda

IMM_RESET_S_SDA_E
Addr:	00000000000A3011 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.IMM_RESET_S_SDA_E
Constant(s):	PU_IMM_RESET_S_SDA_E
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			imm_reset_s_sda_003 resets output s_sda

FIFO4_REGISTER_READ_003
Addr:	00000000000A3012 (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.FIFO4_REGISTER_READ_E
Constant(s):	PU_FIFO4_REGISTER_READ_E
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.FIFO_BITS_OUT_INST.NO_FSILAT.LATCH.LATC.L2(0:7) [00000000]
	8:15	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.FIFO_BITS_OUT_INST.NO_FSILAT.LATCH.LATC.L2(9:16) [00000000]
	16:23	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.FIFO_BITS_OUT_INST.NO_FSILAT.LATCH.LATC.L2(18:25) [00000000]
	24:31	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.TP_I2CM_COMP.FIFO_BITS_OUT_INST.NO_FSILAT.LATCH.LATC.L2(27:34) [00000000]
	32:39	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_32_INST.LATC.L2(32:39) [00000000]
	40	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.I2C_REGS_FSM.PIB_READ_DATA_REG_OUT_40_INST.LATC.L2(40) [0]
Bit(s)	SCOM			Dial: Description
0:7	ROX			FIFO_BITS_READ0_003: As FIFO is not a normal register, cannot be completely verified in regchk . So this is a dummy register to maintain address in HTML fifo data byte 0 .Should be able to read/write 1 bytes
8:15	ROX			fifo_bits_read2_003
16:23	ROX			fifo_bits_read3_003
24:31	ROX			fifo_bits_read4_003
32:39	ROX			PEEK_DATA1_003: 0 : invalid command : Written with New command when Old command is still in progress 1: parity error: 2: back end overrun error: Writing/reading into full/empty fifo resply 3: back end access error: Writing/Reading more data than requested 4: arbitration lost error: I2C bus is held by someother master when trying to access 5: nack receieved error: Slave is not responding back with the ACK. 6: data request: FIFO needs to be accesssed some more times to full fill the expectation 7: state m/c idle : I2C state machine is now in idle state
40	ROX			LBUS_PARITY_ERR1_003: local bus parity error from the local bus to glue logic
41:63	RO			constant=0b00000000000000000000000

CC Protect Mode Register
Addr:	00000000000A33FE (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.PIBI2CM_PROTECT_MODE_REG_E
Constant(s):	PU_PIBI2CM_PROTECT_MODE_REG_E
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.PCBIF_COMP.PROTECT_MODE.RD_PROTECT_ENA_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.PCBIF_COMP.PROTECT_MODE.WR_PROTECT_ENA_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	RW			CC_READ_PROTECT_ENABLE_003: Enable read protection
1	RW			CC_WRITE_PROTECT_ENABLE_003: Enable write protection

Atomic Lock Register
Addr:	00000000000A33FF (SCOM)
Name:	TP.TPCHIP.PIB.I2CM.PIBI2CM_ATOMIC_LOCK_REG_E
Constant(s):	PU_PIBI2CM_ATOMIC_LOCK_REG_E
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.PCBIF_COMP.ATOMIC_LOCK.ATOMIC_LOCK_ENA_INST.LATC.L2(0) [0]
	1:4	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.PCBIF_COMP.ATOMIC_LOCK.ATOMIC_ID_Q_INST.LATC.L2(0:3) [0000]
	8:15	TP.TPCHIP.PIB.I2CM.TP_PIB_I2CM_COMP.I2CM_REGS_ENGINE#3.PCBIF_COMP.ATOMIC_LOCK.ATOMIC_LOCK_ACTIVITY_Q_INST.LATC.L2(0:7) [00000000]
Bit(s)	SCOM			Dial: Description
0	RW			CC_ATOMIC_LOCK_ENABLE_003: Enable atomic lock
1:4	ROX			CC_ATOMIC_ID_003: Atomic ID
5:7	RO			constant=0b000
8:15	ROX			CC_ATOMIC_ACTIVITY_003: Atomic lock counter

Dequeuing location of upstream FIFO
Addr:	00000000000B0000 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_UPFIFO_DATA_OUT
Constant(s):	PU_FSB_UPFIFO_DATA_OUT
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.SBE_FIFO_INST1.UPFIFO_DATA_OUT(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	ROX			upfifo_data_out_port

Applying reset function to upstream and downstream FIFO
Addr:	00000000000B0004 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_UPFIFO_RESET
Constant(s):	PU_FSB_UPFIFO_RESET
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			upfifo_reset

Acknowledging EndOfTransfer (EOT)
Addr:	00000000000B0005 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_UPFIFO_ACK_EOT
Constant(s):	PU_FSB_UPFIFO_ACK_EOT
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			upfifo_ack_EOT

Enqueuing location of downstream FIFO
Addr:	00000000000B0010 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_DOWNFIFO_DATA_IN
Constant(s):	PU_FSB_DOWNFIFO_DATA_IN
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.SBE_FIFO_INST1.DNFIFO_DATA_IN(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	WOX			dnfifo_data_in_port

Signaling location for EndOfTransfer (EOT)
Addr:	00000000000B0012 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_DOWNFIFO_SIG_EOT
Constant(s):	PU_FSB_DOWNFIFO_SIG_EOT
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.SBE_FIFO_INST1.DNFIFO_DATA_IN(33) [0]
Bit(s)	SCOM			Dial: Description
0	WOX			dnfifo_signal_EOT

Signaling location for requesting FIFO reset
Addr:	00000000000B0013 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_DOWNFIFO_REQ_RESET
Constant(s):	PU_FSB_DOWNFIFO_REQ_RESET
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			dnfifo_req_reset

Dequeuing location of Host upstream FIFO
Addr:	00000000000B0020 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HUPFIFO_DATA_OUT
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.SBE_FIFO_INST2.UPFIFO_DATA_OUT(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	ROX			hupfifo_data_out_port

Applying reset function to Host upstream and downstream FIFO
Addr:	00000000000B0024 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HUPFIFO_RESET
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			hupfifo_reset

Acknowledging EndOfTransfer (EOT)
Addr:	00000000000B0025 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HUPFIFO_ACK_EOT
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			hupfifo_ack_EOT

Enqueuing location of Host downstream FIFO
Addr:	00000000000B0030 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HDOWNFIFO_DATA_IN
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.SBE_FIFO_INST2.DNFIFO_DATA_IN(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	WOX			hdnfifo_data_in_port

Signaling location for EndOfTransfer (EOT)
Addr:	00000000000B0032 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HDOWNFIFO_SIG_EOT
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.SBE_FIFO_INST2.DNFIFO_DATA_IN(33) [0]
Bit(s)	SCOM			Dial: Description
0	WOX			hdnfifo_signal_EOT

Signaling location for requesting FIFO reset
Addr:	00000000000B0033 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HDOWNFIFO_REQ_RESET
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0	WOX			hdnfifo_req_reset

GPIO input sample
Addr:	00000000000B0050 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.GPIO_INPUT
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.GPIO.DIN.FSILAT.LATCH.LATC.L2(0:2) [000]
Bit(s)	SCOM			Dial: Description
0	RO			DIN_0: Current state of GPIO Input port 0
1	RO			DIN_1: Current state of GPIO Input port 1
2	RO			DIN_2: Current state of GPIO Input port 2

GPIO data out
Addr:	00000000000B0051 (SCOM) 00000000000B0052 (SCOM1) 00000000000B0053 (SCOM2)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.GPIO_OUTPUT
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.GPIO.DOUT.FSILAT.LATCH.LATC.L2(0:2) [000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0	RW	WO_OR	WO_CLEAR	DO_0: Value is driven to GPIO port 0 if corresponding output enable bit is set
1	RW	WO_OR	WO_CLEAR	DO_1: Value is driven to GPIO port 1 if corresponding output enable bit is set
2	RW	WO_OR	WO_CLEAR	DO_2: Value is driven to GPIO port 2 if corresponding output enable bit is set

GPIO data out enable
Addr:	00000000000B0054 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.GPIO_OUTPUT_EN
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.GPIO.ENA.FSILAT.LATCH.LATC.L2(0:2) [000]
Bit(s)	SCOM			Dial: Description
0	RW			DO_EN_0: If set then GPIO port 0 is enabled as an output and the value of the corresponding GPIO Output is applied. A LBUS reset does NOT effect that enable bit.
1	RW			DO_EN_1: If set then GPIO port 1 is enabled as an output and the value of the corresponding GPIO Output is applied. A LBUS reset does NOT effect that enable bit.
2	RW			DO_EN_2: If set then GPIO port 2 is enabled as an output and the value of the corresponding GPIO Output is applied. A LBUS reset does NOT effect that enable bit.

GPIO interrupt status
Addr:	00000000000B0057 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.GPIO_INT_STATUS
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.GPIO.INT_REG_LTH.FSILAT.LATCH.LATC.L2(0:2) [000]
Bit(s)	SCOM			Dial: Description
0	RO			INT_STAT_0: Displays the interrupt status (latched) of GPIO port 0 A pending interrupt can be acknowledged (cleared) through writing a logical one value to that bit position
1	RO			INT_STAT_1: Displays the interrupt status (latched) of GPIO port 1 A pending interrupt can be acknowledged (cleared) through writing a logical one value to that bit position
2	RO			INT_STAT_2: Displays the interrupt status (latched) of GPIO port 2 A pending interrupt can be acknowledged (cleared) through writing a logical one value to that bit position

GPIO mode
Addr:	00000000000B0059 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.GPIO_MODE
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:4	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.GPIO.MODE_REG(0:4) [00000]
Bit(s)	SCOM			Dial: Description
0:4	RO			num_gpio_ports Number of available GPIO ports minus one. Just add one to that value to get the number of available ports.

GPIO interrupt polarity
Addr:	00000000000B005C (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.GPIO_INT_POLARITY
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.GPIO.POL_LTH.FSILAT.LATCH.LATC.L2(0:2) [000]
Bit(s)	SCOM			Dial: Description
0	RW			INT_POL_0: Used to define the signal level of GPIO port 0 for triggering an interrupt
1	RW			INT_POL_1: Used to define the signal level of GPIO port 1 for triggering an interrupt
2	RW			INT_POL_2: Used to define the signal level of GPIO port 2 for triggering an interrupt

GPIO interrupt enable
Addr:	00000000000B005D (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.GPIO_INT_ENABLE
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.GPIO.INT_ENA_LTH.FSILAT.LATCH.LATC.L2(0:2) [000]
Bit(s)	SCOM			Dial: Description
0	RW			INT_EN_0: Controls interrupt propagation of GPIO port 0. If enabled then an active interrupt will be captured and propagated.
1	RW			INT_EN_1: Controls interrupt propagation of GPIO port 1. If enabled then an active interrupt will be captured and propagated.
2	RW			INT_EN_2: Controls interrupt propagation of GPIO port 2. If enabled then an active interrupt will be captured and propagated.

GPIO interrupt condition for port 0 to 2.
Addr:	00000000000B005E (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.GPIO_INT_COND
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.GPIO.INT_COND(0:2) [000]
Bit(s)	SCOM			Dial: Description
0	RO			int_cond_0
1	RO			int_cond_1
2	RO			int_cond_2

Trigger/SET SBE2FSI Interrupt
Addr:	00000000000B0071 (SCOM)
Name:	TP.TPVSB.FSI.W.FSI_SBE_FIFO.SBE2FSI_INTR_SET
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSBCOMP.Q_SBE2FSI_INTR_LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	WO_OR			SBE2FSI_INTR_STATUS_VEC: Displays SBE-triggered interrupts

spi master error inject register
Addr:	00000000000C0000 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST0_ERROR_INJECT_
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST0.CONFIG.ERROR_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:7	RWX			SPIMST0_ERROR_INJECT_PULSE: error inject pulse
8:15	RWX			SPIMST0_ERROR_INJECT_MASK: error inject mask
16:31	RWX			SPIMST0_ERROR_MASK: error mask
32:63	RWX			SPIMST0_ERROR_UNUSED: error unused

spi master counter configuration register
Addr:	00000000000C0001 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST0_COUNTER
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST0.CONFIG.COUNTER_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:7	RWX			SPIMST0_COUNT_N1: counter N1 register
8:15	RWX			SPIMST0_COUNT_N2: counter N1 register
16:23	RWX			SPIMST0_COUNT_RESERVED_A: counter reserved area a register
24:31	RWX			SPIMST0_LOOPCOUNT: loop count compare register for BNEI operation
32:39	RWX			SPIMST0_LOOPCOUNT2: loop count 2 compare register for BNEI2 operation
40:47	RWX			SPIMST0_SHIFTER_FSM_CONTROL: shifter fsm control bits
48:51	RWX			SPIMST0_N1_CONTROL: shift counter N1 control bits
52:55	RWX			SPIMST0_N2_CONTROL: shift counter N2 control bits
56:63	RWX			SPIMST0_COUNT_RESERVED_B: counter reserved area b register

spi master configuration 1 register
Addr:	00000000000C0002 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST0_CONFIG1
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST0.CONFIG.CONFIG1_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	ROX			SPIMST0_SPI_RESOURCE_LOCK: reserved
1:4	ROX			SPIMST0_PIB_MASTER_ID: PIB master id that has reserved the device
5:63	RWX			SPIMST0_CONFIG1_REG_UNUSED: reserved register space

spi master clock configuration register
Addr:	00000000000C0003 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST0_CLOCK_CONFIG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST0.CONFIG.CLOCK_CONFIG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:11	RWX			SPIMST0_SCK_CLOCK_DIVIDER: SCK_clock_divider
12:19	RWX			SPIMST0_SCK_RECEIVE_DELAY: SCK_receive_delay
20	RWX			SPIMST0_ENABLE_RECEIVE_PACING: enable_receive_pacing
21	RWX			SPIMST0_SPIMST_TRACE_ENABLE: SCK clock_phase
22:23	RWX			SPIMST0_SCK_TRACE_SELECT: trace_select
24:27	RWX			SPIMST0_SCK_RESET_CONTROL: reset_control
28	RWX			SPIMST0_SCK_ECC_SPIMM_ADDR_CORR_DIS: SCK_ecc_spimm_addr_corr_dis
29:30	RWX			SPIMST0_SCK_ECC_CONTROL: ecc_control
31	RWX			SPIMST0_SCK_MMSPISM_ENABLE: mmSPIsm_enable
32:35	RWX			SPIMST0_SPI_SLAVE_RESET: hardware reset signal for spi slave
36	RWX			SPIMST0_LOOPBACK_ENABLE: loopback mode enable
37:63	RWX			SPIMST0_CLOCK_CONFIG_RESERVED: clock config reserved

spi master pattern match register
Addr:	00000000000C0004 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST0_MEMORY_MAPPING
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST0.CONFIG.MEMORY_MAPPING_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:15	RWX			SPIMST0_MEMORY_MAPPING_BASE: memory mapping address base
16:31	RWX			SPIMST0_MEMORY_MAPPING_MASK: memory mapping address mask
32:47	RWX			SPIMST0_PATTERN_MATCH_COMPARE: serial receive pattern match compare value
48:63	RWX			SPIMST0_PATTERN_MATCH_MASK: serial receive pattern match compare value

spi master transmit data register
Addr:	00000000000C0005 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST0_TRANSMIT_DATA_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST0.CONFIG.TRANSMIT_DATA_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RWX			SPIMST0_TRANSMIT_DATA_REG_Q: spi master tranmsit data register

spi master receive data register
Addr:	00000000000C0006 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST0_RECEIVE_DATA_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST0.CONFIG.RECEIVE_DATA_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	ROX			SPIMST0_RECEIVE_DATA_REG_Q: spi master receive data register

spi master sequencer operation register
Addr:	00000000000C0007 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST0_SEQUENCER_OP_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST0.CONFIG.SEQUENCER_OP_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RWX			SPIMST0_SEQUENCER_OP_Q: spi master sequencer operation register

spi master status register
Addr:	00000000000C0008 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST0_STATUS_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.PIB.SPIMC.SPIMST0.CONFIG.SPI_CONFIG_FUNC_Q_INST.NO_FSILAT.LATCH.LATC.L2(12:15) [0000]
	4:7	TP.TPCHIP.PIB.SPIMC.SPIMST0.CONFIG.SPI_CONFIG_FUNC_Q_INST.NO_FSILAT.LATCH.LATC.L2(8:11) [0000]
	8:15	TP.TPCHIP.PIB.SPIMC.SPIMST0.SEQ.FUNC_SEQUENCER_LATCHES_Q_INST.NO_FSILAT.LATCH.LATC.L2(16:23) [00000000]
	16:27	TP.TPCHIP.PIB.SPIMC.SPIMST0.SHIFT.FUNC_SHIFTER_LATCHES_Q_INST.NO_FSILAT.LATCH.LATC.L2(24:35) [000000000000]
	28:31	TP.TPCHIP.PIB.SPIMC.SPIMST0.SEQ.FUNC_SEQUENCER_LATCHES_Q_INST.NO_FSILAT.LATCH.LATC.L2(4:7) [0000]
	32:63	TP.TPCHIP.PIB.SPIMC.SPIMST0.CONFIG.SPI_STATUS_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RWX			SPIMST0_RDR_FULL_STATUS: indication for receive data register full
1	RWX			SPIMST0_RDR_OVER_STATUS: indication for receive data register overrun
2	RWX			SPIMST0_RDR_UNDER_STATUS: indication for receive data register underrun
3	RWX			SPIMST0_RDR_RESERVED_STATUS: indication for receive data register reserved status, unused
4	RWX			SPIMST0_TDR_FULL_STATUS: indication for transmit data register full
5	RWX			SPIMST0_TDR_OVER_STATUS: indication for transmit data register overrun
6	RWX			SPIMST0_TDR_UNDER_STATUS: indication for transmit data register underrun
7	RWX			SPIMST0_TDR_RESERVED_STATUS: indication for transmit data register reserved status, unused
8:15	ROX			SPIMST0_SEQUENCER_FSM: sequencer finit state machine bit coding
16:27	ROX			SPIMST0_SHIFTER_FSM: shifter finit state machine bit coding
28:31	ROX			SPIMST0_SEQUENCER_OP_INDEX: sequencer operation index
32	RWX			SPIMST0_COUNTER_REG_PARITY_ERRS: counter configuration register parity error
33	RWX			SPIMST0_CLOCK_REG_PARITY_ERR: clock configuration register parity error
34	RWX			SPIMST0_SEQUENCER_REG_PARITY_ERR: sequencer configuration register parity error
35	RWX			SPIMST0_SEQUENCER_FSM_PARITY_ERR: sequencer fsm parity error
36	RWX			SPIMST0_SHIFTER_FSM_PARITY_ERR: shifter fsm parity error
37	RWX			SPIMST0_PATTERN_REG_PARITY_ERR: pattern match register parity error
38	RWX			SPIMST0_TDR_REG_PARITY_ERR: transmit data register parity error
39	RWX			SPIMST0_RDR_REG_PARITY_ERR: receive data register parity error
40	RWX			SPIMST0_CONFIG_REG1_PARITY_ERR: configuration register 1 parity error
41	RWX			SPIMST0_UNUSED_PARITY_ERR: unused
42	RWX			SPIMST0_ERROR_REG_PARITY_ERR: error register parity error
43	RWX			SPIMST0_ECC_CORRECTABLE_ERR: ecc correctable error
44	RWX			SPIMST0_ECC_UNCORRECTABLE_ERR: ecc uncorrectable error
45:46	RWX			SPIMST0_ECC_STATUS: general ecc status (unsued)
47	RWX			SPIMST0_MM_ADDR_OVERLAP: memory mapped SPI address overlap
48:49	RWX			SPIMST0_ACCESS_VIOLATION: general access violation
50	RWX			SPIMST0_PORT_MULTIPLEXER_ERR: port multiplexer error
51	RWX			SPIMST0_ADDR_OUT_OF_RANGE: address range error
52	RWX			SPIMST0_MEM_MAPPING_OVERLAP: memory mapping overlap error
53	RWX			SPIMST0_SEQUENCER_SLAVE_SEL_ERR: sequencer slave select error
54	RWX			SPIMST0_SEQUENCER_FSM_ERR: sequencer fsm error
55	RWX			SPIMST0_SHIFTER_FSM_ERR: shifter fsm error
56	RWX			SPIMST0_ANY_CONFIG_PARITY_ERR: any config parity error
57	RWX			SPIMST0_SPI_PORT_MUX_INDICATOR: indication of SPI port multiplexer, must indicate zero for this SPI to run
58	RWX			SPIMST0_SPI_SEC_PIB_RETRY_RSP_INFO: indication of SPI security problem during PIB Write access
59:63	RWX			SPIMST0_UNUSED: unused

spi master error inject register
Addr:	00000000000C0020 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST1_ERROR_INJECT_
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST1.CONFIG.ERROR_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:7	RWX			SPIMST1_ERROR_INJECT_PULSE: error inject pulse
8:15	RWX			SPIMST1_ERROR_INJECT_MASK: error inject mask
16:31	RWX			SPIMST1_ERROR_MASK: error mask
32:63	RWX			SPIMST1_ERROR_UNUSED: error unused

spi master counter configuration register
Addr:	00000000000C0021 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST1_COUNTER
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST1.CONFIG.COUNTER_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:7	RWX			SPIMST1_COUNT_N1: counter N1 register
8:15	RWX			SPIMST1_COUNT_N2: counter N1 register
16:23	RWX			SPIMST1_COUNT_RESERVED_A: counter reserved area a register
24:31	RWX			SPIMST1_LOOPCOUNT: loop count compare register for BNEI operation
32:39	RWX			SPIMST1_LOOPCOUNT2: loop count 2 compare register for BNEI2 operation
40:47	RWX			SPIMST1_SHIFTER_FSM_CONTROL: shifter fsm control bits
48:51	RWX			SPIMST1_N1_CONTROL: shift counter N1 control bits
52:55	RWX			SPIMST1_N2_CONTROL: shift counter N2 control bits
56:63	RWX			SPIMST1_COUNT_RESERVED_B: counter reserved area b register

spi master configuration 1 register
Addr:	00000000000C0022 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST1_CONFIG1
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST1.CONFIG.CONFIG1_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	ROX			SPIMST1_SPI_RESOURCE_LOCK: reserved
1:4	ROX			SPIMST1_PIB_MASTER_ID: PIB master id that has reserved the device
5:63	RWX			SPIMST1_CONFIG1_REG_UNUSED: reserved register space

spi master clock configuration register
Addr:	00000000000C0023 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST1_CLOCK_CONFIG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST1.CONFIG.CLOCK_CONFIG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:11	RWX			SPIMST1_SCK_CLOCK_DIVIDER: SCK_clock_divider
12:19	RWX			SPIMST1_SCK_RECEIVE_DELAY: SCK_receive_delay
20	RWX			SPIMST1_ENABLE_RECEIVE_PACING: enable_receive_pacing
21	RWX			SPIMST1_SPIMST_TRACE_ENABLE: SCK clock_phase
22:23	RWX			SPIMST1_SCK_TRACE_SELECT: trace_select
24:27	RWX			SPIMST1_SCK_RESET_CONTROL: reset_control
28	RWX			SPIMST1_SCK_ECC_SPIMM_ADDR_CORR_DIS: SCK_ecc_spimm_addr_corr_dis
29:30	RWX			SPIMST1_SCK_ECC_CONTROL: ecc_control
31	RWX			SPIMST1_SCK_MMSPISM_ENABLE: mmSPIsm_enable
32:35	RWX			SPIMST1_SPI_SLAVE_RESET: hardware reset signal for spi slave
36	RWX			SPIMST1_LOOPBACK_ENABLE: loopback mode enable
37:63	RWX			SPIMST1_CLOCK_CONFIG_RESERVED: clock config reserved

spi master pattern match register
Addr:	00000000000C0024 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST1_MEMORY_MAPPING
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST1.CONFIG.MEMORY_MAPPING_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:15	RWX			SPIMST1_MEMORY_MAPPING_BASE: memory mapping address base
16:31	RWX			SPIMST1_MEMORY_MAPPING_MASK: memory mapping address mask
32:47	RWX			SPIMST1_PATTERN_MATCH_COMPARE: serial receive pattern match compare value
48:63	RWX			SPIMST1_PATTERN_MATCH_MASK: serial receive pattern match compare value

spi master transmit data register
Addr:	00000000000C0025 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST1_TRANSMIT_DATA_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST1.CONFIG.TRANSMIT_DATA_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RWX			SPIMST1_TRANSMIT_DATA_REG_Q: spi master tranmsit data register

spi master receive data register
Addr:	00000000000C0026 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST1_RECEIVE_DATA_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST1.CONFIG.RECEIVE_DATA_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	ROX			SPIMST1_RECEIVE_DATA_REG_Q: spi master receive data register

spi master sequencer operation register
Addr:	00000000000C0027 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST1_SEQUENCER_OP_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST1.CONFIG.SEQUENCER_OP_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RWX			SPIMST1_SEQUENCER_OP_Q: spi master sequencer operation register

spi master status register
Addr:	00000000000C0028 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST1_STATUS_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.PIB.SPIMC.SPIMST1.CONFIG.SPI_CONFIG_FUNC_Q_INST.NO_FSILAT.LATCH.LATC.L2(12:15) [0000]
	4:7	TP.TPCHIP.PIB.SPIMC.SPIMST1.CONFIG.SPI_CONFIG_FUNC_Q_INST.NO_FSILAT.LATCH.LATC.L2(8:11) [0000]
	8:15	TP.TPCHIP.PIB.SPIMC.SPIMST1.SEQ.FUNC_SEQUENCER_LATCHES_Q_INST.NO_FSILAT.LATCH.LATC.L2(16:23) [00000000]
	16:27	TP.TPCHIP.PIB.SPIMC.SPIMST1.SHIFT.FUNC_SHIFTER_LATCHES_Q_INST.NO_FSILAT.LATCH.LATC.L2(24:35) [000000000000]
	28:31	TP.TPCHIP.PIB.SPIMC.SPIMST1.SEQ.FUNC_SEQUENCER_LATCHES_Q_INST.NO_FSILAT.LATCH.LATC.L2(4:7) [0000]
	32:63	TP.TPCHIP.PIB.SPIMC.SPIMST1.CONFIG.SPI_STATUS_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RWX			SPIMST1_RDR_FULL_STATUS: indication for receive data register full
1	RWX			SPIMST1_RDR_OVER_STATUS: indication for receive data register overrun
2	RWX			SPIMST1_RDR_UNDER_STATUS: indication for receive data register underrun
3	RWX			SPIMST1_RDR_RESERVED_STATUS: indication for receive data register reserved status, unused
4	RWX			SPIMST1_TDR_FULL_STATUS: indication for transmit data register full
5	RWX			SPIMST1_TDR_OVER_STATUS: indication for transmit data register overrun
6	RWX			SPIMST1_TDR_UNDER_STATUS: indication for transmit data register underrun
7	RWX			SPIMST1_TDR_RESERVED_STATUS: indication for transmit data register reserved status, unused
8:15	ROX			SPIMST1_SEQUENCER_FSM: sequencer finit state machine bit coding
16:27	ROX			SPIMST1_SHIFTER_FSM: shifter finit state machine bit coding
28:31	ROX			SPIMST1_SEQUENCER_OP_INDEX: sequencer operation index
32	RWX			SPIMST1_COUNTER_REG_PARITY_ERRS: counter configuration register parity error
33	RWX			SPIMST1_CLOCK_REG_PARITY_ERR: clock configuration register parity error
34	RWX			SPIMST1_SEQUENCER_REG_PARITY_ERR: sequencer configuration register parity error
35	RWX			SPIMST1_SEQUENCER_FSM_PARITY_ERR: sequencer fsm parity error
36	RWX			SPIMST1_SHIFTER_FSM_PARITY_ERR: shifter fsm parity error
37	RWX			SPIMST1_PATTERN_REG_PARITY_ERR: pattern match register parity error
38	RWX			SPIMST1_TDR_REG_PARITY_ERR: transmit data register parity error
39	RWX			SPIMST1_RDR_REG_PARITY_ERR: receive data register parity error
40	RWX			SPIMST1_CONFIG_REG1_PARITY_ERR: configuration register 1 parity error
41	RWX			SPIMST1_UNUSED_PARITY_ERR: unused
42	RWX			SPIMST1_ERROR_REG_PARITY_ERR: error register parity error
43	RWX			SPIMST1_ECC_CORRECTABLE_ERR: ecc correctable error
44	RWX			SPIMST1_ECC_UNCORRECTABLE_ERR: ecc uncorrectable error
45:46	RWX			SPIMST1_ECC_STATUS: general ecc status (unsued)
47	RWX			SPIMST1_MM_ADDR_OVERLAP: memory mapped SPI address overlap
48:49	RWX			SPIMST1_ACCESS_VIOLATION: general access violation
50	RWX			SPIMST1_PORT_MULTIPLEXER_ERR: port multiplexer error
51	RWX			SPIMST1_ADDR_OUT_OF_RANGE: address range error
52	RWX			SPIMST1_MEM_MAPPING_OVERLAP: memory mapping overlap error
53	RWX			SPIMST1_SEQUENCER_SLAVE_SEL_ERR: sequencer slave select error
54	RWX			SPIMST1_SEQUENCER_FSM_ERR: sequencer fsm error
55	RWX			SPIMST1_SHIFTER_FSM_ERR: shifter fsm error
56	RWX			SPIMST1_ANY_CONFIG_PARITY_ERR: any config parity error
57	RWX			SPIMST1_SPI_PORT_MUX_INDICATOR: indication of SPI port multiplexer, must indicate zero for this SPI to run
58	RWX			SPIMST1_SPI_SEC_PIB_RETRY_RSP_INFO: indication of SPI security problem during PIB Write access
59:63	RWX			SPIMST1_UNUSED: unused

spi master error inject register
Addr:	00000000000C0040 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST2_ERROR_INJECT_
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST2.CONFIG.ERROR_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:7	RWX			SPIMST2_ERROR_INJECT_PULSE: error inject pulse
8:15	RWX			SPIMST2_ERROR_INJECT_MASK: error inject mask
16:31	RWX			SPIMST2_ERROR_MASK: error mask
32:63	RWX			SPIMST2_ERROR_UNUSED: error unused

spi master counter configuration register
Addr:	00000000000C0041 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST2_COUNTER
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST2.CONFIG.COUNTER_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:7	RWX			SPIMST2_COUNT_N1: counter N1 register
8:15	RWX			SPIMST2_COUNT_N2: counter N1 register
16:23	RWX			SPIMST2_COUNT_RESERVED_A: counter reserved area a register
24:31	RWX			SPIMST2_LOOPCOUNT: loop count compare register for BNEI operation
32:39	RWX			SPIMST2_LOOPCOUNT2: loop count 2 compare register for BNEI2 operation
40:47	RWX			SPIMST2_SHIFTER_FSM_CONTROL: shifter fsm control bits
48:51	RWX			SPIMST2_N1_CONTROL: shift counter N1 control bits
52:55	RWX			SPIMST2_N2_CONTROL: shift counter N2 control bits
56:63	RWX			SPIMST2_COUNT_RESERVED_B: counter reserved area b register

spi master configuration 1 register
Addr:	00000000000C0042 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST2_CONFIG1
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST2.CONFIG.CONFIG1_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	ROX			SPIMST2_SPI_RESOURCE_LOCK: reserved
1:4	ROX			SPIMST2_PIB_MASTER_ID: PIB master id that has reserved the device
5:63	RWX			SPIMST2_CONFIG1_REG_UNUSED: reserved register space

spi master clock configuration register
Addr:	00000000000C0043 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST2_CLOCK_CONFIG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST2.CONFIG.CLOCK_CONFIG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:11	RWX			SPIMST2_SCK_CLOCK_DIVIDER: SCK_clock_divider
12:19	RWX			SPIMST2_SCK_RECEIVE_DELAY: SCK_receive_delay
20	RWX			SPIMST2_ENABLE_RECEIVE_PACING: enable_receive_pacing
21	RWX			SPIMST2_SPIMST_TRACE_ENABLE: SCK clock_phase
22:23	RWX			SPIMST2_SCK_TRACE_SELECT: trace_select
24:27	RWX			SPIMST2_SCK_RESET_CONTROL: reset_control
28	RWX			SPIMST2_SCK_ECC_SPIMM_ADDR_CORR_DIS: SCK_ecc_spimm_addr_corr_dis
29:30	RWX			SPIMST2_SCK_ECC_CONTROL: ecc_control
31	RWX			SPIMST2_SCK_MMSPISM_ENABLE: mmSPIsm_enable
32:35	RWX			SPIMST2_SPI_SLAVE_RESET: hardware reset signal for spi slave
36	RWX			SPIMST2_LOOPBACK_ENABLE: loopback mode enable
37:63	RWX			SPIMST2_CLOCK_CONFIG_RESERVED: clock config reserved

spi master pattern match register
Addr:	00000000000C0044 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST2_MEMORY_MAPPING
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST2.CONFIG.MEMORY_MAPPING_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:15	RWX			SPIMST2_MEMORY_MAPPING_BASE: memory mapping address base
16:31	RWX			SPIMST2_MEMORY_MAPPING_MASK: memory mapping address mask
32:47	RWX			SPIMST2_PATTERN_MATCH_COMPARE: serial receive pattern match compare value
48:63	RWX			SPIMST2_PATTERN_MATCH_MASK: serial receive pattern match compare value

spi master transmit data register
Addr:	00000000000C0045 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST2_TRANSMIT_DATA_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST2.CONFIG.TRANSMIT_DATA_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RWX			SPIMST2_TRANSMIT_DATA_REG_Q: spi master tranmsit data register

spi master receive data register
Addr:	00000000000C0046 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST2_RECEIVE_DATA_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST2.CONFIG.RECEIVE_DATA_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	ROX			SPIMST2_RECEIVE_DATA_REG_Q: spi master receive data register

spi master sequencer operation register
Addr:	00000000000C0047 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST2_SEQUENCER_OP_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST2.CONFIG.SEQUENCER_OP_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RWX			SPIMST2_SEQUENCER_OP_Q: spi master sequencer operation register

spi master status register
Addr:	00000000000C0048 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST2_STATUS_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.PIB.SPIMC.SPIMST2.CONFIG.SPI_CONFIG_FUNC_Q_INST.NO_FSILAT.LATCH.LATC.L2(12:15) [0000]
	4:7	TP.TPCHIP.PIB.SPIMC.SPIMST2.CONFIG.SPI_CONFIG_FUNC_Q_INST.NO_FSILAT.LATCH.LATC.L2(8:11) [0000]
	8:15	TP.TPCHIP.PIB.SPIMC.SPIMST2.SEQ.FUNC_SEQUENCER_LATCHES_Q_INST.NO_FSILAT.LATCH.LATC.L2(16:23) [00000000]
	16:27	TP.TPCHIP.PIB.SPIMC.SPIMST2.SHIFT.FUNC_SHIFTER_LATCHES_Q_INST.NO_FSILAT.LATCH.LATC.L2(24:35) [000000000000]
	28:31	TP.TPCHIP.PIB.SPIMC.SPIMST2.SEQ.FUNC_SEQUENCER_LATCHES_Q_INST.NO_FSILAT.LATCH.LATC.L2(4:7) [0000]
	32:63	TP.TPCHIP.PIB.SPIMC.SPIMST2.CONFIG.SPI_STATUS_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RWX			SPIMST2_RDR_FULL_STATUS: indication for receive data register full
1	RWX			SPIMST2_RDR_OVER_STATUS: indication for receive data register overrun
2	RWX			SPIMST2_RDR_UNDER_STATUS: indication for receive data register underrun
3	RWX			SPIMST2_RDR_RESERVED_STATUS: indication for receive data register reserved status, unused
4	RWX			SPIMST2_TDR_FULL_STATUS: indication for transmit data register full
5	RWX			SPIMST2_TDR_OVER_STATUS: indication for transmit data register overrun
6	RWX			SPIMST2_TDR_UNDER_STATUS: indication for transmit data register underrun
7	RWX			SPIMST2_TDR_RESERVED_STATUS: indication for transmit data register reserved status, unused
8:15	ROX			SPIMST2_SEQUENCER_FSM: sequencer finit state machine bit coding
16:27	ROX			SPIMST2_SHIFTER_FSM: shifter finit state machine bit coding
28:31	ROX			SPIMST2_SEQUENCER_OP_INDEX: sequencer operation index
32	RWX			SPIMST2_COUNTER_REG_PARITY_ERRS: counter configuration register parity error
33	RWX			SPIMST2_CLOCK_REG_PARITY_ERR: clock configuration register parity error
34	RWX			SPIMST2_SEQUENCER_REG_PARITY_ERR: sequencer configuration register parity error
35	RWX			SPIMST2_SEQUENCER_FSM_PARITY_ERR: sequencer fsm parity error
36	RWX			SPIMST2_SHIFTER_FSM_PARITY_ERR: shifter fsm parity error
37	RWX			SPIMST2_PATTERN_REG_PARITY_ERR: pattern match register parity error
38	RWX			SPIMST2_TDR_REG_PARITY_ERR: transmit data register parity error
39	RWX			SPIMST2_RDR_REG_PARITY_ERR: receive data register parity error
40	RWX			SPIMST2_CONFIG_REG1_PARITY_ERR: configuration register 1 parity error
41	RWX			SPIMST2_UNUSED_PARITY_ERR: unused
42	RWX			SPIMST2_ERROR_REG_PARITY_ERR: error register parity error
43	RWX			SPIMST2_ECC_CORRECTABLE_ERR: ecc correctable error
44	RWX			SPIMST2_ECC_UNCORRECTABLE_ERR: ecc uncorrectable error
45:46	RWX			SPIMST2_ECC_STATUS: general ecc status (unsued)
47	RWX			SPIMST2_MM_ADDR_OVERLAP: memory mapped SPI address overlap
48:49	RWX			SPIMST2_ACCESS_VIOLATION: general access violation
50	RWX			SPIMST2_PORT_MULTIPLEXER_ERR: port multiplexer error
51	RWX			SPIMST2_ADDR_OUT_OF_RANGE: address range error
52	RWX			SPIMST2_MEM_MAPPING_OVERLAP: memory mapping overlap error
53	RWX			SPIMST2_SEQUENCER_SLAVE_SEL_ERR: sequencer slave select error
54	RWX			SPIMST2_SEQUENCER_FSM_ERR: sequencer fsm error
55	RWX			SPIMST2_SHIFTER_FSM_ERR: shifter fsm error
56	RWX			SPIMST2_ANY_CONFIG_PARITY_ERR: any config parity error
57	RWX			SPIMST2_SPI_PORT_MUX_INDICATOR: indication of SPI port multiplexer, must indicate zero for this SPI to run
58	RWX			SPIMST2_SPI_SEC_PIB_RETRY_RSP_INFO: indication of SPI security problem during PIB Write access
59:63	RWX			SPIMST2_UNUSED: unused

spi master error inject register
Addr:	00000000000C0060 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST3_ERROR_INJECT_
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST3.CONFIG.ERROR_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:7	RWX			SPIMST3_ERROR_INJECT_PULSE: error inject pulse
8:15	RWX			SPIMST3_ERROR_INJECT_MASK: error inject mask
16:31	RWX			SPIMST3_ERROR_MASK: error mask
32:63	RWX			SPIMST3_ERROR_UNUSED: error unused

spi master counter configuration register
Addr:	00000000000C0061 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST3_COUNTER
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST3.CONFIG.COUNTER_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:7	RWX			SPIMST3_COUNT_N1: counter N1 register
8:15	RWX			SPIMST3_COUNT_N2: counter N1 register
16:23	RWX			SPIMST3_COUNT_RESERVED_A: counter reserved area a register
24:31	RWX			SPIMST3_LOOPCOUNT: loop count compare register for BNEI operation
32:39	RWX			SPIMST3_LOOPCOUNT2: loop count 2 compare register for BNEI2 operation
40:47	RWX			SPIMST3_SHIFTER_FSM_CONTROL: shifter fsm control bits
48:51	RWX			SPIMST3_N1_CONTROL: shift counter N1 control bits
52:55	RWX			SPIMST3_N2_CONTROL: shift counter N2 control bits
56:63	RWX			SPIMST3_COUNT_RESERVED_B: counter reserved area b register

spi master configuration 1 register
Addr:	00000000000C0062 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST3_CONFIG1
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST3.CONFIG.CONFIG1_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	ROX			SPIMST3_SPI_RESOURCE_LOCK: reserved
1:4	ROX			SPIMST3_PIB_MASTER_ID: PIB master id that has reserved the device
5:63	RWX			SPIMST3_CONFIG1_REG_UNUSED: reserved register space

spi master clock configuration register
Addr:	00000000000C0063 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST3_CLOCK_CONFIG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST3.CONFIG.CLOCK_CONFIG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:11	RWX			SPIMST3_SCK_CLOCK_DIVIDER: SCK_clock_divider
12:19	RWX			SPIMST3_SCK_RECEIVE_DELAY: SCK_receive_delay
20	RWX			SPIMST3_ENABLE_RECEIVE_PACING: enable_receive_pacing
21	RWX			SPIMST3_SPIMST_TRACE_ENABLE: SCK clock_phase
22:23	RWX			SPIMST3_SCK_TRACE_SELECT: trace_select
24:27	RWX			SPIMST3_SCK_RESET_CONTROL: reset_control
28	RWX			SPIMST3_SCK_ECC_SPIMM_ADDR_CORR_DIS: SCK_ecc_spimm_addr_corr_dis
29:30	RWX			SPIMST3_SCK_ECC_CONTROL: ecc_control
31	RWX			SPIMST3_SCK_MMSPISM_ENABLE: mmSPIsm_enable
32:35	RWX			SPIMST3_SPI_SLAVE_RESET: hardware reset signal for spi slave
36	RWX			SPIMST3_LOOPBACK_ENABLE: loopback mode enable
37:63	RWX			SPIMST3_CLOCK_CONFIG_RESERVED: clock config reserved

spi master pattern match register
Addr:	00000000000C0064 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST3_MEMORY_MAPPING
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST3.CONFIG.MEMORY_MAPPING_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:15	RWX			SPIMST3_MEMORY_MAPPING_BASE: memory mapping address base
16:31	RWX			SPIMST3_MEMORY_MAPPING_MASK: memory mapping address mask
32:47	RWX			SPIMST3_PATTERN_MATCH_COMPARE: serial receive pattern match compare value
48:63	RWX			SPIMST3_PATTERN_MATCH_MASK: serial receive pattern match compare value

spi master transmit data register
Addr:	00000000000C0065 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST3_TRANSMIT_DATA_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST3.CONFIG.TRANSMIT_DATA_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RWX			SPIMST3_TRANSMIT_DATA_REG_Q: spi master tranmsit data register

spi master receive data register
Addr:	00000000000C0066 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST3_RECEIVE_DATA_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST3.CONFIG.RECEIVE_DATA_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	ROX			SPIMST3_RECEIVE_DATA_REG_Q: spi master receive data register

spi master sequencer operation register
Addr:	00000000000C0067 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST3_SEQUENCER_OP_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST3.CONFIG.SEQUENCER_OP_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RWX			SPIMST3_SEQUENCER_OP_Q: spi master sequencer operation register

spi master status register
Addr:	00000000000C0068 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST3_STATUS_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.PIB.SPIMC.SPIMST3.CONFIG.SPI_CONFIG_FUNC_Q_INST.NO_FSILAT.LATCH.LATC.L2(12:15) [0000]
	4:7	TP.TPCHIP.PIB.SPIMC.SPIMST3.CONFIG.SPI_CONFIG_FUNC_Q_INST.NO_FSILAT.LATCH.LATC.L2(8:11) [0000]
	8:15	TP.TPCHIP.PIB.SPIMC.SPIMST3.SEQ.FUNC_SEQUENCER_LATCHES_Q_INST.NO_FSILAT.LATCH.LATC.L2(16:23) [00000000]
	16:27	TP.TPCHIP.PIB.SPIMC.SPIMST3.SHIFT.FUNC_SHIFTER_LATCHES_Q_INST.NO_FSILAT.LATCH.LATC.L2(24:35) [000000000000]
	28:31	TP.TPCHIP.PIB.SPIMC.SPIMST3.SEQ.FUNC_SEQUENCER_LATCHES_Q_INST.NO_FSILAT.LATCH.LATC.L2(4:7) [0000]
	32:63	TP.TPCHIP.PIB.SPIMC.SPIMST3.CONFIG.SPI_STATUS_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RWX			SPIMST3_RDR_FULL_STATUS: indication for receive data register full
1	RWX			SPIMST3_RDR_OVER_STATUS: indication for receive data register overrun
2	RWX			SPIMST3_RDR_UNDER_STATUS: indication for receive data register underrun
3	RWX			SPIMST3_RDR_RESERVED_STATUS: indication for receive data register reserved status, unused
4	RWX			SPIMST3_TDR_FULL_STATUS: indication for transmit data register full
5	RWX			SPIMST3_TDR_OVER_STATUS: indication for transmit data register overrun
6	RWX			SPIMST3_TDR_UNDER_STATUS: indication for transmit data register underrun
7	RWX			SPIMST3_TDR_RESERVED_STATUS: indication for transmit data register reserved status, unused
8:15	ROX			SPIMST3_SEQUENCER_FSM: sequencer finit state machine bit coding
16:27	ROX			SPIMST3_SHIFTER_FSM: shifter finit state machine bit coding
28:31	ROX			SPIMST3_SEQUENCER_OP_INDEX: sequencer operation index
32	RWX			SPIMST3_COUNTER_REG_PARITY_ERRS: counter configuration register parity error
33	RWX			SPIMST3_CLOCK_REG_PARITY_ERR: clock configuration register parity error
34	RWX			SPIMST3_SEQUENCER_REG_PARITY_ERR: sequencer configuration register parity error
35	RWX			SPIMST3_SEQUENCER_FSM_PARITY_ERR: sequencer fsm parity error
36	RWX			SPIMST3_SHIFTER_FSM_PARITY_ERR: shifter fsm parity error
37	RWX			SPIMST3_PATTERN_REG_PARITY_ERR: pattern match register parity error
38	RWX			SPIMST3_TDR_REG_PARITY_ERR: transmit data register parity error
39	RWX			SPIMST3_RDR_REG_PARITY_ERR: receive data register parity error
40	RWX			SPIMST3_CONFIG_REG1_PARITY_ERR: configuration register 1 parity error
41	RWX			SPIMST3_UNUSED_PARITY_ERR: unused
42	RWX			SPIMST3_ERROR_REG_PARITY_ERR: error register parity error
43	RWX			SPIMST3_ECC_CORRECTABLE_ERR: ecc correctable error
44	RWX			SPIMST3_ECC_UNCORRECTABLE_ERR: ecc uncorrectable error
45:46	RWX			SPIMST3_ECC_STATUS: general ecc status (unsued)
47	RWX			SPIMST3_MM_ADDR_OVERLAP: memory mapped SPI address overlap
48:49	RWX			SPIMST3_ACCESS_VIOLATION: general access violation
50	RWX			SPIMST3_PORT_MULTIPLEXER_ERR: port multiplexer error
51	RWX			SPIMST3_ADDR_OUT_OF_RANGE: address range error
52	RWX			SPIMST3_MEM_MAPPING_OVERLAP: memory mapping overlap error
53	RWX			SPIMST3_SEQUENCER_SLAVE_SEL_ERR: sequencer slave select error
54	RWX			SPIMST3_SEQUENCER_FSM_ERR: sequencer fsm error
55	RWX			SPIMST3_SHIFTER_FSM_ERR: shifter fsm error
56	RWX			SPIMST3_ANY_CONFIG_PARITY_ERR: any config parity error
57	RWX			SPIMST3_SPI_PORT_MUX_INDICATOR: indication of SPI port multiplexer, must indicate zero for this SPI to run
58	RWX			SPIMST3_SPI_SEC_PIB_RETRY_RSP_INFO: indication of SPI security problem during PIB Write access
59:63	RWX			SPIMST3_UNUSED: unused

spi master error inject register
Addr:	00000000000C0080 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST4_ERROR_INJECT_
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST4.CONFIG.ERROR_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:7	RWX			SPIMST4_ERROR_INJECT_PULSE: error inject pulse
8:15	RWX			SPIMST4_ERROR_INJECT_MASK: error inject mask
16:31	RWX			SPIMST4_ERROR_MASK: error mask
32:63	RWX			SPIMST4_ERROR_UNUSED: error unused

spi master counter configuration register
Addr:	00000000000C0081 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST4_COUNTER
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST4.CONFIG.COUNTER_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:7	RWX			SPIMST4_COUNT_N1: counter N1 register
8:15	RWX			SPIMST4_COUNT_N2: counter N1 register
16:23	RWX			SPIMST4_COUNT_RESERVED_A: counter reserved area a register
24:31	RWX			SPIMST4_LOOPCOUNT: loop count compare register for BNEI operation
32:39	RWX			SPIMST4_LOOPCOUNT2: loop count 2 compare register for BNEI2 operation
40:47	RWX			SPIMST4_SHIFTER_FSM_CONTROL: shifter fsm control bits
48:51	RWX			SPIMST4_N1_CONTROL: shift counter N1 control bits
52:55	RWX			SPIMST4_N2_CONTROL: shift counter N2 control bits
56:63	RWX			SPIMST4_COUNT_RESERVED_B: counter reserved area b register

spi master configuration 1 register
Addr:	00000000000C0082 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST4_CONFIG1
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST4.CONFIG.CONFIG1_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	ROX			SPIMST4_SPI_RESOURCE_LOCK: reserved
1:4	ROX			SPIMST4_PIB_MASTER_ID: PIB master id that has reserved the device
5:63	RWX			SPIMST4_CONFIG1_REG_UNUSED: reserved register space

spi master clock configuration register
Addr:	00000000000C0083 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST4_CLOCK_CONFIG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST4.CONFIG.CLOCK_CONFIG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:11	RWX			SPIMST4_SCK_CLOCK_DIVIDER: SCK_clock_divider
12:19	RWX			SPIMST4_SCK_RECEIVE_DELAY: SCK_receive_delay
20	RWX			SPIMST4_ENABLE_RECEIVE_PACING: enable_receive_pacing
21	RWX			SPIMST4_SPIMST_TRACE_ENABLE: SCK clock_phase
22:23	RWX			SPIMST4_SCK_TRACE_SELECT: trace_select
24:27	RWX			SPIMST4_SCK_RESET_CONTROL: reset_control
28	RWX			SPIMST4_SCK_ECC_SPIMM_ADDR_CORR_DIS: SCK_ecc_spimm_addr_corr_dis
29:30	RWX			SPIMST4_SCK_ECC_CONTROL: ecc_control
31	RWX			SPIMST4_SCK_MMSPISM_ENABLE: mmSPIsm_enable
32:35	RWX			SPIMST4_SPI_SLAVE_RESET: hardware reset signal for spi slave
36	RWX			SPIMST4_LOOPBACK_ENABLE: loopback mode enable
37:63	RWX			SPIMST4_CLOCK_CONFIG_RESERVED: clock config reserved

spi master pattern match register
Addr:	00000000000C0084 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST4_MEMORY_MAPPING
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST4.CONFIG.MEMORY_MAPPING_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:15	RWX			SPIMST4_MEMORY_MAPPING_BASE: memory mapping address base
16:31	RWX			SPIMST4_MEMORY_MAPPING_MASK: memory mapping address mask
32:47	RWX			SPIMST4_PATTERN_MATCH_COMPARE: serial receive pattern match compare value
48:63	RWX			SPIMST4_PATTERN_MATCH_MASK: serial receive pattern match compare value

spi master transmit data register
Addr:	00000000000C0085 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST4_TRANSMIT_DATA_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST4.CONFIG.TRANSMIT_DATA_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RWX			SPIMST4_TRANSMIT_DATA_REG_Q: spi master tranmsit data register

spi master receive data register
Addr:	00000000000C0086 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST4_RECEIVE_DATA_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST4.CONFIG.RECEIVE_DATA_REG_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	ROX			SPIMST4_RECEIVE_DATA_REG_Q: spi master receive data register

spi master sequencer operation register
Addr:	00000000000C0087 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST4_SEQUENCER_OP_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.SPIMC.SPIMST4.CONFIG.SEQUENCER_OP_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RWX			SPIMST4_SEQUENCER_OP_Q: spi master sequencer operation register

spi master status register
Addr:	00000000000C0088 (SCOM)
Name:	TP.TPCHIP.PIB.SPIMC.SPIMST4_STATUS_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.PIB.SPIMC.SPIMST4.CONFIG.SPI_CONFIG_FUNC_Q_INST.NO_FSILAT.LATCH.LATC.L2(12:15) [0000]
	4:7	TP.TPCHIP.PIB.SPIMC.SPIMST4.CONFIG.SPI_CONFIG_FUNC_Q_INST.NO_FSILAT.LATCH.LATC.L2(8:11) [0000]
	8:15	TP.TPCHIP.PIB.SPIMC.SPIMST4.SEQ.FUNC_SEQUENCER_LATCHES_Q_INST.NO_FSILAT.LATCH.LATC.L2(16:23) [00000000]
	16:27	TP.TPCHIP.PIB.SPIMC.SPIMST4.SHIFT.FUNC_SHIFTER_LATCHES_Q_INST.NO_FSILAT.LATCH.LATC.L2(24:35) [000000000000]
	28:31	TP.TPCHIP.PIB.SPIMC.SPIMST4.SEQ.FUNC_SEQUENCER_LATCHES_Q_INST.NO_FSILAT.LATCH.LATC.L2(4:7) [0000]
	32:63	TP.TPCHIP.PIB.SPIMC.SPIMST4.CONFIG.SPI_STATUS_Q_INST.NO_FSILAT.LATCH.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RWX			SPIMST4_RDR_FULL_STATUS: indication for receive data register full
1	RWX			SPIMST4_RDR_OVER_STATUS: indication for receive data register overrun
2	RWX			SPIMST4_RDR_UNDER_STATUS: indication for receive data register underrun
3	RWX			SPIMST4_RDR_RESERVED_STATUS: indication for receive data register reserved status, unused
4	RWX			SPIMST4_TDR_FULL_STATUS: indication for transmit data register full
5	RWX			SPIMST4_TDR_OVER_STATUS: indication for transmit data register overrun
6	RWX			SPIMST4_TDR_UNDER_STATUS: indication for transmit data register underrun
7	RWX			SPIMST4_TDR_RESERVED_STATUS: indication for transmit data register reserved status, unused
8:15	ROX			SPIMST4_SEQUENCER_FSM: sequencer finit state machine bit coding
16:27	ROX			SPIMST4_SHIFTER_FSM: shifter finit state machine bit coding
28:31	ROX			SPIMST4_SEQUENCER_OP_INDEX: sequencer operation index
32	RWX			SPIMST4_COUNTER_REG_PARITY_ERRS: counter configuration register parity error
33	RWX			SPIMST4_CLOCK_REG_PARITY_ERR: clock configuration register parity error
34	RWX			SPIMST4_SEQUENCER_REG_PARITY_ERR: sequencer configuration register parity error
35	RWX			SPIMST4_SEQUENCER_FSM_PARITY_ERR: sequencer fsm parity error
36	RWX			SPIMST4_SHIFTER_FSM_PARITY_ERR: shifter fsm parity error
37	RWX			SPIMST4_PATTERN_REG_PARITY_ERR: pattern match register parity error
38	RWX			SPIMST4_TDR_REG_PARITY_ERR: transmit data register parity error
39	RWX			SPIMST4_RDR_REG_PARITY_ERR: receive data register parity error
40	RWX			SPIMST4_CONFIG_REG1_PARITY_ERR: configuration register 1 parity error
41	RWX			SPIMST4_UNUSED_PARITY_ERR: unused
42	RWX			SPIMST4_ERROR_REG_PARITY_ERR: error register parity error
43	RWX			SPIMST4_ECC_CORRECTABLE_ERR: ecc correctable error
44	RWX			SPIMST4_ECC_UNCORRECTABLE_ERR: ecc uncorrectable error
45:46	RWX			SPIMST4_ECC_STATUS: general ecc status (unsued)
47	RWX			SPIMST4_MM_ADDR_OVERLAP: memory mapped SPI address overlap
48:49	RWX			SPIMST4_ACCESS_VIOLATION: general access violation
50	RWX			SPIMST4_PORT_MULTIPLEXER_ERR: port multiplexer error
51	RWX			SPIMST4_ADDR_OUT_OF_RANGE: address range error
52	RWX			SPIMST4_MEM_MAPPING_OVERLAP: memory mapping overlap error
53	RWX			SPIMST4_SEQUENCER_SLAVE_SEL_ERR: sequencer slave select error
54	RWX			SPIMST4_SEQUENCER_FSM_ERR: sequencer fsm error
55	RWX			SPIMST4_SHIFTER_FSM_ERR: shifter fsm error
56	RWX			SPIMST4_ANY_CONFIG_PARITY_ERR: any config parity error
57	RWX			SPIMST4_SPI_PORT_MUX_INDICATOR: indication of SPI port multiplexer, must indicate zero for this SPI to run
58	RWX			SPIMST4_SPI_SEC_PIB_RETRY_RSP_INFO: indication of SPI security problem during PIB Write access
59:63	RWX			SPIMST4_UNUSED: unused

PIB History Control and Status Register
Addr:	00000000000D0000 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_PIBHIST_CTRL_STATUS_REG
Constant(s):	PU_PSU_PIBHIST_CTRL_STATUS_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_HISTUNIT.HIST_MANUAL_MODE_EN_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_HISTUNIT.HIST_START_NOT_STOP_INST.LATC.L2(0) [0]
	2	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_HISTUNIT.HIST_FREEZE_HISTORY_INST.LATC.L2(0) [0]
	3	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_HISTUNIT.HIST_RESET_HISTORY_INST.LATC.L2(0) [0]
	4	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_HISTUNIT.HIST_TRACE_PSU_TRAFFIC_INST.LATC.L2(0) [0]
	5:7	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_HISTUNIT.HIST_STOP_ON_ERROR_GT_INST.LATC.L2(0:2) [000]
	8	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_HISTUNIT.HIST_FILTER_RD_NOT_WR_INST.LATC.L2(0) [0]
	9	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_HISTUNIT.HIST_FILTER_MASK_RD_NOT_WR_INST.LATC.L2(0) [0]
	10:15	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_HISTUNIT.HIST_CTRL_STATUS_REG_RESERVED_INST.LATC.L2(0:5) [000000]
Bit(s)	SCOM			Dial: Description
0	RW			HIST_MANUAL_MODE_EN: 0: history trace always running (default)1: Enable manual start/stop of history trace
1	RW			HIST_START_NOT_STOP: Only valid if HIST_MANUAL_MODE_EN=1.0: Stop history trace (default)1: Start history trace
2	RWX			HIST_FREEZE_HISTORY: 1: disables history trace and freezes history regsThis bit is also set when the unit stops on error
3	RWX			HIST_RESET_HISTORY: 1: clear history registers and reset control fsm.This bit is self-resetting
4	RW			HIST_TRACE_PSU_TRAFFIC: Controls if the PIB traffic from/to the PIB slave address of the PSU is included in history trace.0: Do not trace PSU traffic (default)1: include PSU traffic
5:7	RW			HIST_STOP_ON_ERROR_GT: Greater than value for rsp_info to stop history sampling e.g.: 000 (default): stop sampling with rsp_info > 0 001: stop sampling with rsp_info > 1, etc. 111: stop on error disabled
8	RW			HIST_FILTER_RD_NOT_WR: Compare R/W value for history trace
9	RW			HIST_FILTER_MASK_RD_NOT_WR: Compare R/W mask for history trace
10:15	RW			HIST_CTRL_STATUS_REG_RESERVED: reserved

PIB History Filter Register
Addr:	00000000000D0001 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_PIBHIST_FILTER_REG
Constant(s):	PU_PSU_PIBHIST_FILTER_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_HISTUNIT.HIST_FILTER_ADDRESS_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_HISTUNIT.HIST_FILTER_MASK_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	RW			HIST_FILTER_ADDRESS: Compare address for history trace
32:63	RW			HIST_FILTER_MASK: Compare mask for history trace

PIB History Last Address Trace Register
Addr:	00000000000D0002 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_PIBHIST_LAST_ADDR_TRACE_REG
Constant(s):	PU_PSU_PIBHIST_LAST_ADDR_TRACE_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_HISTUNIT.PSU_PIBHIST_LAST_ADDR_TRACE_REG_OUT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	ROX			HIST_LAST_ADDR_TRACE: History trace: last address

PIB History Last Request Data Trace Register
Addr:	00000000000D0003 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_PIBHIST_LAST_REQDATA_TRACE_REG
Constant(s):	PU_PSU_PIBHIST_LAST_REQDATA_TRACE_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_HISTUNIT.PSU_PIBHIST_LAST_REQDATA_TRACE_REG_OUT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	ROX			HIST_LAST_REQDATA_TRACE: History trace: last request data

PIB History Last Response Data Trace Register
Addr:	00000000000D0004 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_PIBHIST_LAST_RSPDATA_TRACE_REG
Constant(s):	PU_PSU_PIBHIST_LAST_RSPDATA_TRACE_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_HISTUNIT.PSU_PIBHIST_LAST_RSPDATA_TRACE_REG_OUT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	ROX			HIST_LAST_RSPDATA_TRACE: History trace: last response data

PIB History Second Last Address Trace Register
Addr:	00000000000D0005 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_PIBHIST_2NDLAST_ADDR_TRACE_REG
Constant(s):	PU_PSU_PIBHIST_2NDLAST_ADDR_TRACE_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_HISTUNIT.PSU_PIBHIST_2NDLAST_ADDR_TRACE_REG_OUT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	ROX			HIST_2NDLAST_ADDR_TRACE: History trace: second last address

PIB History Second Last Request Data Trace Register
Addr:	00000000000D0006 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_PIBHIST_2NDLAST_REQDATA_TRACE_REG
Constant(s):	PU_PSU_PIBHIST_2NDLAST_REQDATA_TRACE_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_HISTUNIT.PSU_PIBHIST_2NDLAST_REQDATA_TRACE_REG_OUT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	ROX			HIST_2NDLAST_REQDATA_TRACE: History trace: second last request data

PIB History Second Last Response Data Trace Register
Addr:	00000000000D0007 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_PIBHIST_2NDLAST_RSPDATA_TRACE_REG
Constant(s):	PU_PSU_PIBHIST_2NDLAST_RSPDATA_TRACE_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_HISTUNIT.PSU_PIBHIST_2NDLAST_RSPDATA_TRACE_REG_OUT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	ROX			HIST_2NDLAST_RSPDATA_TRACE: History trace: second last response data

Instrumentation Control and Status Register
Addr:	00000000000D0010 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_INSTR_CTRL_STATUS_REG
Constant(s):	PU_PSU_INSTR_CTRL_STATUS_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:39	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_INSTRUNIT.PSU_INSTR_CTRL_STATUS_REG.LATC.L2(0:39) [0000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:1	RW			INSTR0_MODE: Mode control for instrumentation unit 0:00: disabled01: PIB mode (default)10: PCB interrupt mode11: reserved
2	RW			INSTR0_STOP_TIMER_EN: 0: Stop measurement manually (default)1: Stop measurement based on STOP_TIMER
3:5	RW			INSTR0_STOP_ON_ERROR_GT: Greater than value for rsp_info to stop instrumentation e.g.: 000 (default): stop sampling with rsp_info > 0 001: stop sampling with rsp_info > 1, etc.
6	RWX			INSTR0_START: 1: start measurement (self-resetting with INSTR0_CYCLECNT_RUNNING=1)
7	RWX			INSTR0_STOP: 1: stop measurement (self-resetting with INSTR0_CYCLECNT_RUNNING=0)
8:9	RW			INSTR1_MODE: Mode control for instrumentation unit 1:00: disabled01: PIB mode (default)10: PCB interrupt mode11: reserved
10	RW			INSTR1_STOP_TIMER_EN: 0: Stop measurement manually (default)1: Stop measurement based on STOP_TIMER
11:13	RW			INSTR1_STOP_ON_ERROR_GT: Greater than value for rsp_info to stop instrumentation e.g.: 000 (default): stop sampling with rsp_info > 0 001: stop sampling with rsp_info > 1, etc.
14	RWX			INSTR1_START: 1: start measurement (self-resetting with INSTR1_CYCLECNT_RUNNING=1)
15	RWX			INSTR1_STOP: 1: stop measurement (self-resetting with INSTR1_CYCLECNT_RUNNING=0)
16:17	RW			INSTR2_MODE: Mode control for instrumentation unit 2:00: disabled01: PIB mode (default)10: PCB interrupt mode11: reserved
18	RW			INSTR2_STOP_TIMER_EN: 0: Stop measurement manually (default)1: Stop measurement based on STOP_TIMER
19:21	RW			INSTR2_STOP_ON_ERROR_GT: Greater than value for rsp_info to stop instrumentation e.g.: 000 (default): stop sampling with rsp_info > 0 001: stop sampling with rsp_info > 1, etc.
22	RWX			INSTR2_START: 1: start measurement (self-resetting with INSTR2_CYCLECNT_RUNNING=1)
23	RWX			INSTR2_STOP: 1: stop measurement (self-resetting with INSTR2_CYCLECNT_RUNNING=0)
24	ROX			INSTR0_CYCLECNT_RUNNING: Instrumentation unit 0: flag for cyclecounter running
25	ROX			INSTR0_BUSYCNT_RUNNING: Instrumentation unit 0: flag for busycounter running
26	ROX			INSTR1_CYCLECNT_RUNNING: Instrumentation unit 1: flag for cyclecounter running
27	ROX			INSTR1_BUSYCNT_RUNNING: Instrumentation unit 1: flag for busycounter running
28	ROX			INSTR2_CYCLECNT_RUNNING: Instrumentation unit 2: flag for cyclecounter running
29	ROX			INSTR2_BUSYCNT_RUNNING: Instrumentation unit 2: flag for busycounter running
30	RWX			INSTR0_STOPPED_ON_ERROR: Indicates that instrumentation unit 0 has stopped because of a rsp_info > INSTR0_STOP_ON_ERROR_GT. Resetting this bit after the error condition is gone resumes the measurement.
31	RWX			INSTR1_STOPPED_ON_ERROR: Indicates that instrumentation unit 1 has stopped because of a rsp_info > INSTR1_STOP_ON_ERROR_GT. Resetting this bit after the error condition is gone resumes the measurement.
32	RWX			INSTR2_STOPPED_ON_ERROR: Indicates that instrumentation unit 1 has stopped because of a rsp_info > INSTR1_STOP_ON_ERROR_GT. Resetting this bit after the error condition is gone resumes the measurement.
33	RWX			INSTR0_RESET: 1: clear all measurement registers and resets measurement control of instrumentation unit 0.This bit is self-resetting
34	RWX			INSTR1_RESET: 1: clear all measurement registers and resets measurement control of instrumentation unit 1.This bit is self-resetting
35	RWX			INSTR2_RESET: 1: clear all measurement registers and resets measurement control of instrumentation unit 2.This bit is self-resetting
36	RW			INSTR_INCLUDE_PSU_TRAFFIC: Controls if the PIB traffic from/to the PIB slave address of the PSU is included in measurement.0: Do not measure PSU traffic (default)1: include PSU traffic
37:39	RW			INSTR_CTRL_STATUS_REG_RESERVED: reserved

Instrumentation Stop Timer Register 0
Addr:	00000000000D0020 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_INSTR0_STOP_TIMER_REG
Constant(s):	PU_PSU_INSTR0_STOP_TIMER_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:39	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_INSTRUNIT.PSU_INSTR_MEASREG0.PSU_INSTR_STOP_TIMER_REG_OUT_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:39	RW			INSTR0_STOP_TIMER: 40 bit threshold value for instrumentation unit 0 (in # of PIB cycles)

Instrumentation Filter Register 0
Addr:	00000000000D0021 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_INSTR0_FILTER_REG
Constant(s):	PU_PSU_INSTR0_FILTER_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_INSTRUNIT.PSU_INSTR_MEASREG0.INSTR_FILTER_CONTENT_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_INSTRUNIT.PSU_INSTR_MEASREG0.INSTR_FILTER_MASK_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	RW			INSTR0_FILTER_CONTENT: Compare data for instrumentation unit 0
32:63	RW			INSTR0_FILTER_MASK: Compare mask for instrumentation unit 0

Instrumentation Cycle Count Register 0
Addr:	00000000000D0022 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_INSTR0_CYCLECNT_REG
Constant(s):	PU_PSU_INSTR0_CYCLECNT_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:39	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_INSTRUNIT.PSU_INSTR_MEASREG0.PSU_INSTR_CYCLECNT_REG_OUT_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:39	ROX			INSTR0_CYCLECNT: Measured cycle count of instrumentation unit 0

Instrumentation Active Cycle Count Register 0
Addr:	00000000000D0023 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_INSTR0_ACTCYCLECNT_REG
Constant(s):	PU_PSU_INSTR0_ACTCYCLECNT_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:39	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_INSTRUNIT.PSU_INSTR_MEASREG0.PSU_INSTR_ACTCYCLECNT_REG_OUT_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:39	ROX			INSTR0_ACTCYCLECNT: Measured active cycle count of instrumentation unit 0

Instrumentation Event Count Register 0
Addr:	00000000000D0024 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_INSTR0_EVENTCNT_REG
Constant(s):	PU_PSU_INSTR0_EVENTCNT_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_INSTRUNIT.PSU_INSTR_MEASREG0.PSU_INSTR_EVENTCNT_REG_OUT_INST.LATC.L2(0:15) [0000000000000000]
Bit(s)	SCOM			Dial: Description
0:15	ROX			INSTR0_EVENTCNT: Measured event count of instrumentation unit 0(# of PIB accesses or # of PCB interrupts)

Max Cycle Count Register 0
Addr:	00000000000D0025 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_INSTR0_MAXCYCLECNT_REG
Constant(s):	PU_PSU_INSTR0_MAXCYCLECNT_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:39	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_INSTRUNIT.PSU_INSTR_MEASREG0.PSU_INSTR_MAXCYCLECNT_REG_OUT_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:39	ROX			INSTR0_MAXCYCLECNT: Maximum active cycle count of instrumentation unit 0

Min Cycle Count Register 0
Addr:	00000000000D0026 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_INSTR0_MINCYCLECNT_REG
Constant(s):	PU_PSU_INSTR0_MINCYCLECNT_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:39	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_INSTRUNIT.PSU_INSTR_MEASREG0.PSU_INSTR_MINCYCLECNT_REG_OUT_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:39	ROX			INSTR0_MINCYCLECNT: Minimum active cycle count of instrumentation unit 0Init value: xFFFFFFFFFF

Instrumentation Stop Timer Register 1
Addr:	00000000000D0030 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_INSTR1_STOP_TIMER_REG
Constant(s):	PU_PSU_INSTR1_STOP_TIMER_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:39	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_INSTRUNIT.PSU_INSTR_MEASREG1.PSU_INSTR_STOP_TIMER_REG_OUT_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:39	RW			INSTR1_STOP_TIMER: 40 bit threshold value for instrumentation unit 0 (in # of PIB cycles)

Instrumentation Filter Register 1
Addr:	00000000000D0031 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_INSTR1_FILTER_REG
Constant(s):	PU_PSU_INSTR1_FILTER_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_INSTRUNIT.PSU_INSTR_MEASREG1.INSTR_FILTER_CONTENT_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_INSTRUNIT.PSU_INSTR_MEASREG1.INSTR_FILTER_MASK_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	RW			INSTR1_FILTER_CONTENT: Compare data for instrumentation unit 1
32:63	RW			INSTR1_FILTER_MASK: Compare mask for instrumentation unit 1

Instrumentation Cycle Count Register 1
Addr:	00000000000D0032 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_INSTR1_CYCLECNT_REG
Constant(s):	PU_PSU_INSTR1_CYCLECNT_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:39	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_INSTRUNIT.PSU_INSTR_MEASREG1.PSU_INSTR_CYCLECNT_REG_OUT_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:39	ROX			INSTR1_CYCLECNT: Measured cycle count of instrumentation unit 1

Instrumentation Active Cycle Count Register 1
Addr:	00000000000D0033 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_INSTR1_ACTCYCLECNT_REG
Constant(s):	PU_PSU_INSTR1_ACTCYCLECNT_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:39	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_INSTRUNIT.PSU_INSTR_MEASREG1.PSU_INSTR_ACTCYCLECNT_REG_OUT_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:39	ROX			INSTR1_ACTCYCLECNT: Measured active cycle count of instrumentation unit 1

Instrumentation Event Count Register 1
Addr:	00000000000D0034 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_INSTR1_EVENTCNT_REG
Constant(s):	PU_PSU_INSTR1_EVENTCNT_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_INSTRUNIT.PSU_INSTR_MEASREG1.PSU_INSTR_EVENTCNT_REG_OUT_INST.LATC.L2(0:15) [0000000000000000]
Bit(s)	SCOM			Dial: Description
0:15	ROX			INSTR1_EVENTCNT: Measured event count of instrumentation unit 1(# of PIB accesses or # of PCB interrupts)

Max Cycle Count Register 1
Addr:	00000000000D0035 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_INSTR1_MAXCYCLECNT_REG
Constant(s):	PU_PSU_INSTR1_MAXCYCLECNT_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:39	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_INSTRUNIT.PSU_INSTR_MEASREG1.PSU_INSTR_MAXCYCLECNT_REG_OUT_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:39	ROX			INSTR1_MAXCYCLECNT: Maximum active cycle count of instrumentation unit 1

Min Cycle Count Register 1
Addr:	00000000000D0036 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_INSTR1_MINCYCLECNT_REG
Constant(s):	PU_PSU_INSTR1_MINCYCLECNT_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:39	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_INSTRUNIT.PSU_INSTR_MEASREG1.PSU_INSTR_MINCYCLECNT_REG_OUT_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:39	ROX			INSTR1_MINCYCLECNT: Minimum active cycle count of instrumentation unit 1Init value: xFFFFFFFFFF

Instrumentation Stop Timer Register 2
Addr:	00000000000D0040 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_INSTR2_STOP_TIMER_REG
Constant(s):	PU_PSU_INSTR2_STOP_TIMER_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:39	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_INSTRUNIT.PSU_INSTR_MEASREG2.PSU_INSTR_STOP_TIMER_REG_OUT_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:39	RW			INSTR2_STOP_TIMER: 40 bit threshold value for instrumentation unit 0 (in # of PIB cycles)

Instrumentation Filter Register 2
Addr:	00000000000D0041 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_INSTR2_FILTER_REG
Constant(s):	PU_PSU_INSTR2_FILTER_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_INSTRUNIT.PSU_INSTR_MEASREG2.INSTR_FILTER_CONTENT_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_INSTRUNIT.PSU_INSTR_MEASREG2.INSTR_FILTER_MASK_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	RW			INSTR2_FILTER_CONTENT: Compare data for instrumentation unit 2
32:63	RW			INSTR2_FILTER_MASK: Compare mask for instrumentation unit 2

Instrumentation Cycle Count Register 2
Addr:	00000000000D0042 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_INSTR2_CYCLECNT_REG
Constant(s):	PU_PSU_INSTR2_CYCLECNT_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:39	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_INSTRUNIT.PSU_INSTR_MEASREG2.PSU_INSTR_CYCLECNT_REG_OUT_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:39	ROX			INSTR2_CYCLECNT: Measured cycle count of instrumentation unit 2

Instrumentation Active Cycle Count Register 2
Addr:	00000000000D0043 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_INSTR2_ACTCYCLECNT_REG
Constant(s):	PU_PSU_INSTR2_ACTCYCLECNT_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:39	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_INSTRUNIT.PSU_INSTR_MEASREG2.PSU_INSTR_ACTCYCLECNT_REG_OUT_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:39	ROX			INSTR2_ACTCYCLECNT: Measured active cycle count of instrumentation unit 2

Instrumentation Event Count Register 2
Addr:	00000000000D0044 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_INSTR2_EVENTCNT_REG
Constant(s):	PU_PSU_INSTR2_EVENTCNT_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_INSTRUNIT.PSU_INSTR_MEASREG2.PSU_INSTR_EVENTCNT_REG_OUT_INST.LATC.L2(0:15) [0000000000000000]
Bit(s)	SCOM			Dial: Description
0:15	ROX			INSTR2_EVENTCNT: Measured event count of instrumentation unit 2(# of PIB accesses or # of PCB interrupts)

Max Cycle Count Register 2
Addr:	00000000000D0045 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_INSTR2_MAXCYCLECNT_REG
Constant(s):	PU_PSU_INSTR2_MAXCYCLECNT_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:39	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_INSTRUNIT.PSU_INSTR_MEASREG2.PSU_INSTR_MAXCYCLECNT_REG_OUT_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:39	ROX			INSTR2_MAXCYCLECNT: Maximum active cycle count of instrumentation unit 2

Min Cycle Count Register 2
Addr:	00000000000D0046 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_INSTR2_MINCYCLECNT_REG
Constant(s):	PU_PSU_INSTR2_MINCYCLECNT_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:39	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_INSTRUNIT.PSU_INSTR_MEASREG2.PSU_INSTR_MINCYCLECNT_REG_OUT_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:39	ROX			INSTR2_MINCYCLECNT: Minimum active cycle count of instrumentation unit 2Init value: xFFFFFFFFFF

Host/SBE Mailbox 0 Register
Addr:	00000000000D0050 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_HOST_SBE_MBOX0_REG
Constant(s):	PU_PSU_HOST_SBE_MBOX0_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_SBESUPPUNIT.PSU_HOST_SBE_MBOX0_REG_OUT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			HOST_SBE_MBOX0: Mailbox Register for Host-SBE communication

Host/SBE Mailbox 1 Register
Addr:	00000000000D0051 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_HOST_SBE_MBOX1_REG
Constant(s):	PU_PSU_HOST_SBE_MBOX1_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_SBESUPPUNIT.PSU_HOST_SBE_MBOX1_REG_OUT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			HOST_SBE_MBOX1: Mailbox Register for Host-SBE communication

Host/SBE Mailbox 2 Register
Addr:	00000000000D0052 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_HOST_SBE_MBOX2_REG
Constant(s):	PU_PSU_HOST_SBE_MBOX2_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_SBESUPPUNIT.PSU_HOST_SBE_MBOX2_REG_OUT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			HOST_SBE_MBOX2: Mailbox Register for Host-SBE communication

Host/SBE Mailbox 3 Register
Addr:	00000000000D0053 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_HOST_SBE_MBOX3_REG
Constant(s):	PU_PSU_HOST_SBE_MBOX3_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_SBESUPPUNIT.PSU_HOST_SBE_MBOX3_REG_OUT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			HOST_SBE_MBOX3: Mailbox Register for Host-SBE communication

Host/SBE Mailbox 4 Register
Addr:	00000000000D0054 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_HOST_SBE_MBOX4_REG
Constant(s):	PU_PSU_HOST_SBE_MBOX4_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_SBESUPPUNIT.PSU_HOST_SBE_MBOX4_REG_OUT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			HOST_SBE_MBOX4: Mailbox Register for Host-SBE communication

Host/SBE Mailbox 5 Register
Addr:	00000000000D0055 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_HOST_SBE_MBOX5_REG
Constant(s):	PU_PSU_HOST_SBE_MBOX5_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_SBESUPPUNIT.PSU_HOST_SBE_MBOX5_REG_OUT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			HOST_SBE_MBOX5: Mailbox Register for Host-SBE communication

Host/SBE Mailbox 6 Register
Addr:	00000000000D0056 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_HOST_SBE_MBOX6_REG
Constant(s):	PU_PSU_HOST_SBE_MBOX6_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_SBESUPPUNIT.PSU_HOST_SBE_MBOX6_REG_OUT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			HOST_SBE_MBOX6: Mailbox Register for Host-SBE communication

Host/SBE Mailbox 7 Register
Addr:	00000000000D0057 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PSU_HOST_SBE_MBOX7_REG
Constant(s):	PU_PSU_HOST_SBE_MBOX7_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_SBESUPPUNIT.PSU_HOST_SBE_MBOX7_REG_OUT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			HOST_SBE_MBOX7: Mailbox Register for Host-SBE communication

SBE Doorbell Register
Addr:	00000000000D0060 (SCOM) 00000000000D0061 (SCOM1) 00000000000D0062 (SCOM2)
Name:	TP.TPCHIP.PIB.PSU.PSU_SBE_DOORBELL_REG
Constant(s):	PU_PSU_SBE_DOORBELL_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_SBESUPPUNIT.PSU_SBE_DOORBELL_REG_OUT_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0	RW	WO_AND	WO_OR	SBE_DOORBELL_0: Doorbell Register bit to trigger SBE interrupt psu_sbe_interrupt_msg_available.Set by host firmware to inform the SBE about a waiting message in the Host/SBE Mailbox Registers. psu_sbe_interrupt_msg_available is set if at least one of the 16 doorbell bits is set and its corresponding mask bit is not set.
1	RW	WO_AND	WO_OR	SBE_DOORBELL_1:
2	RW	WO_AND	WO_OR	SBE_DOORBELL_2:
3	RW	WO_AND	WO_OR	SBE_DOORBELL_3:
4	RW	WO_AND	WO_OR	SBE_DOORBELL_4:
5	RW	WO_AND	WO_OR	SBE_DOORBELL_5:
6	RW	WO_AND	WO_OR	SBE_DOORBELL_6:
7	RW	WO_AND	WO_OR	SBE_DOORBELL_7:
8	RW	WO_AND	WO_OR	SBE_DOORBELL_8:
9	RW	WO_AND	WO_OR	SBE_DOORBELL_9:
10	RW	WO_AND	WO_OR	SBE_DOORBELL_10:
11	RW	WO_AND	WO_OR	SBE_DOORBELL_11:
12	RW	WO_AND	WO_OR	SBE_DOORBELL_12:
13	RW	WO_AND	WO_OR	SBE_DOORBELL_13:
14	RW	WO_AND	WO_OR	SBE_DOORBELL_14:
15	RW	WO_AND	WO_OR	SBE_DOORBELL_15:
16	RW	WO_AND	WO_OR	SBE_DOORBELL_MASK_0: Mask bit for Doorbell Register bit 0. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
17	RW	WO_AND	WO_OR	SBE_DOORBELL_MASK_1: Mask bit for Doorbell Register bit 1. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
18	RW	WO_AND	WO_OR	SBE_DOORBELL_MASK_2: Mask bit for Doorbell Register bit 2. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
19	RW	WO_AND	WO_OR	SBE_DOORBELL_MASK_3: Mask bit for Doorbell Register bit 3. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
20	RW	WO_AND	WO_OR	SBE_DOORBELL_MASK_4: Mask bit for Doorbell Register bit 4. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
21	RW	WO_AND	WO_OR	SBE_DOORBELL_MASK_5: Mask bit for Doorbell Register bit 5. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
22	RW	WO_AND	WO_OR	SBE_DOORBELL_MASK_6: Mask bit for Doorbell Register bit 6. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
23	RW	WO_AND	WO_OR	SBE_DOORBELL_MASK_7: Mask bit for Doorbell Register bit 7. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
24	RW	WO_AND	WO_OR	SBE_DOORBELL_MASK_8: Mask bit for Doorbell Register bit 8. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
25	RW	WO_AND	WO_OR	SBE_DOORBELL_MASK_9: Mask bit for Doorbell Register bit 9. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
26	RW	WO_AND	WO_OR	SBE_DOORBELL_MASK_10: Mask bit for Doorbell Register bit 10. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
27	RW	WO_AND	WO_OR	SBE_DOORBELL_MASK_11: Mask bit for Doorbell Register bit 11. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
28	RW	WO_AND	WO_OR	SBE_DOORBELL_MASK_12: Mask bit for Doorbell Register bit 12. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
29	RW	WO_AND	WO_OR	SBE_DOORBELL_MASK_13: Mask bit for Doorbell Register bit 13. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
30	RW	WO_AND	WO_OR	SBE_DOORBELL_MASK_14: Mask bit for Doorbell Register bit 14. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
31	RW	WO_AND	WO_OR	SBE_DOORBELL_MASK_15: Mask bit for Doorbell Register bit 15. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.

Host Doorbell Register
Addr:	00000000000D0063 (SCOM) 00000000000D0064 (SCOM1) 00000000000D0065 (SCOM2)
Name:	TP.TPCHIP.PIB.PSU.PSU_HOST_DOORBELL_REG
Constant(s):	PU_PSU_HOST_DOORBELL_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_SBESUPPUNIT.PSU_HOST_DOORBELL_REG_OUT_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0	RW	WO_AND	WO_OR	HOST_DOORBELL_0: Doorbell Register to trigger Host Bridge interrupt tppsu_tpbr_interrupt_msg_available.Set by the SBE to inform host firmware about a response message in the Host/SBE Mailbox Registers. tppsu_tpbr_interrupt_msg_available is set if at least one of the 16 doorbell bits is set and its corresponding mask bit is not set.
1	RW	WO_AND	WO_OR	HOST_DOORBELL_1:
2	RW	WO_AND	WO_OR	HOST_DOORBELL_2:
3	RW	WO_AND	WO_OR	HOST_DOORBELL_3:
4	RW	WO_AND	WO_OR	HOST_DOORBELL_4:
5	RW	WO_AND	WO_OR	HOST_DOORBELL_5:
6	RW	WO_AND	WO_OR	HOST_DOORBELL_6:
7	RW	WO_AND	WO_OR	HOST_DOORBELL_7:
8	RW	WO_AND	WO_OR	HOST_DOORBELL_8:
9	RW	WO_AND	WO_OR	HOST_DOORBELL_9:
10	RW	WO_AND	WO_OR	HOST_DOORBELL_10:
11	RW	WO_AND	WO_OR	HOST_DOORBELL_11:
12	RW	WO_AND	WO_OR	HOST_DOORBELL_12:
13	RW	WO_AND	WO_OR	HOST_DOORBELL_13:
14	RW	WO_AND	WO_OR	HOST_DOORBELL_14:
15	RW	WO_AND	WO_OR	HOST_DOORBELL_15:
16	RW	WO_AND	WO_OR	HOST_DOORBELL_MASK_0: Mask bit for Doorbell Register bit 0. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
17	RW	WO_AND	WO_OR	HOST_DOORBELL_MASK_1: Mask bit for Doorbell Register bit 1. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
18	RW	WO_AND	WO_OR	HOST_DOORBELL_MASK_2: Mask bit for Doorbell Register bit 2. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
19	RW	WO_AND	WO_OR	HOST_DOORBELL_MASK_3: Mask bit for Doorbell Register bit 3. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
20	RW	WO_AND	WO_OR	HOST_DOORBELL_MASK_4: Mask bit for Doorbell Register bit 4. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
21	RW	WO_AND	WO_OR	HOST_DOORBELL_MASK_5: Mask bit for Doorbell Register bit 5. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
22	RW	WO_AND	WO_OR	HOST_DOORBELL_MASK_6: Mask bit for Doorbell Register bit 6. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
23	RW	WO_AND	WO_OR	HOST_DOORBELL_MASK_7: Mask bit for Doorbell Register bit 7. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
24	RW	WO_AND	WO_OR	HOST_DOORBELL_MASK_8: Mask bit for Doorbell Register bit 8. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
25	RW	WO_AND	WO_OR	HOST_DOORBELL_MASK_9: Mask bit for Doorbell Register bit 9. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
26	RW	WO_AND	WO_OR	HOST_DOORBELL_MASK_10: Mask bit for Doorbell Register bit 10. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
27	RW	WO_AND	WO_OR	HOST_DOORBELL_MASK_11: Mask bit for Doorbell Register bit 11. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
28	RW	WO_AND	WO_OR	HOST_DOORBELL_MASK_12: Mask bit for Doorbell Register bit 12. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
29	RW	WO_AND	WO_OR	HOST_DOORBELL_MASK_13: Mask bit for Doorbell Register bit 13. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
30	RW	WO_AND	WO_OR	HOST_DOORBELL_MASK_14: Mask bit for Doorbell Register bit 14. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.
31	RW	WO_AND	WO_OR	HOST_DOORBELL_MASK_15: Mask bit for Doorbell Register bit 15. A '1' in this bit prevents the corresponding doorbell bit from generating an interrupt.

Disable hang counter stop for system xstop
Addr:	00000000000D0070 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.HANG_PULSE_CONFIG_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_HANG_PULSE_GEN.CONFIG_REG.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	RW			DISABLE_STOP_ON_XSTOP: Disable hang counter stop for system xstop

Hang pulse generation register 0
Addr:	00000000000D0071 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.HANG_PULSE_0_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:6	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_HANG_PULSE_GEN.HANG_PULSE_0_REG.LATC.L2(0:6) [0000000]
Bit(s)	SCOM			Dial: Description
0:5	RW			HANG_PULSE_REG_0: Value of Constant Hang Pulse 0. Time period = 2^value * (precounter_reg+1) / pcb_freq, 34>=value>0
6	RW			SUPPRESS_HANG_0: If set to '1', hang pulses are suppressed in case of a xstop

Pre-Divider for hang counter 0
Addr:	00000000000D0072 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PRE_COUNTER_REG_0
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_HANG_PULSE_GEN.PRECOUNT_VAL_0_REG.LATC.L2(0:7) [00000000]
Bit(s)	SCOM			Dial: Description
0:7	RW			PRE_COUNTER0: Divider for Constant Hang Counter Clock. Divides clock by n+1 (default: n=0)

Hang pulse generation register 1
Addr:	00000000000D0073 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.HANG_PULSE_1_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:6	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_HANG_PULSE_GEN.HANG_PULSE_1_REG.LATC.L2(0:6) [0000000]
Bit(s)	SCOM			Dial: Description
0:5	RW			HANG_PULSE_REG_1: Value of Constant Hang Pulse 1. Time period = 2^value * (precounter_reg+1) / pcb_freq, 34>=value>0
6	RW			SUPPRESS_HANG_1: If set to '1', hang pulses are suppressed in case of a xstop

Pre-Divider for hang counter 1
Addr:	00000000000D0074 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PRE_COUNTER_REG_1
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_HANG_PULSE_GEN.PRECOUNT_VAL_1_REG.LATC.L2(0:7) [00000000]
Bit(s)	SCOM			Dial: Description
0:7	RW			PRE_COUNTER1: Divider for Constant Hang Counter Clock. Divides clock by n+1 (default: n=0)

Hang pulse generation register 2
Addr:	00000000000D0075 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.HANG_PULSE_2_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:6	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_HANG_PULSE_GEN.HANG_PULSE_2_REG.LATC.L2(0:6) [0000000]
Bit(s)	SCOM			Dial: Description
0:5	RW			HANG_PULSE_REG_2: Value of Constant Hang Pulse 2. Time period = 2^value * (precounter_reg+1) / pcb_freq, 34>=value>0
6	RW			SUPPRESS_HANG_2: If set to '1', hang pulses are suppressed in case of a xstop

Pre-Divider for hang counter 2
Addr:	00000000000D0076 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PRE_COUNTER_REG_2
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_HANG_PULSE_GEN.PRECOUNT_VAL_2_REG.LATC.L2(0:7) [00000000]
Bit(s)	SCOM			Dial: Description
0:7	RW			PRE_COUNTER2: Divider for Constant Hang Counter Clock. Divides clock by n+1 (default: n=0)

Hang pulse generation register 3
Addr:	00000000000D0077 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.HANG_PULSE_3_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:6	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_HANG_PULSE_GEN.HANG_PULSE_3_REG.LATC.L2(0:6) [0000000]
Bit(s)	SCOM			Dial: Description
0:5	RW			HANG_PULSE_REG_3: Value of Constant Hang Pulse 3. Time period = 2^value * (precounter_reg+1) / pcb_freq, 34>=value>0
6	RW			SUPPRESS_HANG_3: If set to '1', hang pulses are suppressed in case of a xstop

Pre-Divider for hang counter 3
Addr:	00000000000D0078 (SCOM)
Name:	TP.TPCHIP.PIB.PSU.PRE_COUNTER_REG_3
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.PIB.PSU.PSUCOMP.PSU_HANG_PULSE_GEN.PRECOUNT_VAL_3_REG.LATC.L2(0:7) [00000000]
Bit(s)	SCOM			Dial: Description
0:7	RW			PRE_COUNTER3: Divider for Constant Hang Counter Clock. Divides clock by n+1 (default: n=0)

PPE External Interface XCR
Addr:	00000000000E0000 (SCOM)
Name:	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.PPE_XIXCR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: External Control Register (XCR) and Count (CTR). Note this XIR is slightly modified from P9, which did not include CTR. Note: this register is SCOM-only, not local register accessible.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.LT_XIR_XCR_CMND.LATC.L2(0:2) [000]
	32:63	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_CTR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RO			constant=0b0
1:3	WOX			PPE_XIXCR_XCR: PPE External Control Register See PPE Specification for bit definitions.
4:31	RO			constant=0b0000000000000000000000000000
32:63	RO			NULL_CTR_CTR:

PPE External Interface RAMRA
Addr:	00000000000E0001 (SCOM)
Name:	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.PPE_XIRAMRA
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: Ram Restore Acceleration Register. Can be used to restore SPRG0 plus Resume (or Single Step) with one command. Note: this register is SCOM-only, not local register accessible.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:3	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.LT_XIR_XCR_CMND.LATC.L2(0:2) [000]
	32:63	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_SPRG0.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RO			constant=0b0
1:3	WOX			PPE_XIXCR_XCR: PPE External Control Register See PPE Specification for bit definitions.
4:31	RO			constant=0b0000000000000000000000000000
32:63	WO			SPRG0

PPE External Interface RAMGA
Addr:	00000000000E0002 (SCOM)
Name:	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.PPE_XIRAMGA
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: Ram GPR Acceleration Register. Can be used to modify a GPR with one command (where IR = MFSPRG0 instruction 0xFC2082A6 .. 0xFFD082A6). Note: this register is SCOM-only, not local register accessible.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_ISP.LT_IR.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_SPRG0.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	WO			PPE_XIRAMEDR_IR: PPE Instruction Register. Writes cause a RAM operation. Provides the requested PPE Instruction to execute.
32:63	WO			SPRG0

PPE External Interface RAMDBG
Addr:	00000000000E0003 (SCOM)
Name:	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.PPE_XIRAMDBG
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: Ram & Debug Register. Read status and data. Allows write ability to modify only SPRG0 for a subsequent RAM operation. Note: this register is SCOM-only, not local register accessible.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.XSR_INT_SPR(0) [0]
	1:3	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_XSR_HC.LATC.L2(0:2) [000]
	4	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_XSR_HCP.LATC.L2(0) [0]
	5	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_XSR_RIP.LATC.L2(0) [0]
	6	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_XSR_SIP.LATC.L2(0) [0]
	7	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_XSR_TRAP.LATC.L2(0) [0]
	8	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_XSR_IAC.LATC.L2(0) [0]
	9:11	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(9:11) [000]
	12	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_XSR_RDAC.LATC.L2(0) [0]
	13	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_XSR_WDAC.LATC.L2(0) [0]
	14	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(13) [0]
	15	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_XSR_TRH.LATC.L2(0) [0]
	16:19	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_DECODER.FSM_STATE_LATCH.LATC.L2(0:3) [0000]
	20	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(12) [0]
	21	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_XSR_EP.LATC.L2(0) [0]
	24:25	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_ISR_24_25.LATC.L2(24:25) [00]
	28:31	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_ISR_28_31.LATC.L2(28:31) [0000]
	32:63	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_SPRG0.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	ROX			XSR_HS
1:3	RWX			XSR_HC
4	ROX			XSR_HCP
5	ROX			XSR_RIP
6	ROX			XSR_SIP
7	RWX			XSR_TRAP
8	RWX			XSR_IAC
9:11	ROX			NULL_MSR_SIBRC:
12	RWX			XSR_RDAC
13	RWX			XSR_WDAC
14	ROX			NULL_MSR_WE:
15	ROX			XSR_TRH
16:19	ROX			XSR_SMS
20	ROX			NULL_MSR_LP:
21	ROX			XSR_EP
22:23	RO			constant=0b00
24	ROX			XSR_PTR
25	ROX			XSR_ST
26:27	RO			constant=0b00
28	ROX			XSR_MFE
29:31	ROX			XSR_MCS
32:63	RWX			SPRG0

PPE External Interface RAMEDR
Addr:	00000000000E0004 (SCOM)
Name:	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.PPE_XIRAMEDR
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: Ram & Error Diagnosis Register. Can be used to read IR and EDR for debug. Also provides ability to RAM an instruction without modifying SPRG0. Note: this register is SCOM-only, not local register accessible.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_ISP.LT_IR.LATC.L2(0:31) [00000000000000000000000000000000]
	32:63	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_EDR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	RW			PPE_XIRAMEDR_IR: PPE Instruction Register. Writes cause a RAM operation. Provides the requested PPE Instruction to execute.
32:63	ROX			PPE_XIRAMEDR_EDR: Error Data Register, set on PPE interrupts caused by an error. See PPE Specification for definition.

PPE External Interface DBGPRO
Addr:	00000000000E0005 (SCOM)
Name:	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.PPE_XIDBGPRO
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: Debug & Runtime Profiling Read program location and status. Also used to write XSR & IAR. Note: this register is SCOM-only, not local register accessible.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.XSR_INT_SPR(0) [0]
	1:3	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_XSR_HC.LATC.L2(0:2) [000]
	4	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_XSR_HCP.LATC.L2(0) [0]
	5	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_XSR_RIP.LATC.L2(0) [0]
	6	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_XSR_SIP.LATC.L2(0) [0]
	7	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_XSR_TRAP.LATC.L2(0) [0]
	8	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_XSR_IAC.LATC.L2(0) [0]
	9:11	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(9:11) [000]
	12	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_XSR_RDAC.LATC.L2(0) [0]
	13	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_XSR_WDAC.LATC.L2(0) [0]
	14	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(13) [0]
	15	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_XSR_TRH.LATC.L2(0) [0]
	16:19	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_DECODER.FSM_STATE_LATCH.LATC.L2(0:3) [0000]
	20	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_MSR_9_13.LATC.L2(12) [0]
	21	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_XSR_EP.LATC.L2(0) [0]
	24:25	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_ISR_24_25.LATC.L2(24:25) [00]
	28:31	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_ISR_28_31.LATC.L2(28:31) [0000]
	32:61	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_ISP.LT_IAR.LATC.L2(0:29) [000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	ROX			XSR_HS
1:3	RWX			XSR_HC
4	ROX			XSR_HCP
5	ROX			XSR_RIP
6	ROX			XSR_SIP
7	RWX			XSR_TRAP
8	RWX			XSR_IAC
9:11	ROX			NULL_MSR_SIBRC:
12	RWX			XSR_RDAC
13	RWX			XSR_WDAC
14	ROX			NULL_MSR_WE:
15	ROX			XSR_TRH
16:19	ROX			XSR_SMS
20	ROX			NULL_MSR_LP:
21	ROX			XSR_EP
22:23	RO			constant=0b00
24	ROX			XSR_PTR
25	ROX			XSR_ST
26:27	RO			constant=0b00
28	ROX			XSR_MFE
29:31	ROX			XSR_MCS
32:61	RWX			IAR
62:63	RO			constant=0b00

MIB External Interface SIB Info
Addr:	00000000000E0006 (SCOM)
Name:	TP.TPCHIP.PIB.SBE.SBEPM.MIB_XISIB
Constant(s):	PU_MIB_XISIB
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	32	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_R_NW_Q_INST.LATC.L2(0) [0]
	33	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_BUSY_Q_INST.LATC.L2(0) [0]
	34	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.PIB_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0]
	49:51	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.INCLUDE_PIBINTF_COMP.PIBINTF_COMP.PIB_RSP_INFO_Q_0_INST.LATC.L2(0:2) [000]
	62	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.IFETCH_PIB_PENDING_Q_INST.LATC.L2(0) [0]
	63	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.PIB_DATAOP_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0:31	ROX			MIB_XISIB_PIB_ADDR: PIB transaction buffer current or previous transaction byte address
32	ROX			MIB_XISIB_PIB_R_NW: PIB transaction buffer current or previous transaction type, read if '1' and write if '0'.
33	ROX			MIB_XISIB_PIB_BUSY: Indicates if the transaction buffer is occupied with an ongoing transaction. Busy is cleared when the transaction is completed.
34	ROX			MIB_XISIB_PIB_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the PIB interface can continue to service I-fetches (only in case of SBE instance).
35:48	RO			constant=0b00000000000000
49:51	ROX			MIB_XISIB_PIB_RSP_INFO: PIB transaction buffer response info. Current or previous transaction got an error on the PIB interface when non-zero.
52:61	RO			constant=0b0000000000
62	ROX			MIB_XISIB_PIB_IFETCH_PENDING: Indicates a instruction fetch is pending on the PIB interface when set to '1'.
63	ROX			MIB_XISIB_PIB_DATAOP_PENDING: Indicates a data transaction is pending on the PIB interface when set to '1'.

PPE External Interface MEM Info
Addr:	00000000000E0007 (SCOM)
Name:	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.PPE_XIMEM
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: Memory Interface Info for debug Note: this register is SCOM-only, not local register accessible.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.MEM_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	32	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.MEM_R_NW_Q_INST.LATC.L2(0) [0]
	33	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.MEM_BUSY_Q_INST.LATC.L2(0) [0]
	34	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.MEM_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0]
	35:42	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.MEM_BYTE_ENABLE_Q_0_INST.LATC.L2(0:7) [00000000]
	43	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.MEM_LINE_MODE_Q_INST.LATC.L2(0) [0]
	49:51	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.MEM_ERROR_Q_0_INST.LATC.L2(0:2) [000]
	62	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.IFETCH_MEM_PENDING_Q_INST.LATC.L2(0) [0]
	63	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.MEM_DATAOP_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0:31	ROX			PPE_XIMEM_MEM_ADDR: MEM transaction buffer current or previous transaction byte address.
32	ROX			PPE_XIMEM_MEM_R_NW: MEM transaction buffer current or previous transaction type, read if 1 and write if 0.
33	ROX			PPE_XIMEM_MEM_BUSY: Indicates if the transaction buffer is occupied with an ongoing transaction. Busy is cleared when the transaction is completed.
34	ROX			PPE_XIMEM_MEM_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the memory interface can continue to service I-fetches.
35:42	ROX			PPE_XIMEM_MEM_BYTE_ENABLE: MEM transaction buffer current or previous transaction byte enables.
43	ROX			PPE_XIMEM_MEM_LINE_MODE: MEM transaction buffer current or previous transaction line mode. Indicates a 32B read request when set to 1.
44:48	RO			constant=0b00000
49:51	ROX			PPE_XIMEM_MEM_ERROR: MEM transaction buffer error code. Current or previous transaction got an error on the memory interface when non-zero.
52:61	RO			constant=0b0000000000
62	ROX			PPE_XIMEM_MEM_IFETCH_PENDING: Indicates a instruction fetch is pending on the MEM interface when set to 1.
63	ROX			PPE_XIMEM_MEM_DATAOP_PENDING: Indicates a data transaction is pending on the MEM interface when set to 1.

PPE External Interface SGB Info
Addr:	00000000000E0008 (SCOM)
Name:	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.PPE_XISGB
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: Store Gather Buffer Info for debug Note: this register is SCOM-only, not local register accessible.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.STR_GTHR_ADDR_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
	35	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.MEM_IMPRECISE_ERROR_PENDING_Q_INST.LATC.L2(0) [0]
	36:39	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.STR_GTHR_VALID_Q_0_INST.LATC.L2(0:3) [0000]
	63	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.STR_GTHR_FLUSH_PENDING_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0:31	ROX			STORE_ADDRESS
32:34	RO			constant=0b000
35	ROX			PPE_XIMEM_MEM_IMPRECISE_ERROR_PENDING: Indicates that the current or previous transaction had an imprecise error. Cleared when it is reported back to PPE. Note: The address of the erroneous transaction is copied into the SGB address latches such that the memory interface can continue to service I-fetches.
36:39	ROX			SGB_BYTE_VALID
40:62	RO			constant=0b00000000000000000000000
63	ROX			SGB_FLUSH_PENDING

PPE External Interface Icache Info
Addr:	00000000000E0009 (SCOM)
Name:	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.PPE_XIICAC
Constant(s):
Comments:	Access to the Memory Bolt-ons External Interface Register (XIR) bus: Instruction Cache Info for debug Note: this register is SCOM-only, not local register accessible.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.ICACHE_COMP.ICACHE_TAG_ADDR_LATCH.LATC.L2(0:26) [000000000000000000000000000]
	32	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.ICACHE_COMP.ICACHE_ERR_LATCH.LATC.L2(0) [0]
	34	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.IFETCH_PIB_PENDING_Q_INST.LATC.L2(0) [0]
	35	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.IFETCH_MEM_PENDING_Q_INST.LATC.L2(0) [0]
	36:39	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.ICACHE_COMP.ICACHE_VALID_LATCH.LATC.L2(0:3) [0000]
Bit(s)	SCOM			Dial: Description
0:26	ROX			ICACHE_TAG_ADDR
27:31	RO			constant=0b00000
32	ROX			ICACHE_ERR
33	RO			constant=0b0
34	ROX			MIB_XISIB_PIB_IFETCH_PENDING: Indicates a instruction fetch is pending on the PIB interface when set to '1'.
35	ROX			PPE_XIMEM_MEM_IFETCH_PENDING: Indicates a instruction fetch is pending on the MEM interface when set to 1.
36:39	ROX			ICACHE_VALID
40:63	RO			constant=0b000000000000000000000000

PPE External Interface DBGINF
Addr:	00000000000E000F (SCOM)
Name:	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.PPE_XIDBGINF
Constant(s):
Comments:	Access to the PPE cores External Interface Register (XIR) bus: Debug Information (register 15) New for P10. Read registers containing the most recent program address information, the Save & Restore (most recent interrupt) and Link Register (most recent branch & link for procedure calls). Note: this register is SCOM-only, not local register accessible.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:29	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_SRR0.LATC.L2(0:29) [000000000000000000000000000000]
	32:63	TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.I_C_PPE42_SPR.LT_LR.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:29	RO			NULL_SRR0_SRR0: PPE Save & Restore Register 0 Contains address of the most recent interrupt taken.
30:31	RO			constant=0b00
32:63	RO			NULL_LR_LR: PPE Link Register. Contains address of the instruction following the most recent Branch with Link instruction executed, to give an idea from whence the code recently came.

Chiplet Control Register 0 - VITL CCFG
Addr:	0000000001000000 (SCOM) 0000000001000010 (SCOM1) 0000000001000020 (SCOM2)
Name:	TP.TPCHIP.TPC.CPLT_CTRL0
Constant(s):	PERV_1_CPLT_CTRL0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.TPC.EPS.CTRL.CPLT_CTRL0_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0	RW	WO_OR	WO_CLEAR	CTRL_CC_ABSTCLK_MUXSEL_DC: Select ABIST clock source for Arrays on Chiplet Boundary. When set to 1, clocks where used from Chiplet with ABIST
1	RW	WO_OR	WO_CLEAR	TC_UNIT_SYNCCLK_MUXSEL_DC: Select the sync clock for async latches (init value 1)
2	RW	WO_OR	WO_CLEAR	CTRL_CC_FLUSHMODE_INH: Prevent plats from going into flush mode (init value 1)
3	RW	WO_OR	WO_CLEAR	CTRL_CC_FORCE_ALIGN: Force align signal to be sent (init value 1, drop before dropping flushmode_inh)
4	RW	WO_OR	WO_CLEAR	TC_UNIT_ARY_WRT_THRU_DC: Set Array into write thru mode, used for LBIST
5	RW	WO_OR	WO_CLEAR	UNUSED_5A: unused
6	RW	WO_OR	WO_CLEAR	TC_VITL_PROTECTION: VITL LBIST protection - turn on for LBIST only
7	RW	WO_OR	WO_CLEAR	UNUSED_7A: unused
8	RW	WO_OR	WO_CLEAR	CTRL_CC_ABIST_RECOV_DISABLE_DC: new signal to disable recovery
9	RW	WO_OR	WO_CLEAR	UNUSED_9A: unused
10	RW	WO_OR	WO_CLEAR	UNUSED_10A: unused
11	RW	WO_OR	WO_CLEAR	RESERVED_11A: reserved
12	RW	WO_OR	WO_CLEAR	UNUSED_12A: unused
13	RW	WO_OR	WO_CLEAR	TC_UNIT_DETERMINISTIC_TEST_ENA_DC: Forces login into deterministic test mode e.g. for LBIST
14	RW	WO_OR	WO_CLEAR	TC_UNIT_CONSTRAIN_SAFESCAN_DC: Safe scan of N1L latches. Prevent lck when switching SE
15	RW	WO_OR	WO_CLEAR	TC_UNIT_RRFA_TEST_ENA_DC:
16	RW	WO_OR	WO_CLEAR	UNUSED_16A: unused
17	RW	WO_OR	WO_CLEAR	UNUSED_17A: unused
18	RW	WO_OR	WO_CLEAR	RESERVED_18A: reserved
19	RW	WO_OR	WO_CLEAR	RESERVED_19A: reserved
20:27	RW	WO_OR	WO_CLEAR	TC_PSRO_SEL_DC: PSRO Select
28	RW	WO_OR	WO_CLEAR	UNUSED_28A: unused
29	RW	WO_OR	WO_CLEAR	UNUSED_29A: unused
30	RW	WO_OR	WO_CLEAR	UNUSED_30A: unused
31	RW	WO_OR	WO_CLEAR	UNUSED_31A: unused
32	RW	WO_OR	WO_CLEAR	RESERVED_32A: reserved
33	RW	WO_OR	WO_CLEAR	RESERVED_33A: reserved
34	RW	WO_OR	WO_CLEAR	RESERVED_34A: reserved
35	RW	WO_OR	WO_CLEAR	RESERVED_35A: reserved
36	RW	WO_OR	WO_CLEAR	UNUSED_36A: unused
37	RW	WO_OR	WO_CLEAR	UNUSED_37A: unused
38	RW	WO_OR	WO_CLEAR	RESERVED_38A: reserved
39	RW	WO_OR	WO_CLEAR	RESERVED_39A: reserved
40:41	RW	WO_OR	WO_CLEAR	CTRL_MISC_CLKDIV_SEL_DC: Clock Divider Select 00=1024:1 01=64:1 10=16:1 11=4:1
42	RW	WO_OR	WO_CLEAR	RESERVED_42A: reserved
43	RW	WO_OR	WO_CLEAR	RESERVED_43A: reserved
44	RW	WO_OR	WO_CLEAR	UNUSED_44A: unused
45	RW	WO_OR	WO_CLEAR	CTRL_CC_OTP_PRGMODE_DC: TE=1 only - OTP ROM Program Mode
46	RW	WO_OR	WO_CLEAR	CTRL_CC_SSS_CALIBRATE_DC: TE=1 only -Sensors Calibration
47	RW	WO_OR	WO_CLEAR	CTRL_CC_PIN_LBIST_DC: TE=1 only - PIN LBIST mode - LBIST is controlled via Pin, not by OPCG
48	RW	WO_OR	WO_CLEAR	FREE_USAGE_48A: free usage
49	RW	WO_OR	WO_CLEAR	FREE_USAGE_49A: free usage
50	RW	WO_OR	WO_CLEAR	FREE_USAGE_50A: free usage
51	RW	WO_OR	WO_CLEAR	FREE_USAGE_51A: free usage
52	RW	WO_OR	WO_CLEAR	FREE_USAGE_52A: free usage
53	RW	WO_OR	WO_CLEAR	FREE_USAGE_53A: free usage
54	RW	WO_OR	WO_CLEAR	FREE_USAGE_54A: free usage
55	RW	WO_OR	WO_CLEAR	RESERVED_55A: reserved
56	RW	WO_OR	WO_CLEAR	FREE_USAGE_56A: free usage
57	RW	WO_OR	WO_CLEAR	FREE_USAGE_57A: free usage
58	RW	WO_OR	WO_CLEAR	FREE_USAGE_58A: free usage
59	RW	WO_OR	WO_CLEAR	FREE_USAGE_59A: free usage
60	RW	WO_OR	WO_CLEAR	FREE_USAGE_60A: free usage
61	RW	WO_OR	WO_CLEAR	FREE_USAGE_61A: free usage
62	RW	WO_OR	WO_CLEAR	FREE_USAGE_62A: free usage
63	RW	WO_OR	WO_CLEAR	FREE_USAGE_63A: free usage

Chiplet Control Register 1 - VITL CCFG
Addr:	0000000001000001 (SCOM) 0000000001000011 (SCOM1) 0000000001000021 (SCOM2)
Name:	TP.TPCHIP.TPC.CPLT_CTRL1
Constant(s):	PERV_1_CPLT_CTRL1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.TPC.EPS.CTRL.CPLT_CTRL1_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0	RW	WO_OR	WO_CLEAR	TC_UNIT_MULTICYCLE_TEST_FENCE_DC: Mutlicycle test fence for LBIST
1	RW	WO_OR	WO_CLEAR	UNUSED_1B: unused
2	RW	WO_OR	WO_CLEAR	UNUSED_2B: unused
3	RW	WO_OR	WO_CLEAR	UNUSED_3B: unused
4	RW	WO_OR	WO_CLEAR	TC_REGION0_FENCE_DC: Fence for perv region
5	RW	WO_OR	WO_CLEAR	TC_REGION1_FENCE_DC: Fence for region 1 - sbe
6	RW	WO_OR	WO_CLEAR	TC_REGION2_FENCE_DC: Fence for region 2 - pib
7	RW	WO_OR	WO_CLEAR	TC_REGION3_FENCE_DC: Fence for region 3 - occ
8	RW	WO_OR	WO_CLEAR	TC_REGION4_FENCE_DC: Fence for region 4 - net
9	RW	WO_OR	WO_CLEAR	TC_REGION5_FENCE_DC: Fence for region 5 - unused
10	RW	WO_OR	WO_CLEAR	TC_REGION6_FENCE_DC: Fence for region 6 - psi
11	RW	WO_OR	WO_CLEAR	TC_REGION7_FENCE_DC: Fence for region 7 - unused
12	RW	WO_OR	WO_CLEAR	TC_REGION8_FENCE_DC: Fence for region 8 - dpllpau
13	RW	WO_OR	WO_CLEAR	TC_REGION9_FENCE_DC: Fence for region 9 - dpllnest
14	RW	WO_OR	WO_CLEAR	TC_REGION10_FENCE_DC: Fence for region 10 - pllperv
15	RW	WO_OR	WO_CLEAR	TC_REGION11_FENCE_DC: Fence for region 11 - unused
16	RW	WO_OR	WO_CLEAR	TC_REGION12_FENCE_DC: Fence for region 12 - unused
17	RW	WO_OR	WO_CLEAR	TC_REGION13_FENCE_DC: Fence for region 13 - unused
18	RW	WO_OR	WO_CLEAR	TC_REGION14_FENCE_DC: Fence for region 14 - unused
19	RW	WO_OR	WO_CLEAR	UNUSED_19B: unused
20	RW	WO_OR	WO_CLEAR	EXPORT_FREEZE:
21	RW	WO_OR	WO_CLEAR	UNUSED_21B: unused
22	RW	WO_OR	WO_CLEAR	TC_STG_ACT_EN_DC:
23	RW	WO_OR	WO_CLEAR	UNUSED_23B: unused
24	RW	WO_OR	WO_CLEAR	UNUSED_24B: unused
25	RW	WO_OR	WO_CLEAR	UNUSED_25B: unused
26	RW	WO_OR	WO_CLEAR	UNUSED_26B: unused
27	RW	WO_OR	WO_CLEAR	UNUSED_27B: unused
28	RW	WO_OR	WO_CLEAR	UNUSED_28B: unused
29	RW	WO_OR	WO_CLEAR	UNUSED_29B: unused
30	RW	WO_OR	WO_CLEAR	UNUSED_30B: unused
31	RW	WO_OR	WO_CLEAR	UNUSED_31B: unused

Chiplet Control Register 2 - Region Partial Good
Addr:	0000000001000002 (SCOM) 0000000001000012 (SCOM1) 0000000001000022 (SCOM2)
Name:	TP.TPCHIP.TPC.CPLT_CTRL2
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	4:18	TP.TPCHIP.TPC.EPS.CTRL.CPLT_CTRL2_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:14) [000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0:3	RO	RO	RO	constant=0b0000
4	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION0_PGOOD: Partial Good for region0 0=bad, 1=good
5	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION1_PGOOD: Partial Good for region 1 - sbe 0=bad, 1=good
6	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION2_PGOOD: Partial Good for region 2 - pib 0=bad, 1=good
7	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION3_PGOOD: Partial Good for region 3 - occ 0=bad, 1=good
8	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION4_PGOOD: Partial Good for region 4 - net 0=bad, 1=good
9	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION5_PGOOD: Partial Good for region 5 - unused 0=bad, 1=good
10	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION6_PGOOD: Partial Good for region 6 - psi 0=bad, 1=good
11	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION7_PGOOD: Partial Good for region 7 - unused 0=bad, 1=good
12	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION8_PGOOD: Partial Good for region 8 - dpllpau 0=bad, 1=good
13	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION9_PGOOD: Partial Good for region 9 - dpllnest 0=bad, 1=good
14	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION10_PGOOD: Partial Good for region 10 - pllperv 0=bad, 1=good
15	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION11_PGOOD: Partial Good for region 11 - unused 0=bad, 1=good
16	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION12_PGOOD: Partial Good for region 12 - unused 0=bad, 1=good
17	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION13_PGOOD: Partial Good for region 13 - unused 0=bad, 1=good
18	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION14_PGOOD: Partial Good for region 14 - unused 0=bad, 1=good

Chiplet Control Register 3 - Region PSCOM Enable
Addr:	0000000001000003 (SCOM) 0000000001000013 (SCOM1) 0000000001000023 (SCOM2)
Name:	TP.TPCHIP.TPC.CPLT_CTRL3
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	4:18	TP.TPCHIP.TPC.EPS.CTRL.CPLT_CTRL3_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:14) [000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0:3	RO	RO	RO	constant=0b0000
4	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION0_PSCOM_EN: Region0 PSCOM enable - set to 1, to allow PSCOM access on this region
5	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION1_PSCOM_EN: region 1 - sbe - PSCOM enable - set to 1, to allow PSCOM access on this region
6	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION2_PSCOM_EN: region 2 - pib - PSCOM enable - set to 1, to allow PSCOM access on this region
7	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION3_PSCOM_EN: region 3 - occ - PSCOM enable - set to 1, to allow PSCOM access on this region
8	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION4_PSCOM_EN: region 4 - net - PSCOM enable - set to 1, to allow PSCOM access on this region
9	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION5_PSCOM_EN: region 5 - unused - PSCOM enable - set to 1, to allow PSCOM access on this region
10	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION6_PSCOM_EN: region 6 - psi - PSCOM enable - set to 1, to allow PSCOM access on this region
11	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION7_PSCOM_EN: region 7 - unused - PSCOM enable - set to 1, to allow PSCOM access on this region
12	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION8_PSCOM_EN: region 8 - dpllpau - PSCOM enable - set to 1, to allow PSCOM access on this region
13	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION9_PSCOM_EN: region 9 - dpllnest - PSCOM enable - set to 1, to allow PSCOM access on this region
14	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION10_PSCOM_EN: region 10 - pllperv - PSCOM enable - set to 1, to allow PSCOM access on this region
15	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION11_PSCOM_EN: region 11 - unused - PSCOM enable - set to 1, to allow PSCOM access on this region
16	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION12_PSCOM_EN: region 12 - unused - PSCOM enable - set to 1, to allow PSCOM access on this region
17	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION13_PSCOM_EN: region 13 - unused - PSCOM enable - set to 1, to allow PSCOM access on this region
18	RW	WO_OR	WO_CLEAR	CTRL_EPS_REGION14_PSCOM_EN: region 14 - unused - PSCOM enable - set to 1, to allow PSCOM access on this region

Chiplet Control Register 4 - Region Flushmode inhibit
Addr:	0000000001000004 (SCOM) 0000000001000014 (SCOM1) 0000000001000024 (SCOM2)
Name:	TP.TPCHIP.TPC.CPLT_CTRL4
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	4:18	TP.TPCHIP.TPC.EPS.CTRL.CPLT_CTRL4_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:14) [000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0:3	RO	RO	RO	constant=0b0000
4	RW	WO_OR	WO_CLEAR	CTRL_CC_REGION0_FLUSHMODE_INH: Region0 flushmode inhibit - set to 1, to bring only this region out of flush
5	RW	WO_OR	WO_CLEAR	CTRL_CC_REGION1_FLUSHMODE_INH: region 1 - sbe - flushmode inhibit - set to 1, to bring only this region out of flush
6	RW	WO_OR	WO_CLEAR	CTRL_CC_REGION2_FLUSHMODE_INH: region 2 - pib - flushmode inhibit - set to 1, to bring only this region out of flush
7	RW	WO_OR	WO_CLEAR	CTRL_CC_REGION3_FLUSHMODE_INH: region 3 - occ - flushmode inhibit - set to 1, to bring only this region out of flush
8	RW	WO_OR	WO_CLEAR	CTRL_CC_REGION4_FLUSHMODE_INH: region 4 - net - flushmode inhibit - set to 1, to bring only this region out of flush
9	RW	WO_OR	WO_CLEAR	CTRL_CC_REGION5_FLUSHMODE_INH: region 5 - unused - flushmode inhibit - set to 1, to bring only this region out of flush
10	RW	WO_OR	WO_CLEAR	CTRL_CC_REGION6_FLUSHMODE_INH: region 6 - psi - flushmode inhibit - set to 1, to bring only this region out of flush
11	RW	WO_OR	WO_CLEAR	CTRL_CC_REGION7_FLUSHMODE_INH: region 7 - unused - flushmode inhibit - set to 1, to bring only this region out of flush
12	RW	WO_OR	WO_CLEAR	CTRL_CC_REGION8_FLUSHMODE_INH: region 8 - dpllpau - flushmode inhibit - set to 1, to bring only this region out of flush
13	RW	WO_OR	WO_CLEAR	CTRL_CC_REGION9_FLUSHMODE_INH: region 9 - dpllnest - flushmode inhibit - set to 1, to bring only this region out of flush
14	RW	WO_OR	WO_CLEAR	CTRL_CC_REGION10_FLUSHMODE_INH: region 10 - pllperv - flushmode inhibit - set to 1, to bring only this region out of flush
15	RW	WO_OR	WO_CLEAR	CTRL_CC_REGION11_FLUSHMODE_INH: region 11 - unused - flushmode inhibit - set to 1, to bring only this region out of flush
16	RW	WO_OR	WO_CLEAR	CTRL_CC_REGION12_FLUSHMODE_INH: region 12 - unused - flushmode inhibit - set to 1, to bring only this region out of flush
17	RW	WO_OR	WO_CLEAR	CTRL_CC_REGION13_FLUSHMODE_INH: region 13 - unused - flushmode inhibit - set to 1, to bring only this region out of flush
18	RW	WO_OR	WO_CLEAR	CTRL_CC_REGION14_FLUSHMODE_INH: region 14 - unused - flushmode inhibit - set to 1, to bring only this region out of flush

Chiplet Control Register 5 - Power Gate
Addr:	0000000001000005 (SCOM) 0000000001000015 (SCOM1) 0000000001000025 (SCOM2)
Name:	TP.TPCHIP.TPC.CPLT_CTRL5
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:19	TP.TPCHIP.TPC.EPS.CTRL.CPLT_CTRL5_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:19) [00000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0	RW	WO_OR	WO_CLEAR	TP_AN_NMMU_PFET_ENABLE_DC: Power Gate Control
1	RW	WO_OR	WO_CLEAR	CPLT_CTRL5_01: Power Gate Control
2	RW	WO_OR	WO_CLEAR	CPLT_CTRL5_02: Power Gate Control
3	RW	WO_OR	WO_CLEAR	CPLT_CTRL5_03: Power Gate Control - EQ: DFT Fence vitl
4	RW	WO_OR	WO_CLEAR	TP_AN_EMO67_PFET_ENABLE_DC: Power Gate Control - EQ: DFT Fence Perv
5	RW	WO_OR	WO_CLEAR	TP_AN_EMO45_PFET_ENABLE_DC: Power Gate Control - EQ: DFT Fence region 1 - sbe -
6	RW	WO_OR	WO_CLEAR	TP_AN_EMO23_PFET_ENABLE_DC: Power Gate Control - EQ: DFT Fence region 2 - pib -
7	RW	WO_OR	WO_CLEAR	TP_AN_EMO01_PFET_ENABLE_DC: Power Gate Control - EQ: DFT Fence region 3 - occ -
8	RW	WO_OR	WO_CLEAR	TP_AN_PAU0_PFET_ENABLE_DC: Power Gate Control - EQ: DFT Fence region 4 - net -
9	RW	WO_OR	WO_CLEAR	CPLT_CTRL5_09: Power Gate Control - EQ: DFT Fence region 5 - unused -
10	RW	WO_OR	WO_CLEAR	CPLT_CTRL5_010: Power Gate Control - EQ: DFT Fence region 6 - psi -
11	RW	WO_OR	WO_CLEAR	TP_AN_PAU3_PFET_ENABLE_DC: Power Gate Control - EQ: DFT Fence region 7 - unused -
12	RW	WO_OR	WO_CLEAR	TP_AN_PAU4_PFET_ENABLE_DC: Power Gate Control - EQ: DFT Fence region 8 - dpllpau -
13	RW	WO_OR	WO_CLEAR	TP_AN_PAU5_PFET_ENABLE_DC: Power Gate Control - EQ: DFT Fence region 9 - dpllnest -
14	RW	WO_OR	WO_CLEAR	TP_AN_PAU6_PFET_ENABLE_DC: Power Gate Control - EQ: DFT Fence region 10 - pllperv -
15	RW	WO_OR	WO_CLEAR	TP_AN_PAU7_PFET_ENABLE_DC: Power Gate Control - EQ: DFT Fence region 11 - unused -
16	RW	WO_OR	WO_CLEAR	TP_AN_PCIE1_PFET_ENABLE_DC: Power Gate Control - EQ: DFT Fence region 12 - unused -
17	RW	WO_OR	WO_CLEAR	TP_AN_PCIE0_PFET_ENABLE_DC: Power Gate Control - EQ: DFT Fence region 13 - unused -
18	RW	WO_OR	WO_CLEAR	CPLT_CTRL5_018: Power Gate Control - EQ: DFT Fence region 14 - unused -
19	RW	WO_OR	WO_CLEAR	CPLT_CTRL5_019: Power Gate Control

Chiplet Config Register 0 - VITL FUNC
Addr:	0000000001000008 (SCOM) 0000000001000018 (SCOM1) 0000000001000028 (SCOM2)
Name:	TP.TPCHIP.TPC.CPLT_CONF0
Constant(s):	PERV_1_CPLT_CONF0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.TPC.EPS.CTRL.CPLT_CONF0_OUT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0:5	RW	WO_OR	WO_CLEAR	CTRL_MISC_PROBE0_SEL_DC: Probe 0 select please look at Probe spec for more details
6	RW	WO_OR	WO_CLEAR	RESERVED_6G: reserved
7	RW	WO_OR	WO_CLEAR	RESERVED_7G: reserved
8:13	RW	WO_OR	WO_CLEAR	CTRL_MISC_PROBE1_SEL_DC: Probe 1 select please look at Probe spec for more details
14	RW	WO_OR	WO_CLEAR	RESERVED_14G: reserved
15	RW	WO_OR	WO_CLEAR	RESERVED_15G: reserved
16:21	RW	WO_OR	WO_CLEAR	CTRL_MISC_PROBE2_SEL_DC: Probe 2 select please look at Probe spec for more details
22	RW	WO_OR	WO_CLEAR	RESERVED_22G: reserved
23	RW	WO_OR	WO_CLEAR	RESERVED_23G: reserved
24:29	RW	WO_OR	WO_CLEAR	CTRL_MISC_PROBE3_SEL_DC: Probe 3 select please look at Probe spec for more details
30	RW	WO_OR	WO_CLEAR	RESERVED_30G: reserved
31	RW	WO_OR	WO_CLEAR	RESERVED_31G: reserved
32	RW	WO_OR	WO_CLEAR	CTRL_MISC_OFLOW_FEH_SEL_DC: ABIST Overflow/Fail Ever Happen Select
33	RW	WO_OR	WO_CLEAR	CTRL_CC_SCAN_PROTECT_DC: Enables Scan Protection - Enables Scan Collision Error Mechanism
34	RW	WO_OR	WO_CLEAR	CTRL_CC_SDIS_DC_N: For Scan Diagnostic to Discable Scan path
35	RW	WO_OR	WO_CLEAR	CTRL_CC_SCAN_DIAG: For System Scan diag control
36	RW	WO_OR	WO_CLEAR	RESERVED_TEST_CONTROL_36G: reserved test control
37	RW	WO_OR	WO_CLEAR	RESERVED_TEST_CONTROL_37G: reserved test control
38	RW	WO_OR	WO_CLEAR	RESERVED_TEST_CONTROL_38G: reserved test control
39	RW	WO_OR	WO_CLEAR	RESERVED_TEST_CONTROL_39G: reserved test control
40	RW	WO_OR	WO_CLEAR	CTRL_EPS_MASK_VITL_PCB_ERR_DC: Mask VITL PCB Errors from CC or CPLT_CTRL
41	RW	WO_OR	WO_CLEAR	CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC: Mask VITL Errors in CC, which are not PCB related
42	RW	WO_OR	WO_CLEAR	RESERVED_42G: RESERVED
43	RW	WO_OR	WO_CLEAR	RESERVED_43G: RESERVED
44	RW	WO_OR	WO_CLEAR	TC_PCB_DBG_GLB_BRCST_EN: DD2 only: Enable Debug Broadcast
45	RW	WO_OR	WO_CLEAR	RESERVED_45G: reserved
46	RW	WO_OR	WO_CLEAR	TC_SKIT_CANARY_MODE_DC:
47	RW	WO_OR	WO_CLEAR	TC_TOPOLOGY_MODE_DC:
48:51	RW	WO_OR	WO_CLEAR	TC_TOPOLOGY_ID_DC: Topology ID
52:55	RW	WO_OR	WO_CLEAR	TP_AN_NEST_PROGDLY_SETTING_DC: Topology Mode
56:63	RW	WO_OR	WO_CLEAR	TP_AN_NEST_DCC_SETTING_DC:

Chiplet Config Register 1 - VITL FUNC
Addr:	0000000001000009 (SCOM) 0000000001000019 (SCOM1) 0000000001000029 (SCOM2)
Name:	TP.TPCHIP.TPC.CPLT_CONF1
Constant(s):	PERV_1_CPLT_CONF1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.TPC.EPS.CTRL.CPLT_CONF1_OUT_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0	RW	WO_OR	WO_CLEAR	UNUSED_0H: unused
1	RW	WO_OR	WO_CLEAR	UNUSED_1H: unused
2	RW	WO_OR	WO_CLEAR	UNUSED_2H: unused
3	RW	WO_OR	WO_CLEAR	UNUSED_3H: unused
4	RW	WO_OR	WO_CLEAR	UNUSED_4H: unused
5	RW	WO_OR	WO_CLEAR	UNUSED_5H: unused
6	RW	WO_OR	WO_CLEAR	UNUSED_6H: unused
7	RW	WO_OR	WO_CLEAR	UNUSED_7H: unused
8	RW	WO_OR	WO_CLEAR	UNUSED_8H: unused
9	RW	WO_OR	WO_CLEAR	UNUSED_9H: unused
10	RW	WO_OR	WO_CLEAR	UNUSED_10H: unused
11	RW	WO_OR	WO_CLEAR	UNUSED_11H: unused
12	RW	WO_OR	WO_CLEAR	UNUSED_12H: unused
13	RW	WO_OR	WO_CLEAR	UNUSED_13H: unused
14	RW	WO_OR	WO_CLEAR	UNUSED_14H: unused
15	RW	WO_OR	WO_CLEAR	UNUSED_15H: unused
16	RW	WO_OR	WO_CLEAR	UNUSED_16H: unused
17	RW	WO_OR	WO_CLEAR	UNUSED_17H: unused
18	RW	WO_OR	WO_CLEAR	UNUSED_18H: unused
19	RW	WO_OR	WO_CLEAR	UNUSED_19H: unused
20	RW	WO_OR	WO_CLEAR	UNUSED_20H: unused
21	RW	WO_OR	WO_CLEAR	UNUSED_21H: unused
22	RW	WO_OR	WO_CLEAR	UNUSED_22H: unused
23	RW	WO_OR	WO_CLEAR	UNUSED_23H: unused
24	RW	WO_OR	WO_CLEAR	UNUSED_24H: unused
25	RW	WO_OR	WO_CLEAR	UNUSED_25H: unused
26	RW	WO_OR	WO_CLEAR	UNUSED_26H: unused
27	RW	WO_OR	WO_CLEAR	UNUSED_27H: unused
28	RW	WO_OR	WO_CLEAR	UNUSED_28H: unused
29	RW	WO_OR	WO_CLEAR	UNUSED_29H: unused
30	RW	WO_OR	WO_CLEAR	UNUSED_30H: unused
31	RW	WO_OR	WO_CLEAR	UNUSED_31H: unused

Chiplet Status Register - Interrupt send out on bit change if not masked via Chiplet Mask Register. Mask only mask the interrupt, not the status register!
Addr:	0000000001000100 (SCOM)
Name:	TP.TPCHIP.TPC.CPLT_STAT0
Constant(s):	PERV_1_CPLT_STAT0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.TPC.EPS.CTRL.CPLT_STAT_OUT_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	ROX			ABIST_DONE_DC: abist_done_dc
1	ROX			EBIST_DONE_DC: ebist_done_dc
2	ROX			RESERVED_2I: reserved
3	ROX			RESERVED_3I: reserved
4	ROX			TC_DIAG_PORT0_OUT: Diagnostic out port
5	ROX			TC_DIAG_PORT1_OUT: Diagnostic out port
6	ROX			RESERVED_6I: reserved
7	ROX			PLL_DESTOUT: pll destout
8	ROX			CC_CTRL_OPCG_DONE_DC: OPCG done. For LBIST, ABIST, or other OPCG runs
9	ROX			CC_CTRL_CHIPLET_IS_ALIGNED_DC: Indicates that Chiplet is aligned
10	ROX			FREE_USAGE_10I: free usage
11	ROX			FREE_USAGE_11I: free usage
12	ROX			FREE_USAGE_12I: free usage
13	ROX			FREE_USAGE_13I: free usage
14	ROX			FREE_USAGE_14I: free usage
15	ROX			FREE_USAGE_15I: free usage
16	ROX			FREE_USAGE_16I: free usage
17	ROX			FREE_USAGE_17I: free usage
18	ROX			FREE_USAGE_18I: free usage
19	ROX			FREE_USAGE_19I: free usage
20	ROX			FREE_USAGE_20I: free usage
21	ROX			FREE_USAGE_21I: free usage
22	ROX			FREE_USAGE_22I: free usage
23	ROX			FREE_USAGE_23I: free usage
24	ROX			GLOBAL_FEH_DC: chiplet specific
25	ROX			FREE_USAGE_25I: free usage
26	ROX			FREE_USAGE_26I: free usage
27	ROX			FREE_USAGE_27I: free usage
28	ROX			FREE_USAGE_28I: free usage
29	ROX			FREE_USAGE_29I: free usage
30	ROX			FREE_USAGE_30I: free usage
31	ROX			FREE_USAGE_31I: free usage

Chiplet Mask Register - Masking the Interrupt on a bitchange of the Chiplet Status Register. Does not mask the status itself!
Addr:	0000000001000101 (SCOM)
Name:	TP.TPCHIP.TPC.CPLT_MASK0
Constant(s):	PERV_1_CPLT_MASK0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.TPC.EPS.CTRL.CPLT_MASK_OUT_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	RW			ITR_MASK: Bitwise masking of cplt_stat0 - will prevent interrupt

CTRL Protect Mode Register
Addr:	00000000010003FE (SCOM)
Name:	TP.TPCHIP.TPC.CTRL_PROTECT_MODE_REG
Constant(s):	PERV_1_CTRL_PROTECT_MODE_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.TPC.EPS.CTRL.PCB_IF.PROTECT_MODE.RD_PROTECT_ENA_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.TPC.EPS.CTRL.PCB_IF.PROTECT_MODE.WR_PROTECT_ENA_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	RW			CTRL_READ_PROTECT_ENABLE: Enable read protection
1	RW			CTRL_WRITE_PROTECT_ENABLE: Enable write protection

Atomic Lock Register
Addr:	00000000010003FF (SCOM)
Name:	TP.TPCHIP.TPC.CTRL_ATOMIC_LOCK_REG
Constant(s):	PERV_1_CTRL_ATOMIC_LOCK_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.TPC.EPS.CTRL.PCB_IF.ATOMIC_LOCK.ATOMIC_LOCK_ENA_INST.LATC.L2(0) [0]
	1:4	TP.TPCHIP.TPC.EPS.CTRL.PCB_IF.ATOMIC_LOCK.ATOMIC_ID_Q_INST.LATC.L2(0:3) [0000]
	8:15	TP.TPCHIP.TPC.EPS.CTRL.PCB_IF.ATOMIC_LOCK.ATOMIC_LOCK_ACTIVITY_Q_INST.LATC.L2(0:7) [00000000]
Bit(s)	SCOM			Dial: Description
0	RW			CTRL_ATOMIC_LOCK_ENABLE: Enable atomic lock
1:4	ROX			CTRL_ATOMIC_ID: Atomic ID
5:7	RO			constant=0b000
8:15	ROX			CTRL_ATOMIC_ACTIVITY: Atomic lock counter

PSCOMLE mode register
Addr:	0000000001010000 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.PSC.PSC.PSCOM_MODE_REG
Constant(s):	PERV_1_PSCOM_MODE_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:11	TP.TPCHIP.TPC.EPS.PSC.PSC.PSCOM_MODE_LT_INST.LATC.L2(0:11) [000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			ABORT_ON_PCB_ADDR_PARITY_ERROR: abort_on_PCB_addr_parity_error
1	RW			ABORT_ON_PCB_WDATA_PARITY_ERROR: abort_on_PCB_wdata_parity_error
2	RW			UNUSED_MODE_REG_BIT_2: unused_mode_reg_bit_2
3	RW			ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR: abort_on_DL_return_wdata_parity_error
4	RW			WATCHDOG_ENABLE: watchdog_enable
5:6	RW			SCOM_HANG_LIMIT: 0b11: 256, 0b10:512, 0b01:768, 0b00:1023
7	RW			FORCE_ALL_RINGS: set to logic 1 if all rings should be enable independent of ring address
8	RW			FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE: fsm_selfreset_on_statevec_parityerror_enable
9:11	RW			RESERVED_PSCOM_MODE_LT: reserved

PSCOMLE error register
Addr:	0000000001010001 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.PSC.PSC.PSCOM_STATUS_ERROR_REG
Constant(s):	PERV_1_PSCOM_STATUS_ERROR_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:17	TP.TPCHIP.TPC.EPS.PSC.PSC.PSCOM_ERR_LT_0_INST.LATC.L2(0:17) [000000000000000000]
	18:35	TP.TPCHIP.TPC.EPS.PSC.PSC.PSCOM_ERR_TRAP_LT_0_INST.LATC.L2(0:17) [000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RWX			ACCUMULATED_PCB_WDATA_PARITY_ERROR: Accumulated_PCB_wdata_parity_error
1	RWX			ACCUMULATED_PCB_ADDRESS_PARITY_ERROR: Accumulated_PCB_address_parity_error
2	RWX			ACCUMULATED_DL_RETURN_WDATA_PARITY_ERROR: Accumulated_DL_return_wdata_parity_error
3	RWX			ACCUMULATED_DL_RETURN_P0_ERROR: Accumulated_DL_return_P0_error
4	RWX			ACCUMULATED_UL_RDATA_PARITY_ERROR: Accumulated_UL_rdata_parity_error
5	RWX			ACCUMULATED_UL_P0_ERROR: Accumulated_UL_P0_error
6	RWX			ACCUMULATED_PARITY_ERROR_ON_INTERFACE_MACHINE: Accumulated_parity_error_on_interface_machine
7	RWX			ACCUMULATED_PARITY_ERROR_ON_P2S_MACHINE: Accumulated_parity_error_on_p2s_machine
8	RWX			ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH: Accumulated_timeout_while_waiting_for_ULCCH
9	RWX			ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN: Accumulated_timeout_while_waiting_for_DLDCH_return
10	RWX			ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH: Accumulated_timeout_while_waiting_for_ULDCH
11	RWX			ACCUMULATED_PSCOM_LOCK_ERR: Accumulated_pscom_lock_err
12	RWX			ACCUMULATED_PSCOM_PARALLEL_READ_WRITE_NVLD: Accumulated_pscom_parallel_read_write_nvld
13	RWX			ACCUMULATED_PSCOM_PARALLEL_ADDR_INVALID: Accumulated_pscom_parallel_addr_invalid
14	RWX			ACCUMULATED_PCB_COMMAND_PARITY_ERROR: Accumulated_PCB_command_parity_error
15	RWX			ACCUMULATED_GENERAL_TIMEOUT: Accumulated_General_timeout
16	RWX			ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION: Accumulated_satellite_acknowledge_access_violation
17	RWX			ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER: Accumulated_satellite_acknowledge_invalid_register
18	RWX			TRAPPED_PCB_WDATA_PARITY_ERROR: Trapped_PCB_wdata_parity_error
19	RWX			TRAPPED_PCB_ADDRESS_PARITY_ERROR: Trapped_PCB_address_parity_error
20	RWX			TRAPPED_DL_RETURN_WDATA_PARITY_ERROR: Trapped_DL_return_wdata_parity_error
21	RWX			TRAPPED_DL_RETURN_P0_ERROR: Trapped_DL_return_P0_error
22	RWX			TRAPPED_UL_RDATA_PARITY_ERROR: Trapped_UL_rdata_parity_error
23	RWX			TRAPPED_UL_P0_ERROR: Trapped_UL_P0_error
24	RWX			TRAPPED_PARITY_ERROR_ON_INTERFACE_MACHINE: Trapped_parity_error_on_interface_machine
25	RWX			TRAPPED_PARITY_ERROR_ON_P2S_MACHINE: Trapped_parity_error_on_p2s_machine
26	RWX			TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH: Trapped_timeout_while_waiting_for_ULCCH
27	RWX			TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN: Trapped_timeout_while_waiting_for_DLDCH_return
28	RWX			TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH: Trapped_timeout_while_waiting_for_ULDCH
29	RWX			TRAPPED_PSCOM_LOCK_ERR: Trapped_pscom_lock_err
30	RWX			TRAPPED_PSCOM_PARALLEL_READ_WRITE_NVLD: Trapped_pscom_parallel_read_write_nvld
31	RWX			TRAPPED_PSCOM_PARALLEL_ADDR_INVALID: Trapped_pscom_parallel_addr_invalid
32	RWX			TRAPPED_PCB_COMMAND_PARITY_ERROR: Trapped_PCB_command_parity_error
33	RWX			TRAPPED_GENERAL_TIMEOUT: Trapped_General_timeout
34	RWX			TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION: Trapped_satellite_acknowledge_access_violation
35	RWX			TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER: Trapped_satellite_acknowledge_invalid_register

PSCOMLE error mask register
Addr:	0000000001010002 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.PSC.PSC.PSCOM_ERROR_MASK
Constant(s):	PERV_1_PSCOM_ERROR_MASK
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:17	TP.TPCHIP.TPC.EPS.PSC.PSC.PSCOM_ERR_MASK_LT_INST.LATC.L2(0:17) [000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			MASK_PCB_WDATA_PARITY_ERROR: mask_PCB_wdata_parity_error
1	RW			MASK_PCB_ADDRESS_PARITY_ERROR: mask_PCB_address_parity_error
2	RW			MASK_DL_RETURN_WDATA_PARITY_ERROR: mask_DL_return_wdata_parity_error
3	RW			MASK_DL_RETURN_P0_ERROR: mask_DL_return_P0_error
4	RW			MASK_UL_RDATA_PARITY_ERROR: mask_UL_rdata_parity_error
5	RW			MASK_UL_P0_ERROR: mask_UL_P0_error
6	RW			MASK_PARITY_ERROR_ON_INTERFACE_MACHINE: mask_parity_error_on_interface_machine
7	RW			MASK_PARITY_ERROR_ON_P2S_MACHINE: mask_parity_error_on_p2s_machine
8	RW			MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH: mask_timeout_while_waiting_for_ULCCH
9	RW			MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN: mask_timeout_while_waiting_for_DLDCH_return
10	RW			MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH: mask_timeout_while_waiting_for_ULDCH
11	RW			MASK_PSCOM_LOCK_ERR: mask_pscom_lock_err
12	RW			MASK_PSCOM_PARALLEL_READ_WRITE_NVLD: mask_pscom_parallel_read_write_nvld
13	RW			MASK_PSCOM_PARALLEL_ADDR_INVALID: mask_pscom_parallel_addr_invalid
14	RW			MASK_PCB_COMMAND_PARITY_ERROR: mask_PCB_command_parity_error
15	RW			MASK_GENERAL_TIMEOUT: mask_general_timeout
16	RW			MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION: mask_satellite_acknowledge_access_violation
17	RW			MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER: mask_satellite_acknowledge_invalid_register

PSCOMLE Address Trap Register
Addr:	0000000001010003 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.PSC.PSC.ADDR_TRAP_REG
Constant(s):	PERV_1_ADDR_TRAP_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:17	TP.TPCHIP.TPC.EPS.PSC.PSC.ADDR_LAST_TRAP_LT_INST.LATC.L2(0:17) [000000000000000000]
	18:30	TP.TPCHIP.TPC.EPS.PSC.PSC.FSM_STATE_CAPTURE_LT_0_INST.LATC.L2(0:12) [0000000000000]
	31:34	TP.TPCHIP.TPC.EPS.PSC.PSC.SATELLITE_ACK_TRAP_LT_0_INST.LATC.L2(0:3) [0000]
	35:38	TP.TPCHIP.TPC.EPS.PSC.PSC.PCB_REQ_MASTER_ADDR_TRAP_LT_INST.LATC.L2(0:3) [0000]
Bit(s)	SCOM			Dial: Description
0:15	ROX			PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR: PCB_address_of_last_transaction_with_error
16	ROX			PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR: PCB_read_notwrite_of_last_transaction_with_error
17	ROX			RESERVED_ADDR_LAST_TRAP_LT: reserved_0
18:30	ROX			SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR: Serial2Parallel_state_machine_at_time_of_error
31	ROX			SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY: Satellite acknoledge bit: set to 1 if no parity error detected of Sat.No and Ack-bits
32	ROX			SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR: set if write parity error detected by satellite
33	ROX			SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION: set if invalid read or write access detected by satellite
34	ROX			SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER: set if invalid register address detected by satellite
35:38	ROX			LAST_MASTERID: MasterID of the last non-internal PSCOM transation

Ring Lock Enable Register
Addr:	0000000001010005 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.PSC.PSC.WRITE_PROTECT_ENABLE_REG
Constant(s):	PERV_1_WRITE_PROTECT_ENABLE_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:1	TP.TPCHIP.TPC.EPS.PSC.PSC.WRITE_PROTECT_Q_INST.LATC.L2(0:1) [00]
Bit(s)	SCOM			Dial: Description
0	RW			ENABLE_RING_LOCKING: General enable of ring locking upon write to specific ring
1	RW			RESERVED_RING_LOCKING: reserved

WRITE PROTECT RINGS Register
Addr:	0000000001010006 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.PSC.PSC.WRITE_PROTECT_RINGS_REG
Constant(s):	PERV_1_WRITE_PROTECT_RINGS_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.TPC.EPS.PSC.PSC.WRITE_PROTECT_RINGS_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	RW			WRITE_PROTECT_RINGS: write protect bit map for each ring

Atomic Lock Mask Register
Addr:	0000000001010007 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.PSC.PSC.ATOMIC_LOCK_MASK_LATCH_REG
Constant(s):	PERV_1_ATOMIC_LOCK_MASK_LATCH_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.TPC.EPS.PSC.PSC.ATOMIC_LOCK_ENABLE_MASK_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	RW			ATOMIC_LOCK_MASK: bit mask for atomic locking on a ring-by-ring basis

Ring Fence Enable Mask Register
Addr:	0000000001010008 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.PSC.PSC.RING_FENCE_MASK_LATCH_REG
Constant(s):	PERV_1_RING_FENCE_MASK_LATCH_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:31	TP.TPCHIP.TPC.EPS.PSC.PSC.RING_FENCE_ENABLE_MASK_Q_INST.LATC.L2(1:31) [0000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RO			constant=0b0
1:31	RW			RING_FENCE_ENABLE_MASK: bit mask for ring fenceing on a ring-by-ring basis

Trace Array High Data Register
Addr:	0000000001010400 (SCOM)
Name:	TP.TPCHIP.TPC.TRA0.TR0.TRACE_HI_DATA_REG
Constant(s):	PERV_1_TPCHIP_TRA0_TR0_TRACE_HI_DATA_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.TPC.TRA0.TR0.SAMP.TRACE_DATA_LT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	ROX			TRACE_HI_DATA: Trace Array Data 0:63

Trace Array Low Data Register
Addr:	0000000001010401 (SCOM)
Name:	TP.TPCHIP.TPC.TRA0.TR0.TRACE_LO_DATA_REG
Constant(s):	PERV_1_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.TPC.TRA0.TR0.SAMP.TRACE_DATA_LT_INST.LATC.L2(64:95) [00000000000000000000000000000000]
	32:41	TP.TPCHIP.TPC.TRA0.TR0.SAMP.TR_ADDRESS_LT_INST.LATC.L2(0:9) [0000000000]
	42:50	TP.TPCHIP.TPC.TRA0.TR0.SAMP.TR_LAST_BANK_LT_INST.LATC.L2(0:8) [000000000]
	51	TP.TPCHIP.TPC.TRA0.TR0.SAMP.TR_LAST_BANK_VALID_LT_INST.LATC.L2(0) [0]
	52	TP.TPCHIP.TPC.TRA0.TR0.SAMP.TR_WRITE_ON_RUN_LT_INST.LATC.L2(0) [0]
	53	TP.TPCHIP.TPC.TRA0.TR0.SAMP.TR_RUN_LT_INST.LATC.L2(0) [0]
	54:63	TP.TPCHIP.TPC.TRA0.TR0.SAMP.TR_HOLD_ADDRESS_LT_INST.LATC.L2(0:9) [0000000000]
Bit(s)	SCOM			Dial: Description
0:31	ROX			TRACE_LO_DATA: Trace Array Data 64:95
32:41	ROX			TRACE_ADDRESS: Trace Address
42:50	ROX			TRACE_LAST_BANK: Trace Last Bank
51	ROX			TRACE_LAST_BANK_VALID: Trace Last Bank Valid
52	ROX			TRACE_WRITE_ON_RUN: Trace Write-On-Run indicator
53	ROX			TRACE_RUNNING: Trace Run indicator
54:63	ROX			TRACE_HOLD_ADDRESS: Trace Hold Address (pointing to last entry)

trace control configuration register
Addr:	0000000001010402 (SCOM)
Name:	TP.TPCHIP.TPC.TRA0.TR0.TRACE_TRCTRL_CONFIG
Constant(s):	PERV_1_TPCHIP_TRA0_TR0_TRACE_TRCTRL_CONFIG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:27	TP.TPCHIP.TPC.TRA0.TR0.CTRL.SCOMABLE_0.TRCTRL_CONFIG_Q_INST.LATC.L2(0:27) [0000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			STORE_ON_TRIG_MODE: enable store on trigger mode
1	RW			WRITE_ON_RUN_MODE: NOT IMPLEMENTED, use TRACE_TRDATA_CONFIG_9 bit 0 instead: force unconditional write when trace_run
2:9	RW			EXTEND_TRIG_MODE: counter value for extended trigger mode
10	RW			BANK_MODE: enable bank mode
11	RW			ENH_TRACE_MODE: Suppress writing timestamps in store on trigger mode
12:13	RW			LOCAL_CLOCK_GATE_CONTROL: local clock gate control selection: x0 = normal clock gating; x1, = rd_act to trace array turned off
14:17	RW			TRACE_SELECT_CONTROL: selector for 2 sets of external trace bus multiplexers tra_mux0_sel(0:1) and tra_mux1_sel(0:1)
18	RW			TRACE_RUN_HOLD_OFF: hold trace_off when trace_run input is inactive
19	ROX			TRACE_RUN_STATUS: Actual current ORed status of trace_run inputs (trace_run from debug macro and unit logic)
20	RWX			TRACE_RUN_STICKY: trace_run sticky bit, set by trace_run, reset by write to trace_control_reg
21	RW			DISABLE_BANK_EDGE_DETECT: disable trace bank edge detect mode
22	RW			DISABLE_SCOM_TRCTRL_TRARR_RD_ACT: disable constant rd_act
23	RW			MASTER_CLOCK_ENABLE_INT: master clock enable switch
24:27	RW			TRACE_CONTROL_UNUSED: unused

trdata configuration register 0
Addr:	0000000001010403 (SCOM)
Name:	TP.TPCHIP.TPC.TRA0.TR0.TRACE_TRDATA_CONFIG_0
Constant(s):	PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.TPC.TRA0.TR0.DATA.SCOMABLE_CMP_MSK.CMP_MSK_INITONE_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			CMP_MSK_LT_B_0_TO_63: Trace data compression mask for trace bus bits 0 to 63. '1' means record an entry when this bit changes, '0' means ignore this bit. Setting the mask to all zeros will result in no trace entries being recorded just from bit changes.

trdata configuration register 1
Addr:	0000000001010404 (SCOM)
Name:	TP.TPCHIP.TPC.TRA0.TR0.TRACE_TRDATA_CONFIG_1
Constant(s):	PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:23	TP.TPCHIP.TPC.TRA0.TR0.DATA.SCOMABLE_CMP_MSK.CMP_MSK_INITONE_Q_0_INST.LATC.L2(64:87) [000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:23	RW			CMP_MSK_LT_B_64_TO_87: Trace data compression mask for bits 64 to 87. See TRACE_TRDATA_CONFIG_0 for meaning of bits.

trdata configuration register 2
Addr:	0000000001010405 (SCOM)
Name:	TP.TPCHIP.TPC.TRA0.TR0.TRACE_TRDATA_CONFIG_2
Constant(s):	PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_2
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:23	TP.TPCHIP.TPC.TRA0.TR0.DATA.PATTERN_MISR.PATA_Q_INST.LATC.L2(0:23) [000000000000000000000000]
	24:47	TP.TPCHIP.TPC.TRA0.TR0.DATA.PATTERN_MISR.PATB_Q_INST.LATC.L2(0:23) [000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:23	RW			PATTERNA: pattern_match_pata_0_to_23: pattern A for trace data compare function
24:47	RW			PATTERNB: pattern_match_patb_0_to_23: pattern B for trace data compare function

trdata configuration register 3
Addr:	0000000001010406 (SCOM)
Name:	TP.TPCHIP.TPC.TRA0.TR0.TRACE_TRDATA_CONFIG_3
Constant(s):	PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_3
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:23	TP.TPCHIP.TPC.TRA0.TR0.DATA.PATTERN_MISR.PATC_Q_INST.LATC.L2(0:23) [000000000000000000000000]
	24:47	TP.TPCHIP.TPC.TRA0.TR0.DATA.PATTERN_MISR.PATD_Q_INST.LATC.L2(0:23) [000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:23	RW			PATTERNC: pattern_match_patc_0_to_23: pattern C for trace data compare function
24:47	RW			PATTERND: pattern_match_patd_0_to_23: pattern D for trace data compare function

trdata configuration register 4
Addr:	0000000001010407 (SCOM)
Name:	TP.TPCHIP.TPC.TRA0.TR0.TRACE_TRDATA_CONFIG_4
Constant(s):	PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:23	TP.TPCHIP.TPC.TRA0.TR0.DATA.PATTERN_MISR.MSKA_Q_INST.LATC.L2(0:23) [000000000000000000000000]
	24:47	TP.TPCHIP.TPC.TRA0.TR0.DATA.PATTERN_MISR.MSKB_Q_INST.LATC.L2(0:23) [000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:23	RW			MASKA: mska: mask bits for pattern A trace data compare function: set to 1 to mask off individual bits
24:47	RW			MASKB: mskb: mask bits for pattern B trace data compare function: set to 1 to mask off individual bits

trdata configuration register 5
Addr:	0000000001010408 (SCOM)
Name:	TP.TPCHIP.TPC.TRA0.TR0.TRACE_TRDATA_CONFIG_5
Constant(s):	PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_5
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:23	TP.TPCHIP.TPC.TRA0.TR0.DATA.PATTERN_MISR.MSKC_Q_INST.LATC.L2(0:23) [000000000000000000000000]
	24:47	TP.TPCHIP.TPC.TRA0.TR0.DATA.PATTERN_MISR.MSKD_Q_INST.LATC.L2(0:23) [000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:23	RW			MASKC: mskc
24:47	RW			MASKD: mskd

trdata configuration register 9
Addr:	0000000001010409 (SCOM)
Name:	TP.TPCHIP.TPC.TRA0.TR0.TRACE_TRDATA_CONFIG_9
Constant(s):	PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:37	TP.TPCHIP.TPC.TRA0.TR0.DATA.SCOMABLE_CTRL.TRDATA_SCOM_CTRL_Q_0_INST.LATC.L2(0:37) [00000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			DISABLE_COMPRESSION: Disable Trace Data Compression (store data every cycle)
1	RW			ERROR_BIT_COMPRESSION_CARE_MASK: Take into account (care about) changes in the Error bit for trace data compression (default = 0)
2:3	RW			MATCHA_MUXSEL: Match PATTERNA against: 0b00 = Trace bus bits (00:23) 0b01 = Trace bus bits (24:47) 0b10 = Trace bus bits (48:71) 0b11 = Trace bus bits (72:87) | 8 zeroes Dial enums: BITS_00_TO_23=>0b00 BITS_24_TO_47=>0b01 BITS_48_TO_71=>0b10 BITS_72_TO_87_Z8=>0b11
4:5	RW			MATCHB_MUXSEL: Match PATTERNB against: 0b00 = Trace bus bits (00:23) 0b01 = Trace bus bits (24:47) 0b10 = Trace bus bits (48:71) 0b11 = Trace bus bits (72:87) | 8 zeroes Dial enums: BITS_00_TO_23=>0b00 BITS_24_TO_47=>0b01 BITS_48_TO_71=>0b10 BITS_72_TO_87_Z8=>0b11
6:7	RW			MATCHC_MUXSEL: Match PATTERNC against: 0b00 = Trace bus bits (00:23) 0b01 = Trace bus bits (24:47) 0b10 = Trace bus bits (48:71) 0b11 = Trace bus bits (72:87) | 8 zeroes Dial enums: BITS_00_TO_23=>0b00 BITS_24_TO_47=>0b01 BITS_48_TO_71=>0b10 BITS_72_TO_87_Z8=>0b11
8:9	RW			MATCHD_MUXSEL: Match PATTERND against: 0b00 = Trace bus bits (00:23) 0b01 = Trace bus bits (24:47) 0b10 = Trace bus bits (48:71) 0b11 = Trace bus bits (72:87) | 8 zeroes Dial enums: BITS_00_TO_23=>0b00 BITS_24_TO_47=>0b01 BITS_48_TO_71=>0b10 BITS_72_TO_87_Z8=>0b11
10:13	RW			TRIG0_OR_MASK: NOTE: the OR of all selected MATCHes is ORd with result of TRIG0_AND 0b1XXX selects MATCHA OR 0bX1XX selects MATCHB OR 0bXX1X selects MATCHC OR 0bXXX1 selects MATCHD OR 0b0000 selects to not OR any MATCHes
14:17	RW			TRIG0_AND_MASK: NOTE: the AND of following selected MATCHes is ORd with result of TRIG0_OR 0b1XXX selects MATCHA AND 0bX1XX selects MATCHB AND 0bXX1X selects MATCHC AND 0bXXX1 selects MATCHD AND 0b0000 selects to not AND any MATCHes together to form TRIG0
18:21	RW			TRIG1_OR_MASK: NOTE: the OR of all selected MATCHes is ORd with result of TRIG1_AND 0b1XXX selects MATCHA OR 0bX1XX selects MATCHB OR 0bXX1X selects MATCHC OR 0bXXX1 selects MATCHD OR 0b0000 selects to not OR any MATCHes to form TRIG1
22:25	RW			TRIG1_AND_MASK: NOTE: the AND of following selected MATCHes is ORd with result of TRIG1_OR 0b1XXX selects MATCHA AND 0bX1XX selects MATCHB AND 0bXX1X selects MATCHC AND 0bXXX1 selects MATCHD AND 0b0000 selects to not AND any MATCHes together to form TRIG1
26	RW			TRIG0_NOT_MODE: Invert TRIG0 before using it
27	RW			TRIG1_NOT_MODE: Invert TRIG1 before using it
28:31	RW			MATCH_NOT_MODE: Invert the match polarity before using it to form a TRIGger 0b1000 inverts MATCHA 0b0100 inverts MATCHB 0b0010 inverts MATCHC 0b0001 inverts MATCHD
32	RW			ERROR_CMP_MASK: 0 to compare the trace error bit, 1 to ignore it and always match. No, we don't think this makes sense either.
33	RW			ERROR_CMP_PATTERN: Value to compare trace error against
34	RW			TRIG0_ERR_CMP: Include (via OR) error comparison result into trig0
35	RW			TRIG1_ERR_CMP: Include (via OR) error comparison result into trig1
36	RW			DD1_STRETCH_TRIGGER_PULSES: (DD1 workaround) Stretch trigger output pulses to two clocks. Must be enabled for MCFAST and L2FAST traces.
37	RW			spare_lt

Trace Array High Data Register
Addr:	0000000001010440 (SCOM)
Name:	TP.TPCHIP.TPC.TRA0.TR1.TRACE_HI_DATA_REG
Constant(s):	PERV_1_TPCHIP_TRA0_TR1_TRACE_HI_DATA_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.TPC.TRA0.TR1.SAMP.TRACE_DATA_LT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	ROX			TRACE_HI_DATA: Trace Array Data 0:63

Trace Array Low Data Register
Addr:	0000000001010441 (SCOM)
Name:	TP.TPCHIP.TPC.TRA0.TR1.TRACE_LO_DATA_REG
Constant(s):	PERV_1_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.TPC.TRA0.TR1.SAMP.TRACE_DATA_LT_INST.LATC.L2(64:95) [00000000000000000000000000000000]
	32:41	TP.TPCHIP.TPC.TRA0.TR1.SAMP.TR_ADDRESS_LT_INST.LATC.L2(0:9) [0000000000]
	42:50	TP.TPCHIP.TPC.TRA0.TR1.SAMP.TR_LAST_BANK_LT_INST.LATC.L2(0:8) [000000000]
	51	TP.TPCHIP.TPC.TRA0.TR1.SAMP.TR_LAST_BANK_VALID_LT_INST.LATC.L2(0) [0]
	52	TP.TPCHIP.TPC.TRA0.TR1.SAMP.TR_WRITE_ON_RUN_LT_INST.LATC.L2(0) [0]
	53	TP.TPCHIP.TPC.TRA0.TR1.SAMP.TR_RUN_LT_INST.LATC.L2(0) [0]
	54:63	TP.TPCHIP.TPC.TRA0.TR1.SAMP.TR_HOLD_ADDRESS_LT_INST.LATC.L2(0:9) [0000000000]
Bit(s)	SCOM			Dial: Description
0:31	ROX			TRACE_LO_DATA: Trace Array Data 64:95
32:41	ROX			TRACE_ADDRESS: Trace Address
42:50	ROX			TRACE_LAST_BANK: Trace Last Bank
51	ROX			TRACE_LAST_BANK_VALID: Trace Last Bank Valid
52	ROX			TRACE_WRITE_ON_RUN: Trace Write-On-Run indicator
53	ROX			TRACE_RUNNING: Trace Run indicator
54:63	ROX			TRACE_HOLD_ADDRESS: Trace Hold Address (pointing to last entry)

trace control configuration register
Addr:	0000000001010442 (SCOM)
Name:	TP.TPCHIP.TPC.TRA0.TR1.TRACE_TRCTRL_CONFIG
Constant(s):	PERV_1_TPCHIP_TRA0_TR1_TRACE_TRCTRL_CONFIG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:27	TP.TPCHIP.TPC.TRA0.TR1.CTRL.SCOMABLE_0.TRCTRL_CONFIG_Q_INST.LATC.L2(0:27) [0000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			STORE_ON_TRIG_MODE: enable store on trigger mode
1	RW			WRITE_ON_RUN_MODE: NOT IMPLEMENTED, use TRACE_TRDATA_CONFIG_9 bit 0 instead: force unconditional write when trace_run
2:9	RW			EXTEND_TRIG_MODE: counter value for extended trigger mode
10	RW			BANK_MODE: enable bank mode
11	RW			ENH_TRACE_MODE: Suppress writing timestamps in store on trigger mode
12:13	RW			LOCAL_CLOCK_GATE_CONTROL: local clock gate control selection: x0 = normal clock gating; x1, = rd_act to trace array turned off
14:17	RW			TRACE_SELECT_CONTROL: selector for 2 sets of external trace bus multiplexers tra_mux0_sel(0:1) and tra_mux1_sel(0:1)
18	RW			TRACE_RUN_HOLD_OFF: hold trace_off when trace_run input is inactive
19	ROX			TRACE_RUN_STATUS: Actual current ORed status of trace_run inputs (trace_run from debug macro and unit logic)
20	RWX			TRACE_RUN_STICKY: trace_run sticky bit, set by trace_run, reset by write to trace_control_reg
21	RW			DISABLE_BANK_EDGE_DETECT: disable trace bank edge detect mode
22	RW			DISABLE_SCOM_TRCTRL_TRARR_RD_ACT: disable constant rd_act
23	RW			MASTER_CLOCK_ENABLE_INT: master clock enable switch
24:27	RW			TRACE_CONTROL_UNUSED: unused

trdata configuration register 0
Addr:	0000000001010443 (SCOM)
Name:	TP.TPCHIP.TPC.TRA0.TR1.TRACE_TRDATA_CONFIG_0
Constant(s):	PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.TPC.TRA0.TR1.DATA.SCOMABLE_CMP_MSK.CMP_MSK_INITONE_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			CMP_MSK_LT_B_0_TO_63: Trace data compression mask for trace bus bits 0 to 63. '1' means record an entry when this bit changes, '0' means ignore this bit. Setting the mask to all zeros will result in no trace entries being recorded just from bit changes.

trdata configuration register 1
Addr:	0000000001010444 (SCOM)
Name:	TP.TPCHIP.TPC.TRA0.TR1.TRACE_TRDATA_CONFIG_1
Constant(s):	PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:23	TP.TPCHIP.TPC.TRA0.TR1.DATA.SCOMABLE_CMP_MSK.CMP_MSK_INITONE_Q_0_INST.LATC.L2(64:87) [000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:23	RW			CMP_MSK_LT_B_64_TO_87: Trace data compression mask for bits 64 to 87. See TRACE_TRDATA_CONFIG_0 for meaning of bits.

trdata configuration register 2
Addr:	0000000001010445 (SCOM)
Name:	TP.TPCHIP.TPC.TRA0.TR1.TRACE_TRDATA_CONFIG_2
Constant(s):	PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_2
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:23	TP.TPCHIP.TPC.TRA0.TR1.DATA.PATTERN_MISR.PATA_Q_INST.LATC.L2(0:23) [000000000000000000000000]
	24:47	TP.TPCHIP.TPC.TRA0.TR1.DATA.PATTERN_MISR.PATB_Q_INST.LATC.L2(0:23) [000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:23	RW			PATTERNA: pattern_match_pata_0_to_23: pattern A for trace data compare function
24:47	RW			PATTERNB: pattern_match_patb_0_to_23: pattern B for trace data compare function

trdata configuration register 3
Addr:	0000000001010446 (SCOM)
Name:	TP.TPCHIP.TPC.TRA0.TR1.TRACE_TRDATA_CONFIG_3
Constant(s):	PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_3
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:23	TP.TPCHIP.TPC.TRA0.TR1.DATA.PATTERN_MISR.PATC_Q_INST.LATC.L2(0:23) [000000000000000000000000]
	24:47	TP.TPCHIP.TPC.TRA0.TR1.DATA.PATTERN_MISR.PATD_Q_INST.LATC.L2(0:23) [000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:23	RW			PATTERNC: pattern_match_patc_0_to_23: pattern C for trace data compare function
24:47	RW			PATTERND: pattern_match_patd_0_to_23: pattern D for trace data compare function

trdata configuration register 4
Addr:	0000000001010447 (SCOM)
Name:	TP.TPCHIP.TPC.TRA0.TR1.TRACE_TRDATA_CONFIG_4
Constant(s):	PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_4
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:23	TP.TPCHIP.TPC.TRA0.TR1.DATA.PATTERN_MISR.MSKA_Q_INST.LATC.L2(0:23) [000000000000000000000000]
	24:47	TP.TPCHIP.TPC.TRA0.TR1.DATA.PATTERN_MISR.MSKB_Q_INST.LATC.L2(0:23) [000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:23	RW			MASKA: mska: mask bits for pattern A trace data compare function: set to 1 to mask off individual bits
24:47	RW			MASKB: mskb: mask bits for pattern B trace data compare function: set to 1 to mask off individual bits

trdata configuration register 5
Addr:	0000000001010448 (SCOM)
Name:	TP.TPCHIP.TPC.TRA0.TR1.TRACE_TRDATA_CONFIG_5
Constant(s):	PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_5
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:23	TP.TPCHIP.TPC.TRA0.TR1.DATA.PATTERN_MISR.MSKC_Q_INST.LATC.L2(0:23) [000000000000000000000000]
	24:47	TP.TPCHIP.TPC.TRA0.TR1.DATA.PATTERN_MISR.MSKD_Q_INST.LATC.L2(0:23) [000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:23	RW			MASKC: mskc
24:47	RW			MASKD: mskd

trdata configuration register 9
Addr:	0000000001010449 (SCOM)
Name:	TP.TPCHIP.TPC.TRA0.TR1.TRACE_TRDATA_CONFIG_9
Constant(s):	PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:37	TP.TPCHIP.TPC.TRA0.TR1.DATA.SCOMABLE_CTRL.TRDATA_SCOM_CTRL_Q_0_INST.LATC.L2(0:37) [00000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			DISABLE_COMPRESSION: Disable Trace Data Compression (store data every cycle)
1	RW			ERROR_BIT_COMPRESSION_CARE_MASK: Take into account (care about) changes in the Error bit for trace data compression (default = 0)
2:3	RW			MATCHA_MUXSEL: Match PATTERNA against: 0b00 = Trace bus bits (00:23) 0b01 = Trace bus bits (24:47) 0b10 = Trace bus bits (48:71) 0b11 = Trace bus bits (72:87) | 8 zeroes Dial enums: BITS_00_TO_23=>0b00 BITS_24_TO_47=>0b01 BITS_48_TO_71=>0b10 BITS_72_TO_87_Z8=>0b11
4:5	RW			MATCHB_MUXSEL: Match PATTERNB against: 0b00 = Trace bus bits (00:23) 0b01 = Trace bus bits (24:47) 0b10 = Trace bus bits (48:71) 0b11 = Trace bus bits (72:87) | 8 zeroes Dial enums: BITS_00_TO_23=>0b00 BITS_24_TO_47=>0b01 BITS_48_TO_71=>0b10 BITS_72_TO_87_Z8=>0b11
6:7	RW			MATCHC_MUXSEL: Match PATTERNC against: 0b00 = Trace bus bits (00:23) 0b01 = Trace bus bits (24:47) 0b10 = Trace bus bits (48:71) 0b11 = Trace bus bits (72:87) | 8 zeroes Dial enums: BITS_00_TO_23=>0b00 BITS_24_TO_47=>0b01 BITS_48_TO_71=>0b10 BITS_72_TO_87_Z8=>0b11
8:9	RW			MATCHD_MUXSEL: Match PATTERND against: 0b00 = Trace bus bits (00:23) 0b01 = Trace bus bits (24:47) 0b10 = Trace bus bits (48:71) 0b11 = Trace bus bits (72:87) | 8 zeroes Dial enums: BITS_00_TO_23=>0b00 BITS_24_TO_47=>0b01 BITS_48_TO_71=>0b10 BITS_72_TO_87_Z8=>0b11
10:13	RW			TRIG0_OR_MASK: NOTE: the OR of all selected MATCHes is ORd with result of TRIG0_AND 0b1XXX selects MATCHA OR 0bX1XX selects MATCHB OR 0bXX1X selects MATCHC OR 0bXXX1 selects MATCHD OR 0b0000 selects to not OR any MATCHes
14:17	RW			TRIG0_AND_MASK: NOTE: the AND of following selected MATCHes is ORd with result of TRIG0_OR 0b1XXX selects MATCHA AND 0bX1XX selects MATCHB AND 0bXX1X selects MATCHC AND 0bXXX1 selects MATCHD AND 0b0000 selects to not AND any MATCHes together to form TRIG0
18:21	RW			TRIG1_OR_MASK: NOTE: the OR of all selected MATCHes is ORd with result of TRIG1_AND 0b1XXX selects MATCHA OR 0bX1XX selects MATCHB OR 0bXX1X selects MATCHC OR 0bXXX1 selects MATCHD OR 0b0000 selects to not OR any MATCHes to form TRIG1
22:25	RW			TRIG1_AND_MASK: NOTE: the AND of following selected MATCHes is ORd with result of TRIG1_OR 0b1XXX selects MATCHA AND 0bX1XX selects MATCHB AND 0bXX1X selects MATCHC AND 0bXXX1 selects MATCHD AND 0b0000 selects to not AND any MATCHes together to form TRIG1
26	RW			TRIG0_NOT_MODE: Invert TRIG0 before using it
27	RW			TRIG1_NOT_MODE: Invert TRIG1 before using it
28:31	RW			MATCH_NOT_MODE: Invert the match polarity before using it to form a TRIGger 0b1000 inverts MATCHA 0b0100 inverts MATCHB 0b0010 inverts MATCHC 0b0001 inverts MATCHD
32	RW			ERROR_CMP_MASK: 0 to compare the trace error bit, 1 to ignore it and always match. No, we don't think this makes sense either.
33	RW			ERROR_CMP_PATTERN: Value to compare trace error against
34	RW			TRIG0_ERR_CMP: Include (via OR) error comparison result into trig0
35	RW			TRIG1_ERR_CMP: Include (via OR) error comparison result into trig1
36	RW			DD1_STRETCH_TRIGGER_PULSES: (DD1 workaround) Stretch trigger output pulses to two clocks. Must be enabled for MCFAST and L2FAST traces.
37	RW			spare_lt

Debug macro configuration register 0 for config component
Addr:	00000000010107C0 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.DBG.DBG_MODE_REG
Constant(s):	PERV_1_DBG_MODE_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.TPC.EPS.DBG.CONFIG.DBG_LAT_REQ#0.LAT.DBG_REG_MODE.LATC.L2(0) [0]
	1	TP.TPCHIP.TPC.EPS.DBG.CONFIG.DBG_LAT_REQ#1.LAT.DBG_REG_MODE.LATC.L2(0) [0]
	2	TP.TPCHIP.TPC.EPS.DBG.CONFIG.DBG_LAT_REQ#2.LAT.DBG_REG_MODE.LATC.L2(0) [0]
	3	TP.TPCHIP.TPC.EPS.DBG.CONFIG.DBG_LAT_REQ#3.LAT.DBG_REG_MODE.LATC.L2(0) [0]
	4	TP.TPCHIP.TPC.EPS.DBG.CONFIG.DBG_LAT_REQ#4.LAT.DBG_REG_MODE.LATC.L2(0) [0]
	5	TP.TPCHIP.TPC.EPS.DBG.CONFIG.DBG_LAT_REQ#5.LAT.DBG_REG_MODE.LATC.L2(0) [0]
	6	TP.TPCHIP.TPC.EPS.DBG.CONFIG.DBG_LAT_REQ#6.LAT.DBG_REG_MODE.LATC.L2(0) [0]
	7	TP.TPCHIP.TPC.EPS.DBG.CONFIG.DBG_LAT_REQ#7.LAT.DBG_REG_MODE.LATC.L2(0) [0]
	8	TP.TPCHIP.TPC.EPS.DBG.CONFIG.DBG_LAT_REQ#8.LAT.DBG_REG_MODE.LATC.L2(0) [0]
	9	TP.TPCHIP.TPC.EPS.DBG.CONFIG.DBG_LAT_REQ#9.LAT.DBG_REG_MODE.LATC.L2(0) [0]
	10	TP.TPCHIP.TPC.EPS.DBG.CONFIG.DBG_LAT_REQ#10.LAT.DBG_REG_MODE.LATC.L2(0) [0]
	11	TP.TPCHIP.TPC.EPS.DBG.CONFIG.DBG_LAT_REQ#11.LAT.DBG_REG_MODE.LATC.L2(0) [0]
	12	TP.TPCHIP.TPC.EPS.DBG.CONFIG.DBG_LAT_REQ#12.LAT.DBG_REG_MODE.LATC.L2(0) [0]
	13	TP.TPCHIP.TPC.EPS.DBG.CONFIG.DBG_LAT_REQ#13.LAT.DBG_REG_MODE.LATC.L2(0) [0]
	16	TP.TPCHIP.TPC.EPS.DBG.DBG_PSC_SM_STATUS_INT(0) [0]
	17:18	TP.TPCHIP.TPC.EPS.DBG.BKEND.TRACE_STATE_LAT_INST.LATC.L2(0:1) [00]
	19	TP.TPCHIP.TPC.EPS.DBG.BKEND.TRACE_FREEZE_LT_INST.LATC.L2(0) [0]
	20:31	TP.TPCHIP.TPC.EPS.DBG.BKEND.CONDITION_HISTORY_Q_INST.LATC.L2(0:11) [000000000000]
Bit(s)	SCOM			Dial: Description
0:2	RW			GLB_BRCST_MODE: global_broadcast_mode (0 to 2): 100: dbg_trace_run & dbg_trace_freeze 101: pc_tcdbg_trace_run_fncd & dbg_trace_freeze 110: dbg_triggers_out(0 to 1) 111: pc_tcdbg_triggers(0 to 1) (from core) glb_brcst_mode
3:5	RW			TRACE_SEL_MODE: Select source for trace_run and bank 001: core trace run & bank 010: tp broadcast run & 0 011: tc_dbg_inter_brcst latched else: dbg_trace_run & dbg_trace_bank trace_sel_mode
6:7	RW			TRIG_SEL_MODE: Select source for tcdbg_trigger(0) 10: global broadcast 11: pc_tcdbg_trigger (from core) else: dbg_triggers_out(0:1) trig_sel_mode
8	RW			STOP_ON_XSTOP_SELECTION: enable trace stop on checkstop stop_on_xstop_selection
9	RW			STOP_ON_RECOV_ERR_SELECTION: enabel trace stop on recoverable error stop_on_recov_err_selection
10	RW			STOP_ON_SPATTN_SELECTION: enable trace stop on special attention stop_on_spattn_selection
11	RW			STOP_ON_HOSTATTN_SELECTION: enable trace stop on host attention stop_on_hostattn_selection
12	RW			FREEZE_SEL_MODE: select freeze source: 0: local debug freeze 1: via broadcast: tp_tcdbg_glb_brcst(1) master_clock_enable
13	RW			MASTER_CLOCK_ENABLE: master_clock_enable for debug macro
14:15	RO			constant=0b00
16	ROX			trace_run_on trace_run_status
17:18	ROX			TRACE_RUN_STATUS: 00 is stopped, 01 is run, 10 is run-n, 11 is wait-n stopped_00_running_01_runn_10_waitn_11_status
19	ROX			IS_FROZEN_STATUS: 1 is frozen (needs reset) is_frozen_status
20:22	ROX			INST1_CONDITION_HISTORY_STATUS: Shows which condition was triggered, 1xx is condition1, x1x is condition2 or 3, xx1 is condition2 timeout Shows last condition triggered before last trace_run activated (accumulate_history = 0) or accumulated conditions (accumulate_history = 1) inst1_condition_history_status
23:25	ROX			INST2_CONDITION_HISTORY_STATUS: Shows which condition was triggered, 1xx is condition1, x1x is condition2 or 3, xx1 is condition2 timeout Shows last condition triggered before last trace_run activated (accumulate_history = 0) or accumulated conditions (accumulate_history = 1) inst2_condition_history_status
26:31	ROX			unused unused
32:63	RO			constant=0b00000000000000000000000000000000

Debug macro configuration register 1 for front end 1 componet
Addr:	00000000010107C1 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.DBG.DBG_INST1_COND_REG_1
Constant(s):	PERV_1_DBG_INST1_COND_REG_1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#0.LAT.COND_REG_MODE.LATC.L2(0) [0]
	1	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#1.LAT.COND_REG_MODE.LATC.L2(0) [0]
	2	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#2.LAT.COND_REG_MODE.LATC.L2(0) [0]
	3	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#3.LAT.COND_REG_MODE.LATC.L2(0) [0]
	4	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#4.LAT.COND_REG_MODE.LATC.L2(0) [0]
	5	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#5.LAT.COND_REG_MODE.LATC.L2(0) [0]
	6	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#6.LAT.COND_REG_MODE.LATC.L2(0) [0]
	7	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#7.LAT.COND_REG_MODE.LATC.L2(0) [0]
	8	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#8.LAT.COND_REG_MODE.LATC.L2(0) [0]
	9	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#9.LAT.COND_REG_MODE.LATC.L2(0) [0]
	10	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#10.LAT.COND_REG_MODE.LATC.L2(0) [0]
	11	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#11.LAT.COND_REG_MODE.LATC.L2(0) [0]
	12	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#12.LAT.COND_REG_MODE.LATC.L2(0) [0]
	13	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#13.LAT.COND_REG_MODE.LATC.L2(0) [0]
	14	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#14.LAT.COND_REG_MODE.LATC.L2(0) [0]
	15	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#15.LAT.COND_REG_MODE.LATC.L2(0) [0]
	16	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#16.LAT.COND_REG_MODE.LATC.L2(0) [0]
	17	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#17.LAT.COND_REG_MODE.LATC.L2(0) [0]
	18	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#18.LAT.COND_REG_MODE.LATC.L2(0) [0]
	19	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#19.LAT.COND_REG_MODE.LATC.L2(0) [0]
	20	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#20.LAT.COND_REG_MODE.LATC.L2(0) [0]
	21	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#21.LAT.COND_REG_MODE.LATC.L2(0) [0]
	22	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#22.LAT.COND_REG_MODE.LATC.L2(0) [0]
	23	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#23.LAT.COND_REG_MODE.LATC.L2(0) [0]
	24	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#24.LAT.COND_REG_MODE.LATC.L2(0) [0]
	25	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#25.LAT.COND_REG_MODE.LATC.L2(0) [0]
	26	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#26.LAT.COND_REG_MODE.LATC.L2(0) [0]
	27	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#27.LAT.COND_REG_MODE.LATC.L2(0) [0]
	28	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#28.LAT.COND_REG_MODE.LATC.L2(0) [0]
	29	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#29.LAT.COND_REG_MODE.LATC.L2(0) [0]
	30	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#30.LAT.COND_REG_MODE.LATC.L2(0) [0]
	31	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#31.LAT.COND_REG_MODE.LATC.L2(0) [0]
	32	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#32.LAT.COND_REG_MODE.LATC.L2(0) [0]
	33	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#33.LAT.COND_REG_MODE.LATC.L2(0) [0]
	34	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#34.LAT.COND_REG_MODE.LATC.L2(0) [0]
	35	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#35.LAT.COND_REG_MODE.LATC.L2(0) [0]
	36	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#36.LAT.COND_REG_MODE.LATC.L2(0) [0]
	37	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#37.LAT.COND_REG_MODE.LATC.L2(0) [0]
	38	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#38.LAT.COND_REG_MODE.LATC.L2(0) [0]
	39	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#39.LAT.COND_REG_MODE.LATC.L2(0) [0]
	40	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#40.LAT.COND_REG_MODE.LATC.L2(0) [0]
	41	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#41.LAT.COND_REG_MODE.LATC.L2(0) [0]
	42	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#42.LAT.COND_REG_MODE.LATC.L2(0) [0]
	43	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#43.LAT.COND_REG_MODE.LATC.L2(0) [0]
	44	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#44.LAT.COND_REG_MODE.LATC.L2(0) [0]
	45	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#45.LAT.COND_REG_MODE.LATC.L2(0) [0]
	46	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#46.LAT.COND_REG_MODE.LATC.L2(0) [0]
	47	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#47.LAT.COND_REG_MODE.LATC.L2(0) [0]
	48	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#48.LAT.COND_REG_MODE.LATC.L2(0) [0]
	49	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#49.LAT.COND_REG_MODE.LATC.L2(0) [0]
	50	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#50.LAT.COND_REG_MODE.LATC.L2(0) [0]
	51	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#51.LAT.COND_REG_MODE.LATC.L2(0) [0]
	52	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#52.LAT.COND_REG_MODE.LATC.L2(0) [0]
	53	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#53.LAT.COND_REG_MODE.LATC.L2(0) [0]
	54	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#54.LAT.COND_REG_MODE.LATC.L2(0) [0]
	55	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#55.LAT.COND_REG_MODE.LATC.L2(0) [0]
	56	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#56.LAT.COND_REG_MODE.LATC.L2(0) [0]
	57	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#57.LAT.COND_REG_MODE.LATC.L2(0) [0]
	58	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#58.LAT.COND_REG_MODE.LATC.L2(0) [0]
	59	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#59.LAT.COND_REG_MODE.LATC.L2(0) [0]
	60	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#60.LAT.COND_REG_MODE.LATC.L2(0) [0]
	61	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#61.LAT.COND_REG_MODE.LATC.L2(0) [0]
	62	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#62.LAT.COND_REG_MODE.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0:7	RW			INST1_COND1_SEL_A: Multiplexer for cond1_trig_in(0) 000 select constant 0 001 select constant 1 -- CONDITION FEEDBACK -- 002 select inst1_dbg_cond1 003 select inst1_dbg_cond2 004 select inst1_dbg_cond3 005 select inst1_dbg_cond2timeout 006 select inst2_dbg_cond1 007 select inst2_dbg_cond2 008 select inst2_dbg_cond3 009 select inst2_dbg_cond2timeout 010 select inst3_dbg_cond1 – unused, tied down 011 select inst3_dbg_cond2 – unused, tied down 012 select inst3_dbg_cond3 – unused, tied down 013 select inst3_dbg_cond2timeout – unused, tied down 014 select inst4_dbg_cond1 – unused, tied down 015 select inst4_dbg_cond2 – unused, tied down 016 select inst4_dbg_cond3 – unused, tied down 017 select inst4_dbg_cond2timeout – unused, tied down 018 select inst1_dbg_trig_sp 019 select inst2_dbg_trig_sp 020 select inst3_dbg_trig_sp – unused, tied down 021 select inst4_dbg_trig_sp – unused, tied down 022 select tctrc_tcdbg_trigger_a(0) 023 select tctrc_tcdbg_trigger_b(0) 024 select tctrc_tcdbg_trigger_a(0) and tctrc_tcdbg_trigger_b(0) 025 select tctrc_tcdbg_trigger_a(1) 026 select tctrc_tcdbg_trigger_b(1) 027 select tctrc_tcdbg_trigger_a(1) and tctrc_tcdbg_trigger_b(1) 028 select tctrc_tcdbg_trigger_a(2) 029 select tctrc_tcdbg_trigger_b(2) 030 select tctrc_tcdbg_trigger_a(2) and tctrc_tcdbg_trigger_b(2) 031 select tctrc_tcdbg_trigger_a(3) 032 select tctrc_tcdbg_trigger_b(3) 033 select tctrc_tcdbg_trigger_a(3) and tctrc_tcdbg_trigger_b(3) 034 select tctrc_tcdbg_trigger_a(4) 035 select tctrc_tcdbg_trigger_b(4) 036 select tctrc_tcdbg_trigger_a(4) and tctrc_tcdbg_trigger_b(4) 037 select tctrc_tcdbg_trigger_a(5) 038 select tctrc_tcdbg_trigger_b(5) 039 select tctrc_tcdbg_trigger_a(5) and tctrc_tcdbg_trigger_b(5) 040 select tctrc_tcdbg_trigger_a(6) 041 select tctrc_tcdbg_trigger_b(6) 042 select tctrc_tcdbg_trigger_a(6) and tctrc_tcdbg_trigger_b(6) 043 select tctrc_tcdbg_trigger_a(7) 044 select tctrc_tcdbg_trigger_b(7) 045 select tctrc_tcdbg_trigger_a(7) and tctrc_tcdbg_trigger_b(7) 046 select tctrc_tcdbg_trigger_a(8) 047 select tctrc_tcdbg_trigger_b(8) 048 select tctrc_tcdbg_trigger_a(8) and tctrc_tcdbg_trigger_b(8) 049 select tctrc_tcdbg_trigger_a(9) 050 select tctrc_tcdbg_trigger_b(9) 051 select tctrc_tcdbg_trigger_a(9) and tctrc_tcdbg_trigger_b(9) 052 select tctrc_tcdbg_trigger_a(10) 053 select tctrc_tcdbg_trigger_b(10) 054 select tctrc_tcdbg_trigger_a(10) and tctrc_tcdbg_trigger_b(10) 055 select tctrc_tcdbg_trigger_a(11) 056 select tctrc_tcdbg_trigger_b(11) 057 select tctrc_tcdbg_trigger_a(11) and tctrc_tcdbg_trigger_b(11) 058 select tctrc_tcdbg_trigger_a(12) 059 select tctrc_tcdbg_trigger_b(12) 060 select tctrc_tcdbg_trigger_a(12) and tctrc_tcdbg_trigger_b(12) 061 select tctrc_tcdbg_trigger_a(13) 062 select tctrc_tcdbg_trigger_b(13) 063 select tctrc_tcdbg_trigger_a(13) and tctrc_tcdbg_trigger_b(13) 064 select tctrc_tcdbg_trigger_a(14) 065 select tctrc_tcdbg_trigger_b(14) 066 select tctrc_tcdbg_trigger_a(14) and tctrc_tcdbg_trigger_b(14) -- LOGIC (UNIT) TRIGGERS -- EP: 0:3 L3C0, 4:7 L3C1, 8:9 GX, 10 TP (hang), 11 spare, 12:13 MCA, 14:15 spare ES: 0:4 L4C, 5:6 L4F, 7:8 TPTOD, 9 TP (hang), 10:15 spare 067 select logic_trigger_in(0) 068 select logic_trigger_in(1) 069 select logic_trigger_in(2) 070 select logic_trigger_in(3) 071 select logic_trigger_in(4) 072 select logic_trigger_in(5) 073 select logic_trigger_in(6) 074 select logic_trigger_in(7) 075 select logic_trigger_in(8) 076 select logic_trigger_in(9) 077 select logic_trigger_in(10) 078 select logic_trigger_in(11) 079 select logic_trigger_in(12) 080 select logic_trigger_in(13) 081 select logic_trigger_in(14) 082 select logic_trigger_in(15) 083 select pc_tcdbg_trigger(0) 084 select pc_tcdbg_trigger(1) 085 select tctrc_tcdbg_glb_brcst(0) 086 select tctrc_tcdbg_glb_brcst(1) 087 select xstop_err 088 select recov_err 089 select spattn 090 select hostattn 091 select fir_dbg_local_xstop_err 092 select tc_dbg_inter_brcst(0) 093 select tc_dbg_inter_brcst(1) -- CORE TRIGGERS (EP chip only) -- Note: set core_slave_mode to honor ec[0:5]_tc_trace_run 094 select core trigger 0: any rising edge of ec[0:5]_tc_trace_run(0) 095 select core trigger 1: any rising edge of ec[0:5]_tc_trace_run(1) 096 select core trigger 2: any falling edge of ec[0:5]_tc_trace_run(0) 097 select core trigger 3: any falling edge of ec[0:5]_tc_trace_run(1) 098 select glb_trig_or_trace_in(0) 099 select glb_trig_or_trace_in(1) 100 select core_local_brcst_trc(0) 101 select core_local_brcst_trc(1) 102 select glb_freeze_brcst_rec(0) 103 select trig_2_extern_in(0) 104 select trig_2_extern_in(1) 105 select dbg_triggers_out(2) 106 select dbg_triggers_out(3) 107 select dbg_triggers_out(4) 108 select dbg_triggers_out(5) 109 select dbg_triggers_out(6) 100 select tcdbg_trigger_in(0) 111 select tcdbg_trigger_in(1)
8:15	RW			INST1_COND1_SEL_B: Multiplexer for cond1_trig_in(1) Selection as cond1_trig_in(0)
16:23	RW			INST1_COND2_SEL_A: Multiplexer for cond2_trig_in(0) Selection as cond1_trig_in(0)
24:31	RW			INST1_COND2_SEL_B: Multiplexer for cond2_trig_in(1) Selection as cond1_trig_in(0)
32	RW			INST1_C1_INAROW_MODE: front end instance 1 c1_inarow_mode
33	RW			INST1_AND_TRIGGER_MODE1: front end instance 1 and trigger mode condition1
34	RW			INST1_NOT_TRIGGER_MODE1: front end instance 1 inverted trigger mode condition1
35	RW			INST1_EDGE_TRIGGER_MODE1: front end instance 1 edge trigger mode condition1
36:38	RWX			INST1_UNUSED_1: UNUSED
39	RW			INST1_C2_INAROW_MODE: front end instance 1 Counter 2 in-a-rwo mode
40	RW			INST1_AND_TRIGGER_MODE2: front end instance 1 and trigger mode2
41	RW			INST1_NOT_TRIGGER_MODE2: front end instance 1 inverted (not) trigger
42	RW			INST1_EDGE_TRIGGER_MODE2: front end instance 1edge trigger
43:45	RWX			INST1_UNUSED_2: UNUSED
46	RW			INST1_COND3_ENABLE_RESET: front end instance 1 condition3 enable
47	RW			INST1_EXACT_TO_MODE: front end instance 1 exact timeout mode
48	RW			INST1_RESET_C2TIMER_ON_C1: front end instance 1 reset condition2 timer on condition1
49	RW			INST1_RESET_C3_ON_C0: front end instance 1 reset condition3 on condition0
50	RW			INST1_SLOW_TO_MODE: front end instance 1 slow timeout mode
51	RW			INST1_EXACT_RESET_C3_ON_TO: front end instance 1 exact reset condition3 on timeout
52:55	RW			INST1_C1_COUNT_LT: inst1 condition1 counter compare value
56:59	RW			INST1_C2_COUNT_LT: inst1 condition2 counter compare value
60:62	RW			INST1_RESET_C3_SELECT: front end instance 1: reset condition3 for reset_c3_on_c0 0b100: dbg_cross_couple_triggers(4) 0b101: dbg_cross_couple_triggers(12) 0b110: dbg_cross_couple_triggers(20) 0b111: dbg_cross_couple_triggers(28)

Debug macro configuration register 2 for fronte end 1 component
Addr:	00000000010107C2 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.DBG.DBG_INST1_COND_REG_2
Constant(s):	PERV_1_DBG_INST1_COND_REG_2
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#64.LAT.COND_REG_MODE.LATC.L2(0) [0]
	1	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#65.LAT.COND_REG_MODE.LATC.L2(0) [0]
	2	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#66.LAT.COND_REG_MODE.LATC.L2(0) [0]
	3	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#67.LAT.COND_REG_MODE.LATC.L2(0) [0]
	4	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#68.LAT.COND_REG_MODE.LATC.L2(0) [0]
	5	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#69.LAT.COND_REG_MODE.LATC.L2(0) [0]
	6	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#70.LAT.COND_REG_MODE.LATC.L2(0) [0]
	7	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#71.LAT.COND_REG_MODE.LATC.L2(0) [0]
	8	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#72.LAT.COND_REG_MODE.LATC.L2(0) [0]
	9	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#73.LAT.COND_REG_MODE.LATC.L2(0) [0]
	10	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#74.LAT.COND_REG_MODE.LATC.L2(0) [0]
	11	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#75.LAT.COND_REG_MODE.LATC.L2(0) [0]
	12	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#76.LAT.COND_REG_MODE.LATC.L2(0) [0]
	13	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#77.LAT.COND_REG_MODE.LATC.L2(0) [0]
	14	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#78.LAT.COND_REG_MODE.LATC.L2(0) [0]
	15	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#79.LAT.COND_REG_MODE.LATC.L2(0) [0]
	16	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#80.LAT.COND_REG_MODE.LATC.L2(0) [0]
	17	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#81.LAT.COND_REG_MODE.LATC.L2(0) [0]
	18	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#82.LAT.COND_REG_MODE.LATC.L2(0) [0]
	19	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#83.LAT.COND_REG_MODE.LATC.L2(0) [0]
	20	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#84.LAT.COND_REG_MODE.LATC.L2(0) [0]
	21	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#85.LAT.COND_REG_MODE.LATC.L2(0) [0]
	22	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#86.LAT.COND_REG_MODE.LATC.L2(0) [0]
	23	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#87.LAT.COND_REG_MODE.LATC.L2(0) [0]
	24	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#88.LAT.COND_REG_MODE.LATC.L2(0) [0]
	25	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#89.LAT.COND_REG_MODE.LATC.L2(0) [0]
	26	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#90.LAT.COND_REG_MODE.LATC.L2(0) [0]
	27	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#91.LAT.COND_REG_MODE.LATC.L2(0) [0]
	28	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#92.LAT.COND_REG_MODE.LATC.L2(0) [0]
	29	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#93.LAT.COND_REG_MODE.LATC.L2(0) [0]
	30	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#94.LAT.COND_REG_MODE.LATC.L2(0) [0]
	31	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#95.LAT.COND_REG_MODE.LATC.L2(0) [0]
	32	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#96.LAT.COND_REG_MODE.LATC.L2(0) [0]
	33	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#97.LAT.COND_REG_MODE.LATC.L2(0) [0]
	34	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#98.LAT.COND_REG_MODE.LATC.L2(0) [0]
	35	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#99.LAT.COND_REG_MODE.LATC.L2(0) [0]
	36	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#100.LAT.COND_REG_MODE.LATC.L2(0) [0]
	37	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#101.LAT.COND_REG_MODE.LATC.L2(0) [0]
	38	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#102.LAT.COND_REG_MODE.LATC.L2(0) [0]
	39	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#103.LAT.COND_REG_MODE.LATC.L2(0) [0]
	40	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#104.LAT.COND_REG_MODE.LATC.L2(0) [0]
	41	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#105.LAT.COND_REG_MODE.LATC.L2(0) [0]
	42	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#106.LAT.COND_REG_MODE.LATC.L2(0) [0]
	43	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#0.LAT_REQ#107.LAT.COND_REG_MODE.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0:4	RW			INST1_CROSS_COUPLE_SELECT_1_A: Cross coupling is the same of all selectors: 00000 - selects inst1_cond1_trig_a 00001 - selects inst1_cond1_trig_b 00010 - selects inst1_cond2_trig_a 00011 - selects inst1_cond2_trig_b 00100 - selects inst1_condition1 00101 - selects inst1_condition2 00110 - selects inst1_condition3 00111 - selects inst1_cond2_timeout 01000 - selects inst2_cond1_trig_a 01001 - selects inst2_cond1_trig_b 01010 - selects inst2_cond2_trig_a 01011 - selects inst2_cond2_trig_b 01100 - selects inst2_condition1 01101 - selects inst2_condition2 01110 - selects inst2_condition3 01111 - selects inst2_cond2_timeout 10000 - selects inst3_cond1_trig_a 10001 - selects inst3_cond1_trig_b 10010 - selects inst3_cond2_trig_a 10011 - selects inst3_cond2_trig_b 10100 - selects inst3_condition1 10101 - selects inst3_condition2 10110 - selects inst3_condition3 10111 - selects inst3_cond2_timeout 11000 - selects inst4_cond1_trig_a 11001 - selects inst4_cond1_trig_b 11010 - selects inst4_cond2_trig_a 11011 - selects inst4_cond2_trig_b 11100 - selects inst4_condition1 11101 - selects inst4_condition2 11110 - selects inst4_condition3 11111 - selects inst4_cond2_timeout
5:9	RW			INST1_CROSS_COUPLE_SELECT_1_B: inst1_cross_couple_select_1_b
10:14	RW			INST1_CROSS_COUPLE_SELECT_2_A: inst1_cross_couple_select_2_a
15:19	RW			INST1_CROSS_COUPLE_SELECT_2_B: inst1_cross_couple_select_2_b
20:43	RW			INST1_TO_CMP_LT: compare value for special counter sp_cnt_lt in debug component 1

Addr:	00000000010107C3 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.DBG.DBG_INST1_COND_REG_3
Constant(s):	PERV_1_DBG_INST1_COND_REG_3
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0:63	RO			constant=0b0000000000000000000000000000000000000000000000000000000000000000

Debug macro configuration register 1 for front end 1 componet
Addr:	00000000010107C4 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.DBG.DBG_INST2_COND_REG_1
Constant(s):	PERV_1_DBG_INST2_COND_REG_1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#0.LAT.COND_REG_MODE.LATC.L2(0) [0]
	1	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#1.LAT.COND_REG_MODE.LATC.L2(0) [0]
	2	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#2.LAT.COND_REG_MODE.LATC.L2(0) [0]
	3	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#3.LAT.COND_REG_MODE.LATC.L2(0) [0]
	4	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#4.LAT.COND_REG_MODE.LATC.L2(0) [0]
	5	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#5.LAT.COND_REG_MODE.LATC.L2(0) [0]
	6	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#6.LAT.COND_REG_MODE.LATC.L2(0) [0]
	7	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#7.LAT.COND_REG_MODE.LATC.L2(0) [0]
	8	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#8.LAT.COND_REG_MODE.LATC.L2(0) [0]
	9	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#9.LAT.COND_REG_MODE.LATC.L2(0) [0]
	10	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#10.LAT.COND_REG_MODE.LATC.L2(0) [0]
	11	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#11.LAT.COND_REG_MODE.LATC.L2(0) [0]
	12	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#12.LAT.COND_REG_MODE.LATC.L2(0) [0]
	13	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#13.LAT.COND_REG_MODE.LATC.L2(0) [0]
	14	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#14.LAT.COND_REG_MODE.LATC.L2(0) [0]
	15	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#15.LAT.COND_REG_MODE.LATC.L2(0) [0]
	16	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#16.LAT.COND_REG_MODE.LATC.L2(0) [0]
	17	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#17.LAT.COND_REG_MODE.LATC.L2(0) [0]
	18	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#18.LAT.COND_REG_MODE.LATC.L2(0) [0]
	19	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#19.LAT.COND_REG_MODE.LATC.L2(0) [0]
	20	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#20.LAT.COND_REG_MODE.LATC.L2(0) [0]
	21	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#21.LAT.COND_REG_MODE.LATC.L2(0) [0]
	22	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#22.LAT.COND_REG_MODE.LATC.L2(0) [0]
	23	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#23.LAT.COND_REG_MODE.LATC.L2(0) [0]
	24	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#24.LAT.COND_REG_MODE.LATC.L2(0) [0]
	25	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#25.LAT.COND_REG_MODE.LATC.L2(0) [0]
	26	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#26.LAT.COND_REG_MODE.LATC.L2(0) [0]
	27	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#27.LAT.COND_REG_MODE.LATC.L2(0) [0]
	28	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#28.LAT.COND_REG_MODE.LATC.L2(0) [0]
	29	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#29.LAT.COND_REG_MODE.LATC.L2(0) [0]
	30	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#30.LAT.COND_REG_MODE.LATC.L2(0) [0]
	31	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#31.LAT.COND_REG_MODE.LATC.L2(0) [0]
	32	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#32.LAT.COND_REG_MODE.LATC.L2(0) [0]
	33	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#33.LAT.COND_REG_MODE.LATC.L2(0) [0]
	34	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#34.LAT.COND_REG_MODE.LATC.L2(0) [0]
	35	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#35.LAT.COND_REG_MODE.LATC.L2(0) [0]
	36	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#36.LAT.COND_REG_MODE.LATC.L2(0) [0]
	37	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#37.LAT.COND_REG_MODE.LATC.L2(0) [0]
	38	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#38.LAT.COND_REG_MODE.LATC.L2(0) [0]
	39	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#39.LAT.COND_REG_MODE.LATC.L2(0) [0]
	40	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#40.LAT.COND_REG_MODE.LATC.L2(0) [0]
	41	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#41.LAT.COND_REG_MODE.LATC.L2(0) [0]
	42	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#42.LAT.COND_REG_MODE.LATC.L2(0) [0]
	43	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#43.LAT.COND_REG_MODE.LATC.L2(0) [0]
	44	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#44.LAT.COND_REG_MODE.LATC.L2(0) [0]
	45	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#45.LAT.COND_REG_MODE.LATC.L2(0) [0]
	46	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#46.LAT.COND_REG_MODE.LATC.L2(0) [0]
	47	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#47.LAT.COND_REG_MODE.LATC.L2(0) [0]
	48	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#48.LAT.COND_REG_MODE.LATC.L2(0) [0]
	49	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#49.LAT.COND_REG_MODE.LATC.L2(0) [0]
	50	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#50.LAT.COND_REG_MODE.LATC.L2(0) [0]
	51	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#51.LAT.COND_REG_MODE.LATC.L2(0) [0]
	52	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#52.LAT.COND_REG_MODE.LATC.L2(0) [0]
	53	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#53.LAT.COND_REG_MODE.LATC.L2(0) [0]
	54	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#54.LAT.COND_REG_MODE.LATC.L2(0) [0]
	55	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#55.LAT.COND_REG_MODE.LATC.L2(0) [0]
	56	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#56.LAT.COND_REG_MODE.LATC.L2(0) [0]
	57	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#57.LAT.COND_REG_MODE.LATC.L2(0) [0]
	58	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#58.LAT.COND_REG_MODE.LATC.L2(0) [0]
	59	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#59.LAT.COND_REG_MODE.LATC.L2(0) [0]
	60	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#60.LAT.COND_REG_MODE.LATC.L2(0) [0]
	61	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#61.LAT.COND_REG_MODE.LATC.L2(0) [0]
	62	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#62.LAT.COND_REG_MODE.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0:7	RW			INST2_COND1_SEL_A: Multiplexer for cond1_trig_in(0) 000 select constant 0 001 select constant 1 -- CONDITION FEEDBACK -- 002 select inst1_dbg_cond1 003 select inst1_dbg_cond2 004 select inst1_dbg_cond3 005 select inst1_dbg_cond2timeout 006 select inst2_dbg_cond1 007 select inst2_dbg_cond2 008 select inst2_dbg_cond3 009 select inst2_dbg_cond2timeout 010 select inst3_dbg_cond1 – unused, tied down 011 select inst3_dbg_cond2 – unused, tied down 012 select inst3_dbg_cond3 – unused, tied down 013 select inst3_dbg_cond2timeout – unused, tied down 014 select inst4_dbg_cond1 – unused, tied down 015 select inst4_dbg_cond2 – unused, tied down 016 select inst4_dbg_cond3 – unused, tied down 017 select inst4_dbg_cond2timeout – unused, tied down 018 select inst1_dbg_trig_sp 019 select inst2_dbg_trig_sp 020 select inst3_dbg_trig_sp – unused, tied down 021 select inst4_dbg_trig_sp – unused, tied down 022 select tctrc_tcdbg_trigger_a(0) 023 select tctrc_tcdbg_trigger_b(0) 024 select tctrc_tcdbg_trigger_a(0) and tctrc_tcdbg_trigger_b(0) 025 select tctrc_tcdbg_trigger_a(1) 026 select tctrc_tcdbg_trigger_b(1) 027 select tctrc_tcdbg_trigger_a(1) and tctrc_tcdbg_trigger_b(1) 028 select tctrc_tcdbg_trigger_a(2) 029 select tctrc_tcdbg_trigger_b(2) 030 select tctrc_tcdbg_trigger_a(2) and tctrc_tcdbg_trigger_b(2) 031 select tctrc_tcdbg_trigger_a(3) 032 select tctrc_tcdbg_trigger_b(3) 033 select tctrc_tcdbg_trigger_a(3) and tctrc_tcdbg_trigger_b(3) 034 select tctrc_tcdbg_trigger_a(4) 035 select tctrc_tcdbg_trigger_b(4) 036 select tctrc_tcdbg_trigger_a(4) and tctrc_tcdbg_trigger_b(4) 037 select tctrc_tcdbg_trigger_a(5) 038 select tctrc_tcdbg_trigger_b(5) 039 select tctrc_tcdbg_trigger_a(5) and tctrc_tcdbg_trigger_b(5) 040 select tctrc_tcdbg_trigger_a(6) 041 select tctrc_tcdbg_trigger_b(6) 042 select tctrc_tcdbg_trigger_a(6) and tctrc_tcdbg_trigger_b(6) 043 select tctrc_tcdbg_trigger_a(7) 044 select tctrc_tcdbg_trigger_b(7) 045 select tctrc_tcdbg_trigger_a(7) and tctrc_tcdbg_trigger_b(7) 046 select tctrc_tcdbg_trigger_a(8) 047 select tctrc_tcdbg_trigger_b(8) 048 select tctrc_tcdbg_trigger_a(8) and tctrc_tcdbg_trigger_b(8) 049 select tctrc_tcdbg_trigger_a(9) 050 select tctrc_tcdbg_trigger_b(9) 051 select tctrc_tcdbg_trigger_a(9) and tctrc_tcdbg_trigger_b(9) 052 select tctrc_tcdbg_trigger_a(10) 053 select tctrc_tcdbg_trigger_b(10) 054 select tctrc_tcdbg_trigger_a(10) and tctrc_tcdbg_trigger_b(10) 055 select tctrc_tcdbg_trigger_a(11) 056 select tctrc_tcdbg_trigger_b(11) 057 select tctrc_tcdbg_trigger_a(11) and tctrc_tcdbg_trigger_b(11) 058 select tctrc_tcdbg_trigger_a(12) 059 select tctrc_tcdbg_trigger_b(12) 060 select tctrc_tcdbg_trigger_a(12) and tctrc_tcdbg_trigger_b(12) 061 select tctrc_tcdbg_trigger_a(13) 062 select tctrc_tcdbg_trigger_b(13) 063 select tctrc_tcdbg_trigger_a(13) and tctrc_tcdbg_trigger_b(13) 064 select tctrc_tcdbg_trigger_a(14) 065 select tctrc_tcdbg_trigger_b(14) 066 select tctrc_tcdbg_trigger_a(14) and tctrc_tcdbg_trigger_b(14) -- LOGIC (UNIT) TRIGGERS -- EP: 0:3 L3C0, 4:7 L3C1, 8:9 GX, 10 TP (hang), 11 spare, 12:13 MCA, 14:15 spare ES: 0:4 L4C, 5:6 L4F, 7:8 TPTOD, 9 TP (hang), 10:15 spare 067 select logic_trigger_in(0) 068 select logic_trigger_in(1) 069 select logic_trigger_in(2) 070 select logic_trigger_in(3) 071 select logic_trigger_in(4) 072 select logic_trigger_in(5) 073 select logic_trigger_in(6) 074 select logic_trigger_in(7) 075 select logic_trigger_in(8) 076 select logic_trigger_in(9) 077 select logic_trigger_in(10) 078 select logic_trigger_in(11) 079 select logic_trigger_in(12) 080 select logic_trigger_in(13) 081 select logic_trigger_in(14) 082 select logic_trigger_in(15) 083 select pc_tcdbg_trigger(0) 084 select pc_tcdbg_trigger(1) 085 select tctrc_tcdbg_glb_brcst(0) 086 select tctrc_tcdbg_glb_brcst(1) 087 select xstop_err 088 select recov_err 089 select spattn 090 select hostattn 091 select fir_dbg_local_xstop_err 092 select tc_dbg_inter_brcst(0) 093 select tc_dbg_inter_brcst(1) -- CORE TRIGGERS (EP chip only) -- Note: set core_slave_mode to honor ec[0:5]_tc_trace_run 094 select core trigger 0: any rising edge of ec[0:5]_tc_trace_run(0) 095 select core trigger 1: any rising edge of ec[0:5]_tc_trace_run(1) 096 select core trigger 2: any falling edge of ec[0:5]_tc_trace_run(0) 097 select core trigger 3: any falling edge of ec[0:5]_tc_trace_run(1) 098 select glb_trig_or_trace_in(0) 099 select glb_trig_or_trace_in(1) 100 select core_local_brcst_trc(0) 101 select core_local_brcst_trc(1) 102 select glb_freeze_brcst_rec(0) 103 select trig_2_extern_in(0) 104 select trig_2_extern_in(1) 105 select dbg_triggers_out(2) 106 select dbg_triggers_out(3) 107 select dbg_triggers_out(4) 108 select dbg_triggers_out(5) 109 select dbg_triggers_out(6) 100 select tcdbg_trigger_in(0) 111 select tcdbg_trigger_in(1)
8:15	RW			INST2_COND1_SEL_B: Multiplexer for cond1_trig_in(1) Selection as cond1_trig_in(0)
16:23	RW			INST2_COND2_SEL_A: Multiplexer for cond2_trig_in(0) Selection as cond1_trig_in(0)
24:31	RW			INST2_COND2_SEL_B: Multiplexer for cond2_trig_in(1) Selection as cond1_trig_in(0)
32	RW			INST2_C1_INAROW_MODE: front end instance 1 c1_inarow_mode
33	RW			INST2_AND_TRIGGER_MODE1: front end instance 1 and trigger mode condition1
34	RW			INST2_NOT_TRIGGER_MODE1: front end instance 1 inverted trigger mode condition1
35	RW			INST2_EDGE_TRIGGER_MODE1: front end instance 1 edge trigger mode condition1
36:38	RWX			INST2_UNUSED_1: UNUSED
39	RW			INST2_C2_INAROW_MODE: front end instance 1 Counter 2 in-a-rwo mode
40	RW			INST2_AND_TRIGGER_MODE2: front end instance 1 and trigger mode2
41	RW			INST2_NOT_TRIGGER_MODE2: front end instance 1 inverted (not) trigger
42	RW			INST2_EDGE_TRIGGER_MODE2: front end instance 1edge trigger
43:45	RWX			INST2_UNUSED_2: UNUSED
46	RW			INST2_COND3_ENABLE_RESET: front end instance 1 condition3 enable
47	RW			INST2_EXACT_TO_MODE: front end instance 1 exact timeout mode
48	RW			INST2_RESET_C2TIMER_ON_C1: front end instance 1 reset condition2 timer on condition1
49	RW			INST2_RESET_C3_ON_C0: front end instance 1 reset condition3 on condition0
50	RW			INST2_SLOW_TO_MODE: front end instance 1 slow timeout mode
51	RW			INST2_EXACT_RESET_C3_ON_TO: front end instance 1 exact reset condition3 on timeout
52:55	RW			INST2_C1_COUNT_LT: inst2 condition1 counter compare value
56:59	RW			INST2_C2_COUNT_LT: inst2 condition2 counter compare value
60:62	RW			INST2_RESET_C3_SELECT: front end instance 1: reset condition3 for reset_c3_on_c0 0b100: dbg_cross_couple_triggers(4) 0b101: dbg_cross_couple_triggers(12) 0b110: dbg_cross_couple_triggers(20) 0b111: dbg_cross_couple_triggers(28)

Debug macro configuration register 2 for fronte end 1 component
Addr:	00000000010107C5 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.DBG.DBG_INST2_COND_REG_2
Constant(s):	PERV_1_DBG_INST2_COND_REG_2
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#64.LAT.COND_REG_MODE.LATC.L2(0) [0]
	1	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#65.LAT.COND_REG_MODE.LATC.L2(0) [0]
	2	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#66.LAT.COND_REG_MODE.LATC.L2(0) [0]
	3	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#67.LAT.COND_REG_MODE.LATC.L2(0) [0]
	4	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#68.LAT.COND_REG_MODE.LATC.L2(0) [0]
	5	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#69.LAT.COND_REG_MODE.LATC.L2(0) [0]
	6	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#70.LAT.COND_REG_MODE.LATC.L2(0) [0]
	7	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#71.LAT.COND_REG_MODE.LATC.L2(0) [0]
	8	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#72.LAT.COND_REG_MODE.LATC.L2(0) [0]
	9	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#73.LAT.COND_REG_MODE.LATC.L2(0) [0]
	10	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#74.LAT.COND_REG_MODE.LATC.L2(0) [0]
	11	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#75.LAT.COND_REG_MODE.LATC.L2(0) [0]
	12	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#76.LAT.COND_REG_MODE.LATC.L2(0) [0]
	13	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#77.LAT.COND_REG_MODE.LATC.L2(0) [0]
	14	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#78.LAT.COND_REG_MODE.LATC.L2(0) [0]
	15	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#79.LAT.COND_REG_MODE.LATC.L2(0) [0]
	16	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#80.LAT.COND_REG_MODE.LATC.L2(0) [0]
	17	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#81.LAT.COND_REG_MODE.LATC.L2(0) [0]
	18	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#82.LAT.COND_REG_MODE.LATC.L2(0) [0]
	19	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#83.LAT.COND_REG_MODE.LATC.L2(0) [0]
	20	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#84.LAT.COND_REG_MODE.LATC.L2(0) [0]
	21	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#85.LAT.COND_REG_MODE.LATC.L2(0) [0]
	22	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#86.LAT.COND_REG_MODE.LATC.L2(0) [0]
	23	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#87.LAT.COND_REG_MODE.LATC.L2(0) [0]
	24	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#88.LAT.COND_REG_MODE.LATC.L2(0) [0]
	25	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#89.LAT.COND_REG_MODE.LATC.L2(0) [0]
	26	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#90.LAT.COND_REG_MODE.LATC.L2(0) [0]
	27	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#91.LAT.COND_REG_MODE.LATC.L2(0) [0]
	28	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#92.LAT.COND_REG_MODE.LATC.L2(0) [0]
	29	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#93.LAT.COND_REG_MODE.LATC.L2(0) [0]
	30	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#94.LAT.COND_REG_MODE.LATC.L2(0) [0]
	31	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#95.LAT.COND_REG_MODE.LATC.L2(0) [0]
	32	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#96.LAT.COND_REG_MODE.LATC.L2(0) [0]
	33	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#97.LAT.COND_REG_MODE.LATC.L2(0) [0]
	34	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#98.LAT.COND_REG_MODE.LATC.L2(0) [0]
	35	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#99.LAT.COND_REG_MODE.LATC.L2(0) [0]
	36	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#100.LAT.COND_REG_MODE.LATC.L2(0) [0]
	37	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#101.LAT.COND_REG_MODE.LATC.L2(0) [0]
	38	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#102.LAT.COND_REG_MODE.LATC.L2(0) [0]
	39	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#103.LAT.COND_REG_MODE.LATC.L2(0) [0]
	40	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#104.LAT.COND_REG_MODE.LATC.L2(0) [0]
	41	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#105.LAT.COND_REG_MODE.LATC.L2(0) [0]
	42	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#106.LAT.COND_REG_MODE.LATC.L2(0) [0]
	43	TP.TPCHIP.TPC.EPS.DBG.CONFIG.NUM_OF_COND_COMP#1.LAT_REQ#107.LAT.COND_REG_MODE.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0:4	RW			INST2_CROSS_COUPLE_SELECT_1_A: Cross coupling is the same of all selectors: 00000 - selects inst1_cond1_trig_a 00001 - selects inst1_cond1_trig_b 00010 - selects inst1_cond2_trig_a 00011 - selects inst1_cond2_trig_b 00100 - selects inst1_condition1 00101 - selects inst1_condition2 00110 - selects inst1_condition3 00111 - selects inst1_cond2_timeout 01000 - selects inst2_cond1_trig_a 01001 - selects inst2_cond1_trig_b 01010 - selects inst2_cond2_trig_a 01011 - selects inst2_cond2_trig_b 01100 - selects inst2_condition1 01101 - selects inst2_condition2 01110 - selects inst2_condition3 01111 - selects inst2_cond2_timeout 10000 - selects inst3_cond1_trig_a 10001 - selects inst3_cond1_trig_b 10010 - selects inst3_cond2_trig_a 10011 - selects inst3_cond2_trig_b 10100 - selects inst3_condition1 10101 - selects inst3_condition2 10110 - selects inst3_condition3 10111 - selects inst3_cond2_timeout 11000 - selects inst4_cond1_trig_a 11001 - selects inst4_cond1_trig_b 11010 - selects inst4_cond2_trig_a 11011 - selects inst4_cond2_trig_b 11100 - selects inst4_condition1 11101 - selects inst4_condition2 11110 - selects inst4_condition3 11111 - selects inst4_cond2_timeout
5:9	RW			INST2_CROSS_COUPLE_SELECT_1_B: inst2_cross_couple_select_1_b
10:14	RW			INST2_CROSS_COUPLE_SELECT_2_A: inst2_cross_couple_select_2_a
15:19	RW			INST2_CROSS_COUPLE_SELECT_2_B: inst2_cross_couple_select_2_b
20:43	RW			INST2_TO_CMP_LT: compare value for special counter sp_cnt_lt in debug component 2

Addr:	00000000010107C6 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.DBG.DBG_INST2_COND_REG_3
Constant(s):	PERV_1_DBG_INST2_COND_REG_3
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
Bit(s)	SCOM			Dial: Description
0:63	RO			constant=0b0000000000000000000000000000000000000000000000000000000000000000

Debug Macro configuration register 10 for debug backend component
Addr:	00000000010107CD (SCOM)
Name:	TP.TPCHIP.TPC.EPS.DBG.DBG_TRACE_REG_0
Constant(s):	PERV_1_DBG_TRACE_REG_0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#0.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	1	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#1.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	2	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#2.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	3	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#3.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	4	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#4.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	5	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#5.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	6	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#6.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	7	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#7.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	8	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#8.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	9	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#9.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	10	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#10.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	11	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#11.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	12	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#12.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	13	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#13.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	14	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#14.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	15	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#15.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	16	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#16.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	17	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#17.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	18	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#18.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	19	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#19.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	32	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#32.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	33	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#33.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	34	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#34.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	35	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#35.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	36	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#36.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	37	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#37.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	38	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#38.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	39	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#39.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	40	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#40.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	41	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#41.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	42	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#42.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	43	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#43.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	44	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#44.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	45	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#45.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	46	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#46.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	47	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#47.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	48	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#48.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	49	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#49.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	50	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#50.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	51	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#51.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	52	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#52.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	53	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#53.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	54	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#54.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	55	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#55.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	56	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#56.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	57	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#57.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	RW			INST1_COND3_ENABLE: Enable of instance 1 condition 3
1	RW			INST2_COND3_ENABLE: Enable of instance 2 condition 3
2	RW			INST3_COND3_ENABLE: UNUSED
3	RW			INST4_COND3_ENABLE: UNUSED
4	RW			INST1_SLOW_LFSR_MODE: Enable slow lfsr mode of front end instance 1
5	RW			INST2_SLOW_LFSR_MODE: Enable slow lfsr mode of front end instance 2
6	RW			INST3_SLOW_LFSR_MODE: UNUSED
7	RW			INST4_SLOW_LFSR_MODE: UNUSED
8:9	RW			INST1_CONDITION1_TRIG_SEL: Select inst1 condition1 for output (external) triggers 00 = do nothing 01 = trigger_out(0) 10 = trigger_out(1) 11 = trigger_out(2)
10:11	RW			INST1_CONDITION2_TRIG_SEL: Select inst1 condition2 for output (external) triggers 00 = do nothing 01 = trigger_out(0) 10 = trigger_out(1) 11 = trigger_out(2)
12:13	RW			INST1_C2_TIMEOUT_TRIG_SEL: Select inst1 c2 time-out counter for output (external) triggers 00 = do nothing 01 = trigger_out(0) 10 = trigger_out(1) 11 = trigger_out(2)
14:15	RW			INST2_CONDITION1_TRIG_SEL: Select inst2 condition1 for output (external) triggers 00 = do nothing 01 = trigger_out(0) 10 = trigger_out(1) 11 = trigger_out(2)
16:17	RW			INST2_CONDITION2_TRIG_SEL: Select inst2 condition2 trigger for output (external) triggers 00 = do nothing 01 = trigger_out(0) 10 = trigger_out(1) 11 = trigger_out(2)
18:19	RW			INST2_C2_TIMEOUT_TRIG_SEL: Select inst2 c2 time-out counter for output (external) triggers 00 = do nothing 01 = trigger_out(0) 10 = trigger_out(1) 11 = trigger_out(2)
20:31	RO			constant=0b000000000000
32	RW			EXT_TRIG_ON_STOP: enable trigger on stop
33	RW			EXT_TRIG_ON_FREEZE: enable trigger on freeze
34:38	RW			CORE_RAS0_TRIG_SEL: Select which of the debug events of the debug front end component will be used for dbg_triggers_out(3) of the debug backend component 00001 = inst1_condition1_lt 00010 = inst1_cond2_3_event 00100 = inst1_cond2_timeout 01001 = inst2_condition1_lt 01010 = inst2_cond2_3_event 01100 = inst2_cond2_timeout 10001 = inst3_condition1_lt unused 10010 = inst3_cond2_3_event unused 10100 = inst3_cond2_timeout unused 11001 = inst4_condition1_lt unused 11010 = inst4_cond2_3_event unused 11100 = inst4_cond2_timeout unused
39:43	RW			CORE_RAS1_TRIG_SEL: Select which of the debug event of the debug front end component s will be multiplexed to dbg_triggers_out(4) of the debug backend component 00001 = inst1_condition1_lt 00010 = inst1_cond2_3_event 00100 = inst1_cond2_timeout 01001 = inst2_condition1_lt 01010 = inst2_cond2_3_event 01100 = inst2_cond2_timeout 10001 = inst3_condition1_lt unused 10010 = inst3_cond2_3_event unused 10100 = inst3_cond2_timeout unused 11001 = inst4_condition1_lt unused 11010 = inst4_cond2_3_event unused 11100 = inst4_cond2_timeout unused
44:45	RW			PC_TP_TRIG_SEL: select which of the debug events will be multiplexed to dbg_triggers_out(5 to 6) of the debug backend logic component 00 = triggers_out_lt(0) & triggers_out_lt(1) 01 = triggers_out_lt(0) & triggers_out_lt(2) 10 = triggers_out_lt(1) & triggers_out_lt(2) 11 = unused
46:49	RW			DBG_ARM_SEL: select which of the debug events will be multiplexed to dbg_wat_arm (unused) XXXX = unused
50:53	RW			TRIG0_LEVEL_SEL: Select additional conditions for output (external) trigger signal trigger_out(0) Note: some are N/A for zG+ (inst3/4 conditions are tied to zero) 0001 = inst1_cond3_state_int(1) 0010 = inst1_cond3_state_int(0) 0011 = inst2_cond3_state_int(1) 0100 = inst2_cond3_state_int(0) 0101 = inst3_cond3_state_int(1) 0110 = inst3_cond3_state_int(0) 0111 = inst4_cond3_state_int(1) 1000 = inst4_cond3_state_int(0) 1001 = inst1_cond3_state_int(1) or inst2_cond3_state_int(1) 1010 = inst1_cond3_state_int(1) and inst2_cond3_state_int(1) 1011 = inst3_cond3_state_int(1) or inst4_cond3_state_int(1) 1100 = inst3_cond3_state_int(1) and inst4_cond3_state_int(1) 1101 = inst1_cond3_state_int(1) or inst2_cond3_state_int(1) or inst3_cond3_state_int(1) 1110 = inst1_cond3_state_int(1) and inst2_cond3_state_int(1) and inst3_cond3_state_int(1) 1111 = inst1_cond3_state_int(1) or inst2_cond3_state_int(1) or inst3_cond3_state_int(1) or inst4_cond3_state_int(1)
54:57	RW			TRIG1_LEVEL_SEL: Select additional conditions for output (external) trigger signal trigger_out(1) Note: some are N/A for zG+ (inst3/4 conditions are tied to zero) 0001 = inst1_cond3_state_int(1) 0010 = inst1_cond3_state_int(0) 0011 = inst2_cond3_state_int(1) 0100 = inst2_cond3_state_int(0) 0101 = inst3_cond3_state_int(1) 0110 = inst3_cond3_state_int(0) 0111 = inst4_cond3_state_int(1) 1000 = inst4_cond3_state_int(0) 1001 = inst1_cond3_state_int(1) or inst2_cond3_state_int(1) 1010 = inst1_cond3_state_int(1) and inst2_cond3_state_int(1) 1011 = inst3_cond3_state_int(1) or inst4_cond3_state_int(1) 1100 = inst3_cond3_state_int(1) and inst4_cond3_state_int(1) 1101 = inst1_cond3_state_int(1) or inst2_cond3_state_int(1) or inst3_cond3_state_int(1) 1110 = inst1_cond3_state_int(1) and inst2_cond3_state_int(1) and inst3_cond3_state_int(1) 1111 = inst1_cond3_state_int(1) or inst2_cond3_state_int(1) or inst3_cond3_state_int(1) or inst4_cond3_state_int(1)
58:63	RO			constant=0b000000

Debug macro configuration register 11 for backend component
Addr:	00000000010107CE (SCOM)
Name:	TP.TPCHIP.TPC.EPS.DBG.DBG_TRACE_REG_1
Constant(s):	PERV_1_DBG_TRACE_REG_1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#64.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	1	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#65.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	2	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#66.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	3	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#67.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	4	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#68.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	5	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#69.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	6	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#70.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	7	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#71.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	8	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#72.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	9	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#73.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	10	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#74.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	11	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#75.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	24	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#88.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	25	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#89.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	26	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#90.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	27	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#91.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	28	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#92.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	29	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#93.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	36	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#100.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	37	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#101.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	38	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#102.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	39	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#103.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	40	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#104.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	41	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#105.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	48	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#112.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	49	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#113.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	50	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#114.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	51	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#115.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	52	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#116.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	53	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#117.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	54	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#118.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	55	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#119.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0:1	RW			INST1_CONDITION1_ACTION_DO: Inst1 action selection , condition1: 00 = nothing, 01 = start, 10 = stop, 11 = run-N: start now, stop after n cycles
2:3	RW			INST1_CONDITION2_ACTION_DO: Inst1 action selection , condition2: 00 = nothing, 01 = start, 10 = stop, 11 = run-N: start now, stop after n cycles
4:5	RW			INST1_C2_TIMEOUT_ACTION_DO: Inst1 action selection , c2_timeout: 00 = nothing, 01 = start, 10 = stop, 11 = run-N: start now, stop after n cycles
6:7	RW			INST2_CONDITION1_ACTION_DO: inst2 action selection , condition1: 00 = nothing, 01 = start, 10 = stop, 11 = run-N: start now, stop after n cycles
8:9	RW			INST2_CONDITION2_ACTION_DO: Inst2 action selection , condition2: 00 = nothing, 01 = start, 10 = stop, 11 = run-N: start now, stop after n cycles
10:11	RW			INST2_C2_TIMEOUT_ACTION_DO: Inst2 action selection , c2_timeout: 00 = nothing, 01 = start, 10 = stop, 11 = run-N: start now, stop after n cycles
12:23	RO			constant=0b000000000000
24	RW			INST1_CONDITION1_ACTION_WAITN: for wait-N
25	RW			INST1_CONDITION2_ACTION_WAITN: for wait-N
26	RW			INST1_C2_TIMEOUT_ACTION_WAITN: for wait-N
27	RW			INST2_CONDITION1_ACTION_WAITN: for wait-N
28	RW			INST2_CONDITION2_ACTION_WAITN: for wait-N
29	RW			INST2_C2_TIMEOUT_ACTION_WAITN: for wait-N
30:35	RO			constant=0b000000
36	RW			INST1_CONDITION1_ACTION_BANK: trace bank switch (inst1, condition1)
37	RW			INST1_CONDITION2_ACTION_BANK: trace bank switch (inst1, condition2)
38	RW			INST1_C2_TIMEOUT_ACTION_BANK: trace bank switch (inst1, c2_timeout)
39	RW			INST2_CONDITION1_ACTION_BANK: trace bank switch (inst2, condition1)
40	RW			INST2_CONDITION2_ACTION_BANK: trace bank switch (inst2, condition2)
41	RW			INST2_C2_TIMEOUT_ACTION_BANK: trace bank switch (inst2, c2_timeout)
42:47	RO			constant=0b000000
48:50	RW			INST1_CHECKSTOP_MODE_LT: Select additional condition with fir_error_lt for dbg_fir_xstop_on_trig output: 000 = inst1_condition1_lt 001 = inst1_condition2_lt 010 = inst1_condition3_lt 011 = inst1_cond2_timeout_lt 1XX = disable checkstop_mode
51	RW			INST1_CHECKSTOP_MODE_SELECTOR: enable_fir_trig_xstop: enable checkstop on debug trigger: 0 = disable checksop on debug trigger 1 = enable checksop on debug trigger
52:54	RW			INST2_CHECKSTOP_MODE_LT: Select additional condition with fir_error_lt for dbg_fir_xstop_on_trig output: 000 = inst2_condition1_lt 001 = inst2_condition2_lt 010 = inst2_condition3_lt 011 = inst2_cond2_timeout_lt 1XX = disable checkstop_mode
55	RW			INST2_CHECKSTOP_MODE_SELECTOR: enable_fir_error_xstop: enable checkstop on fir error: 0 = disable checkstop on fir error 1 = enable checkstop on fir error
56:63	RO			constant=0b00000000

Debug Macro configuration register 12 for backend component
Addr:	00000000010107CF (SCOM)
Name:	TP.TPCHIP.TPC.EPS.DBG.DBG_TRACE_MODE_REG_2
Constant(s):	PERV_1_DBG_TRACE_MODE_REG_2
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#128.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	1	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#129.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	2	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#130.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	3	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#131.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	4	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#132.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	5	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#133.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	6	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#134.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	7	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#135.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	8	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#136.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	9	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#137.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	10	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#138.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	11	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#139.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	12	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#140.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	13	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#141.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	14	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#142.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	15	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#143.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	16	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#144.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	17	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#145.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	18	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#146.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	19	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#147.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	20	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#148.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	21	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#149.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	22	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#150.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
	23	TP.TPCHIP.TPC.EPS.DBG.CONFIG.TRAC_LAT_REQ#151.LAT.TRAC_REG_MODE.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0:15	RW			RUNN_COUNT_COMPARE_VALUE: Compare value for the run-N counter used in trace modes run-N and wait-N
16	RW			IMM_FREEZE_MODE: immediate freeze mode
17	RW			STOP_ON_ERR: stop and freeze on xstop
18	RW			BANK_ON_RUNN_MATCH: bank switch on runn match
19	RW			FORCE_TEST_MODE: force run-N condition to be true
20	RW			ACCUM_HIST_MODE: accumulate history mode, do not clear history mode when trace_run active
21	RW			FRZ_COUNT_ON_FRZ: freeze condition counters on trace freeze
22:23	RW			EXTEND_BANK: extends bank signal so that it can be picked up by trace if slower trace macro (0x11 = 4:1, 0x10 = 3:1, 0x01 = 2:1, else 1x

Trace start/stop/rest using scom command, use write data(0/1/2) = 1
Addr:	00000000010107D0 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.DBG.DEBUG_TRACE_CONTROL
Constant(s):	PERV_1_DEBUG_TRACE_CONTROL
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPCHIP.TPC.EPS.DBG.CONFIG.DEBUG_TRACE_CONTROL(0:2) [000]
Bit(s)	SCOM			Dial: Description
0	WOX			scom_trace_start
1	WOX			scom_trace_stop
2	WOX			scom_trace_reset

xtra / dedicated trace mode register for core triggers
Addr:	00000000010107D1 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.DBG.XTRA_TRACE_MODE
Constant(s):	PERV_1_XTRA_TRACE_MODE
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:41	TP.TPCHIP.TPC.EPS.DBG.CONFIG.XTRA_TRACE_MODE_LT_INST.LATC.L2(0:41) [000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:41	RW			XTRA_TRACE_MODE_DATA: xtra / dedicated trace mode register for core triggers

OCC_SCOM OCC LFIR
Addr:	0000000001010800 (SCOM) 0000000001010801 (SCOM1) 0000000001010802 (SCOM2)
Name:	TP.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCLFIR
Constant(s):	PERV_1_OCC_SCOM_OCCLFIR
Comments:	OCC Local Fault Isolation Register
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:61	TP.TPCHIP.OCC.OCI.SCOM.LFIR.PAR_OFF.LEM_FIR.LOCALFIR.FIR.FIR.LATC.L2(0:61) [00000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIR_OCC_FW0: Input tied to 0. Used by OCC Firmware to produce an attention to the FSP.
1	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIR_OCC_FW1: Input tied to 0. Used by OCC Firmware to produce an attention tothe FSP.
2	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIR_QME_ERROR_NOTIFY: Input tied to 0. Used by STOP GPE code to indicated to HYP that a QME has indicated a fault.
3	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIR_STOP_RECOVERY_NOTIFY_PRD: Input tied to 0. Written by stop recovery firmware to indicate that the host side actions are complete and that FFDC information is available for analysis toward subsequent garding and/or deconfiguration. Intended to produce a recoverable attention (via Action register settings) to the PRD component for such analysis.
4	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_OCC_HB_ERROR: OCC Heartbeat Error
5	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_GPE0_WATCHDOG_TIMEOUT: GPE0 asserted a watchdog timeout condition
6	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_GPE1_WATCHDOG_TIMEOUT: GPE1 asserted a watchdog timeout condition
7	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_GPE2_WATCHDOG_TIMEOUT: GPE2 asserted a watchdog timeout condition
8	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_GPE3_WATCHDOG_TIMEOUT: GPE3 asserted a watchdog timeout condition
9	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_GPE0_ERROR: GPE0 asserted an error condition that caused it to halt. Implemented as an OR of the four error outputs from the PPE.
10	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_GPE1_ERROR: GPE1 asserted an error condition that caused it to halt. Implemented as an OR of the four error outputs from the PPE.
11	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_GPE2_ERROR: GPE2 asserted an error condition that caused it to halt. Implemented as an OR of the four error outputs from the PPE.
12	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_GPE3_ERROR: GPE3 asserted an error condition that caused it to halt. Implemented as an OR of the four error outputs from the PPE.
13	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_OCB_ERROR: OCB Error (recoverable error)
14	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_SRT_UE: SRAM Uncorrectable Error (recoverable error) Note: this being on will also have either a srt_read_error or srt_write_error on as well as these each have the UE error included. UE is broken out specifically to allow for array faster characterization.
15	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_SRT_CE: SRAM Correctable Error (masked (product); recoverable error (mfg)
16	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_GPE0_HALTED: GPE0 asserted a halt condition
17	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_GPE1_HALTED: GPE1 asserted a halt condition
18	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_GPE2_HALTED: GPE2 asserted a halt condition
19	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_GPE3_HALTED: GPE3 asserted a halt condition
20	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_GPE0_WRITE_PROTECT_ERROR: GPE0 attempted to write outside the region defined in GPESWPR
21	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_GPE1_WRITE_PROTECT_ERROR: GPE1 attempted to write outside the region defined in GPESWPR
22	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_GPE2_WRITE_PROTECT_ERROR: GPE2 attempted to write outside the region defined in GPESWPR
23	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_GPE3_WRITE_PROTECT_ERROR: GPE3 attempted to write outside the region defined in GPESWPR
24:25	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_SPARE_24_25: Implemented but not used, inputs tied to 0
26	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_EXTERNAL_TRAP: External Trigger pin active (recoverable (product)
27	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_PPC405_CORE_RESET: PPC405 Core Reset Output asserted (??? firmware)
28	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_PPC405_CHIP_RESET: PPC405 Chip Reset Output asserted (??? firmware)
29	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_PPC405_SYSTEM_RESET: PPC405 System Reset Output asserted (??? firmware)
30	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_PPC405_DBGMSRWE: PPC405 Wait State asserted (??? firmware)
31	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_PPC405_DBGSTOPACK: PPC405 Stop Ack output asserted (recoverable -> logging) Process stopped execution
32	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_OCB_DB_ERROR: OCB Direct Bridge Error - See OCCERRRPT2[8:11] for error source
33	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_OCB_PIB_ADDR_PARITY_ERR: OCB PIB Address Parity Error - (PIB read or write operation). Note: may be set for either direct bridge or indirect channel operations. This bit is set by hardware under normal operations but can be forced using the OR mask register. This bit can be cleared using the AND mask register.
34	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_OCB_IDC_ERROR: Indirect Channel Error See OCCERRRPT2[4:7] for the channel and then the OCB Control/Status Register for the reason
35	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_OPIT_PARITY_ERROR: Parity error detected on OPIT interrupt bus. Interrupts are hung.
36	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_OPIT_FSM_ERR: OPIT interrupt state machine error occurred.
37:41	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_SPARE_37_41: Implemented but not used. Input tied to 0
42	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_JTAGACC_ERR: JTAG accelerator error See OJSTAT register for reason
43	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_OCB_OCI_OCISLV_ERR: Any OCI Slave error occurreds
44	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_C405_ECC_UE: PPC405 cache UE
45	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_C405_ECC_CE: PPC405 cache CE
46	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_C405_OCI_MACHINECHECK: PPC405 Machine Check
47	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_SRAM_SPARE_DIRECT_ERROR: SRAM spare direct error Summary. See OCCERRRPT2[0:3] for details
48	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_SRT_OTHER_ERROR: SRAM Controller Error - A read, write, or parity error occurred in the SRAM tank controller. See OCCERRRPT2[12:18] for more information
49:50	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_SPARE_49_50: Implemented but notused. Input tied to 0
51	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_GPE0_OCISLV_ERR: OCI slave error for GPE0 (see OCCERRPT for details)
52	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_GPE1_OCISLV_ERR: OCI slave error for GPE1 (see OCCERRPT for details)
53	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_GPE2_OCISLV_ERR: OCI slave error for GPE2 (see OCCERRPT for details)
54	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_GPE3_OCISLV_ERR: OCI slave error for GPE3 (see OCCERRPT for details)
55	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_C405ICU_M_TIMEOUT: PPC405 ICU timeout on OCI request
56	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_C405DCU_M_TIMEOUT: PPC405 DCU timeout on OCI request
57	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_OCC_COMPLEX_FAULT: Used by OCC to indicate that a fault occurred (to achieve safe mode). Connected to OCCMISC[firmware_fault].
58	RWX	WOX_AND	WOX_OR	OCC_SCOM_OCCLFIR_OCC_COMPLEX_NOTIFY: Used by OCC to notify another firmware entity that an event occurred. Connected to OCCMISC[firmware_notify].
59:61	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIR_SPARE_59_61: Implemented but not used. Inputs tied to 0.
62:63	RO	RO	RO	constant=0b00

OCC_SCOM OCC LFIR MASK
Addr:	0000000001010803 (SCOM) 0000000001010804 (SCOM1) 0000000001010805 (SCOM2)
Name:	TP.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCLFIRMASK
Constant(s):	PERV_1_OCC_SCOM_OCCLFIRMASK
Comments:	OCC Local Fault Isolation Mask Register (Action0, Action1, Mask) = Action Select (0,0,0) = Checkstop Error (0,1,0) = Recoverable Error (1,0,0) = OCC Interrupt (1,1,0) = Malfunction Alert (x,x,1) = MASKED
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:61	TP.TPCHIP.OCC.OCI.SCOM.LFIR.PAR_OFF.LEM_FIR.LOCALFIR.FIR.FIR_MASK.LATC.L2(0:61) [00000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_OCC_FW0_MASK:
1	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_OCC_FW1_MASK:
2	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_QME_ERROR_MASK:
3	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_STOP_RECOVERY_NOTIFY_PRD_MASK:
4	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_OCC_HB_ERROR_MASK: OCC Heartbeat Error (malfunction alert)
5	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_GPE0_WATCHDOG_TIMEOUT_MASK: GPE0 asserted a watchdog timeout condition
6	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_GPE1_WATCHDOG_TIMEOUT_MASK: GPE1 asserted a watchdog timeout condition
7	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_GPE2_WATCHDOG_TIMEOUT_MASK: GPE2 asserted a watchdog timeout condition
8	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_GPE3_WATCHDOG_TIMEOUT_MASK: GPE3 asserted a watchdog timeout condition
9	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_GPE0_ERROR_MASK: GPE0 asserted a error condition
10	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_GPE1_ERROR_MASK: GPE1 asserted a error condition
11	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_GPE2_ERROR_MASK: GPE2 asserted a error condition
12	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_GPE3_ERROR_MASK: GPE3 asserted a error condition
13	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_OCB_ERROR_MASK: OCB Error (recoverable error)
14	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_SRT_UE_MASK: SRAM Uncorrectable Error (recoverable error)
15	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_SRT_CE_MASK: SRAM Correctable Error (masked (product); recoverable error (mfg)
16	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_GPE0_HALTED_MASK: GPE0 asserted a halt condition
17	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_GPE1_HALTED_MASK: GPE1 asserted a halt condition
18	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_GPE2_HALTED_MASK: GPE2 asserted a halt condition
19	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_GPE3_HALTED_MASK: GPE3 asserted a halt condition
20	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_GPE0_WRITE_PROTECT_ERROR_MASK: GPE0 asserted a write protect error condition
21	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_GPE1_WRITE_PROTECT_ERROR_MASK: GPE1 asserted a write protect error condition
22	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_GPE2_WRITE_PROTECT_ERROR_MASK: GPE2 asserted a write protect error condition
23	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_GPE3_WRITE_PROTECT_ERROR_MASK: GPE3 asserted a write protect error condition
24:25	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_SPARE_24_25_MASK:
26	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_EXTERNAL_TRAP_MASK: External Trigger pin active (recoverable (product)
27	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_PPC405_CORE_RESET_MASK: PPC405 Core Reset Output asserted (??? firmware)
28	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_PPC405_CHIP_RESET_MASK: PPC405 Chip Reset Output asserted (??? firmware)
29	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_PPC405_SYSTEM_RESET_MASK: PPC405 System Reset Output asserted (??? firmware)
30	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_PPC405_DBGMSRWE_MASK: PPC405 Wait State asserted (??? firmware)
31	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_PPC405_DBGSTOPACK_MASK: PPC405 Stop Ack output asserted (recoverable -> logging) Process stopped execution
32	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_OCB_DB_ERROR_MASK: OCB Direct Bridge Error Mask
33	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_OCB_PIB_ADDR_PARITY_ERR_MASK: OCB PIB address parity error
34	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_OCB_IDC_ERROR_MASK: Indirect Channel Error
35	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_OPIT_PARITY_ERROR_MASK: OPIT Parity error mask
36	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_OPIT_FSM_ERR: OPIT interrupt state machine error mask
37:41	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_SPARE_37_41_MASK:
42	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_JTAGACC_ERR_MASK: JTAG accelerator error
43	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_SPARE_ERR_38_MASK:
44	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_C405_ECC_UE_MASK: PPC405 cache Uncorrectable Error (UE)
45	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_C405_ECC_CE_MASK: PPC405 cache Correctable Error (CE)
46	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_C405_OCI_MACHINECHECK_MASK: PPC405 Machine Check
47	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_SRAM_SPARE_DIRECT_ERROR_MASK: SRAM spare direct error
48	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_SRT_OTHER_ERROR_MASK: SRAM Tank other error
49:50	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_SPARE_49_50_MASK:
51	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_GPE0_OCISLV_ERR_MASK: OCI slave error for GPE0 (see OCCERRPT for details)
52	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_GPE1_OCISLV_ERR_MASK: OCI slave error for GPE0 (see OCCERRPT for details)
53	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_GPE2_OCISLV_ERR_MASK: OCI slave error for GPE0 (see OCCERRPT for details)
54	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_GPE3_OCISLV_ERR_MASK: OCI slave error for GPE0 (see OCCERRPT for details)
55	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_C405ICU_M_TIMEOUT_MASK: PPC405 ICU timeout on OCI request
56	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_C405DCU_M_TIMEOUT_MASK: PPC405 DCU timeout on OCI request
57	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_OCC_COMPLEX_FAULT_MASK: Used by OCC to indicate that a fault occurred (to achieve save mode).
58	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_OCC_COMPLEX_NOTIFY_MASK: Used by OCC to notify another firmware entity that an event occurred.
59:61	RW	WO_AND	WO_OR	OCC_SCOM_OCCLFIRMASK_SPARE_59_61_MASK:
62:63	RO	RO	RO	constant=0b00

OCC_SCOM OCC LFIR Action0
Addr:	0000000001010806 (SCOM)
Name:	TP.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCLFIRACT0
Constant(s):	PERV_1_OCC_SCOM_OCCLFIRACT0
Comments:	OCC Local Fault Isolation Action0 Register (Action0, Action1, Mask) = Action Select (0,0,0) = Checkstop Error (0,1,0) = Recoverable Error (1,0,0) = OCC Interrupt (1,1,0) = Malfunction Alert (x,x,1) = MASKED
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:61	TP.TPCHIP.OCC.OCI.SCOM.LFIR.PAR_OFF.LEM_FIR.LOCALFIR.FIR.DO_ACTION0.FIR_ACTION0.LATC.L2(0:61) [00000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:61	RW			OCC_SCOM_OCCLFIRACT0_FIR_ACTION0: MSB of action select for corresponding bit in FIR
62:63	RO			constant=0b00

OCC_SCOM OCC LFIR Action1
Addr:	0000000001010807 (SCOM)
Name:	TP.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCLFIRACT1
Constant(s):	PERV_1_OCC_SCOM_OCCLFIRACT1
Comments:	OCC Local Fault Isolation Action1 Register (Action0, Action1, Mask) = Action Select (0,0,0) = Checkstop Error (0,1,0) = Recoverable Error (1,0,0) = OCC Interrupt (1,1,0) = Malfunction Alert (x,x,1) = MASKED
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:61	TP.TPCHIP.OCC.OCI.SCOM.LFIR.PAR_OFF.LEM_FIR.LOCALFIR.FIR.DO_ACTION1.FIR_ACTION1.LATC.L2(0:61) [00000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:61	RW			OCC_SCOM_OCCLFIRACT1_FIR_ACTION1: LSB of action select for corresponding bit in FIR
62:63	RO			constant=0b00

OCC_SCOM OCC Error Report Register
Addr:	000000000101080A (SCOM)
Name:	TP.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCERRRPT
Constant(s):	PERV_1_OCC_SCOM_OCCERRRPT
Comments:	OCC Error Report Register (read/clear c_err_rpt). A write to any bit in this register will clear the entire register.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:9	TP.TPCHIP.OCC.OCI.SCOM.SRT_CERR.HOLD_LATCH_INST.HOLD.LATC.L2(0:9) [0000000000]
	10:15	TP.TPCHIP.OCC.OCI.SCOM.JTAG_CERR.HOLD_LATCH_INST.HOLD.LATC.L2(0:5) [000000]
	16:19	TP.TPCHIP.OCC.OCI.SCOM.PPC405_CERR.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000]
	20:26	TP.TPCHIP.OCC.OCI.SCOM.GPE0SPORE_CERR.HOLD_LATCH_INST.HOLD.LATC.L2(0:6) [0000000]
	28:34	TP.TPCHIP.OCC.OCI.SCOM.GPE1SPORE_CERR.HOLD_LATCH_INST.HOLD.LATC.L2(0:6) [0000000]
	36:42	TP.TPCHIP.OCC.OCI.SCOM.GPE2SPORE_CERR.HOLD_LATCH_INST.HOLD.LATC.L2(0:6) [0000000]
	44:50	TP.TPCHIP.OCC.OCI.SCOM.GPE3SPORE_CERR.HOLD_LATCH_INST.HOLD.LATC.L2(0:6) [0000000]
	52:57	TP.TPCHIP.OCC.OCI.SCOM.OCB_CERR.HOLD_LATCH_INST.HOLD.LATC.L2(0:5) [000000]
Bit(s)	SCOM			Dial: Description
0:9	RWX_WCLRPART			OCC_SCOM_OCCERRRPT_SRAM_CERRRPT: sram_oci_error_bus(0:9) 0 - fsm error write machine0 1 - fsm error write machine1 2 - fsm error read machine0 3 - fsm error read machine1 4 - write buffer underflow 5 - write buffer overflow 6:9 - spares
10:15	RWX_WCLRPART			OCC_SCOM_OCCERRRPT_JTAGACC_CERRPT: JTAG accelerator errors See OJSTAT register for description
16	RWX_WCLRPART			OCC_SCOM_OCCERRRPT_C405_DCU_ECC_UE: PPC405 data cache ue detected
17	RWX_WCLRPART			OCC_SCOM_OCCERRRPT_C405_DCU_ECC_CE: PPC405 data cache ce detected
18	RWX_WCLRPART			OCC_SCOM_OCCERRRPT_C405_ICU_ECC_UE: PPC405 instruction cache ue detected
19	RWX_WCLRPART			OCC_SCOM_OCCERRRPT_C405_ICU_ECC_CE: PPC405 instruction cache ce detected
20:26	RWX_WCLRPART			OCC_SCOM_OCCERRRPT_GPE0_OCISLV_ERR: OCI slave error in GPE 0 0 - address parity error 1 - byte enable parity error 2 - write data parity error 3 - byte enable error (non-word aligned) 4 - transfer size error (non-xero transfer size) 5 - invalid address 6 - read error (register is not readable)
27	RO			constant=0b0
28:34	RWX_WCLRPART			OCC_SCOM_OCCERRRPT_GPE1_OCISLV_ERR: OCI slave error in GPE 1 0 - address parity error 1 - byte enable parity error 2 - write data parity error 3 - byte enable error (non-word aligned) 4 - transfer size error (non-xero transfer size) 5 - invalid address 6 - read error (register is not readable)
35	RO			constant=0b0
36:42	RWX_WCLRPART			OCC_SCOM_OCCERRRPT_GPE2_OCISLV_ERR: OCI slave error in GPE 2 0 - address parity error 1 - byte enable parity error 2 - write data parity error 3 - byte enable error (non-word aligned) 4 - transfer size error (non-xero transfer size) 5 - invalid address 6 - read error (register is not readable)
43	RO			constant=0b0
44:50	RWX_WCLRPART			OCC_SCOM_OCCERRRPT_GPE3_OCISLV_ERR: OCI slave error in GPE 3 0 - address parity error 1 - byte enable parity error 2 - write data parity error 3 - byte enable error (non-word aligned) 4 - transfer size error (non-xero transfer size) 5 - invalid address 6 - read error (register is not readable)
51	RO			constant=0b0
52:57	RWX_WCLRPART			OCC_SCOM_OCCERRRPT_OCB_OCISLV_ERR: OCI slave error in OCB 0 - address parity error 1 - byte enable parity error 2 - write data parity error 3 - byte enable error (non-word aligned) 4 - transfer size error (non-xero transfer size) 5 - invalid address
58:63	RO			constant=0b000000

OCC_SCOM OCC Error Report Register 2
Addr:	000000000101080B (SCOM)
Name:	TP.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCERRRPT2
Constant(s):
Comments:	OCC Error Report Register 2 (read/clear c_err_rpt). A write to any bit in this register will clear the entire register.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.OCC.OCI.SCOM.OCCERRRPT2A.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000]
	4:7	TP.TPCHIP.OCC.OCI.SCOM.OCCERRRPT2B.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000]
	8:11	TP.TPCHIP.OCC.OCI.SCOM.OCCERRRPT2C.HOLD_LATCH_INST.HOLD.LATC.L2(0:3) [0000]
	12:18	TP.TPCHIP.OCC.OCI.SCOM.OCCERRRPT2D.HOLD_LATCH_INST.HOLD.LATC.L2(0:6) [0000000]
Bit(s)	SCOM			Dial: Description
0	RWX_WCLRPART			OCC_SCOM_OCCERRRPT2_SRAM_SPARE_DIRECT_ERROR0: SRAM spare direct error
1	RWX_WCLRPART			OCC_SCOM_OCCERRRPT2_SRAM_SPARE_DIRECT_ERROR1: SRAM spare direct error
2	RWX_WCLRPART			OCC_SCOM_OCCERRRPT2_SRAM_SPARE_DIRECT_ERROR2: SRAM spare direct error
3	RWX_WCLRPART			OCC_SCOM_OCCERRRPT2_SRAM_SPARE_DIRECT_ERROR3: SRAM spare direct error
4	RWX_WCLRPART			OCC_SCOM_OCCERRRPT2_OCB_IDC0_ERROR: Indirect Channel 0 Error See OCB Control/Status 0 Register for the reason
5	RWX_WCLRPART			OCC_SCOM_OCCERRRPT2_OCB_IDC1_ERROR: Indirect Channel 1 Error See OCB Control/Status 1 Register for the reason
6	RWX_WCLRPART			OCC_SCOM_OCCERRRPT2_OCB_IDC2_ERROR: Indirect Channel 2 Error See OCB Control/Status 2 Register for the reason
7	RWX_WCLRPART			OCC_SCOM_OCCERRRPT2_OCB_IDC3_ERROR: Indirect Channel 3 Error See OCB Control/Status 3 Register for the reason
8	RWX_WCLRPART			OCC_SCOM_OCCERRRPT2_OCB_DB_OCI_TIMEOUT: OCB Direct Bridge OCI Timeout. Asserted to flag that no OCI slave acknowledged the direct bridge request. This bit is set by hardware under normal operations but can be forced using the OR mask register. This bit can be cleared using the AND mask register.
9	RWX_WCLRPART			OCC_SCOM_OCCERRRPT2_OCB_DB_OCI_READ_DATA_PARITY: OCB Direct Bridge OCI Read Data Parity Error This bit is set by hardware under normal operations but can be forced using the OR mask register. This bit can be cleared using the AND mask register.
10	RWX_WCLRPART			OCC_SCOM_OCCERRRPT2_OCB_DB_OCI_SLAVE_ERROR: OCB Direct Bridge OCI SlvError received. This bit is set by hardware under normal operations but can be forced using the OR mask register. This bit can be cleared using the AND mask register.
11	RWX_WCLRPART			OCC_SCOM_OCCERRRPT2_OCB_DB_PIB_DATA_PARITY_ERR: OCB Direct Bridge PIB Data Error - Indicates the PIB data parity was in error for a PIB write operation to a direct bridge address. Note: write data parity errors to an indirect bridge address are captured in the the OCB Control Status [n] Register for the addressed channel. This bit is set by hardware under normal operations but can be forced using the OR mask register. This bit can be cleared using the AND mask register.
12	RWX_WCLRPART			OCC_SCOM_OCCERRRPT2_SRT_READ_ERROR: SRAM Read Error - asserts if a "read" operation and any of the following: SRAM Tank Address Parity error; SRAM Uncorrectable error
13	RWX_WCLRPART			OCC_SCOM_OCCERRRPT2_SRT_WRITE_ERROR: SRAM Write Error - asserts if a "write" operation and any of the following: SRAM Tank Address Parity error; if <8B write (requiring a read, modify, write operation), then (SRAM Tank Byte Enable Parity error; SRAM Write Data Parity error; SRAM Uncorrectable error). Note: a write data parity error on OCI will be passed to the Tank, and will be detected by this bit.
14	RWX_WCLRPART			OCC_SCOM_OCCERRRPT2_SRT_DATAOUT_PERR: SRAM controller detected parity error on tank read data
15	RWX_WCLRPART			OCC_SCOM_OCCERRRPT2_SRT_OCI_WRITE_DATA_PARITY: SRAM controller detected OCI write data parity error
16	RWX_WCLRPART			OCC_SCOM_OCCERRRPT2_SRT_OCI_BE_PARITY_ERR: SRAM controller detected an OCI byte enable parity error
17	RWX_WCLRPART			OCC_SCOM_OCCERRRPT2_SRT_OCI_ADDR_PARITY_ERR: SRAM controller detected an OCI address parity error
18	RWX_WCLRPART			OCC_SCOM_OCCERRRPT2_SRT_FSM_ERR: Indicates an fsm error in the read or write machines of the SRAM controller
19:63	RO			constant=0b000000000000000000000000000000000000000000000

PBA Local Fault Isolation Register
Addr:	0000000001010CC0 (SCOM) 0000000001010CC1 (SCOM1) 0000000001010CC2 (SCOM2)
Name:	TP.TPBR.PBA.PBAO.PBAFIR
Constant(s):
Comments:	PBA Local Fault Isolation Register. Register bits are set for any error condition detected by the PBA. The PBAFIR will freeze upon logging the first error not masked in PBAFIRMASK.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:19	TP.TPBR.PBA.PBAO.SCOM.LSCOMFIR.PAR_OFF.LEM_FIR.LOCALFIR.FIR.FIR.LATC.L2(0:19) [00000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0	RWX	WOX_AND	WOX_OR	PBAFIR_OCI_APAR_ERR: OCI Address Parity Error Det Address parity error detected by PBA OCI Slave logic for any valid address. OCI Operation is ignored.
1	RWX	WOX_AND	WOX_OR	PBAFIR_OCI_SLAVE_INIT: PBA OCI Slave Initialization Error This is asserted when the upper two OCI address bits indicate they target the PBA Slave but the PBA slave is not setup properly. : No buffer allocated in targetted PBASLVCTLn PBASLVCTLn not enabled for master_id Multiple PBASLVCTLn are enabled for a master_id
2	RWX	WOX_AND	WOX_OR	PBAFIR_OCI_WRPAR_ERR: OCI Write Data Parity Error Detected Data parity error detected by PBA OCI Slave logic. This write and any previous gathered writes are not forwarded.
3	RWX	WOX_AND	WOX_OR	PBAFIR_RESERVED_3: Spare -was OCI Re-Request Timeout
4	RWX	WOX_AND	WOX_OR	PBAFIR_BCUE_SETUP_ERR: BCUE Setup Error Block Copy Unload Engine Setup Errors. See PBAERRRPT1. Unexpected Start received while running Timeout Response for OCI Request
5	RWX	WOX_AND	WOX_OR	PBAFIR_BCUE_OCI_DATERR: BCUE Read Data Parity Error OR MRDERR Asserted Block Copy Unload Engine detected parity error on read data from the OCI.
6	RWX	WOX_AND	WOX_OR	PBAFIR_BCDE_SETUP_ERR: BCDE Setup Error Block Copy Download Engine Setup Errors. See PBAERRRPT1 Unexpected Start received while running Timeout Response for OCI Request (OCI Address error)
7	RWX	WOX_AND	WOX_OR	PBAFIR_BCDE_OCI_DATERR: BCDE Write Data error indicated by OCI Slave Block Copy Download Engine received WRDERR indication from OCI Slave.
8	RWX	WOX_AND	WOX_OR	PBAFIR_INTERNAL_ERR: Internal Logic Error. See PBAERRRPT2 for more detailed information.
9	RWX	WOX_AND	WOX_OR	PBAFIR_OCI_BAD_REG_ADDR: Illegal access to OCI Register. Invalid address, read to write-only, write to read-only.
10	RWX	WOX_AND	WOX_OR	PBAFIR_AXPUSH_WRERR: Push Write Error. Push queue did not get OCI ADDRACK for push write request. Either the address is invalid or the targeted detected and address parity error. See PBAERRRPT2 for per queue information.
11	RWX	WOX_AND	WOX_OR	PBAFIR_AXIPUSH_WRERR: Push Write Error. Push queue did not get OCI ADDRACK for push write request. Either the address is invalid or the targeted detected and address parity error. See PBAERRRPT2 for per queue information.
12	RWX	WOX_AND	WOX_OR	PBAFIR_AXFLOW_ERR: Illegal PBAX Flow. See PBAERRRPT2 for more info. Write to PBAXSNDTX when PBAXSNDSTAT[snd_in_progress]=1 OR PBAXCFG[pbax_en] = 0 Underflow Error
13	RWX	WOX_AND	WOX_OR	PBAFIR_AXIFLOW_ERR: Illegal PBAX Flow. See PBAERRRPT2 for more info. Write to PBAXISNDTX when PBAXISNDSTAT[snd_in_progress]=1 OR PBAXICFG[pbax_en] = 0 Underflow Error
14	RWX	WOX_AND	WOX_OR	PBAFIR_AXSND_RSVERR: PBAXSND Reservation Error. Reservation request and Reservations not enabled, push queue not enabled, or push queue is full.
15	RWX	WOX_AND	WOX_OR	PBAFIR_AXISND_RSVERR: PBAXISND Reservation Error. Reservation request and Reservations not enabled, push queue not enabled, or push queue is full.
16	RWX	WOX_AND	WOX_OR	PBAFIR_HTM_WRITE_OVERFLOW: The htm fifo interface was not able to keep up with the frequency variation between PBAO and PBAF and has overflowed and lost htm trace records.
17	RWX	WOX_AND	WOX_OR	PBAFIR_INVALID_TOPOLOGY_ID: The PBA has been configured to use the PowerBus Topology Translate tables, and the request did not hit a valid entry. NOTE: Per HW540198 the request will still be sent to the powerbus and may generate secondary errors. Not having the topology id table programmed is a fatal error.
18	RWX	WOX_AND	WOX_OR	PBAFIR_RESERVED_18: Spare
19	RWX	WOX_AND	WOX_OR	PBAFIR_RESERVED_19: Spare
20:63	RO	RO	RO	constant=0b00000000000000000000000000000000000000000000

PBA Local Fault Isolation Mask Register
Addr:	0000000001010CC3 (SCOM) 0000000001010CC4 (SCOM1) 0000000001010CC5 (SCOM2)
Name:	TP.TPBR.PBA.PBAO.PBAFIRMASK
Constant(s):
Comments:	PBA Local Fault Isolation Mask Register. Reset value of PBAFIRMSK set according to RAS FIR Review for DD1.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:19	TP.TPBR.PBA.PBAO.SCOM.LSCOMFIR.PAR_OFF.LEM_FIR.LOCALFIR.FIR.FIR_MASK.LATC.L2(0:19) [00000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0	RW	WO_AND	WO_OR	PBAFIRMASK_OCI_APAR_ERR_MASK: oci_apar_err_mask
1	RW	WO_AND	WO_OR	PBAFIRMASK_OCI_SLAVE_INIT_MASK: oci_slave_init_mask
2	RW	WO_AND	WO_OR	PBAFIRMASK_OCI_WRPAR_ERR_MASK: oci_wrpar_err_mask
3	RW	WO_AND	WO_OR	PBAFIRMASK_RESERVED_3: Reserved
4	RW	WO_AND	WO_OR	PBAFIRMASK_BCUE_SETUP_ERR_MASK: bcue_setup_err_mask
5	RW	WO_AND	WO_OR	PBAFIRMASK_BCUE_OCI_DATERR_MASK: bcue_oci_daterr_mask
6	RW	WO_AND	WO_OR	PBAFIRMASK_BCDE_SETUP_ERR_MASK: bcde_setup_err_mask
7	RW	WO_AND	WO_OR	PBAFIRMASK_BCDE_OCI_DATERR_MASK: bcde_oci_daterr_mask
8	RW	WO_AND	WO_OR	PBAFIRMASK_INTERNALS_ERR_MASK: internal_err_mask
9	RW	WO_AND	WO_OR	PBAFIRMASK_OCI_BAD_REG_ADDR_MASK: oci_bad_reg_addr_mask
10	RW	WO_AND	WO_OR	PBAFIRMASK_AXPUSH_WRERR_MASK: axpush_wrerr_mask
11	RW	WO_AND	WO_OR	PBAFIRMASK_AXIPUSH_WRERR_MASK: axipush_wrerr_mask
12	RW	WO_AND	WO_OR	PBAFIRMASK_AXFLOW_ERR_MASK: axflow_err_mask
13	RW	WO_AND	WO_OR	PBAFIRMASK_AXIFLOW_ERR_MASK: axiflow_err_mask
14	RW	WO_AND	WO_OR	PBAFIRMASK_AXSND_RSVERR_MASK: axsnd_rsverr_mask
15	RW	WO_AND	WO_OR	PBAFIRMASK_AXISND_RSVERR_MASK: axsind_rsverr_mask
16	RW	WO_AND	WO_OR	PBAFIRMASK_HTM_OVERFLOW_MASK: htm_overflow_mask
17	RW	WO_AND	WO_OR	PBAFIRMASK_INVALID_TOPOLOGY_ID_MASK: invalid_topology_id_mask
18:19	RW	WO_AND	WO_OR	PBAFIRMASK_RESERVED_MASK: reserved_mask
20:63	RO	RO	RO	constant=0b00000000000000000000000000000000000000000000

PBA FIR Action0
Addr:	0000000001010CC6 (SCOM)
Name:	TP.TPBR.PBA.PBAO.PBAFIRACT0
Constant(s):
Comments:	PBA Local Fault Isolation Action0 Register. All Errors are configured as Recoverable in this register by the hardware as the default value.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:19	TP.TPBR.PBA.PBAO.SCOM.LSCOMFIR.PAR_OFF.LEM_FIR.LOCALFIR.FIR.DO_ACTION0.FIR_ACTION0.LATC.L2(0:19) [00000000000000000000]
Bit(s)	SCOM			Dial: Description
0:19	RW			PBAFIRACT0_FIR_ACTION0: MSB of action select for corresponding bit in FIR (Action0, Action1, Mask) = Action Select (0,0,0) = Checkstop Error (PBA_TC_XSTOP) (0,1,0) = Recoverable Error (PBA_TC_RECOV) (1,0,0) = N/A (1,1,0) = N/A (x,x,1) = MASKED
20:63	RO			constant=0b00000000000000000000000000000000000000000000

PBA FIR Action1
Addr:	0000000001010CC7 (SCOM)
Name:	TP.TPBR.PBA.PBAO.PBAFIRACT1
Constant(s):
Comments:	OCC Local Fault Isolation Action1 Register. All Errors are configured as Recoverable in this register by the hardware as the default value.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:19	TP.TPBR.PBA.PBAO.SCOM.LSCOMFIR.PAR_OFF.LEM_FIR.LOCALFIR.FIR.DO_ACTION1.FIR_ACTION1.LATC.L2(0:19) [00000000000000000000]
Bit(s)	SCOM			Dial: Description
0:19	RW			PBAFIRACT1_FIR_ACTION1: MSB of action select for corresponding bit in FIR (Action0, Action1, Mask) = Action Select (0,0,0) = Checkstop Error (PBA_TC_XSTOP) (0,1,0) = Recoverable Error (PBA_TC_RECOV) (1,0,0) = N/A (1,1,0) = N/A (x,x,1) = MASKED
20:63	RO			constant=0b00000000000000000000000000000000000000000000

PBA OCC Action
Addr:	0000000001010CCA (SCOM)
Name:	TP.TPBR.PBA.PBAO.PBAOCCACT
Constant(s):
Comments:	This register controls whether an error input to the FIR will pulse the pba_occ_error indication to the OCC logic. This register resets to all zero and is must be initialized by OCC Firmware.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:19	TP.TPBR.PBA.PBAO.SCOM.PBA_OCC_ACTION_Q_0_INST.LATC.L2(0:19) [00000000000000000000]
Bit(s)	SCOM			Dial: Description
0:19	RW			PBAOCCACT_OCC_ACTION_SET: OCC Action Set 0 - FIR Input does not cause pba_occ_error to be pulsed. 1 - FIR input causes pba_occ_error to be pulsed.
20:63	RO			constant=0b00000000000000000000000000000000000000000000

PBA Configuration Register for OCI
Addr:	0000000001010CCB (SCOM)
Name:	TP.TPBR.PBA.PBAO.PBAOCFG
Constant(s):
Comments:	This register is used to setup system-specific settings for the PowerBus and for Debug Chicken Switches
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:19	TP.TPBR.PBA.PBAO.SCOM.PBAO_CFG_Q_0_INST.LATC.L2(0:19) [00000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			PBAOCFG_CHSW_HANG_ON_ADRERROR: Enable PBA OCI Slave Hang on PowerBus Address error. 0 - Address error on powerbus request will self-recover (Default) 1 - Address error on powerbus request will need SLVRST to recover otherwise it will hang.
1	RW			PBAOCFG_CHSW_DIS_OCIABUSPAR_CHECK: Disable OCI Address Parity Checking and Generation OFF - PBA OCI Slave uses oci_pba_s_addrparen to control whether address parity is checked. PBA OCI Master asserts pba_oci_m_addrparen. ON - PBA OCI Slave does not check address parity. PBA OCI Master does not assert pba_oci_m_addrparen.
2	RW			PBAOCFG_CHSW_DIS_OCIBEPAR_CHECK: Disable OCI BE Parity Checking and Generation OFF - PBA OCI Slave uses oci_pba_s_beparen to control whether BE parity is checked. PBA OCI Master asserts pba_oci_m_beparen. ON - PBA OCI Slave does not check BE parity. PBA OCI Master does not assert pba_oci_m_beparen.
3	RW			PBAOCFG_CHSW_HANG_ON_DERROR: Enable PBA OCI Slave hang on PowerBus Data Error 0 - PowerBus data error will self-recover after sending RDDACK w/ an error response to the OCI Master (Default) 1 - PowerBus data error will cause hang after sending RDDACK w/ an error response. Buffer FSM cannot be reset.
4	RW			PBAOCFG_CHSW_DIS_WRITE_MATCH_REARB: Disable PBA OCI Slave Write Ordering Match. Disable Rearb for incoming write that matches in the same cacheline as a pending write. This will allow sequential, non-gathered writes to get queued. This will allow overlapping writes to get out of order if the pending write is retried by the Memory Controller.
5	RW			PBAOCFG_CHSW_DIS_OCIDATAPAR_GEN: Disable OCI Data Parity Generation This bit is used to control data parity generate by the PBA OCI Master and OCI Slave. OFF - PBA OCI Slave assert pba_oci_s_rdbusparen with valid read data. PBA OCI Master assert pba_oci_m_wrbusparen with valid write data. ON - PBA OCI Slave does not assert pba_oci_s_rdbusparen with valid read data. PBA OCI Master does not assert pba_oci_m_wrbusparen with valid write data.
6	RW			PBAOCFG_CHSW_DIS_OCIDATAPAR_CHECK: Disable OCI Data Parity Checking OFF - PBA OCI Slave uses oci_pba_s_wrbusparen to control whether the write data parity is checked. PBA OCI Master uses pba_oci_m_rdbusparen to control whether the read data parity is checked. ON - PBA OCI Slave does not check write data parity. PBA OCI Master does not check read data parity.
7	RW			PBAOCFG_CHSW_USE_TOPOLOGY_ID_SCOPE: Use the P10 topology ID to set initial scope OFF - The starting scope specified in PBABAR will be used ON - The starting scope will be determined by command address bits 15:19 and topology id and mode.
8	RW			PBAOCFG_HTM_ENABLE: Enable the asynchronous queue to transfer HTM records to the nest domain. Must also set PBAFCFG[HTM_ENABLE]
9:11	RW			PBAOCFG_RESERVED_9_11: Spare
12	RW			PBAOCFG_CHSW_DISABLE_LN_RD: Disable LocalNode Scope for Reads when using the topplogyID tables
13	RW			PBAOCFG_CHSW_DISABLE_NN_RN_RD: Disable NearNode/RemoteNode Scope for Reads when using the topplogyID tables
14	RW			PBAOCFG_CHSW_DISABLE_GROUP_RD: Disable Group Scope for Reads when using the topplogyID tables
15	RW			PBAOCFG_RESERVED_15: Reserved
16	RW			PBAOCFG_CHSW_DISABLE_LN_WR: Disable LocalNode Scope for Writes when using the topplogyID tables
17	RW			PBAOCFG_CHSW_DISABLE_NN_RN_WR: Disable NearNode/RemoteNode Scope for Writes when using the topplogyID tables
18	RW			PBAOCFG_CHSW_DISABLE_GROUP_WR: Disable Group Scope for Writes when using the topplogyID tables
19	RW			PBAOCFG_RESERVED_19: Reserved
20:63	RO			constant=0b00000000000000000000000000000000000000000000

PBA Error Report 1 Register
Addr:	0000000001010CCD (SCOM)
Name:	TP.TPBR.PBA.PBAO.PBAERRRPT1
Constant(s):
Comments:	PBA Error Report Register 1shows the hold condition from the c_err_rpt logic for each individual error detected by the PBA. Writing any value to the PBAERRRPT0 will force a reset to clear all hold bits in all the PBAERRPTn.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:5	TP.TPBR.PBA.PBAO.SCOM.OCI_REREQTO_ERR_OUT_0_INST.HOLD_LATCH_INST.HOLD.LATC.L2(0:5) [000000]
	6:7	TP.TPBR.PBA.PBAO.SCOM.BCDE_SETUP_ERR_ERR_OUT_0_INST.HOLD_LATCH_INST.HOLD.LATC.L2(0:1) [00]
	8:9	TP.TPBR.PBA.PBAO.SCOM.BCUE_SETUP_ERR_ERR_OUT_0_INST.HOLD_LATCH_INST.HOLD.LATC.L2(0:1) [00]
	10:11	TP.TPBR.PBA.PBAO.SCOM.BCUE_OCI_DATERR_ERR_OUT_0_INST.HOLD_LATCH_INST.HOLD.LATC.L2(0:1) [00]
Bit(s)	SCOM			Dial: Description
0:5	ROX			PBAERRRPT1_RESERVED_0_5: Reserved tied to zero
6:7	ROX			PBAERRRPT1_CERR_BCDE_SETUP_ERR: CERR_OBS: PBAFIR(20) BCDE Setup Error 0 - unexpected start when already running, 1 - powerbus addr error
8:9	ROX			PBAERRRPT1_CERR_BCUE_SETUP_ERR: CERR_OBS: PBAFIR(16) BCUE Setup Error 0 - unexpected start when already running, 1 - powerbus addr error
10:11	ROX			PBAERRRPT1_CERR_BCUE_OCI_DATAERR: CERR_OBS: PBAFIR(19) 0 - BCUE received MRDERR, 1 - BCUE Read Parity Error..
12:63	RO			constant=0b0000000000000000000000000000000000000000000000000000

PBA Error Report 2 Register
Addr:	0000000001010CCE (SCOM)
Name:	TP.TPBR.PBA.PBAO.PBAERRRPT2
Constant(s):
Comments:	PBA Error Report Register 2 (read/clear c_err_rpt) shows the hold condition from the c_err_rpt logic for each individual error detected by the PBA. Writing any value to the PBAERRRPT0 will force a reset to clear all hold bits in all the PBAERRPTn.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:16	TP.TPBR.PBA.PBAO.SCOM.INTERNAL_ERR_ERR_OUT_0_INST.HOLD_LATCH_INST.HOLD.LATC.L2(0:16) [00000000000000000]
	17:19	TP.TPBR.PBA.PBAO.SCOM.AXFLOW_ERR_ERR_OUT_0_INST.HOLD_LATCH_INST.HOLD.LATC.L2(0:2) [000]
	20:21	TP.TPBR.PBA.PBAO.SCOM.AXPUSH_WRERR_ERR_OUT_0_INST.HOLD_LATCH_INST.HOLD.LATC.L2(0:1) [00]
	22:24	TP.TPBR.PBA.PBAO.SCOM.AXIFLOW_ERR_ERR_OUT_0_INST.HOLD_LATCH_INST.HOLD.LATC.L2(0:2) [000]
	25:26	TP.TPBR.PBA.PBAO.SCOM.AXIPUSH_WRERR_ERR_OUT_0_INST.HOLD_LATCH_INST.HOLD.LATC.L2(0:1) [00]
Bit(s)	SCOM			Dial: Description
0:7	ROX			PBAERRRPT2_CERR_SLV_INTERNAL_ERR: CERR_OBS: PBAFIR(8) PBA Internal Error (OCI Slave) 0 - Multi address match 1 - Multip rdbuf start 2 - Unexp rdbuf start 3 - Cancel rdbuf start 4 - Bad Region or Marker Address in PBAMODE register 5 - RDBUFFSM illegal State 6 - WRBUFFSM illegal State 7 - not defined.
8:11	ROX			PBAERRRPT2_CERR_BCDE_INTERNAL_ERR: CERR_OBS: PBAFIR(8) PBA Internal Error (BCDE) 0 - Unexp addrack 1 - Unexp dataack 2 - wrfsm illegal state 3 - bcefsm illegal state
12:15	ROX			PBAERRRPT2_CERR_BCUE_INTERNAL_ERR: CERR_OBS: PBAFIR(8) PBA Internal Error (BCDE) 0 - Unexp addrack 1 - Unexp dataack 2 - not defined. 3 - bcefsm illegal state
16	ROX			PBAERRRPT2_BAR_PARITY_ERR: A parity error was detect on a PBA_BAR register
17:19	ROX			PBAERRRPT2_CERR_AXFLOW_ERR: CERR_OBS.PBAFIR(12) PBAX Flow error 0 - axflow Setup 1:2 - axflow Underflow per qid.
20:21	ROX			PBAERRRPT2_CERR_AXPUSH_WRERR: CERR_OBS.PBAFIR(10) PBAX Push Write Error 0 - push queue 0 1 - push queue 1
22:24	ROX			PBAERRRPT2_CERR_AXIFLOW_ERR: CERR_OBS.PBAFIR(13) PBAXI Flow error 0 - axflow Setup 1:2 - axflow Underflow per qid.
25:26	ROX			PBAERRRPT2_CERR_AXIPUSH_WRERR: CERR_OBS.PBAFIR(11) PBAXI Push Write Error 0 - push queue 0 1 - push queue 1
27:63	RO			constant=0b0000000000000000000000000000000000000

PBA Read Buffer Valid Status 0
Addr:	0000000001010CD0 (SCOM)
Name:	TP.TPBR.PBA.PBAO.PBARBUFVAL0
Constant(s):
Comments:	These are read-only status registers for the PBA Slave that contain vital information regarding the PowerBus Read data buffer state. These registers are used for debug and error recovery.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:1	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#0.RD.SLVNUM_Q_0_INST.LATC.L2(0:1) [00]
	2:24	TP.TPBR.PBA.PBAO.OCISLAD.A.CUR_RD_ADDR_0_Q_INST.LATC.L2(2:24) [00000000000000000000000]
	28	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#0.RD.PREFETCH_Q_INST.LATC.L2(0) [0]
	31	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#0.RD.ABORT_Q_INST.LATC.L2(0) [0]
	33:39	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#0.RD.RDBUFFSM_Q_0_INST.LATC.L2(1:7) [0000000]
	41:43	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#0.RD.MASTERID_HOLD_Q_0_INST.LATC.L2(0:2) [000]
Bit(s)	SCOM			Dial: Description
0:1	ROX			PBARBUFVAL0_RD_SLVNUM: Rd_slvnum This is the pbaslvctl that defines the the master_id, and buffer controls for this OCI address. It is set by the OCI Slave Control logic when the buffer is selected. Dial enums: SLVCTL0=>0b00 SLVCTL1=>0b01 SLVCTL2=>0b10 SLVCTL3=>0b11
2:24	ROX			PBARBUFVAL0_CUR_RD_ADDR: Current Rd Address 128-byte cache line address for the current buffer. It is set by the OCI Slave Control logic when the buffer is selected. This is an EA prior to the PBABASE and PBAMASK is applied.
25:27	RO			constant=0b000
28	ROX			PBARBUFVAL0_PREFETCH: Prefetch Status This bit is set when the next cacheline is prefetched and is used as extra info to decide if the buffer can be reused for another operation and forced to the Timeout state when the buffer is in the Valid, PB CRESP Error, or PB Data Error state. This bit is cleared when an OCI Request matches the address or when the Rd Buffer Status goes to the Empty State. 0FF - OCI Read Address requested this buffered address ON - PowerBus Read request kicked off for next cacheline prefetch
29:30	RO			constant=0b00
31	ROX			PBARBUFVAL0_ABORT: Abort Status This bit is set when the OCI Master has aborted the request or the PBASLVRST[SLV Reset] was written while the read data is being fetched. This bit clears when the Rd Buffer Status goes to the Empty State. OFF - Request has not been aborted ON - Request has been aborted
32	RO			constant=0b0
33:39	ROX			PBARBUFVAL0_BUFFER_STATUS: Rd Buffer Status These bits indicate which bit is set in the one-hot Read in Progress state machine. Zero is not a valid state after clocks have started. Dial enums: EMPTY=>0b0000001 FETCHING=>0b0000010 VALID=>0b0000100 VALIDWFP=>0b0001000 DATAERR=>0b0010000 CRESPERR=>0b0100000 REREQ_TO=>0b1000000
40	RO			constant=0b0 Dial enums: EMPTY=>0b0000001 FETCHING=>0b0000010 VALID=>0b0000100 VALIDWFP=>0b0001000 DATAERR=>0b0010000 CRESPERR=>0b0100000 REREQ_TO=>0b1000000
41:43	ROX			PBARBUFVAL0_MASTERID: Master Id These bits indicate the Master Id that requested the read operation.
44:63	RO			constant=0b00000000000000000000

PBA Read Buffer Valid Status 1
Addr:	0000000001010CD1 (SCOM)
Name:	TP.TPBR.PBA.PBAO.PBARBUFVAL1
Constant(s):
Comments:	These are read-only status registers for the PBA Slave that contain vital information regarding the PowerBus Read data buffer state. These registers are used for debug and error recovery.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:1	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#1.RD.SLVNUM_Q_0_INST.LATC.L2(0:1) [00]
	2:24	TP.TPBR.PBA.PBAO.OCISLAD.A.CUR_RD_ADDR_1_Q_INST.LATC.L2(2:24) [00000000000000000000000]
	28	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#1.RD.PREFETCH_Q_INST.LATC.L2(0) [0]
	31	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#1.RD.ABORT_Q_INST.LATC.L2(0) [0]
	33:39	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#1.RD.RDBUFFSM_Q_0_INST.LATC.L2(1:7) [0000000]
	41:43	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#1.RD.MASTERID_HOLD_Q_0_INST.LATC.L2(0:2) [000]
Bit(s)	SCOM			Dial: Description
0:1	ROX			PBARBUFVAL1_RD_SLVNUM: Rd_slvnum This is the pbaslvctl that defines the the master_id, and buffer controls for this OCI address. It is set by the OCI Slave Control logic when the buffer is selected. Dial enums: SLVCTL0=>0b00 SLVCTL1=>0b01 SLVCTL2=>0b10 SLVCTL3=>0b11
2:24	ROX			PBARBUFVAL1_CUR_RD_ADDR: Current Rd Address 128-byte cache line address for the current buffer. It is set by the OCI Slave Control logic when the buffer is selected. This is an EA prior to the PBABASE and PBAMASK is applied.
25:27	RO			constant=0b000
28	ROX			PBARBUFVAL1_PREFETCH: Prefetch Status This bit is set when the next cacheline is prefetched and is used as extra info to decide if the buffer can be reused for another operation and forced to the Timeout state when the buffer is in the Valid, PB CRESP Error, or PB Data Error state. This bit is cleared when an OCI Request matches the address or when the Rd Buffer Status goes to the Empty State. 0FF - OCI Read Address requested this buffered address ON - PowerBus Read request kicked off for next cacheline prefetch
29:30	RO			constant=0b00
31	ROX			PBARBUFVAL1_ABORT: Abort Status This bit is set when the OCI Master has aborted the request or the PBASLVRST[SLV Reset] was written while the read data is being fetched. This bit clears when the Rd Buffer Status goes to the Empty State. OFF - Request has not been aborted ON - Request has been aborted
32	RO			constant=0b0
33:39	ROX			PBARBUFVAL1_BUFFER_STATUS: Rd Buffer Status These bits indicate which bit is set in the one-hot Read in Progress state machine. Zero is not a valid state after clocks have started. Dial enums: EMPTY=>0b0000001 FETCHING=>0b0000010 VALID=>0b0000100 VALIDWFP=>0b0001000 DATAERR=>0b0010000 CRESPERR=>0b0100000 REREQ_TO=>0b1000000
40	RO			constant=0b0 Dial enums: EMPTY=>0b0000001 FETCHING=>0b0000010 VALID=>0b0000100 VALIDWFP=>0b0001000 DATAERR=>0b0010000 CRESPERR=>0b0100000 REREQ_TO=>0b1000000
41:43	ROX			PBARBUFVAL1_MASTERID: Master Id These bits indicate the Master Id that requested the read operation.
44:63	RO			constant=0b00000000000000000000

PBA Read Buffer Valid Status 2
Addr:	0000000001010CD2 (SCOM)
Name:	TP.TPBR.PBA.PBAO.PBARBUFVAL2
Constant(s):
Comments:	These are read-only status registers for the PBA Slave that contain vital information regarding the PowerBus Read data buffer state. These registers are used for debug and error recovery.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:1	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#2.RD.SLVNUM_Q_0_INST.LATC.L2(0:1) [00]
	2:24	TP.TPBR.PBA.PBAO.OCISLAD.B.CUR_RD_ADDR_0_Q_INST.LATC.L2(2:24) [00000000000000000000000]
	28	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#2.RD.PREFETCH_Q_INST.LATC.L2(0) [0]
	31	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#2.RD.ABORT_Q_INST.LATC.L2(0) [0]
	33:39	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#2.RD.RDBUFFSM_Q_0_INST.LATC.L2(1:7) [0000000]
	41:43	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#2.RD.MASTERID_HOLD_Q_0_INST.LATC.L2(0:2) [000]
Bit(s)	SCOM			Dial: Description
0:1	ROX			PBARBUFVAL2_RD_SLVNUM: Rd_slvnum This is the pbaslvctl that defines the the master_id, and buffer controls for this OCI address. It is set by the OCI Slave Control logic when the buffer is selected. Dial enums: SLVCTL0=>0b00 SLVCTL1=>0b01 SLVCTL2=>0b10 SLVCTL3=>0b11
2:24	ROX			PBARBUFVAL2_CUR_RD_ADDR: Current Rd Address 128-byte cache line address for the current buffer. It is set by the OCI Slave Control logic when the buffer is selected. This is an EA prior to the PBABASE and PBAMASK is applied.
25:27	RO			constant=0b000
28	ROX			PBARBUFVAL2_PREFETCH: Prefetch Status This bit is set when the next cacheline is prefetched and is used as extra info to decide if the buffer can be reused for another operation and forced to the Timeout state when the buffer is in the Valid, PB CRESP Error, or PB Data Error state. This bit is cleared when an OCI Request matches the address or when the Rd Buffer Status goes to the Empty State. 0FF - OCI Read Address requested this buffered address ON - PowerBus Read request kicked off for next cacheline prefetch
29:30	RO			constant=0b00
31	ROX			PBARBUFVAL2_ABORT: Abort Status This bit is set when the OCI Master has aborted the request or the PBASLVRST[SLV Reset] was written while the read data is being fetched. This bit clears when the Rd Buffer Status goes to the Empty State. OFF - Request has not been aborted ON - Request has been aborted
32	RO			constant=0b0
33:39	ROX			PBARBUFVAL2_BUFFER_STATUS: Rd Buffer Status These bits indicate which bit is set in the one-hot Read in Progress state machine. Zero is not a valid state after clocks have started. Dial enums: EMPTY=>0b0000001 FETCHING=>0b0000010 VALID=>0b0000100 VALIDWFP=>0b0001000 DATAERR=>0b0010000 CRESPERR=>0b0100000 REREQ_TO=>0b1000000
40	RO			constant=0b0 Dial enums: EMPTY=>0b0000001 FETCHING=>0b0000010 VALID=>0b0000100 VALIDWFP=>0b0001000 DATAERR=>0b0010000 CRESPERR=>0b0100000 REREQ_TO=>0b1000000
41:43	ROX			PBARBUFVAL2_MASTERID: Master Id These bits indicate the Master Id that requested the read operation.
44:63	RO			constant=0b00000000000000000000

PBA Read Buffer Valid Status 3
Addr:	0000000001010CD3 (SCOM)
Name:	TP.TPBR.PBA.PBAO.PBARBUFVAL3
Constant(s):
Comments:	These are read-only status registers for the PBA Slave that contain vital information regarding the PowerBus Read data buffer state. These registers are used for debug and error recovery.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:1	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#3.RD.SLVNUM_Q_0_INST.LATC.L2(0:1) [00]
	2:24	TP.TPBR.PBA.PBAO.OCISLAD.B.CUR_RD_ADDR_1_Q_INST.LATC.L2(2:24) [00000000000000000000000]
	28	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#3.RD.PREFETCH_Q_INST.LATC.L2(0) [0]
	31	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#3.RD.ABORT_Q_INST.LATC.L2(0) [0]
	33:39	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#3.RD.RDBUFFSM_Q_0_INST.LATC.L2(1:7) [0000000]
	41:43	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#3.RD.MASTERID_HOLD_Q_0_INST.LATC.L2(0:2) [000]
Bit(s)	SCOM			Dial: Description
0:1	ROX			PBARBUFVAL3_RD_SLVNUM: Rd_slvnum This is the pbaslvctl that defines the the master_id, and buffer controls for this OCI address. It is set by the OCI Slave Control logic when the buffer is selected. Dial enums: SLVCTL0=>0b00 SLVCTL1=>0b01 SLVCTL2=>0b10 SLVCTL3=>0b11
2:24	ROX			PBARBUFVAL3_CUR_RD_ADDR: Current Rd Address 128-byte cache line address for the current buffer. It is set by the OCI Slave Control logic when the buffer is selected. This is an EA prior to the PBABASE and PBAMASK is applied.
25:27	RO			constant=0b000
28	ROX			PBARBUFVAL3_PREFETCH: Prefetch Status This bit is set when the next cacheline is prefetched and is used as extra info to decide if the buffer can be reused for another operation and forced to the Timeout state when the buffer is in the Valid, PB CRESP Error, or PB Data Error state. This bit is cleared when an OCI Request matches the address or when the Rd Buffer Status goes to the Empty State. 0FF - OCI Read Address requested this buffered address ON - PowerBus Read request kicked off for next cacheline prefetch
29:30	RO			constant=0b00
31	ROX			PBARBUFVAL3_ABORT: Abort Status This bit is set when the OCI Master has aborted the request or the PBASLVRST[SLV Reset] was written while the read data is being fetched. This bit clears when the Rd Buffer Status goes to the Empty State. OFF - Request has not been aborted ON - Request has been aborted
32	RO			constant=0b0
33:39	ROX			PBARBUFVAL3_BUFFER_STATUS: Rd Buffer Status These bits indicate which bit is set in the one-hot Read in Progress state machine. Zero is not a valid state after clocks have started. Dial enums: EMPTY=>0b0000001 FETCHING=>0b0000010 VALID=>0b0000100 VALIDWFP=>0b0001000 DATAERR=>0b0010000 CRESPERR=>0b0100000 REREQ_TO=>0b1000000
40	RO			constant=0b0 Dial enums: EMPTY=>0b0000001 FETCHING=>0b0000010 VALID=>0b0000100 VALIDWFP=>0b0001000 DATAERR=>0b0010000 CRESPERR=>0b0100000 REREQ_TO=>0b1000000
41:43	ROX			PBARBUFVAL3_MASTERID: Master Id These bits indicate the Master Id that requested the read operation.
44:63	RO			constant=0b00000000000000000000

PBA Read Buffer Valid Status 4
Addr:	0000000001010CD4 (SCOM)
Name:	TP.TPBR.PBA.PBAO.PBARBUFVAL4
Constant(s):
Comments:	These are read-only status registers for the PBA Slave that contain vital information regarding the PowerBus Read data buffer state. These registers are used for debug and error recovery.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:1	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#4.RD.SLVNUM_Q_0_INST.LATC.L2(0:1) [00]
	2:24	TP.TPBR.PBA.PBAO.OCISLAD.C.CUR_RD_ADDR_0_Q_INST.LATC.L2(2:24) [00000000000000000000000]
	28	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#4.RD.PREFETCH_Q_INST.LATC.L2(0) [0]
	31	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#4.RD.ABORT_Q_INST.LATC.L2(0) [0]
	33:39	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#4.RD.RDBUFFSM_Q_0_INST.LATC.L2(1:7) [0000000]
	41:43	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#4.RD.MASTERID_HOLD_Q_0_INST.LATC.L2(0:2) [000]
Bit(s)	SCOM			Dial: Description
0:1	ROX			PBARBUFVAL4_RD_SLVNUM: Rd_slvnum This is the pbaslvctl that defines the the master_id, and buffer controls for this OCI address. It is set by the OCI Slave Control logic when the buffer is selected. Dial enums: SLVCTL0=>0b00 SLVCTL1=>0b01 SLVCTL2=>0b10 SLVCTL3=>0b11
2:24	ROX			PBARBUFVAL4_CUR_RD_ADDR: Current Rd Address 128-byte cache line address for the current buffer. It is set by the OCI Slave Control logic when the buffer is selected. This is an EA prior to the PBABASE and PBAMASK is applied.
25:27	RO			constant=0b000
28	ROX			PBARBUFVAL4_PREFETCH: Prefetch Status This bit is set when the next cacheline is prefetched and is used as extra info to decide if the buffer can be reused for another operation and forced to the Timeout state when the buffer is in the Valid, PB CRESP Error, or PB Data Error state. This bit is cleared when an OCI Request matches the address or when the Rd Buffer Status goes to the Empty State. 0FF - OCI Read Address requested this buffered address ON - PowerBus Read request kicked off for next cacheline prefetch
29:30	RO			constant=0b00
31	ROX			PBARBUFVAL4_ABORT: Abort Status This bit is set when the OCI Master has aborted the request or the PBASLVRST[SLV Reset] was written while the read data is being fetched. This bit clears when the Rd Buffer Status goes to the Empty State. OFF - Request has not been aborted ON - Request has been aborted
32	RO			constant=0b0
33:39	ROX			PBARBUFVAL4_BUFFER_STATUS: Rd Buffer Status These bits indicate which bit is set in the one-hot Read in Progress state machine. Zero is not a valid state after clocks have started. Dial enums: EMPTY=>0b0000001 FETCHING=>0b0000010 VALID=>0b0000100 VALIDWFP=>0b0001000 DATAERR=>0b0010000 CRESPERR=>0b0100000 REREQ_TO=>0b1000000
40	RO			constant=0b0 Dial enums: EMPTY=>0b0000001 FETCHING=>0b0000010 VALID=>0b0000100 VALIDWFP=>0b0001000 DATAERR=>0b0010000 CRESPERR=>0b0100000 REREQ_TO=>0b1000000
41:43	ROX			PBARBUFVAL4_MASTERID: Master Id These bits indicate the Master Id that requested the read operation.
44:63	RO			constant=0b00000000000000000000

PBA Read Buffer Valid Status 5
Addr:	0000000001010CD5 (SCOM)
Name:	TP.TPBR.PBA.PBAO.PBARBUFVAL5
Constant(s):
Comments:	These are read-only status registers for the PBA Slave that contain vital information regarding the PowerBus Read data buffer state. These registers are used for debug and error recovery.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:1	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#5.RD.SLVNUM_Q_0_INST.LATC.L2(0:1) [00]
	2:24	TP.TPBR.PBA.PBAO.OCISLAD.C.CUR_RD_ADDR_1_Q_INST.LATC.L2(2:24) [00000000000000000000000]
	28	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#5.RD.PREFETCH_Q_INST.LATC.L2(0) [0]
	31	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#5.RD.ABORT_Q_INST.LATC.L2(0) [0]
	33:39	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#5.RD.RDBUFFSM_Q_0_INST.LATC.L2(1:7) [0000000]
	41:43	TP.TPBR.PBA.PBAO.OCISLCTL.RDBUF#5.RD.MASTERID_HOLD_Q_0_INST.LATC.L2(0:2) [000]
Bit(s)	SCOM			Dial: Description
0:1	ROX			PBARBUFVAL5_RD_SLVNUM: Rd_slvnum This is the pbaslvctl that defines the the master_id, and buffer controls for this OCI address. It is set by the OCI Slave Control logic when the buffer is selected. Dial enums: SLVCTL0=>0b00 SLVCTL1=>0b01 SLVCTL2=>0b10 SLVCTL3=>0b11
2:24	ROX			PBARBUFVAL5_CUR_RD_ADDR: Current Rd Address 128-byte cache line address for the current buffer. It is set by the OCI Slave Control logic when the buffer is selected. This is an EA prior to the PBABASE and PBAMASK is applied.
25:27	RO			constant=0b000
28	ROX			PBARBUFVAL5_PREFETCH: Prefetch Status This bit is set when the next cacheline is prefetched and is used as extra info to decide if the buffer can be reused for another operation and forced to the Timeout state when the buffer is in the Valid, PB CRESP Error, or PB Data Error state. This bit is cleared when an OCI Request matches the address or when the Rd Buffer Status goes to the Empty State. 0FF - OCI Read Address requested this buffered address ON - PowerBus Read request kicked off for next cacheline prefetch
29:30	RO			constant=0b00
31	ROX			PBARBUFVAL5_ABORT: Abort Status This bit is set when the OCI Master has aborted the request or the PBASLVRST[SLV Reset] was written while the read data is being fetched. This bit clears when the Rd Buffer Status goes to the Empty State. OFF - Request has not been aborted ON - Request has been aborted
32	RO			constant=0b0
33:39	ROX			PBARBUFVAL5_BUFFER_STATUS: Rd Buffer Status These bits indicate which bit is set in the one-hot Read in Progress state machine. Zero is not a valid state after clocks have started. Dial enums: EMPTY=>0b0000001 FETCHING=>0b0000010 VALID=>0b0000100 VALIDWFP=>0b0001000 DATAERR=>0b0010000 CRESPERR=>0b0100000 REREQ_TO=>0b1000000
40	RO			constant=0b0 Dial enums: EMPTY=>0b0000001 FETCHING=>0b0000010 VALID=>0b0000100 VALIDWFP=>0b0001000 DATAERR=>0b0010000 CRESPERR=>0b0100000 REREQ_TO=>0b1000000
41:43	ROX			PBARBUFVAL5_MASTERID: Master Id These bits indicate the Master Id that requested the read operation.
44:63	RO			constant=0b00000000000000000000

PBA Write Buffer Valid Status 0
Addr:	0000000001010CD8 (SCOM)
Name:	TP.TPBR.PBA.PBAO.PBAWBUFVAL0
Constant(s):
Comments:	These are read-only status registers for the PBA Slave that contain vital information regarding the PowerBus Write data buffer state. These registers are used for debug and error recovery.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:1	TP.TPBR.PBA.PBAO.OCISLCTL.WRBUF#0.WR.SLVNUM_Q_0_INST.LATC.L2(0:1) [00]
	2:31	TP.TPBR.PBA.PBAO.OCISLAD.W0.START_WR_ADDR_Q_2_INST.LATC.L2(2:31) [000000000000000000000000000000]
	35:39	TP.TPBR.PBA.PBAO.OCISLCTL.WRBUF#0.WR.WRBUFFSM_Q_0_INST.LATC.L2(0:4) [00000]
	41:47	TP.TPBR.PBA.PBAO.OCISLAD.W0.BYTE_COUNT_Q_INST.LATC.L2(1:7) [0000000]
Bit(s)	SCOM			Dial: Description
0:1	ROX			PBAWBUFVAL0_WR_SLVNUM: Wr_slvnum This is the pbaslvctl that defines the the master_id, and buffer controls for this OCI address. It is set by the OCI Slave Control logic when the buffer is selected. Dial enums: SLVCTL0=>0b00 SLVCTL1=>0b01 SLVCTL2=>0b10 SLVCTL3=>0b11
2:31	ROX			PBAWBUFVAL0_START_WR_ADDR: Starting Write Address These bits save the starting OCI address for the gathered write operation and are valid only If the write buffer status is not EMPTY.
32:34	RO			constant=0b000
35:39	ROX			PBAWBUFVAL0_WR_BUFFER_STATUS: Write Buffer Status These bits indicate which bit is set in the one-hot Write in Progress state machine. Zero is not a valid state after clocks have started. Dial enums: EMPTY=>0b00001 GATHERING=>0b00010 WAIT=>0b00100 WRITING=>0b01000 CRESPERR=>0b10000
40	RO			constant=0b0 Dial enums: EMPTY=>0b00001 GATHERING=>0b00010 WAIT=>0b00100 WRITING=>0b01000 CRESPERR=>0b10000
41:47	ROX			PBAWBUFVAL0_WR_BYTE_COUNT: Write Byte Count These bits are the number of bytes in the gathered write operation. Starting Write Address plus Write Byte Count is the Next Write Address from the same master required to continue gathering. 0000000 - 128 bytes 0000001 - 1 byte 0000010 - 2 bytes 0000011 - 3 bytes . . . 1111111 - 127 bytes
48:63	RO			constant=0b0000000000000000

PBA Write Buffer Valid Status 1
Addr:	0000000001010CD9 (SCOM)
Name:	TP.TPBR.PBA.PBAO.PBAWBUFVAL1
Constant(s):
Comments:	These are read-only status registers for the PBA Slave that contain vital information regarding the PowerBus Write data buffer state. These registers are used for debug and error recovery.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:1	TP.TPBR.PBA.PBAO.OCISLCTL.WRBUF#1.WR.SLVNUM_Q_0_INST.LATC.L2(0:1) [00]
	2:31	TP.TPBR.PBA.PBAO.OCISLAD.W1.START_WR_ADDR_Q_2_INST.LATC.L2(2:31) [000000000000000000000000000000]
	35:39	TP.TPBR.PBA.PBAO.OCISLCTL.WRBUF#1.WR.WRBUFFSM_Q_0_INST.LATC.L2(0:4) [00000]
	41:47	TP.TPBR.PBA.PBAO.OCISLAD.W1.BYTE_COUNT_Q_INST.LATC.L2(1:7) [0000000]
Bit(s)	SCOM			Dial: Description
0:1	ROX			PBAWBUFVAL1_WR_SLVNUM: Wr_slvnum This is the pbaslvctl that defines the the master_id, and buffer controls for this OCI address. It is set by the OCI Slave Control logic when the buffer is selected. Dial enums: SLVCTL0=>0b00 SLVCTL1=>0b01 SLVCTL2=>0b10 SLVCTL3=>0b11
2:31	ROX			PBAWBUFVAL1_START_WR_ADDR: Starting Write Address These bits save the starting OCI address for the gathered write operation and are valid only If the write buffer status is not EMPTY.
32:34	RO			constant=0b000
35:39	ROX			PBAWBUFVAL1_WR_BUFFER_STATUS: Write Buffer Status These bits indicate which bit is set in the one-hot Write in Progress state machine. Zero is not a valid state after clocks have started. Dial enums: EMPTY=>0b00001 GATHERING=>0b00010 WAIT=>0b00100 WRITING=>0b01000 CRESPERR=>0b10000
40	RO			constant=0b0 Dial enums: EMPTY=>0b00001 GATHERING=>0b00010 WAIT=>0b00100 WRITING=>0b01000 CRESPERR=>0b10000
41:47	ROX			PBAWBUFVAL1_WR_BYTE_COUNT: Write Byte Count These bits are the number of bytes in the gathered write operation. Starting Write Address plus Write Byte Count is the Next Write Address from the same master required to continue gathering. 0000000 - 128 bytes 0000001 - 1 byte 0000010 - 2 bytes 0000011 - 3 bytes . . . 1111111 - 127 bytes
48:63	RO			constant=0b0000000000000000

PBA Base Address Range Register 0
Addr:	0000000001010CDA (SCOM)
Name:	TP.TPBR.PBA.PBAO.PBABAR0
Constant(s):
Comments:	This register is used with the PBABARMSK0 to define the PowerBus address range accessible by the request. It must be initialized by PHYP before enabling and sending OCI transactions that target the PBA and before starting the Block Copy Engine. Even Data Parity is calculated and saved when this register is written. The PBA_FIR[Internal Err] indication is set when a parity error is detected.
SelectedAttributes:	Secure=true, Magic=true
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPBR.PBA.PBAO.SCOM.PBA_BAR0_Q_0_INST.LATC.L2(0:3) [0000]
	8:43	TP.TPBR.PBA.PBAO.SCOM.PBA_BAR0_Q_0_INST.LATC.L2(4:39) [000000000000000000000000000000000000]
	48:63	TP.TPBR.PBA.PBAO.SCOM.PBA_BAR0_Q_0_INST.LATC.L2(40:55) [0000000000000000]
Bit(s)	SCOM			Dial: Description
0:2	RW			PBABAR0_CMD_SCOPE: PowerBus Command Scope These bits are initialized by PHYP to indicate the command scope of the PowerBus request. The PBA will always use the defined scope first. The request will be reissued with an increased scope if the original request gets a retry response that indicates a larger scope is required. Nodal Scope for dma and atomic write ttypes will be forced to a minimum of Group by PBA.. Dial enums: LOCAL=>0b000 NEARNODE=>0b010 GROUP=>0b011 REMOTE=>0b100 VECTORED=>0b101
3	RW			PBABAR0_RESERVED_3: Spare
4:7	RO			constant=0b0000
8:43	RW			PBABAR0_ADDR: PowerBus_Base_Address These bits and the PBA Base Address Mask register define how the OCI address is mapped to the Power Bus by the PBA Slave and how the PowerBus Address offset is mapped by the Block Copy Engine. 8:22 - PB Base Address bit not maskable. Used as-is on the Power Bus. 23:43 - PB Base Address bits maskable w/ PBABARMSKn
44:47	RO			constant=0b0000
48:63	RW			PBABAR0_VTARGET: PowerBus Vectored Group Target This may be initialized by software to specify the initial vectored group target when the cmd_scope is configured to Vectored Group Scope. If zero or not all 1s, PBA will update the Target value it uses when sending commands with scope=Vg based on the CRESP of the request when retrying the request. If set to FF, PBA will always drive the Target value to FF when sending commands with scope=Vg.

PBA Base Address Range Register 1
Addr:	0000000001010CDB (SCOM)
Name:	TP.TPBR.PBA.PBAO.PBABAR1
Constant(s):
Comments:	This register is used with the PBABARMSK0 to define the PowerBus address range accessible by the request. It must be initialized by PHYP before enabling and sending OCI transactions that target the PBA and before starting the Block Copy Engine. Even Data Parity is calculated and saved when this register is written. The PBA_FIR[Internal Err] indication is set when a parity error is detected.
SelectedAttributes:	Secure=true, Magic=true
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPBR.PBA.PBAO.SCOM.PBA_BAR1_Q_0_INST.LATC.L2(0:3) [0000]
	8:43	TP.TPBR.PBA.PBAO.SCOM.PBA_BAR1_Q_0_INST.LATC.L2(4:39) [000000000000000000000000000000000000]
	48:63	TP.TPBR.PBA.PBAO.SCOM.PBA_BAR1_Q_0_INST.LATC.L2(40:55) [0000000000000000]
Bit(s)	SCOM			Dial: Description
0:2	RW			PBABAR1_CMD_SCOPE: PowerBus Command Scope These bits are initialized by PHYP to indicate the command scope of the PowerBus request. The PBA will always use the defined scope first. The request will be reissued with an increased scope if the original request gets a retry response that indicates a larger scope is required. Nodal Scope for dma and atomic write ttypes will be forced to a minimum of Group by PBA.. Dial enums: LOCAL=>0b000 NEARNODE=>0b010 GROUP=>0b011 REMOTE=>0b100 VECTORED=>0b101
3	RW			PBABAR1_RESERVED_3: Spare
4:7	RO			constant=0b0000
8:43	RW			PBABAR1_ADDR: PowerBus_Base_Address These bits and the PBA Base Address Mask register define how the OCI address is mapped to the Power Bus by the PBA Slave and how the PowerBus Address offset is mapped by the Block Copy Engine. 8:22 - PB Base Address bit not maskable. Used as-is on the Power Bus. 23:43 - PB Base Address bits maskable w/ PBABARMSKn
44:47	RO			constant=0b0000
48:63	RW			PBABAR1_VTARGET: PowerBus Vectored Group Target This may be initialized by software to specify the initial vectored group target when the cmd_scope is configured to Vectored Group Scope. If zero or not all 1s, PBA will update the Target value it uses when sending commands with scope=Vg based on the CRESP of the request when retrying the request. If set to FF, PBA will always drive the Target value to FF when sending commands with scope=Vg.

PBA Base Address Range Register 2
Addr:	0000000001010CDC (SCOM)
Name:	TP.TPBR.PBA.PBAO.PBABAR2
Constant(s):
Comments:	This register is used with the PBABARMSK0 to define the PowerBus address range accessible by the request. It must be initialized by PHYP before enabling and sending OCI transactions that target the PBA and before starting the Block Copy Engine. Even Data Parity is calculated and saved when this register is written. The PBA_FIR[Internal Err] indication is set when a parity error is detected.
SelectedAttributes:	Secure=true, Magic=true
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPBR.PBA.PBAO.SCOM.PBA_BAR2_Q_0_INST.LATC.L2(0:3) [0000]
	8:43	TP.TPBR.PBA.PBAO.SCOM.PBA_BAR2_Q_0_INST.LATC.L2(4:39) [000000000000000000000000000000000000]
	48:63	TP.TPBR.PBA.PBAO.SCOM.PBA_BAR2_Q_0_INST.LATC.L2(40:55) [0000000000000000]
Bit(s)	SCOM			Dial: Description
0:2	RW			PBABAR2_CMD_SCOPE: PowerBus Command Scope These bits are initialized by PHYP to indicate the command scope of the PowerBus request. The PBA will always use the defined scope first. The request will be reissued with an increased scope if the original request gets a retry response that indicates a larger scope is required. Nodal Scope for dma and atomic write ttypes will be forced to a minimum of Group by PBA.. Dial enums: LOCAL=>0b000 NEARNODE=>0b010 GROUP=>0b011 REMOTE=>0b100 VECTORED=>0b101
3	RW			PBABAR2_RESERVED_3: Spare
4:7	RO			constant=0b0000
8:43	RW			PBABAR2_ADDR: PowerBus_Base_Address These bits and the PBA Base Address Mask register define how the OCI address is mapped to the Power Bus by the PBA Slave and how the PowerBus Address offset is mapped by the Block Copy Engine. 8:22 - PB Base Address bit not maskable. Used as-is on the Power Bus. 23:43 - PB Base Address bits maskable w/ PBABARMSKn
44:47	RO			constant=0b0000
48:63	RW			PBABAR2_VTARGET: PowerBus Vectored Group Target This may be initialized by software to specify the initial vectored group target when the cmd_scope is configured to Vectored Group Scope. If zero or not all 1s, PBA will update the Target value it uses when sending commands with scope=Vg based on the CRESP of the request when retrying the request. If set to FF, PBA will always drive the Target value to FF when sending commands with scope=Vg.

PBA Base Address Range Register 3
Addr:	0000000001010CDD (SCOM)
Name:	TP.TPBR.PBA.PBAO.PBABAR3
Constant(s):
Comments:	This register is used with the PBABARMSK0 to define the PowerBus address range accessible by the request. It must be initialized by PHYP before enabling and sending OCI transactions that target the PBA and before starting the Block Copy Engine. Even Data Parity is calculated and saved when this register is written. The PBA_FIR[Internal Err] indication is set when a parity error is detected.
SelectedAttributes:	Secure=true, Magic=true
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPBR.PBA.PBAO.SCOM.PBA_BAR3_Q_0_INST.LATC.L2(0:3) [0000]
	8:43	TP.TPBR.PBA.PBAO.SCOM.PBA_BAR3_Q_0_INST.LATC.L2(4:39) [000000000000000000000000000000000000]
	48:63	TP.TPBR.PBA.PBAO.SCOM.PBA_BAR3_Q_0_INST.LATC.L2(40:55) [0000000000000000]
Bit(s)	SCOM			Dial: Description
0:2	RW			PBABAR3_CMD_SCOPE: PowerBus Command Scope These bits are initialized by PHYP to indicate the command scope of the PowerBus request. The PBA will always use the defined scope first. The request will be reissued with an increased scope if the original request gets a retry response that indicates a larger scope is required. Nodal Scope for dma and atomic write ttypes will be forced to a minimum of Group by PBA.. Dial enums: LOCAL=>0b000 NEARNODE=>0b010 GROUP=>0b011 REMOTE=>0b100 VECTORED=>0b101
3	RW			PBABAR3_RESERVED_3: Spare
4:7	RO			constant=0b0000
8:43	RW			PBABAR3_ADDR: PowerBus_Base_Address These bits and the PBA Base Address Mask register define how the OCI address is mapped to the Power Bus by the PBA Slave and how the PowerBus Address offset is mapped by the Block Copy Engine. 8:22 - PB Base Address bit not maskable. Used as-is on the Power Bus. 23:43 - PB Base Address bits maskable w/ PBABARMSKn
44:47	RO			constant=0b0000
48:63	RW			PBABAR3_VTARGET: PowerBus Vectored Group Target This may be initialized by software to specify the initial vectored group target when the cmd_scope is configured to Vectored Group Scope. If zero or not all 1s, PBA will update the Target value it uses when sending commands with scope=Vg based on the CRESP of the request when retrying the request. If set to FF, PBA will always drive the Target value to FF when sending commands with scope=Vg.

PBA Base Address Range Mask Register 0
Addr:	0000000001010CDE (SCOM)
Name:	TP.TPBR.PBA.PBAO.PBABARMSK0
Constant(s):
Comments:	This register is used with the PBABARn to define the PowerBus address range accessible by the request. It must be initialized by PHYP before enabling and sending OCI transactions that target the PBA and before starting the Block Copy Engine. PBABARMSK3[mask] intializes to x000007 to define an 8Mbyte range at IPL time.
SelectedAttributes:	Secure=true, Magic=true
Latches	Bits	Latch Name [flushval]
	23:43	TP.TPBR.PBA.PBAO.SCOM.PBA_BARMSK0_Q_23_INST.LATC.L2(23:43) [000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:22	RO			constant=0b00000000000000000000000
23:43	RW			PBABARMSK0_MSK: PowerBus_Base_Address_Mask When set to a 1, the OCI Address (5:11) and PBASLVCTL[ExtAddr(23:36)] is used instead of the PB Base Address in that bit position. See the diagram of the OCI Address Mapping to PowerBus. Default to allow access to 1st 8M of memory.
44:63	RO			constant=0b00000000000000000000

PBA Base Address Range Mask Register 1
Addr:	0000000001010CDF (SCOM)
Name:	TP.TPBR.PBA.PBAO.PBABARMSK1
Constant(s):
Comments:	This register is used with the PBABARn to define the PowerBus address range accessible by the request. It must be initialized by PHYP before enabling and sending OCI transactions that target the PBA and before starting the Block Copy Engine. PBABARMSK3[mask] intializes to x000007 to define an 8Mbyte range at IPL time.
SelectedAttributes:	Secure=true, Magic=true
Latches	Bits	Latch Name [flushval]
	23:43	TP.TPBR.PBA.PBAO.SCOM.PBA_BARMSK1_Q_23_INST.LATC.L2(23:43) [000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:22	RO			constant=0b00000000000000000000000
23:43	RW			PBABARMSK1_MSK: PowerBus_Base_Address_Mask When set to a 1, the OCI Address (5:11) and PBASLVCTL[ExtAddr(23:36)] is used instead of the PB Base Address in that bit position. See the diagram of the OCI Address Mapping to PowerBus. Default to allow access to 1st 8M of memory.
44:63	RO			constant=0b00000000000000000000

PBA Base Address Range Mask Register 2
Addr:	0000000001010CE0 (SCOM)
Name:	TP.TPBR.PBA.PBAO.PBABARMSK2
Constant(s):
Comments:	This register is used with the PBABARn to define the PowerBus address range accessible by the request. It must be initialized by PHYP before enabling and sending OCI transactions that target the PBA and before starting the Block Copy Engine. PBABARMSK3[mask] intializes to x000007 to define an 8Mbyte range at IPL time.
SelectedAttributes:	Secure=true, Magic=true
Latches	Bits	Latch Name [flushval]
	23:43	TP.TPBR.PBA.PBAO.SCOM.PBA_BARMSK2_Q_23_INST.LATC.L2(23:43) [000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:22	RO			constant=0b00000000000000000000000
23:43	RW			PBABARMSK2_MSK: PowerBus_Base_Address_Mask When set to a 1, the OCI Address (5:11) and PBASLVCTL[ExtAddr(23:36)] is used instead of the PB Base Address in that bit position. See the diagram of the OCI Address Mapping to PowerBus. Default to allow access to 1st 8M of memory.
44:63	RO			constant=0b00000000000000000000

PBA Base Address Range Mask Register 3
Addr:	0000000001010CE1 (SCOM)
Name:	TP.TPBR.PBA.PBAO.PBABARMSK3
Constant(s):
Comments:	This register is used with the PBABARn to define the PowerBus address range accessible by the request. It must be initialized by PHYP before enabling and sending OCI transactions that target the PBA and before starting the Block Copy Engine. PBABARMSK3[mask] intializes to x000007 to define an 8Mbyte range at IPL time.
SelectedAttributes:	Secure=true, Magic=true
Latches	Bits	Latch Name [flushval]
	23:43	TP.TPBR.PBA.PBAO.SCOM.PBA_BARMSK3_Q_23_INST.LATC.L2(23:43) [000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:22	RO			constant=0b00000000000000000000000
23:43	RW			PBABARMSK3_MSK: PowerBus_Base_Address_Mask When set to a 1, the OCI Address (5:11) and PBASLVCTL[ExtAddr(23:36)] is used instead of the PB Base Address in that bit position. See the diagram of the OCI Address Mapping to PowerBus. Default to allow access to 1st 8M of memory.
44:63	RO			constant=0b00000000000000000000

PBA Powerbus Topology Xlate Table Register0
Addr:	0000000001010CE2 (SCOM)
Name:	TP.TPBR.PBA.PBAO.PBAPBTXT0
Constant(s):
Comments:	These 4 contiguous registers define the topology ID translation table for the QME, using Powerbus address 15:19 to lookup the initial scope to use Entry 0..31 across these four registers.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:39	TP.TPBR.PBA.PBAO.SCOM.PBA_PBTXT0_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:7	RW			PBAPBTXT0_ENTRY_VALID: Valid for each Entry nibble below
8:11	RW			PBAPBTXT0_ENTRY0: Scope for Entry(n*8 + 0)
12:15	RW			PBAPBTXT0_ENTRY1: Scope for Entry(n*8 + 1)
16:19	RW			PBAPBTXT0_ENTRY2: Scope for Entry(n*8 + 2)
20:23	RW			PBAPBTXT0_ENTRY3: Scope for Entry(n*8 + 3)
24:27	RW			PBAPBTXT0_ENTRY4: Scope for Entry(n*8 + 4)
28:31	RW			PBAPBTXT0_ENTRY5: Scope for Entry(n*8 + 5)
32:35	RW			PBAPBTXT0_ENTRY6: Scope for Entry(n*8 + 6)
36:39	RW			PBAPBTXT0_ENTRY7: Scope for Entry(n*8 + 7)
40:63	RO			constant=0b000000000000000000000000

PBA Powerbus Topology Xlate Table Register1
Addr:	0000000001010CE3 (SCOM)
Name:	TP.TPBR.PBA.PBAO.PBAPBTXT1
Constant(s):
Comments:	These 4 contiguous registers define the topology ID translation table for the QME, using Powerbus address 15:19 to lookup the initial scope to use Entry 0..31 across these four registers.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:39	TP.TPBR.PBA.PBAO.SCOM.PBA_PBTXT1_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:7	RW			PBAPBTXT1_ENTRY_VALID: Valid for each Entry nibble below
8:11	RW			PBAPBTXT1_ENTRY0: Scope for Entry(n*8 + 0)
12:15	RW			PBAPBTXT1_ENTRY1: Scope for Entry(n*8 + 1)
16:19	RW			PBAPBTXT1_ENTRY2: Scope for Entry(n*8 + 2)
20:23	RW			PBAPBTXT1_ENTRY3: Scope for Entry(n*8 + 3)
24:27	RW			PBAPBTXT1_ENTRY4: Scope for Entry(n*8 + 4)
28:31	RW			PBAPBTXT1_ENTRY5: Scope for Entry(n*8 + 5)
32:35	RW			PBAPBTXT1_ENTRY6: Scope for Entry(n*8 + 6)
36:39	RW			PBAPBTXT1_ENTRY7: Scope for Entry(n*8 + 7)
40:63	RO			constant=0b000000000000000000000000

PBA Powerbus Topology Xlate Table Register2
Addr:	0000000001010CE4 (SCOM)
Name:	TP.TPBR.PBA.PBAO.PBAPBTXT2
Constant(s):
Comments:	These 4 contiguous registers define the topology ID translation table for the QME, using Powerbus address 15:19 to lookup the initial scope to use Entry 0..31 across these four registers.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:39	TP.TPBR.PBA.PBAO.SCOM.PBA_PBTXT2_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:7	RW			PBAPBTXT2_ENTRY_VALID: Valid for each Entry nibble below
8:11	RW			PBAPBTXT2_ENTRY0: Scope for Entry(n*8 + 0)
12:15	RW			PBAPBTXT2_ENTRY1: Scope for Entry(n*8 + 1)
16:19	RW			PBAPBTXT2_ENTRY2: Scope for Entry(n*8 + 2)
20:23	RW			PBAPBTXT2_ENTRY3: Scope for Entry(n*8 + 3)
24:27	RW			PBAPBTXT2_ENTRY4: Scope for Entry(n*8 + 4)
28:31	RW			PBAPBTXT2_ENTRY5: Scope for Entry(n*8 + 5)
32:35	RW			PBAPBTXT2_ENTRY6: Scope for Entry(n*8 + 6)
36:39	RW			PBAPBTXT2_ENTRY7: Scope for Entry(n*8 + 7)
40:63	RO			constant=0b000000000000000000000000

PBA Powerbus Topology Xlate Table Register3
Addr:	0000000001010CE5 (SCOM)
Name:	TP.TPBR.PBA.PBAO.PBAPBTXT3
Constant(s):
Comments:	These 4 contiguous registers define the topology ID translation table for the QME, using Powerbus address 15:19 to lookup the initial scope to use Entry 0..31 across these four registers.
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:39	TP.TPBR.PBA.PBAO.SCOM.PBA_PBTXT3_Q_0_INST.LATC.L2(0:39) [0000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:7	RW			PBAPBTXT3_ENTRY_VALID: Valid for each Entry nibble below
8:11	RW			PBAPBTXT3_ENTRY0: Scope for Entry(n*8 + 0)
12:15	RW			PBAPBTXT3_ENTRY1: Scope for Entry(n*8 + 1)
16:19	RW			PBAPBTXT3_ENTRY2: Scope for Entry(n*8 + 2)
20:23	RW			PBAPBTXT3_ENTRY3: Scope for Entry(n*8 + 3)
24:27	RW			PBAPBTXT3_ENTRY4: Scope for Entry(n*8 + 4)
28:31	RW			PBAPBTXT3_ENTRY5: Scope for Entry(n*8 + 5)
32:35	RW			PBAPBTXT3_ENTRY6: Scope for Entry(n*8 + 6)
36:39	RW			PBAPBTXT3_ENTRY7: Scope for Entry(n*8 + 7)
40:63	RO			constant=0b000000000000000000000000

RX Cntl Reg
Addr:	0000000001011020 (SCOM)
Name:	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.RX_PSI_CNTL
Constant(s):	PU_RX_PSI_CNTL
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.RX_PSI_IORESET_WO_PULSE_SLOW_SIGNAL(0) [0]
	1	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_RX_PSI_PATTERN_CHECK_EN.L.L.LATC.L2(0) [0]
	2:3	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_RX_PSI_PATTERN_SEL.L.L.LATC.L2(0:1) [00]
	4	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_RX_PSI_CLK_INVERT.L.L.LATC.L2(0) [0]
	5	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_RX_PSI_LANE_INVERT.L.L.LATC.L2(0) [0]
	6	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_RX_PSI_PDWN.L.L.LATC.L2(0) [0]
	7:13	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_RX_PSI_CLK_DLY.L.L.LATC.L2(0:6) [0000000]
	14:20	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_RX_PSI_DATA_DLY.L.L.LATC.L2(0:6) [0000000]
	21:25	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_RX_PSI_DEGLITCH_CLK_DLY.L.L.LATC.L2(0:4) [00000]
	26:30	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_RX_PSI_DEGLITCH_DATA_DLY.L.L.LATC.L2(0:4) [00000]
Bit(s)	SCOM			Dial: Description
0	NCX			rx_psi_ioreset_wo_pulse_slow_signal
1	RWX			RX_PSI_PATTERN_CHECK_EN: Enables the drive pattern to be tested.. DMB 0b0 = No pattern checking 0b1 = Check for drive pattern Dial enums: DISABLED=>0b0 ENABLED=>0b1
2:3	RWX			RX_PSI_PATTERN_SEL: RX pattern select. DMB 0b00 = ei4 busy patt A 0b01 = ei4 busy patt B 0b10 = 16 bit legacy 0b11 = IE3 Busy IAP PAttern Dial enums: EI4A=>0b00 EI4B=>0b01 LEGACY16=>0b10 EI3BUSY=>0b11
4	RWX			RX_PSI_CLK_INVERT: Used to invert the polarity of the CLK.. DMB 0b0 = Normal CLK Polarity (default) 0b1 = CLK Inverted Dial enums: NORMAL=>0b0 INVERTED=>0b1
5	RWX			RX_PSI_LANE_INVERT: Used to invert the polarity of the data lane.. DMB 0b0 = Normal Data Lane Polarity (default) 0b1 = Data Lane Inverted Dial enums: NORMAL=>0b0 INVERTED=>0b1
6	RWX			RX_PSI_PDWN: Used to power down the PSI RX clock and data path.. MBS 0b0 = Operational (default) 0b1 = Clock and data path are powered off Dial enums: NORMAL=>0b0 POWERDOWN=>0b1
7:13	RWX			RX_PSI_CLK_DLY: Clock delay settingr. Default value is 300ps at the fast corner.. DMB
14:20	RWX			RX_PSI_DATA_DLY: Data delay setting. Default value is 300ps at the fast corner.. DMB
21:25	RWX			RX_PSI_DEGLITCH_CLK_DLY: Clock deglitcher delay setting. Default value is 300ps at the fast corner.. DMB
26:30	RWX			RX_PSI_DEGLITCH_DATA_DLY: Data deglitcher-match delay setting. To match clock line, default value is 300ps at the fast corner.. DMB
31	RO			constant=0b0

RX Mode Reg
Addr:	0000000001011021 (SCOM)
Name:	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.RX_PSI_MODE
Constant(s):	PU_RX_PSI_MODE
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_RX_PSI_VREF.L.L.LATC.L2(0:7) [00000000]
	12	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_RX_PSI_TERM_TEST_MODE.L.L.LATC.L2(0) [0]
	15:19	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_RX_PSI_TERM_MODE_ENC.L.L.LATC.L2(0:4) [00000]
	20:22	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_RX_PSI_PEAK.L.L.LATC.L2(0:2) [000]
	24:31	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_RX_PSI_MODE_SPARE.L.L.LATC.L2(0:7) [00000000]
Bit(s)	SCOM			Dial: Description
0:7	RWX			RX_PSI_VREF: VREF SETTING (0-7). Step size is about Vio*5/1100.. DMB
8:11	RO			constant=0b0000
12	RWX			RX_PSI_TERM_TEST_MODE: Termination Segment Test mode. MBS 0b0 = Mission mode enable 0b1 = Termination Segment Test Mode Dial enums: NORMAL=>0b0 TERM_TEST=>0b1
13:14	RO			constant=0b00 Dial enums: NORMAL=>0b0 TERM_TEST=>0b1
15:19	RWX			RX_PSI_TERM_MODE_ENC: Slice enable for pfet. fet pairs for termination mode. Bits 0:3 determine how many 1pt2kohm pairs to enable, out of 14. Bit 4 enables a half-strength 2.4kohm pfet. fet pair, and also controls whether that pair is enabled in test mode.. MBS
20:22	RWX			RX_PSI_PEAK: PSI RX peaking control
23	RO			constant=0b0
24:31	RWX			RX_PSI_MODE_SPARE: Spares. TBD. DMB

RX Status Reg
Addr:	0000000001011022 (SCOM)
Name:	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.RX_PSI_STATUS
Constant(s):	PU_RX_PSI_STATUS
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.RX_PSI_PATTERN_CHECK_PASS_RO(0) [0]
	1	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.RX_PSI_PATTERN_CHECK_FAIL_RO(0) [0]
	2	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.RX_PSI_NO_PATTERN_FOUND_RO(0) [0]
	4:7	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_RX_PSI_LD_UNLD_DLY.L.L.LATC.L2(0:3) [0000]
	8	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_RX_PSI_OVER_OR_UNDERRUN_ERR.L.L.LATC.L2(0) [0]
	9	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_RX_PSI_STATUS_CLEAR.L.L.LATC.L2(0) [0]
	10:15	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_RX_PSI_STATUS_SPARE.L.L.LATC.L2(0:5) [000000]
Bit(s)	SCOM			Dial: Description
0	ROX			rx_psi_pattern_check_pass_ro_signal
1	ROX			rx_psi_pattern_check_fail_ro_signal
2	ROX			rx_psi_no_pattern_found_ro_signal
3	RO			constant=0b0
4:7	RWX			RX_PSI_LD_UNLD_DLY: Current PSI load to unload delay. TBD. DMB
8	RWX			RX_PSI_OVER_OR_UNDERRUN_ERR: FIFO Overrun or Underrun Error. TBD. DMB
9	RWX			RX_PSI_STATUS_CLEAR: Clears Pattern check status. DMB
10:15	RWX			RX_PSI_STATUS_SPARE: Spares. TBD. DMB
16:31	RO			constant=0b0000000000000000

TX Cntl Reg
Addr:	0000000001011030 (SCOM)
Name:	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.TX_PSI_CNTL
Constant(s):	PU_TX_PSI_CNTL
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.TX_PSI_IORESET_WO_PULSE_SLOW_SIGNAL(0) [0]
	1	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_TX_PSI_DRV_PATTERN_EN.L.L.LATC.L2(0) [0]
	2:3	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_TX_PSI_PATTERN_SEL.L.L.LATC.L2(0:1) [00]
	4:5	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_TX_PSI_CLK_QUIESCE_P.L.L.LATC.L2(0:1) [00]
	6:7	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_TX_PSI_CLK_QUIESCE_N.L.L.LATC.L2(0:1) [00]
	8:9	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_TX_PSI_LANE_QUIESCE.L.L.LATC.L2(0:1) [00]
	10	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_TX_PSI_CLK_INVERT.L.L.LATC.L2(0) [0]
	11	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_TX_PSI_LANE_INVERT.L.L.LATC.L2(0) [0]
	12	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_TX_PSI_PDWN.L.L.LATC.L2(0) [0]
	13	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_TX_PSI_BIST_EN.L.L.LATC.L2(0) [0]
	24:31	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_TX_PSI_CNTL_SPARE.L.L.LATC.L2(0:7) [00000000]
Bit(s)	SCOM			Dial: Description
0	NCX			tx_psi_ioreset_wo_pulse_slow_signal
1	RWX			TX_PSI_DRV_PATTERN_EN: Enables the drive pattern to be driven.. DMB 0b0 = No pattern driven 0b1 = Drive pattern Dial enums: DISABLED=>0b0 ENABLED=>0b1
2:3	RWX			TX_PSI_PATTERN_SEL: TX pattern select. DMB 0b00 = ei4 busy patt A 0b01 = ei4 busy patt B 0b10 = 16 bit legacy 0b11 = IE3 Busy IAP PAttern Dial enums: EI4A=>0b00 EI4B=>0b01 LEGACY16=>0b10 EI3BUSY=>0b11
4:5	RWX			TX_PSI_CLK_QUIESCE_P: Used to force the output of the CLK P lane to a particular value.. DMB 0b00 = Functional CLK (default) 0b01 = Quiesce CLK to a Static 0 value 0b10 = Quiesce CLK to a Static 1 value 0b11 = Tri-State CLK Output Dial enums: FUNCTIONAL=>0b00 QUIESCE_TO_0=>0b01 QUIESCE_TO_1=>0b10 QUIESCE_TO_Z=>0b11
6:7	RWX			TX_PSI_CLK_QUIESCE_N: Used to force the output of the CLK N lane to a particular value.. DMB 0b00 = Functional CLK (default) 0b01 = Quiesce CLK to a Static 0 value 0b10 = Quiesce CLK to a Static 1 value 0b11 = Tri-State CLK Output Dial enums: FUNCTIONAL=>0b00 QUIESCE_TO_0=>0b01 QUIESCE_TO_1=>0b10 QUIESCE_TO_Z=>0b11
8:9	RWX			TX_PSI_LANE_QUIESCE: Used to force the output of the data lane to a particular value.. DMB 0b00 = Functional Data (default) 0b01 = Quiesce Lane to a Static 0 value 0b10 = Quiesce Lane to a Static 1 value 0b11 = Tri-State Lane Output Dial enums: FUNCTIONAL=>0b00 QUIESCE_TO_0=>0b01 QUIESCE_TO_1=>0b10 QUIESCE_TO_Z=>0b11
10	RWX			TX_PSI_CLK_INVERT: Used to invert the polarity of the CLK.. DMB 0b0 = Normal CLK Polarity (default) 0b1 = CLK Inverted Dial enums: NORMAL=>0b0 INVERTED=>0b1
11	RWX			TX_PSI_LANE_INVERT: Used to invert the polarity of the data lane.. DMB 0b0 = Normal Data Lane Polarity (default) 0b1 = Data Lane Inverted Dial enums: NORMAL=>0b0 INVERTED=>0b1
12	RWX			TX_PSI_PDWN: Used to power down the PSI TX clock and data path.. MBS 0b0 = Operational (default) 0b1 = Clock and data path are powered off Dial enums: NORMAL=>0b0 POWERDOWN=>0b1
13	RWX			TX_PSI_BIST_EN: Used to run TX BIST. . JGR 0b0 = TX BIST disabled 0b1 = TX BIST enabled Dial enums: DISABLED=>0b0 ENABLED=>0b1
14:23	RO			constant=0b0000000000 Dial enums: DISABLED=>0b0 ENABLED=>0b1
24:31	RWX			TX_PSI_CNTL_SPARE: Spares. TBD. DMB

TX Mode Reg
Addr:	0000000001011031 (SCOM)
Name:	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.TX_PSI_MODE
Constant(s):	PU_TX_PSI_MODE
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_TX_PSI_PC_TEST_MODE.L.L.LATC.L2(0) [0]
	4:7	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_TX_PSI_MAIN_SLICE_EN_ENC.L.L.LATC.L2(0:3) [0000]
	12:15	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_TX_PSI_PC_SLICE_EN_ENC.L.L.LATC.L2(0:3) [0000]
	16:19	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_TX_PSI_SLEWCTL.L.L.LATC.L2(0:3) [0000]
	24:25	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_TX_PSI_PVTNL_ENC.L.L.LATC.L2(0:1) [00]
	28:29	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_TX_PSI_PVTPL_ENC.L.L.LATC.L2(0:1) [00]
Bit(s)	SCOM			Dial: Description
0	RWX			TX_PSI_PC_TEST_MODE: Driver Segment Test mode. MBS 0b0 = Mission mode enable 0b1 = Driver Output Test Mode Dial enums: NORMAL=>0b0 SEG_TEST=>0b1
1:3	RO			constant=0b000 Dial enums: NORMAL=>0b0 SEG_TEST=>0b1
4:7	RWX			TX_PSI_MAIN_SLICE_EN_ENC: 240ohm main slice enable (binary code - 0000 is zero slices and 0110 is maximum slices). MBS
8:11	RO			constant=0b0000
12:15	RWX			TX_PSI_PC_SLICE_EN_ENC: 240ohm precompensation slice enable (binary code - 0000 is zero slices and 1110 is maximum slices). MBS
16:19	RWX			TX_PSI_SLEWCTL: Driver Slew Control. Bits 2 and 3 are reserved. MBS 0b0000 = 80ps nominal rate 0b0100 = 110ps nominal rate 0b1000 = 140ps nominal rate 0b1100 = 170ps nominal rate Dial enums: SLEW80PS=>0b0000 SLEW110PS=>0b0100 SLEW140PS=>0b1000 SLEW170PS=>0b1100
20:23	RO			constant=0b0000 Dial enums: SLEW80PS=>0b0000 SLEW110PS=>0b0100 SLEW140PS=>0b1000 SLEW170PS=>0b1100
24:25	RWX			TX_PSI_PVTNL_ENC: PVT nfet enables for all driver slices. MBS 0b00 = No pvt nfets enable 0b01 = Min pvt nfet enabled in parallel 0b10 = Max pvt nfet enabled in parallel 0b11 = Both pvt nfets enabled in parallel Dial enums: DISABLE=>0b00 2400OHMS=>0b01 1200OHMS=>0b10 800OHMS=>0b11
26:27	RO			constant=0b00 Dial enums: DISABLE=>0b00 2400OHMS=>0b01 1200OHMS=>0b10 800OHMS=>0b11
28:29	RWX			TX_PSI_PVTPL_ENC: PVT pfet enables for all driver slices. MBS 0b00 = No pvt pfets enable 0b01 = Min pvt pfet enabled in parallel 0b10 = Max pvt pfet enabled in parallel 0b11 = Both pvt pfets enabled in parallel Dial enums: DISABLE=>0b00 2400OHMS=>0b01 1200OHMS=>0b10 800OHMS=>0b11
30:31	RO			constant=0b00 Dial enums: DISABLE=>0b00 2400OHMS=>0b01 1200OHMS=>0b10 800OHMS=>0b11

TX Status Reg
Addr:	0000000001011032 (SCOM)
Name:	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.TX_PSI_STATUS
Constant(s):	PU_TX_PSI_STATUS
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_TX_PSI_STATUS_SPARE.L.L.LATC.L2(0:3) [0000]
	4:6	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.CFG_TX_PSI_BIST_ERROR.L.L.LATC.L2(0:2) [000]
	7:9	PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.TX_PSI_BIST_DONE_RO(0:2) [000]
Bit(s)	SCOM			Dial: Description
0:3	RWX			TX_PSI_STATUS_SPARE: TX Status Spared. TBD. DMB
4:6	RWX			TX_PSI_BIST_ERROR: Indicates a TXBIST clock side error occurred.. JGR 0b000 = No Errors 0b001 = An error has been found on clkn side 0b010 = An error has been found on clkp side 0b011 = Errors have been found on both clkp and clkn 0b100 = An error has been found in data path 0b101 = Errors have been found in data and clkn paths 0b110 = Errors have been found in data and clkp paths 0b111 = Errors have been found in data, clkp, and clkn paths Dial enums: NO_ERROR=>0b000 CLKN_ERROR=>0b001 CLKP_ERROR=>0b010 CLK_ERRORS=>0b011 DATA_ERROR=>0b100 DATA_N_ERROR=>0b101 DATA_P_ERROR=>0b110 ALL_ERRORS=>0b111
7:9	ROX			tx_psi_bist_done_ro_signal Dial enums: NO_ERROR=>0b000 CLKN_ERROR=>0b001 CLKP_ERROR=>0b010 CLK_ERRORS=>0b011 DATA_ERROR=>0b100 DATA_N_ERROR=>0b101 DATA_P_ERROR=>0b110 ALL_ERRORS=>0b111
10:31	RO			constant=0b0000000000000000000000 Dial enums: NO_ERROR=>0b000 CLKN_ERROR=>0b001 CLKP_ERROR=>0b010 CLK_ERRORS=>0b011 DATA_ERROR=>0b100 DATA_N_ERROR=>0b101 DATA_P_ERROR=>0b110 ALL_ERRORS=>0b111

Counter References
Addr:	0000000001020000 (SCOM)
Name:	TP.TPCHIP.TPC.ITR.FMU.FMU_MODE_REG
Constant(s):	PERV_1_FMU_MODE_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:23	TP.TPCHIP.TPC.ITR.FMU.FMU_MODEREG_LT_INST.LATC.L2(0:23) [000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:11	RW			TOD_CNTR_REF: To determine timeframe the oscillator pulses are counted. This value is compared to a 16 bit wide tod pulse counter.
12:15	RW			tod_cntr_ref
16	RW			unused1
17:19	RW			POWER_UP_CNTR_REF: To determine timeframe the fmu starts counting the oscillator pulses. This value is compared to a 3 bit wide tod pulse counter. Needs to be 0b010 in case time to wait must be >= 62.5 ns (16 MHZ)
20:23	RW			unused2

Osc Counter1 - Stressed Osc Counter for NBTI
Addr:	0000000001020001 (SCOM)
Name:	TP.TPCHIP.TPC.ITR.FMU.FMU_OSC_CNTR1_REG
Constant(s):	PERV_1_FMU_OSC_CNTR1_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1	TP.TPCHIP.TPC.ITR.FMU.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(1) [0]
	2	TP.TPCHIP.TPC.ITR.FMU.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(0) [0]
	3	TP.TPCHIP.TPC.ITR.FMU.RESULT_AVAILABLE_LT_INST.LATC.L2(0) [0]
	4:27	TP.TPCHIP.TPC.ITR.FMU.OSC_PULSE1_CNTR_LT_INST.LATC.L2(0:23) [000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RO			constant=0b0
1	ROX			fmu_pulse_gen_reg_err
2	ROX			fmu_modereg_p_err
3	ROX			RESULT_AVAILABLE: FMU result available
4:27	ROX			OSC_PULSE1_CNTR: Osc Counter1 - Stressed Osc Counter for NBTI

Counter References for Int.Pulse
Addr:	0000000001020001 (SCOM)
Name:	TP.TPCHIP.TPC.ITR.FMU.FMU_PULSE_GEN_REG
Constant(s):	PERV_1_FMU_PULSE_GEN_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:11	TP.TPCHIP.TPC.ITR.FMU.FMU_PULSE_GEN_REG_LT_INST.LATC.L2(0:11) [000000000000]
Bit(s)	SCOM			Dial: Description
0	WO			FMU_INT_PULSE_ENA: FMU internal Tod pulse generation enable
1	WO			unused3
2:11	WO			FMU_INT_PULSE_CNTR_REF: Reference value to compare against 10 Bit counter for FMU internal Tod pulse generation

Osc Counter2 - Reference Osc Counter for NBTI
Addr:	0000000001020002 (SCOM)
Name:	TP.TPCHIP.TPC.ITR.FMU.FMU_OSC_CNTR2_REG
Constant(s):	PERV_1_FMU_OSC_CNTR2_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1	TP.TPCHIP.TPC.ITR.FMU.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(1) [0]
	2	TP.TPCHIP.TPC.ITR.FMU.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(0) [0]
	3	TP.TPCHIP.TPC.ITR.FMU.RESULT_AVAILABLE_LT_INST.LATC.L2(0) [0]
	4:27	TP.TPCHIP.TPC.ITR.FMU.OSC_PULSE2_CNTR_LT_INST.LATC.L2(0:23) [000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RO			constant=0b0
1	ROX			fmu_pulse_gen_reg_err
2	ROX			fmu_modereg_p_err
3	ROX			RESULT_AVAILABLE: FMU result available
4:27	ROX			OSC_PULSE2_CNTR: Osc Counter2 - Stressed Osc Counter for NBTI

Force Operations
Addr:	0000000001020003 (SCOM)
Name:	TP.TPCHIP.TPC.ITR.FMU.FMU_FORCE_OP_REG
Constant(s):	PERV_1_FMU_FORCE_OP_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1	TP.TPCHIP.TPC.ITR.FMU.F_RESET [X]
Bit(s)	SCOM			Dial: Description
0	WOX			force_measure
1	WOX			force_fmu_sm_reset

KVREF data register
Addr:	0000000001020004 (SCOM)
Name:	TP.TPCHIP.TPC.ITR.FMU.FMU_KVREF_DATAREG
Constant(s):	PERV_1_FMU_KVREF_DATAREG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.TPC.ITR.FMU.FMU_KVREF_DATAREG_LT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	ROX			fmu_kvref_datareg

KVREF tune data
Addr:	0000000001020005 (SCOM)
Name:	TP.TPCHIP.TPC.ITR.FMU.KVREF_TUNE_DATA
Constant(s):	PERV_1_KVREF_TUNE_DATA
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:11	TP.TPCHIP.TPC.ITR.FMU.FMU_KVREF_TUNEDATA_LT_INST.LATC.L2(0:11) [000000000000]
Bit(s)	SCOM			Dial: Description
0:11	ROX			fmu_kvref_tune_data

VMEAS RESULT register
Addr:	0000000001020006 (SCOM)
Name:	TP.TPCHIP.TPC.ITR.FMU.VMEAS_RESULT_REG
Constant(s):	PERV_1_VMEAS_RESULT_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:9	TP.TPCHIP.TPC.ITR.FMU.VMEAS_TP_RESULT_LT_INST.LATC.L2(0:9) [0000000000]
Bit(s)	SCOM			Dial: Description
0:9	ROX			VMEAS_RESULT

kvref and vmeas mode register
Addr:	0000000001020007 (SCOM)
Name:	TP.TPCHIP.TPC.ITR.FMU.KVREF_AND_VMEAS_MODE_STATUS_REG
Constant(s):	PERV_1_KVREF_AND_VMEAS_MODE_STATUS_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPCHIP.TPC.ITR.FMU.FMU_KVREF_VMEAS_MODEREG_LT_INST.LATC.L2(0:2) [000]
	8	TP.TPCHIP.TPC.ITR.FMU.FMU_MEASURE_VMEAS_LT_INST.LATC.L2(0) [0]
	9:10	TP.TPCHIP.TPC.ITR.FMU.FMU_VMEAS_MIN_MAX_MODE_LT_INST.LATC.L2(0:1) [00]
	16	TP.TPCHIP.TPC.ITR.FMU.KVREF_CAL_DONE_LT_INST.LATC.L2(0) [0]
	17:18	TP.TPCHIP.TPC.ITR.FMU.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(2:3) [00]
	19	TP.TPCHIP.TPC.ITR.FMU.VMEAS_RESULT_VALID_LT_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	RWX			KVREF_START_CAL
1	RW			KVREF_DATA_SEL
2	RW			KVREF_BYPASS
3:7	RO			constant=0b00000
8	RWX			VMEAS_MEASURE
9	RW			VMEAS_MAX_MODE
10	RW			VMEAS_MIN_MODE
11:15	RO			constant=0b00000
16	ROX			KVREF_CAL_DONE
17	ROX			KVREF_TIMEOUT
18	ROX			VMEAS_TIMEOUT
19	ROX			VMEAS_RESULT_VALID

vmeas max result
Addr:	0000000001020008 (SCOM)
Name:	TP.TPCHIP.TPC.ITR.FMU.FMU_VMEAS_MAX_RESULT
Constant(s):	PERV_1_FMU_VMEAS_MAX_RESULT
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:9	TP.TPCHIP.TPC.ITR.FMU.VMEAS_MAX_RESULT_LT_INST.LATC.L2(0:9) [0000000000]
Bit(s)	SCOM			Dial: Description
0:9	ROX			vmeas_max_result

vmeas min result
Addr:	0000000001020009 (SCOM)
Name:	TP.TPCHIP.TPC.ITR.FMU.FMU_VMEAS_MIN_RESULT
Constant(s):	PERV_1_FMU_VMEAS_MIN_RESULT
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:9	TP.TPCHIP.TPC.ITR.FMU.VMEAS_MIN_RESULT_LT_INST.LATC.L2(0:9) [0000000000]
Bit(s)	SCOM			Dial: Description
0:9	ROX			vmeas_min_result

configuration of CC counters
Addr:	0000000001030000 (SCOM)
Name:	TP.TPCHIP.TPC.SYNC_CONFIG
Constant(s):	PERV_1_SYNC_CONFIG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:23	TP.TPCHIP.TPC.EPS.CC.PHASE_SYNC.SYNC_CONFIG_Q_INST.LATC.L2(0:23) [000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:3	RW			SYNC_PULSE_DELAY: Delay incoming sync pulse. Default are 8 latches incl. Async. 0000=8 , 0001=2(ungated), 0010=3, 0011=4, 0100=5, 0101=6, 0110=7, 0111=8 cycles, 1000=9, 1001=10, 1010=11, 1011=12, 1100=13, 1101=14, 1110=15, 1111=16 delay of the reset of the phase counter
4	RW			LISTEN_TO_SYNC_PULSE_DIS: disable phase counter synchronization by sync_pulse signal (default is enabled) ATTENTION: when ENABLE listen_to_sync, chiplet gets corrupted for 200 cycles
5	RW			SYNC_PULSE_INPUT_SEL: default is 0, when set to 1, the alternative input of the sync_pulse will be used ATTENTION: when toggle the input select, chiplet gets corrupted for 200 cycles
6	RW			USE_SYNC_FOR_SCAN: if set, use opcg initial alignment for scan requests
7	RW			CLEAR_CHIPLET_IS_ALIGNED: This bit will clear the chiplet_is_aligned bit - see cplt_stat register
8	RW			PCB_NOT_BLOCKED_BY_CLKCMD: PCB will not waiting for Clock Start/Stop Commands
9	RW			DISABLE_PCB_ITR: disable interrupt generation within CC - interrupt sent on each hld event
10	RW			CONT_SCAN_DISABLE: disable continues scan feature if that is set, you need to check for OPCG_DONE after each cont_scan request
11	RW			SYNC_PULSE_OUT_DIS: disable sync_pulse output when set to 1, master chiplet will not sending sync pulses to slave chiplets anymore
12	RW			REGION_PGOOD_OVERRIDE: Default is 0: When set to 1, region_pgood gets ignored. Allows Clock Start of Partial BAD regions
13	RW			CONT_SCAN_SHORT_WAIT: when 1, it shorts the delay between two scans. zThemis missed that. P10 need to set this bit to get faster scan performance
14	RW			PCIE32_MODE: P10 DD2: 0=DD1 default mode- 48 mode for all chiplets but PCIE, 1=DD2 Phase Counter 32 mode - only in PCIE chiplet allowed
15	RW			PHASE_COUNTER_ON_CLKCHANGE_EN: Enable Phase Counter capture on clk change or runn or xstop
16:23	RWX			PHASE_COUNTER_ON_CLKCHANGE: Capture value of phase counter on Clock Change or XSTOP

OPCG ALIGN
Addr:	0000000001030001 (SCOM)
Name:	TP.TPCHIP.TPC.OPCG_ALIGN
Constant(s):	PERV_1_OPCG_ALIGN
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.TPC.EPS.CC.OPCG.OPCG_ALIGN_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:3	RW			INOP_ALIGN: INOP phase alignment (0: none, 1: 2:1, 2: 3:1, 3: 4:1, 4: 6:1, 5: 8:1, 6: 12:1, 7: 16:1, 8: 24:1, 9-15: max=144:1 )
4:7	RW			SNOP_ALIGN: SNOP phase alignment (0: none, 1: 2:1, 2: 3:1, 3: 4:1, 4: 6:1, 5: 8:1, 6: 12:1, 7: 16:1, 8: 24:1, 9-15: max=144:1 )
8:11	RW			ENOP_ALIGN: ENOP phase alignment (0: none, 1: 2:1, 2: 3:1, 3: 4:1, 4: 6:1, 5: 8:1, 6: 12:1, 7: 16:1, 8: 24:1, 9-15: max=144:1 )
12:19	RW			INOP_WAIT: INOP cycle delay (0-255)
20:31	RW			SNOP_WAIT: SNOP cycle delay (0-4095)
32:39	RW			ENOP_WAIT: ENOP cycle delay (0-255)
40	RW			INOP_FORCE_SG: INOP: Set SG high during INOP
41	RW			SNOP_FORCE_SG: SNOP: Set SG high during SNOP
42	RW			ENOP_FORCE_SG: ENOP: Set SG high during ENOP ( including LOOP phase)
43	RW			NO_WAIT_ON_CLK_CMD: 0: A clock change request will first wait the OPCG_WAIT cycles. 1: A clock change request will not wait, when not in flush
44:45	RW			ALIGN_SOURCE_SELECT: 0: use inopa setting from opcg_reg0, 1: use rising edge of sync pulse, 2: use unit0_sync_lvl to align (for AVP - refresh0 ) 3: use unit1_sync_lvl to align (for AVP - refresh1)
46	RW			UNUSED46: unused
47:51	RW			SCAN_RATIO: scan_ratio (n=0-15: (n+1):1, 16: 24:1, 17: 32:1, 18: 48:1, 19: 64:1, 20: 128:1) - Default 4:1=00011
52:63	RW			OPCG_WAIT_CYCLES: old PAD value, delay at the begin and end of the OPCG run, to allow DC signals to be there at the right time (0 4095), needs to be higher than plat depth ! Default=0x020

OPCG Control Register 0
Addr:	0000000001030002 (SCOM)
Name:	TP.TPCHIP.TPC.OPCG_REG0
Constant(s):	PERV_1_OPCG_REG0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.TPC.EPS.CC.OPCG.OPCG_REG0_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			RUNN_MODE: 0=BIST-mode used for LBIST / 1=RUNN-mode used for ABIST/IOBIST
1	RWX			OPCG_GO: opcg go (start OPCG) - bit will b cleared when OPCG is done - poll for opcg_done in cplt_start reg
2	RWX			RUN_SCAN0: run scan0 (will override all BIST mode settings but the scan_ratio) - will start a scan0 run, bit gets cleared when OPCG is done - poll for opcg_done in cplt_start reg
3	RW			SCAN0_MODE: set PRPGs in scan0_mode but do not run automatic scan0 sequence
4	RWX			OPCG_IN_SLAVE_MODE: when selected, OPCG will wait for Master chiplet to get started. When Keep_MS_Mode is 0, SLAVE_MODE will be cleared after incoming trigger.
5	RWX			OPCG_IN_MASTER_MODE: when selected, OPCG will send out trigger to all Slave chiplets - When Keep_MS_MODE=0, MASTER_MODE gets cleared after sending out one Master trigger
6	RW			KEEP_MS_MODE: when set to 1, OPCG in M/S mode bits will not be cleared after one incoming OPCG trigger. Default is clear M/S mode bits
7	RW			TRIGGER_OPCG_ON_UNIT0_SYNC_LVL: Unit pin used for AVP can trigger OPCG (unit0_sync_lvl)
8	RW			TRIGGER_OPCG_ON_UNIT1_SYNC_LVL: Unit pin used for AVP can trigger OPCG (unit1_sync_lvl)
9:10	RW			UNUSED910: unused
11	RW			RUN_OPCG_ON_UPDATE_DR: start opcg engine when scan updated (update_dr) received (set pulse) Cronus requires this bit=1 for a setpulse WRITE
12	RW			RUN_OPCG_ON_CAPTURE_DR: start opcg engine when scan updated (capture_dr) received (set pulse) Cronus requires this bit=1 for a setpulse READ
13	RW			STOP_RUNN_ON_XSTOP: runn-mode: stop run-n on xstop
14	RW			OPCG_STARTS_BIST: runn-mode: OPCG engine controls start_bist for ABIST or IOBIST (see BIST register)
15	RW			RUNN_HLD_DLY_EN: runn-mode: Enable of the HLD Delay function - programming in OPCG_CAPT1,2,3 to allow staggered stop of Cores during Cache-Contained mode
16:20	RW			UNUSED1620: unused
21:63	RWX			LOOP_COUNT: Loop counter for LBIST and RUNN - write: target value - read: current counter value - will count from 0 to target value

OPCG Control Register 1
Addr:	0000000001030003 (SCOM)
Name:	TP.TPCHIP.TPC.OPCG_REG1
Constant(s):	PERV_1_OPCG_REG1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.TPC.EPS.CC.OPCG.OPCG_REG1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:11	RW			SCAN_COUNT: BIST mode: Channel scan count (s = 0-4095) runn-mode: start_bist match value(0:11)
12:23	RW			MISR_A_VAL: BIST mode: a value for MISR aperture, runn-mode: start_bist match value(12:23)
24:35	RW			MISR_B_VAL: BIST mode: b value for MISR aperture, runn-mode: start_bist match value(24:35)
36:47	RW			MISR_INIT_WAIT: BIST mode: delay MISR aperture, MISRs get active after this number of loops
48	RW			UNUSED48: Unused to suppress the last RUNN clock please look at CLK_REGION register bit 54
49	RW			SCAN_CLK_USE_EVEN: Generate scan clock in even cycle instead of odd. Default is 0 = odd for scan
50	RW			DISABLE_FCE_DURING_FILL: Scan0 and LBIST - disable FCE during NSL Fill - LBIST_COMBINED=1
51	RW			UNUSED51: unused
52	RW			RTIM_THOLD_FORCE: force rtim_thold low when not in test_dc mode (must be 0 at all time)
53	RW			DISABLE_ARY_CLK_DURING_FILL: LBIST and SCAN0: prevent fire of ARY HLD during NSL-fill - LBIST_COMBINED=1
54	RW			SG_HIGH_DURING_FILL: LBIST and SCAN0: Hold SG high during NSL-fill
55:56	RW			LBIST_SKITTER_CTL: BIST mode: 00: enable skitter during lbist_ip, 01: enable skitter when misr_active - see misr_init_wait 10: skitter OPCG_GO mode - falling edge=start, rising edge=stop 11 - unused
57	RW			MISR_MODE: BIST mode: MISR aperture mode (0: a-1 to b-1, 1: start to a and b to end)
58	RW			INFINITE_MODE: infinite mode - RUNN and LBIST will run forever and ignore the loop count
59:63	RW			NSL_FILL_COUNT: BIST mode: NSL-fill count (0-31)

OPCG Control Register 2
Addr:	0000000001030004 (SCOM)
Name:	TP.TPCHIP.TPC.OPCG_REG2
Constant(s):	PERV_1_OPCG_REG2
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.TPC.EPS.CC.OPCG.OPCG_REG2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RWX			OPCG_GO2: opcg go for broadcast sequences (start sequence)
1:3	RW			PRPG_WEIGHTING: prpg_activate: 1/2, 1/4, 1/8, 1/16, 1/2, 3/4, 7/8, 15/16
4:15	RWX			PRPG_SEED: set to 0 for prpg always on, else seed
16:27	RW			PRPG_A_VAL: a value for PRPG aperture
28:39	RW			PRPG_B_VAL: b value for PRPG aperture
40	RW			PRPG_MODE: PRPG aperture mode (0: a-1 to b-1, 1: start to a and b to end)
41:47	RW			UNUSED41_47: unused
48:51	RW			SM_LBIST_CTRL_WEIGHT_SEL_PRIM: Stumpmux LBIST Control - weight select primary
52:55	RW			SM_LBIST_CTRL_WEIGHT_SEL_SEC_OR_APERTURE_MASK: Stumpmux LBIST Control - weight select secondary (when mode_select=0) or aperture_mask (when mode_select=1)
56	RW			SM_LBIST_CTRL_MODE_SELECT: Stumpmux LBIST Control - mode select - 0=secondary weight 1=aperture_mask
57	RW			SM_LBIST_CTRL_PRPG_HOLD_MODE: Stumpmux LBIST Control - PRPG hold mode
58	RW			SM_LBIST_CTRL_LOCAL_OVERRIDE: Stumpmux LBIST Control - Local Override
59	RW			SM_LBIST_CTRL_LOAD_APERTURE_VALUE: Stumpmux LBIST Control - Aperture Value
60:63	RW			SM_LBIST_CTRL_LOAD_APERTURE_SELECT: Stumpmux LBIST Control - Aperture Select

Scan Region and Type
Addr:	0000000001030005 (SCOM)
Name:	TP.TPCHIP.TPC.SCAN_REGION_TYPE
Constant(s):	PERV_1_SCAN_REGION_TYPE
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.TPC.EPS.CC.CLOCK_MUX.SYSTEM_FAST_INIT_Q_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.TPC.EPS.CC.CLOCK_MUX.PARALLEL_SCAN_Q_INST.LATC.L2(0) [0]
	2	TP.TPCHIP.TPC.EPS.CC.CLOCK_MUX.PARALLEL_SCAN_AND_NOTOR_Q_INST.LATC.L2(0) [0]
	3	TP.TPCHIP.TPC.EPS.CC.CCFG.SCAN_REGION_VITL_INST.CCFG_Q_INST.FSILAT.LATC.L2(0) [0]
	4:18	TP.TPCHIP.TPC.EPS.CC.CCFG.SCAN_REGION_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:14) [000000000000000]
	48:59	TP.TPCHIP.TPC.EPS.CC.CCFG.SCAN_TYPE_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:11) [000000000000]
Bit(s)	SCOM			Dial: Description
0	RWX			SYSTEM_FAST_INIT: Default is 0, when its set to 1, the MASK bits in the CMSK chain decide, which part will be scanned or scan0. MASK=1=scan0, MASK=0-part or scan chain
1	RWX			PARALLEL_SCAN: Enable Parallel Scan of several regions with the same data
2	RWX			PARALLEL_SCAN_AND_NOTOR: Default is 0, return data will be OR-ed. When set to 1, the return data will be AND-ed
3	RWX			SCAN_REGION_VITL: scan clock region vitl (Vital = Clock)
4	RWX			SCAN_REGION_PERV: scan clock region perv (Pervasive)
5	RWX			SCAN_REGION_UNIT1: scan clock region 1 - sbe
6	RWX			SCAN_REGION_UNIT2: scan clock region 2 - pib
7	RWX			SCAN_REGION_UNIT3: scan clock region 3 - occ
8	RWX			SCAN_REGION_UNIT4: scan clock region 4 - net
9	RWX			SCAN_REGION_UNIT5: scan clock region 5 - unused
10	RWX			SCAN_REGION_UNIT6: scan clock region 6 - psi
11	RWX			SCAN_REGION_UNIT7: scan clock region 7 - unused
12	RWX			SCAN_REGION_UNIT8: scan clock region 8 - dpllpau
13	RWX			SCAN_REGION_UNIT9: scan clock region 9 - dpllnest
14	RWX			SCAN_REGION_UNIT10: scan clock region 10 - pllperv
15	RWX			SCAN_REGION_UNIT11: scan clock region 11 - unused
16	RWX			SCAN_REGION_UNIT12: scan clock region 12 - unused
17	RWX			SCAN_REGION_UNIT13: scan clock region 13 - unused
18	RWX			SCAN_REGION_UNIT14: scan clock region 14 - unused
19:47	RO			constant=0b00000000000000000000000000000
48	RW			SCAN_TYPE_FUNC: scan chain func (functional)
49	RW			SCAN_TYPE_CFG: scan chain mode (boot config and debug config)
50	RW			SCAN_TYPE_CCFG_GPTR: scan chain ccfg / gptr (Pervasive: CC config, Others: GPTR)
51	RW			SCAN_TYPE_REGF: scan chain regf (register files)
52	RW			SCAN_TYPE_LBIST: scan chain lbst (LBIST)
53	RW			SCAN_TYPE_ABIST: scan chain abst (ABIST)
54	RW			SCAN_TYPE_REPR: scan chain repr (Array Repair)
55	RW			SCAN_TYPE_TIME: scan chain time (Array Timing)
56	RW			SCAN_TYPE_BNDY: scan chain bndy (Boundary IO's)
57	RW			SCAN_TYPE_FARR: scan chain farr (fast array unload)
58	RW			SCAN_TYPE_CMSK: scan chain cmsk (lbist channel mask)
59	RW			SCAN_TYPE_INEX: scan chain idex (c14 asic)
60:63	RO			constant=0b0000

start/stop of Clocks
Addr:	0000000001030006 (SCOM)
Name:	TP.TPCHIP.TPC.CLK_REGION
Constant(s):	PERV_1_CLK_REGION
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.TPC.EPS.CC.CLOCK_MUX.CLOCK_CMD_Q_INST.LATC.L2(0:3) [0000]
	4:18	TP.TPCHIP.TPC.EPS.CC.CCFG.CLOCK_REGION_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:14) [000000000000000]
	48:50	TP.TPCHIP.TPC.EPS.CC.CCFG.CLOCK_TYPE_INST.CCFG_Q_INST.FSILAT.LATC.L2(0:2) [000]
	52	TP.TPCHIP.TPC.EPS.CC.CLOCK_MUX.CLOCK_PULSE_USE_EVEN_Q_INST.LATC.L2(0) [0]
	53	TP.TPCHIP.TPC.EPS.CC.CLOCK_MUX.CLOCK_START_RUNN_SUPPR_FIRST_CLK_Q_INST.LATC.L2(0) [0]
	54	TP.TPCHIP.TPC.EPS.CC.CLOCK_MUX.CLOCK_STOP_RUNN_SUPPR_LAST_CLK_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0:1	RWX			CLOCK_CMD: command for clock control: 00 NOP 01 START 10 STOP 11 PULSE (one pulse)
2	RWX			SLAVE_MODE: when selected, Clock Command will wait for Master chiplet to get started. Bit gets cleared after incoming Slave trigger and Keep_MS_Mode_after_trigger is set to 0
3	RWX			MASTER_MODE: when selected, Clock Command will send out trigger to all Slave chiplets - Bit gets cleared after sending out one Master trigger and Keep_MS_Mode_after_trigger is set to 0
4	RWX			CLOCK_REGION_PERV: for clock region perv (Pervasive)
5	RWX			CLOCK_REGION_UNIT1: for clock region 1 - sbe
6	RWX			CLOCK_REGION_UNIT2: for clock region 2 - pib
7	RWX			CLOCK_REGION_UNIT3: for clock region 3 - occ
8	RWX			CLOCK_REGION_UNIT4: for clock region 4 - net
9	RWX			CLOCK_REGION_UNIT5: for clock region 5 - unused
10	RWX			CLOCK_REGION_UNIT6: for clock region 6 - psi
11	RWX			CLOCK_REGION_UNIT7: for clock region 7 - unused
12	RWX			CLOCK_REGION_UNIT8: for clock region 8 - dpllpau
13	RWX			CLOCK_REGION_UNIT9: for clock region 9 - dpllnest
14	RWX			CLOCK_REGION_UNIT10: for clock region 10 - pllperv
15	RWX			CLOCK_REGION_UNIT11: for clock region 11 - unused
16	RWX			CLOCK_REGION_UNIT12: for clock region 12 - unused
17	RWX			CLOCK_REGION_UNIT13: for clock region 13 - unused
18	RWX			CLOCK_REGION_UNIT14: for clock region 14 - unused
19:47	RO			constant=0b00000000000000000000000000000
48	RWX			SEL_THOLD_SL: select sl tholds
49	RWX			SEL_THOLD_NSL: select nsl tholds
50	RWX			SEL_THOLD_ARY: select array thold
51	RO			constant=0b0
52	RW			CLOCK_PULSE_USE_EVEN: For dual mesh support: default for pulse is ODD phase, when this bit is set, pulse will by applied on EVEN phase
53	RW			CLOCK_START_RUNN_SUPPR_FIRST_CLK: For dual mesh support or 2:1 CC : A clock start or a RUNN will skip the first clock (EVEN) and starts with the ODD clock.
54	RW			CLOCK_STOP_RUNN_SUPPR_LAST_CLK: For dual mesh support or 2:1 CC : A clock stop or a RUNN will skip the last clock (ODD) and stops earlier with an EVEN clock.
55:63	RO			constant=0b000000000

Clocks running sl
Addr:	0000000001030008 (SCOM)
Name:	TP.TPCHIP.TPC.CLOCK_STAT_SL
Constant(s):	PERV_1_CLOCK_STAT_SL
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	4:18	TP.TPCHIP.TPC.EPS.CC.CLOCK_MUX.CLOCK_STATUS_SL_Q_INST.LATC.L2(0:14) [000000000000000]
Bit(s)	SCOM			Dial: Description
0:3	RO			constant=0b1111
4	ROX			CLOCK_STATUS_PERV_SL: status of perv sl hld 0=run, 1=stop
5	ROX			CLOCK_STATUS_UNIT1_SL: status of region 1 - sbe sl hld 0=run, 1=stop
6	ROX			CLOCK_STATUS_UNIT2_SL: status of region 2 - pib sl hld 0=run, 1=stop
7	ROX			CLOCK_STATUS_UNIT3_SL: status of region 3 - occ sl hld 0=run, 1=stop
8	ROX			CLOCK_STATUS_UNIT4_SL: status of region 4 - net sl hld 0=run, 1=stop
9	ROX			CLOCK_STATUS_UNIT5_SL: status of region 5 - unused sl hld 0=run, 1=stop
10	ROX			CLOCK_STATUS_UNIT6_SL: status of region 6 - psi sl hld 0=run, 1=stop
11	ROX			CLOCK_STATUS_UNIT7_SL: status of region 7 - unused sl hld 0=run, 1=stop
12	ROX			CLOCK_STATUS_UNIT8_SL: status of region 8 - dpllpau sl hld 0=run, 1=stop
13	ROX			CLOCK_STATUS_UNIT9_SL: status of region 9 - dpllnest sl hld 0=run, 1=stop
14	ROX			CLOCK_STATUS_UNIT10_SL: status of region 10 - pllperv sl hld 0=run, 1=stop
15	ROX			CLOCK_STATUS_UNIT11_SL: status of region 11 - unused sl hld 0=run, 1=stop
16	ROX			CLOCK_STATUS_UNIT12_SL: status of region 12 - unused sl hld 0=run, 1=stop
17	ROX			CLOCK_STATUS_UNIT13_SL: status of region 13 - unused sl hld 0=run, 1=stop
18	ROX			CLOCK_STATUS_UNIT14_SL: status of region 14 - unused sl hld 0=run, 1=stop
19:63	RO			constant=0b111111111111111111111111111111111111111111111

Clocks running nsl
Addr:	0000000001030009 (SCOM)
Name:	TP.TPCHIP.TPC.CLOCK_STAT_NSL
Constant(s):	PERV_1_CLOCK_STAT_NSL
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	4:18	TP.TPCHIP.TPC.EPS.CC.CLOCK_MUX.CLOCK_STATUS_NSL_Q_INST.LATC.L2(0:14) [000000000000000]
Bit(s)	SCOM			Dial: Description
0:3	RO			constant=0b1111
4	ROX			CLOCK_STATUS_PERV_NSL: status of perv nsl hld 0=run, 1=stop
5	ROX			CLOCK_STATUS_UNIT1_NSL: status of region 1 - sbe nsl hld 0=run, 1=stop
6	ROX			CLOCK_STATUS_UNIT2_NSL: status of region 2 - pib nsl hld 0=run, 1=stop
7	ROX			CLOCK_STATUS_UNIT3_NSL: status of region 3 - occ nsl hld 0=run, 1=stop
8	ROX			CLOCK_STATUS_UNIT4_NSL: status of region 4 - net nsl hld 0=run, 1=stop
9	ROX			CLOCK_STATUS_UNIT5_NSL: status of region 5 - unused nsl hld 0=run, 1=stop
10	ROX			CLOCK_STATUS_UNIT6_NSL: status of region 6 - psi nsl hld 0=run, 1=stop
11	ROX			CLOCK_STATUS_UNIT7_NSL: status of region 7 - unused nsl hld 0=run, 1=stop
12	ROX			CLOCK_STATUS_UNIT8_NSL: status of region 8 - dpllpau nsl hld 0=run, 1=stop
13	ROX			CLOCK_STATUS_UNIT9_NSL: status of region 9 - dpllnest nsl hld 0=run, 1=stop
14	ROX			CLOCK_STATUS_UNIT10_NSL: status of region 10 - pllperv nsl hld 0=run, 1=stop
15	ROX			CLOCK_STATUS_UNIT11_NSL: status of region 11 - unused nsl hld 0=run, 1=stop
16	ROX			CLOCK_STATUS_UNIT12_NSL: status of region 12 - unused nsl hld 0=run, 1=stop
17	ROX			CLOCK_STATUS_UNIT13_NSL: status of region 13 - unused nsl hld 0=run, 1=stop
18	ROX			CLOCK_STATUS_UNIT14_NSL: status of region 14 - unused nsl hld 0=run, 1=stop
19:63	RO			constant=0b111111111111111111111111111111111111111111111

Clocks running ary
Addr:	000000000103000A (SCOM)
Name:	TP.TPCHIP.TPC.CLOCK_STAT_ARY
Constant(s):	PERV_1_CLOCK_STAT_ARY
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	4:18	TP.TPCHIP.TPC.EPS.CC.CLOCK_MUX.CLOCK_STATUS_ARY_Q_INST.LATC.L2(0:14) [000000000000000]
Bit(s)	SCOM			Dial: Description
0:3	RO			constant=0b1111
4	ROX			CLOCK_STATUS_PERV_ARY: status of perv ary hld 0=run, 1=stop
5	ROX			CLOCK_STATUS_UNIT1_ARY: status of region 1 - sbe ary hld 0=run, 1=stop
6	ROX			CLOCK_STATUS_UNIT2_ARY: status of region 2 - pib ary hld 0=run, 1=stop
7	ROX			CLOCK_STATUS_UNIT3_ARY: status of region 3 - occ ary hld 0=run, 1=stop
8	ROX			CLOCK_STATUS_UNIT4_ARY: status of region 4 - net ary hld 0=run, 1=stop
9	ROX			CLOCK_STATUS_UNIT5_ARY: status of region 5 - unused ary hld 0=run, 1=stop
10	ROX			CLOCK_STATUS_UNIT6_ARY: status of region 6 - psi ary hld 0=run, 1=stop
11	ROX			CLOCK_STATUS_UNIT7_ARY: status of region 7 - unused ary hld 0=run, 1=stop
12	ROX			CLOCK_STATUS_UNIT8_ARY: status of region 8 - dpllpau ary hld 0=run, 1=stop
13	ROX			CLOCK_STATUS_UNIT9_ARY: status of region 9 - dpllnest ary hld 0=run, 1=stop
14	ROX			CLOCK_STATUS_UNIT10_ARY: status of region 10 - pllperv ary hld 0=run, 1=stop
15	ROX			CLOCK_STATUS_UNIT11_ARY: status of region 11 - unused ary hld 0=run, 1=stop
16	ROX			CLOCK_STATUS_UNIT12_ARY: status of region 12 - unused ary hld 0=run, 1=stop
17	ROX			CLOCK_STATUS_UNIT13_ARY: status of region 13 - unused ary hld 0=run, 1=stop
18	ROX			CLOCK_STATUS_UNIT14_ARY: status of region 14 - unused ary hld 0=run, 1=stop
19:63	RO			constant=0b111111111111111111111111111111111111111111111

ABIST and IOBIST per region
Addr:	000000000103000B (SCOM)
Name:	TP.TPCHIP.TPC.BIST
Constant(s):	PERV_1_BIST
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.TPC.EPS.CC.BIST.BIST_CONFIG_Q_INST.LATC.L2(0:3) [0000]
	4:18	TP.TPCHIP.TPC.EPS.CC.BIST.BIST_REGIONS_Q_INST.LATC.L2(0:14) [000000000000000]
	48	TP.TPCHIP.TPC.EPS.CC.BIST.BIST_SETUP_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	RW			TC_BIST_START_TEST_DC: keep this 0 during ABIST/IOBIST. It could be used to bypass the RUNN start. When this bit is set, the BIST_START_TEST will go high immediately without waiting for RUNN. BIST will start with the first hld clock cycle.
1	RW			TC_SRAM_ABIST_MODE_DC: select the ABIST engines for SRAMs
2	RW			UNUSED_BC2: unused
3	RW			TC_IOBIST_MODE_DC: select the IOBIST engines
4	RW			BIST_REGION_PERV: region perv: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run.
5	RW			BIST_REGION_UNIT1: region 1 - sbe: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run.
6	RW			BIST_REGION_UNIT2: region 2 - pib: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run.
7	RW			BIST_REGION_UNIT3: region 3 - occ: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run.
8	RW			BIST_REGION_UNIT4: region 4 - net: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run.
9	RW			BIST_REGION_UNIT5: region 5 - unused: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run.
10	RW			BIST_REGION_UNIT6: region 6 - psi: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run.
11	RW			BIST_REGION_UNIT7: region 7 - unused: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run.
12	RW			BIST_REGION_UNIT8: region 8 - dpllpau: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run.
13	RW			BIST_REGION_UNIT9: region 9 - dpllnest: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run.
14	RW			BIST_REGION_UNIT10: region 10 - pllperv: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run.
15	RW			BIST_REGION_UNIT11: region 11 - unused: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run.
16	RW			BIST_REGION_UNIT12: region 12 - unused: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run.
17	RW			BIST_REGION_UNIT13: region 13 - unused: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run.
18	RW			BIST_REGION_UNIT14: region 14 - unused: 1=BIST_START_TEST for this region will be triggered, 0=region take not part of the ABIST/IOBIST run.
19:47	RO			constant=0b00000000000000000000000000000
48	RW			BIST_STROBE_WINDOW_EN: Enable Strobe window only in TE=1 mode OPCGGO tester pin is enabling ABIST compare, once ABIST has been started. Special setup in ABIST engine is required. default is 0. System mode can not enable this feature
49:63	RO			constant=0b000000000000000

XSTOP per region
Addr:	000000000103000C (SCOM)
Name:	TP.TPCHIP.TPC.XSTOP1
Constant(s):	PERV_1_XSTOP1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.TPC.EPS.CC.XSTOP1.XSTOP_CONFIG_Q_INST.LATC.L2(0:3) [0000]
	4:18	TP.TPCHIP.TPC.EPS.CC.XSTOP1.XSTOP_REGIONS_Q_INST.LATC.L2(0:14) [000000000000000]
	48:59	TP.TPCHIP.TPC.EPS.CC.XSTOP1.XSTOP_WAITS_Q_INST.LATC.L2(0:11) [000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			XSTOP1_ENABLE: enable xstop to clockstop of selected regions, 0 = ignore chkstop, 1= stop on chkstop
1	RW			XSTOP1_WAIT_SNOPA: wait for SNOP align to stop clocks on checkstop
2	RW			XSTOP1_TRIGGER_OPCG_GO: trigger opcg on xstop instead of performing clockstop
3	RW			XSTOP1_WAIT_ALWAYS: when set to 1, xstop will wait independent from flush, default is no wait, when flush in not set
4	RW			XSTOP1_REGION_PERV: region perv: 1=region will be stopped, 0=region will keep running on xstop
5	RW			XSTOP1_REGION_UNIT1: region 1 - sbe: 1=region will be stopped, 0=region will keep running on xstop
6	RW			XSTOP1_REGION_UNIT2: region 2 - pib: 1=region will be stopped, 0=region will keep running on xstop
7	RW			XSTOP1_REGION_UNIT3: region 3 - occ: 1=region will be stopped, 0=region will keep running on xstop
8	RW			XSTOP1_REGION_UNIT4: region 4 - net: 1=region will be stopped, 0=region will keep running on xstop
9	RW			XSTOP1_REGION_UNIT5: region 5 - unused: 1=region will be stopped, 0=region will keep running on xstop
10	RW			XSTOP1_REGION_UNIT6: region 6 - psi: 1=region will be stopped, 0=region will keep running on xstop
11	RW			XSTOP1_REGION_UNIT7: region 7 - unused: 1=region will be stopped, 0=region will keep running on xstop
12	RW			XSTOP1_REGION_UNIT8: region 8 - dpllpau: 1=region will be stopped, 0=region will keep running on xstop
13	RW			XSTOP1_REGION_UNIT9: region 9 - dpllnest: 1=region will be stopped, 0=region will keep running on xstop
14	RW			XSTOP1_REGION_UNIT10: region 10 - pllperv: 1=region will be stopped, 0=region will keep running on xstop
15	RW			XSTOP1_REGION_UNIT11: region 11 - unused: 1=region will be stopped, 0=region will keep running on xstop
16	RW			XSTOP1_REGION_UNIT12: region 12 - unused: 1=region will be stopped, 0=region will keep running on xstop
17	RW			XSTOP1_REGION_UNIT13: region 13 - unused: 1=region will be stopped, 0=region will keep running on xstop
18	RW			XSTOP1_REGION_UNIT14: region 14 - unused: 1=region will be stopped, 0=region will keep running on xstop
19:47	RO			constant=0b00000000000000000000000000000
48:59	RW			XSTOP1_WAIT_CYCLES: Defines, how many cycle xstop will wait after dropping flush, before tholds get dropped. 0-4095 cycles possible
60:63	RO			constant=0b0000

XSTOP per region
Addr:	000000000103000D (SCOM)
Name:	TP.TPCHIP.TPC.XSTOP2
Constant(s):	PERV_1_XSTOP2
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.TPC.EPS.CC.XSTOP2.XSTOP_CONFIG_Q_INST.LATC.L2(0:3) [0000]
	4:18	TP.TPCHIP.TPC.EPS.CC.XSTOP2.XSTOP_REGIONS_Q_INST.LATC.L2(0:14) [000000000000000]
	48:59	TP.TPCHIP.TPC.EPS.CC.XSTOP2.XSTOP_WAITS_Q_INST.LATC.L2(0:11) [000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			XSTOP2_ENABLE: enable xstop to clockstop of select regions, 0 = ignore chkstop, 1= stop on chkstop
1	RW			XSTOP2_WAIT_SNOPA: wait for SNOP align to stop clocks on checkstop
2	RW			XSTOP2_TRIGGER_OPCG_GO: trigger opcg on xstop instead of performing clockstop
3	RW			XSTOP2_WAIT_ALWAYS: when set to 1, xstop will wait independent from flush, default is no wait, when flush in not set
4	RW			XSTOP2_REGION_PERV: region perv: 1=region will be stopped, 0=region will keep running on xstop
5	RW			XSTOP2_REGION_UNIT1: region 1 - sbe: 1=region will be stopped, 0=region will keep running on xstop
6	RW			XSTOP2_REGION_UNIT2: region 2 - pib: 1=region will be stopped, 0=region will keep running on xstop
7	RW			XSTOP2_REGION_UNIT3: region 3 - occ: 1=region will be stopped, 0=region will keep running on xstop
8	RW			XSTOP2_REGION_UNIT4: region 4 - net: 1=region will be stopped, 0=region will keep running on xstop
9	RW			XSTOP2_REGION_UNIT5: region 5 - unused: 1=region will be stopped, 0=region will keep running on xstop
10	RW			XSTOP2_REGION_UNIT6: region 6 - psi: 1=region will be stopped, 0=region will keep running on xstop
11	RW			XSTOP2_REGION_UNIT7: region 7 - unused: 1=region will be stopped, 0=region will keep running on xstop
12	RW			XSTOP2_REGION_UNIT8: region 8 - dpllpau: 1=region will be stopped, 0=region will keep running on xstop
13	RW			XSTOP2_REGION_UNIT9: region 9 - dpllnest: 1=region will be stopped, 0=region will keep running on xstop
14	RW			XSTOP2_REGION_UNIT10: region 10 - pllperv: 1=region will be stopped, 0=region will keep running on xstop
15	RW			XSTOP2_REGION_UNIT11: region 11 - unused: 1=region will be stopped, 0=region will keep running on xstop
16	RW			XSTOP2_REGION_UNIT12: region 12 - unused: 1=region will be stopped, 0=region will keep running on xstop
17	RW			XSTOP2_REGION_UNIT13: region 13 - unused: 1=region will be stopped, 0=region will keep running on xstop
18	RW			XSTOP2_REGION_UNIT14: region 14 - unused: 1=region will be stopped, 0=region will keep running on xstop
19:47	RO			constant=0b00000000000000000000000000000
48:59	RW			XSTOP2_WAIT_CYCLES: Defines, how many cycle xstop will wait after dropping flush, before tholds get dropped. 0-4095 cycles possible
60:63	RO			constant=0b0000

XSTOP per region
Addr:	000000000103000E (SCOM)
Name:	TP.TPCHIP.TPC.XSTOP3
Constant(s):	PERV_1_XSTOP3
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.TPC.EPS.CC.XSTOP3.XSTOP_CONFIG_Q_INST.LATC.L2(0:3) [0000]
	4:18	TP.TPCHIP.TPC.EPS.CC.XSTOP3.XSTOP_REGIONS_Q_INST.LATC.L2(0:14) [000000000000000]
	48:59	TP.TPCHIP.TPC.EPS.CC.XSTOP3.XSTOP_WAITS_Q_INST.LATC.L2(0:11) [000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			XSTOP3_ENABLE: enable xstop to clockstop of select regions, 0 = ignore chkstop, 1= stop on chkstop
1	RW			XSTOP3_WAIT_SNOPA: wait for SNOP align to stop clocks on checkstop
2	RW			XSTOP3_TRIGGER_OPCG_GO: trigger opcg on xstop instead of performing clockstop
3	RW			XSTOP3_WAIT_ALWAYS: when set to 1, xstop will wait independent from flush, default is no wait, when flush in not set
4	RW			XSTOP3_REGION_PERV: region perv: 1=region will be stopped, 0=region will keep running on xstop
5	RW			XSTOP3_REGION_UNIT1: region 1 - sbe: 1=region will be stopped, 0=region will keep running on xstop
6	RW			XSTOP3_REGION_UNIT2: region 2 - pib: 1=region will be stopped, 0=region will keep running on xstop
7	RW			XSTOP3_REGION_UNIT3: region 3 - occ: 1=region will be stopped, 0=region will keep running on xstop
8	RW			XSTOP3_REGION_UNIT4: region 4 - net: 1=region will be stopped, 0=region will keep running on xstop
9	RW			XSTOP3_REGION_UNIT5: region 5 - unused: 1=region will be stopped, 0=region will keep running on xstop
10	RW			XSTOP3_REGION_UNIT6: region 6 - psi: 1=region will be stopped, 0=region will keep running on xstop
11	RW			XSTOP3_REGION_UNIT7: region 7 - unused: 1=region will be stopped, 0=region will keep running on xstop
12	RW			XSTOP3_REGION_UNIT8: region 8 - dpllpau: 1=region will be stopped, 0=region will keep running on xstop
13	RW			XSTOP3_REGION_UNIT9: region 9 - dpllnest: 1=region will be stopped, 0=region will keep running on xstop
14	RW			XSTOP3_REGION_UNIT10: region 10 - pllperv: 1=region will be stopped, 0=region will keep running on xstop
15	RW			XSTOP3_REGION_UNIT11: region 11 - unused: 1=region will be stopped, 0=region will keep running on xstop
16	RW			XSTOP3_REGION_UNIT12: region 12 - unused: 1=region will be stopped, 0=region will keep running on xstop
17	RW			XSTOP3_REGION_UNIT13: region 13 - unused: 1=region will be stopped, 0=region will keep running on xstop
18	RW			XSTOP3_REGION_UNIT14: region 14 - unused: 1=region will be stopped, 0=region will keep running on xstop
19:47	RO			constant=0b00000000000000000000000000000
48:59	RW			XSTOP3_WAIT_CYCLES: Defines, how many cycle xstop will wait after dropping flush, before tholds get dropped. 0-4095 cycles possible
60:63	RO			constant=0b0000

Error Status of CC
Addr:	000000000103000F (SCOM)
Name:	TP.TPCHIP.TPC.ERROR_STATUS
Constant(s):	PERV_1_ERROR_STATUS
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_0_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_1_INST.LATC.L2(1) [0]
	2	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_2_INST.LATC.L2(2) [0]
	3	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_3_INST.LATC.L2(3) [0]
	4	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_4_INST.LATC.L2(4) [0]
	5	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_5_INST.LATC.L2(5) [0]
	6	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_6_INST.LATC.L2(6) [0]
	7	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_7_INST.LATC.L2(7) [0]
	8	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_8_INST.LATC.L2(8) [0]
	9	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_9_INST.LATC.L2(9) [0]
	10	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_10_INST.LATC.L2(10) [0]
	11	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_11_INST.LATC.L2(11) [0]
	12	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_12_INST.LATC.L2(12) [0]
	13	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_13_INST.LATC.L2(13) [0]
	14	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_14_INST.LATC.L2(14) [0]
	15	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_15_INST.LATC.L2(15) [0]
	16	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_16_INST.LATC.L2(16) [0]
	17	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_17_INST.LATC.L2(17) [0]
	18	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_18_INST.LATC.L2(18) [0]
	19	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_19_INST.LATC.L2(19) [0]
	20	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_20_INST.LATC.L2(20) [0]
	21	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_21_INST.LATC.L2(21) [0]
	22	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_22_INST.LATC.L2(22) [0]
	23	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_23_INST.LATC.L2(23) [0]
	24	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_24_INST.LATC.L2(24) [0]
	25	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_25_INST.LATC.L2(25) [0]
	26	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_26_INST.LATC.L2(26) [0]
	27	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_27_INST.LATC.L2(27) [0]
	28	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_28_INST.LATC.L2(28) [0]
	29	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_29_INST.LATC.L2(29) [0]
	30	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_30_INST.LATC.L2(30) [0]
	31	TP.TPCHIP.TPC.EPS.CC.ERROR.ERROR_REG_Q_31_INST.LATC.L2(31) [0]
Bit(s)	SCOM			Dial: Description
0	RWX			PCB_WRITE_NOT_ALLOWED_ERR: write on read only register
1	RWX			PCB_READ_NOT_ALLOWED_ERR: read not allowed, maybe write only register
2	RWX			PCB_PARITY_ON_CMD_ERR: parity error on cmd
3	RWX			PCB_ADDRESS_NOT_VALID_ERR: invalid address
4	RWX			PCB_PARITY_ON_ADDR_ERR: parity error on addr
5	RWX			PCB_PARITY_ON_DATA_ERR: parity error on data
6	RWX			PCB_PROTECTED_ACCESS_INVALID_ERR: protection violation
7	RWX			PCB_PARITY_ON_SPCIF_ERR: parity error on spcif
8	RWX			PCB_WRITE_AND_OPCG_IP_ERR: pcb write while OPCG is running
9	RWX			SCAN_READ_AND_OPCG_IP_ERR: scan read when opcg is running
10	RWX			CLOCK_CMD_CONFLICT_ERR: clock cmd in progress
11	RWX			SCAN_COLLISION_ERR: scan region selected of running region
12	RWX			PREVENTED_SCAN_COLLISION_ERR: PCB request to set scan region which is running
13	RWX			OPCG_TRIGGER_ERR: OPCG gets triggered while OPCG is running
14	RWX			PHASE_CNT_CORRUPTION_ERR: phase counters inside chiplet out of sync
15	RWX			CLOCK_CMD_PREVENTED_ERR: security or scan collision prevented a clock start
16	RWX			PARITY_ON_OPCG_SM_ERR: parity error on OPCG state machine
17	RWX			PARITY_ON_CLOCK_MUX_REG_ERR: parity error on scan/clock region/type or clock status reg
18	RWX			PARITY_ON_OPCG_REG_ERR: parity error on OPCG regs
19	RWX			PARITY_ON_SYNC_CONFIG_REG_ERR: parity error on sync config reg
20	RWX			PARITY_ON_XSTOP_REG_ERR: parity error on xstop reg
21	RWX			PARITY_ON_GPIO_REG_ERR: parity error on GP0,4,5,6 regs
22	RWX			CLKCMD_REQUEST_ERR: region clkcmd has two requests start and stop at the same time start clkcmd will win, but this still causes this error bit go high
23	RWX			CBS_PROTOCOL_ERR: CBS protocol error - REQ / ACK sequence wrong ERROR is when REQ goes low before ACK goes high
24	RWX			VITL_ALIGN_ERR: VITL alignment is out of sync to sync pulse
25	RWX			UNIT_SYNC_LVL_ERR: Unit0 and Unit1 sync lvl pulse are not in sync - AVP broken
26	RWX			PARITY_ON_SELFBOOT_CMD_STATE_ERR: Parity error on selfboot cmd state
27	RWX			OPCG_STOPPED_BY_PCB_ERR: OPCG has been stopped by write on a new register
28	RWX			UNUSED_ERROR28: unused
29	RWX			UNUSED_ERROR29: unused
30	RWX			UNUSED_ERROR30: unused
31	RWX			UNUSED_ERROR31: unused

OPCG Control Register Capture1
Addr:	0000000001030010 (SCOM)
Name:	TP.TPCHIP.TPC.OPCG_CAPT1
Constant(s):	PERV_1_OPCG_CAPT1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.TPC.EPS.CC.OPCG.OPCG_CAPT1_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:3	RW			COUNT: 0000=12 cycle 0001 - 1100= cycle 1-12 1101-1111=24 normal, no fast
4:8	RW			SEQ_01: sequence cycle 1 for normal/slow region (sl, nsl, ary, se, fce)
9:13	RW			SEQ_02: sequence cycle 2 for normal/slow region (sl, nsl, ary, se, fce)
14:18	RW			SEQ_03: sequence cycle 3 for normal/slow region (sl, nsl, ary, se, fce)
19:23	RW			SEQ_04: sequence cycle 4 for normal/slow region (sl, nsl, ary, se, fce)
24:28	RW			SEQ_05: sequence cycle 5 for normal/slow region (sl, nsl, ary, se, fce)
29:33	RW			SEQ_06: sequence cycle 6 for normal/slow region (sl, nsl, ary, se, fce)
34:38	RW			SEQ_07: sequence cycle 7 for normal/slow region (sl, nsl, ary, se, fce)
39:43	RW			SEQ_08: sequence cycle 8 for normal/slow region (sl, nsl, ary, se, fce)
44:48	RW			SEQ_09: sequence cycle 9 for normal/slow region (sl, nsl, ary, se, fce)
49:53	RW			SEQ_10: sequence cycle 10 for normal/slow region (sl, nsl, ary, se, fce)
54:58	RW			SEQ_11: sequence cycle 11 for normal/slow region (sl, nsl, ary, se, fce)
59:63	RW			SEQ_12: sequence cycle 12 for normal/slow region (sl, nsl, ary, se, fce)

OPCG Control Register Capture 2
Addr:	0000000001030011 (SCOM)
Name:	TP.TPCHIP.TPC.OPCG_CAPT2
Constant(s):	PERV_1_OPCG_CAPT2
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.TPC.EPS.CC.OPCG.OPCG_CAPT2_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:3	RW			UNUSED_CAPT2:
4:8	RW			SEQ_13_01EVEN: sequence cycle 1 - even - for fast region or cycle 13 for normal region (sl, nsl, ary, se, fce)
9:13	RW			SEQ_14_01ODD: sequence cycle 1 - odd - for fast region or cycle 14 for normal region (sl, nsl, ary, se, fce)
14:18	RW			SEQ_15_02EVEN: sequence cycle 2 - even - for fast region or cycle 15 for normal region (sl, nsl, ary, se, fce)
19:23	RW			SEQ_16_02ODD: sequence cycle 2 - odd - for fast region or cycle 16 for normal region (sl, nsl, ary, se, fce)
24:28	RW			SEQ_17_03EVEN: sequence cycle 3 - even - for fast region or cycle 17 for normal region (sl, nsl, ary, se, fce)
29:33	RW			SEQ_18_03ODD: sequence cycle 3 - odd - for fast region or cycle 18 for normal region (sl, nsl, ary, se, fce)
34:38	RW			SEQ_19_04EVEN: sequence cycle 4 - even - for fast region or cycle 19 for normal region (sl, nsl, ary, se, fce)
39:43	RW			SEQ_20_04ODD: sequence cycle 4 - odd - for fast region or cycle 20 for normal region (sl, nsl, ary, se, fce)
44:48	RW			SEQ_21_05EVEN: sequence cycle 5 - even - for fast region or cycle 21 for normal region (sl, nsl, ary, se, fce)
49:53	RW			SEQ_22_05ODD: sequence cycle 5 - odd - for fast region or cycle 22 for normal region (sl, nsl, ary, se, fce)
54:58	RW			SEQ_23_06EVEN: sequence cycle 6 - even - for fast region or cycle 23 for normal region (sl, nsl, ary, se, fce)
59:63	RW			SEQ_24_06ODD: sequence cycle 6 - odd - for fast region or cycle 24 for normal region (sl, nsl, ary, se, fce)

OPCG Control Register Capture 3
Addr:	0000000001030012 (SCOM)
Name:	TP.TPCHIP.TPC.OPCG_CAPT3
Constant(s):	PERV_1_OPCG_CAPT3
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.TPC.EPS.CC.OPCG.OPCG_CAPT3_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:3	RW			UNUSED_CAPT3:
4:8	RW			SEQ_07EVEN: sequence cycle 7 - even - for fast region (sl, nsl, ary, se, fce)
9:13	RW			SEQ_07ODD: sequence cycle 7 - odd - for fast region (sl, nsl, ary, se, fce)
14:18	RW			SEQ_08EVEN: sequence cycle 8 - even - for fast region (sl, nsl, ary, se, fce)
19:23	RW			SEQ_08ODD: sequence cycle 8 - odd - for fast region (sl, nsl, ary, se, fce)
24:28	RW			SEQ_09EVEN: sequence cycle 9 - even - for fast region (sl, nsl, ary, se, fce)
29:33	RW			SEQ_09ODD: sequence cycle 9 - odd - for fast region (sl, nsl, ary, se, fce)
34:38	RW			SEQ_10EVEN: sequence cycle 10 - even - for fast region (sl, nsl, ary, se, fce)
39:43	RW			SEQ_10ODD: sequence cycle 10 - odd - for fast region (sl, nsl, ary, se, fce)
44:48	RW			SEQ_11EVEN: sequence cycle 11 - even - for fast region (sl, nsl, ary, se, fce)
49:53	RW			SEQ_11ODD: sequence cycle 11 - odd - for fast region (sl, nsl, ary, se, fce)
54:58	RW			SEQ_12EVEN: sequence cycle 12 - even - for fast region (sl, nsl, ary, se, fce)
59:63	RW			SEQ_12ODD: sequence cycle 12 - odd - for fast region (sl, nsl, ary, se, fce)

Debug CBS CC Register
Addr:	0000000001030013 (SCOM)
Name:	TP.TPCHIP.TPC.DBG_CBS_CC
Constant(s):	PERV_1_DBG_CBS_CC
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.TPC.EPS.CC.SELFBOOT.DBG_CBS_CC_REG_Q_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	ROX			DBG_RESET_EP: Reset Endpoint - Is the CC and CTRL in reset state
1	ROX			DBG_OPCG_IP: OPCG in progress, not in idle
2	ROX			DBG_VITL_CLKOFF: VITL HLD stopped, when enabled, need plat-depth cycles to switch this latch
3	ROX			DBG_TEST_ENABLE: Test Enable
4	ROX			DBG_CBS_REQ: CBS Interface - Request (Latched)
5:7	ROX			DBG_CBS_CMD: CBS Interface - Command (Latched)
8:12	ROX			DBG_CBS_STATE: CBS Command State Machine 00000=Idle
13	ROX			DBG_SECURITY_DEBUG_MODE: status of the security mode bit
14	ROX			DBG_CBS_PROTOCOL_ERROR: CBS Protocol Error - REQ raised, although state machine is not in IDLE - need reset_ep to clear this bit. No impact on IPL
15	ROX			DBG_PCB_IDLE: PCB Interface in IDLE state
16:19	ROX			DBG_CURRENT_OPCG_MODE: current / latest OPCG MODE - 0=NOP, 1=LBIST, 2=ABIST, 3=RUNN, 4=SCAN0, 5=SCAN, 6=SCAN rotate, 7=SCAN w UpdateDR, 8=SCAN w CaptureDR, 9=nonblocking SCAN, 10=CLK Change Request, 11-15=unused
20:23	ROX			DBG_LAST_OPCG_MODE: previous OPCG MODE
24	ROX			DBG_PCB_ERROR: PCB Interface Error, read CC Error Reg or set CBS_CMD=001 to switch FSI CBS Debug Information to CC Error Register.
25	ROX			DBG_PARITY_ERROR: Any Parity Error, non PCB Parity - read CC Error Reg or set CBS_CMD=001 to switch FSI CBS Debug Information to CC Error Register.
26	ROX			DBG_CC_ERROR: Any other CC Error - read CC Error Reg or set CBS_CMD=001 to switch FSI CBS Debug Information to CC Error Register.
27	ROX			DBG_CHIPLET_IS_ALIGNED: Is 1 when the a valid align pulse ws send out.
28	ROX			DBG_PCB_REQUEST_SINCE_RESET: RESET will clear that bit, the first PCB request will set it.
29	ROX			DBG_PARANOIA_TEST_ENABLE_CHANGE: rising or falling edge on test enable, after reset - need reset_ep to clear, no impact on IPL
30	ROX			DBG_PARANOIA_VITL_CLKOFF_CHANGE: rising or falling edge on vitl_clkoff, after reset - need reset_ep to clear, no impact on IPL
31	ROX			TP_TPFSI_CBS_ACK: only represenation of CC ack signal going to FSI

XSTOP per region
Addr:	0000000001030014 (SCOM)
Name:	TP.TPCHIP.TPC.XSTOP4
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.TPC.EPS.CC.XSTOP4.XSTOP_CONFIG_Q_INST.LATC.L2(0:3) [0000]
	4:18	TP.TPCHIP.TPC.EPS.CC.XSTOP4.XSTOP_REGIONS_Q_INST.LATC.L2(0:14) [000000000000000]
	48:59	TP.TPCHIP.TPC.EPS.CC.XSTOP4.XSTOP_WAITS_Q_INST.LATC.L2(0:11) [000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			XSTOP4_ENABLE: enable xstop to clockstop of selected regions, 0 = ignore chkstop, 1= stop on chkstop
1	RW			XSTOP4_WAIT_SNOPA: wait for SNOP align to stop clocks on checkstop
2	RW			XSTOP4_TRIGGER_OPCG_GO: trigger opcg on xstop instead of performing clockstop
3	RW			XSTOP4_WAIT_ALWAYS: when set to 1, xstop will wait independent from flush, default is no wait, when flush in not set
4	RW			XSTOP4_REGION_PERV: region perv: 1=region will be stopped, 0=region will keep running on xstop
5	RW			XSTOP4_REGION_UNIT1: region 1 - sbe: 1=region will be stopped, 0=region will keep running on xstop
6	RW			XSTOP4_REGION_UNIT2: region 2 - pib: 1=region will be stopped, 0=region will keep running on xstop
7	RW			XSTOP4_REGION_UNIT3: region 3 - occ: 1=region will be stopped, 0=region will keep running on xstop
8	RW			XSTOP4_REGION_UNIT4: region 4 - net: 1=region will be stopped, 0=region will keep running on xstop
9	RW			XSTOP4_REGION_UNIT5: region 5 - unused: 1=region will be stopped, 0=region will keep running on xstop
10	RW			XSTOP4_REGION_UNIT6: region 6 - psi: 1=region will be stopped, 0=region will keep running on xstop
11	RW			XSTOP4_REGION_UNIT7: region 7 - unused: 1=region will be stopped, 0=region will keep running on xstop
12	RW			XSTOP4_REGION_UNIT8: region 8 - dpllpau: 1=region will be stopped, 0=region will keep running on xstop
13	RW			XSTOP4_REGION_UNIT9: region 9 - dpllnest: 1=region will be stopped, 0=region will keep running on xstop
14	RW			XSTOP4_REGION_UNIT10: region 10 - pllperv: 1=region will be stopped, 0=region will keep running on xstop
15	RW			XSTOP4_REGION_UNIT11: region 11 - unused: 1=region will be stopped, 0=region will keep running on xstop
16	RW			XSTOP4_REGION_UNIT12: region 12 - unused: 1=region will be stopped, 0=region will keep running on xstop
17	RW			XSTOP4_REGION_UNIT13: region 13 - unused: 1=region will be stopped, 0=region will keep running on xstop
18	RW			XSTOP4_REGION_UNIT14: region 14 - unused: 1=region will be stopped, 0=region will keep running on xstop
19:47	RO			constant=0b00000000000000000000000000000
48:59	RW			XSTOP4_WAIT_CYCLES: Defines, how many cycle xstop will wait after dropping flush, before tholds get dropped. 0-4095 cycles possible
60:63	RO			constant=0b0000

XSTOP per region
Addr:	0000000001030015 (SCOM)
Name:	TP.TPCHIP.TPC.XSTOP5
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.TPC.EPS.CC.XSTOP5.XSTOP_CONFIG_Q_INST.LATC.L2(0:3) [0000]
	4:18	TP.TPCHIP.TPC.EPS.CC.XSTOP5.XSTOP_REGIONS_Q_INST.LATC.L2(0:14) [000000000000000]
	48:59	TP.TPCHIP.TPC.EPS.CC.XSTOP5.XSTOP_WAITS_Q_INST.LATC.L2(0:11) [000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			XSTOP5_ENABLE: enable xstop to clockstop of selected regions, 0 = ignore chkstop, 1= stop on chkstop
1	RW			XSTOP5_WAIT_SNOPA: wait for SNOP align to stop clocks on checkstop
2	RW			XSTOP5_TRIGGER_OPCG_GO: trigger opcg on xstop instead of performing clockstop
3	RW			XSTOP5_WAIT_ALWAYS: when set to 1, xstop will wait independent from flush, default is no wait, when flush in not set
4	RW			XSTOP5_REGION_PERV: region perv: 1=region will be stopped, 0=region will keep running on xstop
5	RW			XSTOP5_REGION_UNIT1: region 1 - sbe: 1=region will be stopped, 0=region will keep running on xstop
6	RW			XSTOP5_REGION_UNIT2: region 2 - pib: 1=region will be stopped, 0=region will keep running on xstop
7	RW			XSTOP5_REGION_UNIT3: region 3 - occ: 1=region will be stopped, 0=region will keep running on xstop
8	RW			XSTOP5_REGION_UNIT4: region 4 - net: 1=region will be stopped, 0=region will keep running on xstop
9	RW			XSTOP5_REGION_UNIT5: region 5 - unused: 1=region will be stopped, 0=region will keep running on xstop
10	RW			XSTOP5_REGION_UNIT6: region 6 - psi: 1=region will be stopped, 0=region will keep running on xstop
11	RW			XSTOP5_REGION_UNIT7: region 7 - unused: 1=region will be stopped, 0=region will keep running on xstop
12	RW			XSTOP5_REGION_UNIT8: region 8 - dpllpau: 1=region will be stopped, 0=region will keep running on xstop
13	RW			XSTOP5_REGION_UNIT9: region 9 - dpllnest: 1=region will be stopped, 0=region will keep running on xstop
14	RW			XSTOP5_REGION_UNIT10: region 10 - pllperv: 1=region will be stopped, 0=region will keep running on xstop
15	RW			XSTOP5_REGION_UNIT11: region 11 - unused: 1=region will be stopped, 0=region will keep running on xstop
16	RW			XSTOP5_REGION_UNIT12: region 12 - unused: 1=region will be stopped, 0=region will keep running on xstop
17	RW			XSTOP5_REGION_UNIT13: region 13 - unused: 1=region will be stopped, 0=region will keep running on xstop
18	RW			XSTOP5_REGION_UNIT14: region 14 - unused: 1=region will be stopped, 0=region will keep running on xstop
19:47	RO			constant=0b00000000000000000000000000000
48:59	RW			XSTOP5_WAIT_CYCLES: Defines, how many cycle xstop will wait after dropping flush, before tholds get dropped. 0-4095 cycles possible
60:63	RO			constant=0b0000

Region CCFLUSH Status
Addr:	0000000001030016 (SCOM)
Name:	TP.TPCHIP.TPC.REGION_CCFLUSH_STATUS
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	4:18	TP.TPCHIP.TPC.EPS.CC.CLOCK_MUX.REGION_FLUSHMODE_INH_Q_INST.LATC.L2(0:14) [000000000000000]
Bit(s)	SCOM			Dial: Description
0:3	RO			constant=0b0000
4:18	ROX			REGION_CCFLUSH: Region CCFLUSH status - 0=region not in flush, 1= region in flush state
19:63	RO			constant=0b000000000000000000000000000000000000000000000

OPCG GO - Start OPCG on WRITE to this register
Addr:	0000000001030020 (SCOM)
Name:	TP.TPCHIP.TPC.PCB_OPCG_GO
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.TPC.EPS.CC.OPCG.PCB_WRITE_OPCG_GO_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	WOX			PCB_OPCGGO: opcg go (start OPCG) - write this register to start OPCG

Careful use only: a WRITE of xFACE000000000000 will reset the phase counter. Alignment of the chiplet is broken
Addr:	0000000001030028 (SCOM)
Name:	TP.TPCHIP.TPC.PHASE_COUNTER_RESET
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.TPC.EPS.CC.PCB.PCB_WRITE_RESET_PHASE_COUNTER_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	WOX			PHASECOUNTER_RESET: Careful use only: a WRITE of xFACE000000000000 will reset the phase counter. Alignment of the chiplet is broken

OPCG STOP - Stop OPCG when in RUNN or LBIST
Addr:	0000000001030030 (SCOM)
Name:	TP.TPCHIP.TPC.PCB_OPCG_STOP
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.TPC.EPS.CC.OPCG.PCB_WRITE_OPCG_LOOP_STOP_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	WOX			PCB_OPCGSTOP: opcg stop (stop OPCG) - write this register to stop OPCG during RUNN or LBIST

CC Protect Mode Register
Addr:	00000000010303FE (SCOM)
Name:	TP.TPCHIP.TPC.CC_PROTECT_MODE_REG
Constant(s):	PERV_1_CC_PROTECT_MODE_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.TPC.EPS.CC.PCB.PCB_IF.PROTECT_MODE.RD_PROTECT_ENA_INST.LATC.L2(0) [0]
	1	TP.TPCHIP.TPC.EPS.CC.PCB.PCB_IF.PROTECT_MODE.WR_PROTECT_ENA_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	RW			CC_READ_PROTECT_ENABLE: Enable read protection
1	RW			CC_WRITE_PROTECT_ENABLE: Enable write protection

Atomic Lock Register
Addr:	00000000010303FF (SCOM)
Name:	TP.TPCHIP.TPC.CC_ATOMIC_LOCK_REG
Constant(s):	PERV_1_CC_ATOMIC_LOCK_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.TPC.EPS.CC.PCB.PCB_IF.ATOMIC_LOCK.ATOMIC_LOCK_ENA_INST.LATC.L2(0) [0]
	1:4	TP.TPCHIP.TPC.EPS.CC.PCB.PCB_IF.ATOMIC_LOCK.ATOMIC_ID_Q_INST.LATC.L2(0:3) [0000]
	8:15	TP.TPCHIP.TPC.EPS.CC.PCB.PCB_IF.ATOMIC_LOCK.ATOMIC_LOCK_ACTIVITY_Q_INST.LATC.L2(0:7) [00000000]
Bit(s)	SCOM			Dial: Description
0	RW			CC_ATOMIC_LOCK_ENABLE: Enable atomic lock
1:4	ROX			CC_ATOMIC_ID: Atomic ID
5:7	RO			constant=0b000
8:15	ROX			CC_ATOMIC_ACTIVITY: Atomic lock counter

Scan in 32bit mode
Addr:	0000000001038000 (SCOM)
Name:	TP.TPCHIP.TPC.SCAN32
Constant(s):
Comments:	nn38000 - write 32 bit and/or read 64 bit of the scan buffer - no scan cycles will be shifted nn38001 - nn3801F - write of 01 - 31 bits left aligned into the scan buffer(masking), shifting 01-31 cycles and read 64 bit nn38020 - write 32 bit, shift 32 bit, read 64 bit scan buffer nn38nnn - write max 32 bits, rotate nnn cycles, read of the 64bit scan buffer Order: WRITE - Shift - READ PCB Timout possible, if scan count is too high or scan ratio to slow Write max 32 bits (left aligned) - read will respond full 64 bit scan buffer
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.TPC.EPS.CC.SCANPCB.SCANDATA_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	RW			scan32_reg
32:63	RO			constant=0b11011110101011011011111011101111

Long rotate scan - Only rotate the ring
Addr:	0000000001039000 (SCOM)
Name:	TP.TPCHIP.TPC.SCAN_LONG_ROTATE
Constant(s):
Comments:	Used to rotate the ring only, the cycle number is programmmed in the scom data, not in the address example putscom nn39000 0000123400000000 - will rotate x1234 cycles PCB network will NOT be blocked - poll opcg done !
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	12:31	TP.TPCHIP.TPC.EPS.CC.SCANPCB.BIT_COUNT_Q_0_INST.LATC.L2(0:19) [00000000000000000000]
Bit(s)	SCOM			Dial: Description
0:11	n/a			not implemented
12:31	WOX

Scan in 32bit mode with Update DR
Addr:	000000000103A000 (SCOM)
Name:	TP.TPCHIP.TPC.SCAN_UPDATEDR
Constant(s):
Comments:	see scan32 - after the scan CC will apply a functional clock to update non-scannable latches used e.g. to load PLL cntrl ring PCB network blocked until scan has finished - timeout possible
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.TPC.EPS.CC.SCANPCB.SCANDATA_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	RW			scan_updatedr_reg
32:63	RO			constant=0b11011110101011011011111011101111

Scan in 32bit mode with Update DR - PCB will not be blocked
Addr:	000000000103B000 (SCOM)
Name:	TP.TPCHIP.TPC.SCAN_UPDATEDR_LONG
Constant(s):
Comments:	see scan32 - after the scan CC will apply a functional clock to update non-scannable latches used e.g. to load PLL cntrl ring PCB network will NOT be blocked - poll opcg done !
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.TPC.EPS.CC.SCANPCB.SCANDATA_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	WOX			scan_updatedr_long_reg
32:63	RO			constant=0b11011110101011011011111011101111

Scan in 32bit mode with CAPTURE DR
Addr:	000000000103C000 (SCOM)
Name:	TP.TPCHIP.TPC.SCAN_CAPTUREDR
Constant(s):
Comments:	see scan32 - before the scan CC will apply a functional clock to CAPTURE non-scannable latches used e.g. to unload PLL cntrl ring PCB network blocked until scan has finished - timeout possible
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.TPC.EPS.CC.SCANPCB.SCANDATA_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	RW			scan_capturedr_reg
32:63	RO			constant=0b11011110101011011011111011101111

Scan in 32bit mode with CAPTURE DR - PCB will not be blocked
Addr:	000000000103D000 (SCOM)
Name:	TP.TPCHIP.TPC.SCAN_CAPTUREDR_LONG
Constant(s):
Comments:	see scan32 - before the scan CC will apply a functional clock to CAPTURE non-scannable latches used e.g. to unload PLL cntrl ring PCB network will NOT be blocked - poll opcg done !
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:31	TP.TPCHIP.TPC.EPS.CC.SCANPCB.SCANDATA_Q_0_INST.LATC.L2(0:31) [00000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:31	WOX			scan_capturedr_long_reg
32:63	RO			constant=0b11011110101011011011111011101111

Scan in 64bit mode
Addr:	000000000103E000 (SCOM)
Name:	TP.TPCHIP.TPC.SCAN64
Constant(s):
Comments:	nn3E000 - write and/or read of 64 bit scan buffer - no shift nn3E001 - nn3803F - write of 01 - 63 bits left aligned into the scan buffer(masking), shifting 01-63 cycles and read 64 bit nn3E040 - write an/or read of 64 bit scan buffer - shift 64 bit - order Write Shift Read nn3Ennn - write max 64 bit, shift nnn cycles, read max 64 bit
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.TPC.EPS.CC.SCANPCB.SCANDATA_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			scan64_reg

Scan in 64bit mode - Continues Scanning - non-blocking scan
Addr:	000000000103F000 (SCOM)
Name:	TP.TPCHIP.TPC.SCAN64CONTSCAN
Constant(s):
Comments:	nn3F000 - write and/or read of 64 bit scan buffer - no shift nn3F001 - nn3803F - write of 01 - 63 bits left aligned into the scan buffer(masking), shifting 01-63 cycles and read 64 bit nn3F040 - write an/or read of 64 bit scan buffer - shift 64 bit - order Write Shift Read nn3Fnnn - write max 64 bit, shift nnn cycles, read max 64 bit
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.TPC.EPS.CC.SCANPCB.SCANDATA_Q_0_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	RW			scan64contscan_reg

XSTOP Register - after masking - OLD XFIR
Addr:	0000000001040000 (SCOM)
Name:	TP.TPCHIP.TPC.XSTOP
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:53	TP.TPCHIP.TPC.EPS.FIR.COMP.XSTOP_MASKED_REG_Q_INST.LATC.L2(0:53) [000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	ROX			ANY_XSTOP: any xstop
1	ROX			SYSTEM_XSTOP: system_xstop
2	ROX			XSTOP_ANY_SPATTN: any_spattn
3	ROX			DBG_FIR_XSTOP_ON_TRIG: dbg_fir_xstop_on_trig
4	ROX			XSTOP_PERV: perv
5	ROX			XSTOP_IN05: OCC
6	ROX			XSTOP_IN06: PBAO
7	ROX			XSTOP_IN07: unused
8	ROX			XSTOP_IN08: unused
9	ROX			XSTOP_IN09: unused
10	ROX			XSTOP_IN10: unused
11	ROX			XSTOP_IN11: unused
12	ROX			XSTOP_IN12: unused
13	ROX			XSTOP_IN13: unused
14	ROX			XSTOP_IN14: unused
15	ROX			XSTOP_IN15: unused
16	ROX			XSTOP_IN16: unused
17	ROX			XSTOP_IN17: unused
18	ROX			XSTOP_IN18: unused
19	ROX			XSTOP_IN19: unused
20	ROX			XSTOP_IN20: unused
21	ROX			XSTOP_IN21: unused
22	ROX			XSTOP_IN22: unused
23	ROX			XSTOP_IN23: unused
24	ROX			XSTOP_IN24: unused
25	ROX			XSTOP_IN25: unused
26	ROX			XSTOP_IN26: unused
27	ROX			XSTOP_IN27: unused
28	ROX			XSTOP_IN28: unused
29	ROX			XSTOP_IN29: unused
30	ROX			XSTOP_IN30: unused
31	ROX			XSTOP_IN31: unused
32	ROX			XSTOP_IN32: unused
33	ROX			XSTOP_IN33: unused
34	ROX			XSTOP_IN34: unused
35	ROX			XSTOP_IN35: unused
36	ROX			XSTOP_IN36: unused
37	ROX			XSTOP_IN37: unused
38	ROX			XSTOP_IN38: unused
39	ROX			XSTOP_IN39: unused
40	ROX			XSTOP_IN40: unused
41	ROX			XSTOP_IN41: unused
42	ROX			XSTOP_IN42: unused
43	ROX			XSTOP_IN43: unused
44	ROX			XSTOP_IN44: unused
45	ROX			XSTOP_IN45: unused
46	ROX			XSTOP_IN46: unused
47	ROX			XSTOP_IN47: unused
48	ROX			XSTOP_IN48: unused
49	ROX			XSTOP_IN49: unused
50	ROX			XSTOP_IN50: unused
51	ROX			XSTOP_IN51: unused
52	ROX			XSTOP_IN52: unused
53	ROX			XSTOP_IN53: unused

RECOV Error Register - after masking - OLD RFIR
Addr:	0000000001040001 (SCOM)
Name:	TP.TPCHIP.TPC.RECOV
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:53	TP.TPCHIP.TPC.EPS.FIR.COMP.RECOV_MASKED_REG_Q_INST.LATC.L2(0:53) [000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	ROX			ANY_RECOV: any_recov
1	ROX			RESERVED1R: RESERVED
2	ROX			RECOV_ANY_LOCAL_XSTOP: any_local_xstop
3	ROX			RESERVED3R: RESERVED
4	ROX			RECOV_PERV: perv
5	ROX			RECOV_IN05: OCC
6	ROX			RECOV_IN06: PBAO
7	ROX			RECOV_IN07: unused
8	ROX			RECOV_IN08: unused
9	ROX			RECOV_IN09: unused
10	ROX			RECOV_IN10: unused
11	ROX			RECOV_IN11: unused
12	ROX			RECOV_IN12: unused
13	ROX			RECOV_IN13: unused
14	ROX			RECOV_IN14: unused
15	ROX			RECOV_IN15: unused
16	ROX			RECOV_IN16: unused
17	ROX			RECOV_IN17: unused
18	ROX			RECOV_IN18: unused
19	ROX			RECOV_IN19: unused
20	ROX			RECOV_IN20: unused
21	ROX			RECOV_IN21: unused
22	ROX			RECOV_IN22: unused
23	ROX			RECOV_IN23: unused
24	ROX			RECOV_IN24: unused
25	ROX			RECOV_IN25: unused
26	ROX			RECOV_IN26: unused
27	ROX			RECOV_IN27: unused
28	ROX			RECOV_IN28: unused
29	ROX			RECOV_IN29: unused
30	ROX			RECOV_IN30: unused
31	ROX			RECOV_IN31: unused
32	ROX			RECOV_IN32: unused
33	ROX			RECOV_IN33: unused
34	ROX			RECOV_IN34: unused
35	ROX			RECOV_IN35: unused
36	ROX			RECOV_IN36: unused
37	ROX			RECOV_IN37: unused
38	ROX			RECOV_IN38: unused
39	ROX			RECOV_IN39: unused
40	ROX			RECOV_IN40: unused
41	ROX			RECOV_IN41: unused
42	ROX			RECOV_IN42: unused
43	ROX			RECOV_IN43: unused
44	ROX			RECOV_IN44: unused
45	ROX			RECOV_IN45: unused
46	ROX			RECOV_IN46: unused
47	ROX			RECOV_IN47: unused
48	ROX			RECOV_IN48: unused
49	ROX			RECOV_IN49: unused
50	ROX			RECOV_IN50: unused
51	ROX			RECOV_IN51: unused
52	ROX			RECOV_IN52: unused
53	ROX			RECOV_IN53: unused

Special Attention Register - after masking
Addr:	0000000001040002 (SCOM)
Name:	TP.TPCHIP.TPC.SPATTN
Constant(s):	PERV_1_SPATTN
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:35	TP.TPCHIP.TPC.EPS.FIR.COMP.SPATTN_MASKED_REG_Q_INST.LATC.L2(0:35) [000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	ROX			ANY_SPATTN: any_spattn
1	ROX			RESERVED1S: RESERVED
2	ROX			RESERVED2S: RESERVED
3	ROX			RESERVED3S: RESERVED
4	ROX			SPATTN_PERV: perv
5	ROX			SPATTN_IN05: unused
6	ROX			SPATTN_IN06: unused
7	ROX			SPATTN_IN07: unused
8	ROX			SPATTN_IN08: unused
9	ROX			SPATTN_IN09: unused
10	ROX			SPATTN_IN10: unused
11	ROX			SPATTN_IN11: unused
12	ROX			SPATTN_IN12: unused
13	ROX			SPATTN_IN13: unused
14	ROX			SPATTN_IN14: unused
15	ROX			SPATTN_IN15: unused
16	ROX			SPATTN_IN16: unused
17	ROX			SPATTN_IN17: unused
18	ROX			SPATTN_IN18: unused
19	ROX			SPATTN_IN19: unused
20	ROX			SPATTN_IN20: unused
21	ROX			SPATTN_IN21: unused
22	ROX			SPATTN_IN22: unused
23	ROX			SPATTN_IN23: unused
24	ROX			SPATTN_IN24: unused
25	ROX			SPATTN_IN25: unused
26	ROX			SPATTN_IN26: unused
27	ROX			SPATTN_IN27: unused
28	ROX			SPATTN_IN28: unused
29	ROX			SPATTN_IN29: unused
30	ROX			SPATTN_IN30: unused
31	ROX			SPATTN_IN31: unused
32	ROX			SPATTN_IN32: unused
33	ROX			SPATTN_IN33: unused
34	ROX			SPATTN_IN34: unused
35	ROX			SPATTN_IN35: unused

Local XSTOP Register - after masking
Addr:	0000000001040003 (SCOM)
Name:	TP.TPCHIP.TPC.LOCAL_XSTOP
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.TPC.EPS.FIR.COMP.LXSTOP_MASKED_REG_Q_INST.LATC.L2(0:15) [0000000000000000]
Bit(s)	SCOM			Dial: Description
0	ROX			ANY_LOCAL_XSTOP: any local xstop
1	ROX			RESERVED1L: RESERVED
2	ROX			RESERVED2L: RESERVED
3	ROX			RESERVED3L: RESERVED
4	ROX			LOCAL_XSTOP_PERV: perv
5	ROX			LOCAL_XSTOP_IN05: unused
6	ROX			LOCAL_XSTOP_IN06: unused
7	ROX			LOCAL_XSTOP_IN07: unused
8	ROX			LOCAL_XSTOP_IN08: unused
9	ROX			LOCAL_XSTOP_IN09: unused
10	ROX			LOCAL_XSTOP_IN10: unused
11	ROX			LOCAL_XSTOP_IN11: unused
12	ROX			LOCAL_XSTOP_IN12: unused
13	ROX			LOCAL_XSTOP_IN13: unused
14	ROX			LOCAL_XSTOP_IN14: unused
15	ROX			LOCAL_XSTOP_IN15: unused

Host Attention - Type4 - Register - after masking
Addr:	0000000001040004 (SCOM)
Name:	TP.TPCHIP.TPC.HOSTATTN
Constant(s):	PERV_1_HOSTATTN
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:53	TP.TPCHIP.TPC.EPS.FIR.COMP.HOSTATTN_MASKED_REG_Q_INST.LATC.L2(0:53) [000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	ROX			ANY_HOSTATTN: any host attn
1	ROX			RESERVED1H: RESERVED
2	ROX			RESERVED2H: RESERVED
3	ROX			RESERVED3H: RESERVED
4	ROX			HOSTATTN_PERV: perv
5	ROX			HOSTATTN_IN05: unused
6	ROX			HOSTATTN_IN06: unused
7	ROX			HOSTATTN_IN07: unused
8	ROX			HOSTATTN_IN08: unused
9	ROX			HOSTATTN_IN09: unused
10	ROX			HOSTATTN_IN10: unused
11	ROX			HOSTATTN_IN11: unused
12	ROX			HOSTATTN_IN12: unused
13	ROX			HOSTATTN_IN13: unused
14	ROX			HOSTATTN_IN14: unused
15	ROX			HOSTATTN_IN15: unused
16	ROX			HOSTATTN_IN16: unused
17	ROX			HOSTATTN_IN17: unused
18	ROX			HOSTATTN_IN18: unused
19	ROX			HOSTATTN_IN19: unused
20	ROX			HOSTATTN_IN20: unused
21	ROX			HOSTATTN_IN21: unused
22	ROX			HOSTATTN_IN22: unused
23	ROX			HOSTATTN_IN23: unused
24	ROX			HOSTATTN_IN24: unused
25	ROX			HOSTATTN_IN25: unused
26	ROX			HOSTATTN_IN26: unused
27	ROX			HOSTATTN_IN27: unused
28	ROX			HOSTATTN_IN28: unused
29	ROX			HOSTATTN_IN29: unused
30	ROX			HOSTATTN_IN30: unused
31	ROX			HOSTATTN_IN31: unused
32	ROX			HOSTATTN_IN32: unused
33	ROX			HOSTATTN_IN33: unused
34	ROX			HOSTATTN_IN34: unused
35	ROX			HOSTATTN_IN35: unused
36	ROX			HOSTATTN_IN36: unused
37	ROX			HOSTATTN_IN37: unused
38	ROX			HOSTATTN_IN38: unused
39	ROX			HOSTATTN_IN39: unused
40	ROX			HOSTATTN_IN40: unused
41	ROX			HOSTATTN_IN41: unused
42	ROX			HOSTATTN_IN42: unused
43	ROX			HOSTATTN_IN43: unused
44	ROX			HOSTATTN_IN44: unused
45	ROX			HOSTATTN_IN45: unused
46	ROX			HOSTATTN_IN46: unused
47	ROX			HOSTATTN_IN47: unused
48	ROX			HOSTATTN_IN48: unused
49	ROX			HOSTATTN_IN49: unused
50	ROX			HOSTATTN_IN50: unused
51	ROX			HOSTATTN_IN51: unused
52	ROX			HOSTATTN_IN52: unused
53	ROX			HOSTATTN_IN53: unused

XSTOP Register - Unmasked incoming Errors - Debug only
Addr:	0000000001040010 (SCOM)
Name:	TP.TPCHIP.TPC.XSTOP_UNMASKED
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:53	TP.TPCHIP.TPC.EPS.FIR.COMP.XSTOP_REG_Q_INST.LATC.L2(1:53) [00000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RO			constant=0b0
1:53	ROX			XSTOP_UNMASKED_IN:

RECOV Error Register - Unmasked incoming Errors - Debug only
Addr:	0000000001040011 (SCOM)
Name:	TP.TPCHIP.TPC.RECOV_UNMASKED
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:53	TP.TPCHIP.TPC.EPS.FIR.COMP.RECOV_REG_Q_INST.LATC.L2(1:53) [00000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RO			constant=0b0
1:53	ROX			RECOV_UNMASKED_IN:

Special Attention - Unmasked incoming Errors - Debug only
Addr:	0000000001040012 (SCOM)
Name:	TP.TPCHIP.TPC.SPATTN_UNMASKED
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:35	TP.TPCHIP.TPC.EPS.FIR.COMP.SPATTN_REG_Q_INST.LATC.L2(1:35) [00000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RO			constant=0b0
1:35	ROX			SPATTN_UNMASKED_IN:

Local XSTOP Register - Unmasked incoming Errors - Debug only
Addr:	0000000001040013 (SCOM)
Name:	TP.TPCHIP.TPC.LOCAL_XSTOP_UNMASKED
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:15	TP.TPCHIP.TPC.EPS.FIR.COMP.LXSTOP_REG_Q_INST.LATC.L2(1:15) [000000000000000]
Bit(s)	SCOM			Dial: Description
0	RO			constant=0b0
1:15	ROX			LOCAL_XSTOP_UNMASKED_IN:

Host Attention - Type4 - Unmasked incoming Errors - Debug only
Addr:	0000000001040014 (SCOM)
Name:	TP.TPCHIP.TPC.HOSTATTN_UNMASKED
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:53	TP.TPCHIP.TPC.EPS.FIR.COMP.HOSTATTN_REG_Q_INST.LATC.L2(1:53) [00000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RO			constant=0b0
1:53	ROX			HOSTATTN_UNMASKED_IN:

WOF Who is on First of the Recovable Errors Register
Addr:	0000000001040021 (SCOM)
Name:	TP.TPCHIP.TPC.WOF
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:53	TP.TPCHIP.TPC.EPS.FIR.COMP.WOF_YES.RECOV_WOF_Q_INST.LATC.L2(0:53) [000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW_WCLRPART			ANY_WOF: any_recov
1	RW_WCLRPART			RESERVED1W: RESERVED
2	RW_WCLRPART			WOF_ANY_LOCAL_XSTOP: any_local_xstop
3	RW_WCLRPART			RESERVED3W: RESERVED
4	RW_WCLRPART			WOF_PERV: perv
5	RW_WCLRPART			WOF_IN05: OCC
6	RW_WCLRPART			WOF_IN06: PBAO
7	RW_WCLRPART			WOF_IN07: unused
8	RW_WCLRPART			WOF_IN08: unused
9	RW_WCLRPART			WOF_IN09: unused
10	RW_WCLRPART			WOF_IN010: unused
11	RW_WCLRPART			WOF_IN011: unused
12	RW_WCLRPART			WOF_IN012: unused
13	RW_WCLRPART			WOF_IN013: unused
14	RW_WCLRPART			WOF_IN014: unused
15	RW_WCLRPART			WOF_IN015: unused
16	RW_WCLRPART			WOF_IN016: unused
17	RW_WCLRPART			WOF_IN017: unused
18	RW_WCLRPART			WOF_IN018: unused
19	RW_WCLRPART			WOF_IN019: unused
20	RW_WCLRPART			WOF_IN020: unused
21	RW_WCLRPART			WOF_IN021: unused
22	RW_WCLRPART			WOF_IN022: unused
23	RW_WCLRPART			WOF_IN023: unused
24	RW_WCLRPART			WOF_IN024: unused
25	RW_WCLRPART			WOF_IN025: unused
26	RW_WCLRPART			WOF_IN026: unused
27	RW_WCLRPART			WOF_IN027: unused
28	RW_WCLRPART			WOF_IN028: unused
29	RW_WCLRPART			WOF_IN029: unused
30	RW_WCLRPART			WOF_IN030: unused
31	RW_WCLRPART			WOF_IN031: unused
32	RW_WCLRPART			WOF_IN032: unused
33	RW_WCLRPART			WOF_IN033: unused
34	RW_WCLRPART			WOF_IN034: unused
35	RW_WCLRPART			WOF_IN035: unused
36	RW_WCLRPART			WOF_IN036: unused
37	RW_WCLRPART			WOF_IN037: unused
38	RW_WCLRPART			WOF_IN038: unused
39	RW_WCLRPART			WOF_IN039: unused
40	RW_WCLRPART			WOF_IN040: unused
41	RW_WCLRPART			WOF_IN041: unused
42	RW_WCLRPART			WOF_IN042: unused
43	RW_WCLRPART			WOF_IN043: unused
44	RW_WCLRPART			WOF_IN044: unused
45	RW_WCLRPART			WOF_IN045: unused
46	RW_WCLRPART			WOF_IN046: unused
47	RW_WCLRPART			WOF_IN047: unused
48	RW_WCLRPART			WOF_IN048: unused
49	RW_WCLRPART			WOF_IN049: unused
50	RW_WCLRPART			WOF_IN050: unused
51	RW_WCLRPART			WOF_IN051: unused
52	RW_WCLRPART			WOF_IN052: unused
53	RW_WCLRPART			WOF_IN053: unused

XSTOP Mask - OLD FIR_MASK
Addr:	0000000001040040 (SCOM) 0000000001040050 (SCOM1) 0000000001040060 (SCOM2)
Name:	TP.TPCHIP.TPC.XSTOP_MASK
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:53	TP.TPCHIP.TPC.EPS.FIR.COMP.XSTOP_MASK_Q_INST.LATC.L2(0:53) [000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0	RW	WO_OR	WO_CLEAR	XSTOP_MASK_UNUSED: Unused XSTOP Mask bit0
1	RW	WO_OR	WO_CLEAR	XSTOP_MASK01: XSTOP Mask for bit1 - 0=firing 1=blocked - OLD FIR_MASK
2	RW	WO_OR	WO_CLEAR	XSTOP_MASK02: XSTOP Mask for bit2 - 0=firing 1=blocked - OLD FIR_MASK
3	RW	WO_OR	WO_CLEAR	XSTOP_MASK03: XSTOP Mask for bit3 - 0=firing 1=blocked - OLD FIR_MASK
4	RW	WO_OR	WO_CLEAR	XSTOP_MASK04: XSTOP Mask for bit4 - 0=firing 1=blocked - OLD FIR_MASK
5	RW	WO_OR	WO_CLEAR	XSTOP_MASK05: XSTOP Mask for bit5 - 0=firing 1=blocked - OLD FIR_MASK
6	RW	WO_OR	WO_CLEAR	XSTOP_MASK06: XSTOP Mask for bit6 - 0=firing 1=blocked - OLD FIR_MASK
7	RW	WO_OR	WO_CLEAR	XSTOP_MASK07: XSTOP Mask for bit7 - 0=firing 1=blocked - OLD FIR_MASK
8	RW	WO_OR	WO_CLEAR	XSTOP_MASK08: XSTOP Mask for bit8 - 0=firing 1=blocked - OLD FIR_MASK
9	RW	WO_OR	WO_CLEAR	XSTOP_MASK09: XSTOP Mask for bit9 - 0=firing 1=blocked - OLD FIR_MASK
10	RW	WO_OR	WO_CLEAR	XSTOP_MASK10: XSTOP Mask for bit10 - 0=firing 1=blocked - OLD FIR_MASK
11	RW	WO_OR	WO_CLEAR	XSTOP_MASK11: XSTOP Mask for bit11 - 0=firing 1=blocked - OLD FIR_MASK
12	RW	WO_OR	WO_CLEAR	XSTOP_MASK12: XSTOP Mask for bit12 - 0=firing 1=blocked - OLD FIR_MASK
13	RW	WO_OR	WO_CLEAR	XSTOP_MASK13: XSTOP Mask for bit13 - 0=firing 1=blocked - OLD FIR_MASK
14	RW	WO_OR	WO_CLEAR	XSTOP_MASK14: XSTOP Mask for bit14 - 0=firing 1=blocked - OLD FIR_MASK
15	RW	WO_OR	WO_CLEAR	XSTOP_MASK15: XSTOP Mask for bit15 - 0=firing 1=blocked - OLD FIR_MASK
16	RW	WO_OR	WO_CLEAR	XSTOP_MASK16: XSTOP Mask for bit16 - 0=firing 1=blocked - OLD FIR_MASK
17	RW	WO_OR	WO_CLEAR	XSTOP_MASK17: XSTOP Mask for bit17 - 0=firing 1=blocked - OLD FIR_MASK
18	RW	WO_OR	WO_CLEAR	XSTOP_MASK18: XSTOP Mask for bit18 - 0=firing 1=blocked - OLD FIR_MASK
19	RW	WO_OR	WO_CLEAR	XSTOP_MASK19: XSTOP Mask for bit19 - 0=firing 1=blocked - OLD FIR_MASK
20	RW	WO_OR	WO_CLEAR	XSTOP_MASK20: XSTOP Mask for bit20 - 0=firing 1=blocked - OLD FIR_MASK
21	RW	WO_OR	WO_CLEAR	XSTOP_MASK21: XSTOP Mask for bit21 - 0=firing 1=blocked - OLD FIR_MASK
22	RW	WO_OR	WO_CLEAR	XSTOP_MASK22: XSTOP Mask for bit22 - 0=firing 1=blocked - OLD FIR_MASK
23	RW	WO_OR	WO_CLEAR	XSTOP_MASK23: XSTOP Mask for bit23 - 0=firing 1=blocked - OLD FIR_MASK
24	RW	WO_OR	WO_CLEAR	XSTOP_MASK24: XSTOP Mask for bit24 - 0=firing 1=blocked - OLD FIR_MASK
25	RW	WO_OR	WO_CLEAR	XSTOP_MASK25: XSTOP Mask for bit25 - 0=firing 1=blocked - OLD FIR_MASK
26	RW	WO_OR	WO_CLEAR	XSTOP_MASK26: XSTOP Mask for bit26 - 0=firing 1=blocked - OLD FIR_MASK
27	RW	WO_OR	WO_CLEAR	XSTOP_MASK27: XSTOP Mask for bit27 - 0=firing 1=blocked - OLD FIR_MASK
28	RW	WO_OR	WO_CLEAR	XSTOP_MASK28: XSTOP Mask for bit28 - 0=firing 1=blocked - OLD FIR_MASK
29	RW	WO_OR	WO_CLEAR	XSTOP_MASK29: XSTOP Mask for bit29 - 0=firing 1=blocked - OLD FIR_MASK
30	RW	WO_OR	WO_CLEAR	XSTOP_MASK30: XSTOP Mask for bit30 - 0=firing 1=blocked - OLD FIR_MASK
31	RW	WO_OR	WO_CLEAR	XSTOP_MASK31: XSTOP Mask for bit31 - 0=firing 1=blocked - OLD FIR_MASK
32	RW	WO_OR	WO_CLEAR	XSTOP_MASK32: XSTOP Mask for bit32 - 0=firing 1=blocked - OLD FIR_MASK
33	RW	WO_OR	WO_CLEAR	XSTOP_MASK33: XSTOP Mask for bit33 - 0=firing 1=blocked - OLD FIR_MASK
34	RW	WO_OR	WO_CLEAR	XSTOP_MASK34: XSTOP Mask for bit34 - 0=firing 1=blocked - OLD FIR_MASK
35	RW	WO_OR	WO_CLEAR	XSTOP_MASK35: XSTOP Mask for bit35 - 0=firing 1=blocked - OLD FIR_MASK
36	RW	WO_OR	WO_CLEAR	XSTOP_MASK36: XSTOP Mask for bit36 - 0=firing 1=blocked - OLD FIR_MASK
37	RW	WO_OR	WO_CLEAR	XSTOP_MASK37: XSTOP Mask for bit37 - 0=firing 1=blocked - OLD FIR_MASK
38	RW	WO_OR	WO_CLEAR	XSTOP_MASK38: XSTOP Mask for bit38 - 0=firing 1=blocked - OLD FIR_MASK
39	RW	WO_OR	WO_CLEAR	XSTOP_MASK39: XSTOP Mask for bit39 - 0=firing 1=blocked - OLD FIR_MASK
40	RW	WO_OR	WO_CLEAR	XSTOP_MASK40: XSTOP Mask for bit40 - 0=firing 1=blocked - OLD FIR_MASK
41	RW	WO_OR	WO_CLEAR	XSTOP_MASK41: XSTOP Mask for bit41 - 0=firing 1=blocked - OLD FIR_MASK
42	RW	WO_OR	WO_CLEAR	XSTOP_MASK42: XSTOP Mask for bit42 - 0=firing 1=blocked - OLD FIR_MASK
43	RW	WO_OR	WO_CLEAR	XSTOP_MASK43: XSTOP Mask for bit43 - 0=firing 1=blocked - OLD FIR_MASK
44	RW	WO_OR	WO_CLEAR	XSTOP_MASK44: XSTOP Mask for bit44 - 0=firing 1=blocked - OLD FIR_MASK
45	RW	WO_OR	WO_CLEAR	XSTOP_MASK45: XSTOP Mask for bit45 - 0=firing 1=blocked - OLD FIR_MASK
46	RW	WO_OR	WO_CLEAR	XSTOP_MASK46: XSTOP Mask for bit46 - 0=firing 1=blocked - OLD FIR_MASK
47	RW	WO_OR	WO_CLEAR	XSTOP_MASK47: XSTOP Mask for bit47 - 0=firing 1=blocked - OLD FIR_MASK
48	RW	WO_OR	WO_CLEAR	XSTOP_MASK48: XSTOP Mask for bit48 - 0=firing 1=blocked - OLD FIR_MASK
49	RW	WO_OR	WO_CLEAR	XSTOP_MASK49: XSTOP Mask for bit49 - 0=firing 1=blocked - OLD FIR_MASK
50	RW	WO_OR	WO_CLEAR	XSTOP_MASK50: XSTOP Mask for bit50 - 0=firing 1=blocked - OLD FIR_MASK
51	RW	WO_OR	WO_CLEAR	XSTOP_MASK51: XSTOP Mask for bit51 - 0=firing 1=blocked - OLD FIR_MASK
52	RW	WO_OR	WO_CLEAR	XSTOP_MASK52: XSTOP Mask for bit52 - 0=firing 1=blocked - OLD FIR_MASK
53	RW	WO_OR	WO_CLEAR	XSTOP_MASK53: XSTOP Mask for bit53 - 0=firing 1=blocked - OLD FIR_MASK

RECOV Mask - OLD FIR_MASK
Addr:	0000000001040041 (SCOM) 0000000001040051 (SCOM1) 0000000001040061 (SCOM2)
Name:	TP.TPCHIP.TPC.RECOV_MASK
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:53	TP.TPCHIP.TPC.EPS.FIR.COMP.RECOV_MASK_Q_INST.LATC.L2(0:53) [000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0	RW	WO_OR	WO_CLEAR	RECOV_MASK_UNUSED: Unused RECOV Mask bit0
1	RW	WO_OR	WO_CLEAR	RECOV_MASK01: RECOV Mask for bit1 - 0=firing 1=blocked - OLD FIR_MASK
2	RW	WO_OR	WO_CLEAR	RECOV_MASK02: RECOV Mask for bit2 - 0=firing 1=blocked - OLD FIR_MASK
3	RW	WO_OR	WO_CLEAR	RECOV_MASK03: RECOV Mask for bit3 - 0=firing 1=blocked - OLD FIR_MASK
4	RW	WO_OR	WO_CLEAR	RECOV_MASK04: RECOV Mask for bit4 - 0=firing 1=blocked - OLD FIR_MASK
5	RW	WO_OR	WO_CLEAR	RECOV_MASK05: RECOV Mask for bit5 - 0=firing 1=blocked - OLD FIR_MASK
6	RW	WO_OR	WO_CLEAR	RECOV_MASK06: RECOV Mask for bit6 - 0=firing 1=blocked - OLD FIR_MASK
7	RW	WO_OR	WO_CLEAR	RECOV_MASK07: RECOV Mask for bit7 - 0=firing 1=blocked - OLD FIR_MASK
8	RW	WO_OR	WO_CLEAR	RECOV_MASK08: RECOV Mask for bit8 - 0=firing 1=blocked - OLD FIR_MASK
9	RW	WO_OR	WO_CLEAR	RECOV_MASK09: RECOV Mask for bit9 - 0=firing 1=blocked - OLD FIR_MASK
10	RW	WO_OR	WO_CLEAR	RECOV_MASK010: RECOV Mask for bit10 - 0=firing 1=blocked - OLD FIR_MASK
11	RW	WO_OR	WO_CLEAR	RECOV_MASK011: RECOV Mask for bit11 - 0=firing 1=blocked - OLD FIR_MASK
12	RW	WO_OR	WO_CLEAR	RECOV_MASK012: RECOV Mask for bit12 - 0=firing 1=blocked - OLD FIR_MASK
13	RW	WO_OR	WO_CLEAR	RECOV_MASK013: RECOV Mask for bit13 - 0=firing 1=blocked - OLD FIR_MASK
14	RW	WO_OR	WO_CLEAR	RECOV_MASK014: RECOV Mask for bit14 - 0=firing 1=blocked - OLD FIR_MASK
15	RW	WO_OR	WO_CLEAR	RECOV_MASK015: RECOV Mask for bit15 - 0=firing 1=blocked - OLD FIR_MASK
16	RW	WO_OR	WO_CLEAR	RECOV_MASK016: RECOV Mask for bit16 - 0=firing 1=blocked - OLD FIR_MASK
17	RW	WO_OR	WO_CLEAR	RECOV_MASK017: RECOV Mask for bit17 - 0=firing 1=blocked - OLD FIR_MASK
18	RW	WO_OR	WO_CLEAR	RECOV_MASK018: RECOV Mask for bit18 - 0=firing 1=blocked - OLD FIR_MASK
19	RW	WO_OR	WO_CLEAR	RECOV_MASK019: RECOV Mask for bit19 - 0=firing 1=blocked - OLD FIR_MASK
20	RW	WO_OR	WO_CLEAR	RECOV_MASK020: RECOV Mask for bit20 - 0=firing 1=blocked - OLD FIR_MASK
21	RW	WO_OR	WO_CLEAR	RECOV_MASK021: RECOV Mask for bit21 - 0=firing 1=blocked - OLD FIR_MASK
22	RW	WO_OR	WO_CLEAR	RECOV_MASK022: RECOV Mask for bit22 - 0=firing 1=blocked - OLD FIR_MASK
23	RW	WO_OR	WO_CLEAR	RECOV_MASK023: RECOV Mask for bit23 - 0=firing 1=blocked - OLD FIR_MASK
24	RW	WO_OR	WO_CLEAR	RECOV_MASK024: RECOV Mask for bit24 - 0=firing 1=blocked - OLD FIR_MASK
25	RW	WO_OR	WO_CLEAR	RECOV_MASK025: RECOV Mask for bit25 - 0=firing 1=blocked - OLD FIR_MASK
26	RW	WO_OR	WO_CLEAR	RECOV_MASK026: RECOV Mask for bit26 - 0=firing 1=blocked - OLD FIR_MASK
27	RW	WO_OR	WO_CLEAR	RECOV_MASK027: RECOV Mask for bit27 - 0=firing 1=blocked - OLD FIR_MASK
28	RW	WO_OR	WO_CLEAR	RECOV_MASK028: RECOV Mask for bit28 - 0=firing 1=blocked - OLD FIR_MASK
29	RW	WO_OR	WO_CLEAR	RECOV_MASK029: RECOV Mask for bit29 - 0=firing 1=blocked - OLD FIR_MASK
30	RW	WO_OR	WO_CLEAR	RECOV_MASK030: RECOV Mask for bit30 - 0=firing 1=blocked - OLD FIR_MASK
31	RW	WO_OR	WO_CLEAR	RECOV_MASK031: RECOV Mask for bit31 - 0=firing 1=blocked - OLD FIR_MASK
32	RW	WO_OR	WO_CLEAR	RECOV_MASK032: RECOV Mask for bit32 - 0=firing 1=blocked - OLD FIR_MASK
33	RW	WO_OR	WO_CLEAR	RECOV_MASK033: RECOV Mask for bit33 - 0=firing 1=blocked - OLD FIR_MASK
34	RW	WO_OR	WO_CLEAR	RECOV_MASK034: RECOV Mask for bit34 - 0=firing 1=blocked - OLD FIR_MASK
35	RW	WO_OR	WO_CLEAR	RECOV_MASK035: RECOV Mask for bit35 - 0=firing 1=blocked - OLD FIR_MASK
36	RW	WO_OR	WO_CLEAR	RECOV_MASK036: RECOV Mask for bit36 - 0=firing 1=blocked - OLD FIR_MASK
37	RW	WO_OR	WO_CLEAR	RECOV_MASK037: RECOV Mask for bit37 - 0=firing 1=blocked - OLD FIR_MASK
38	RW	WO_OR	WO_CLEAR	RECOV_MASK038: RECOV Mask for bit38 - 0=firing 1=blocked - OLD FIR_MASK
39	RW	WO_OR	WO_CLEAR	RECOV_MASK039: RECOV Mask for bit39 - 0=firing 1=blocked - OLD FIR_MASK
40	RW	WO_OR	WO_CLEAR	RECOV_MASK040: RECOV Mask for bit40 - 0=firing 1=blocked - OLD FIR_MASK
41	RW	WO_OR	WO_CLEAR	RECOV_MASK041: RECOV Mask for bit41 - 0=firing 1=blocked - OLD FIR_MASK
42	RW	WO_OR	WO_CLEAR	RECOV_MASK042: RECOV Mask for bit42 - 0=firing 1=blocked - OLD FIR_MASK
43	RW	WO_OR	WO_CLEAR	RECOV_MASK043: RECOV Mask for bit43 - 0=firing 1=blocked - OLD FIR_MASK
44	RW	WO_OR	WO_CLEAR	RECOV_MASK044: RECOV Mask for bit44 - 0=firing 1=blocked - OLD FIR_MASK
45	RW	WO_OR	WO_CLEAR	RECOV_MASK045: RECOV Mask for bit45 - 0=firing 1=blocked - OLD FIR_MASK
46	RW	WO_OR	WO_CLEAR	RECOV_MASK046: RECOV Mask for bit46 - 0=firing 1=blocked - OLD FIR_MASK
47	RW	WO_OR	WO_CLEAR	RECOV_MASK047: RECOV Mask for bit47 - 0=firing 1=blocked - OLD FIR_MASK
48	RW	WO_OR	WO_CLEAR	RECOV_MASK048: RECOV Mask for bit48 - 0=firing 1=blocked - OLD FIR_MASK
49	RW	WO_OR	WO_CLEAR	RECOV_MASK049: RECOV Mask for bit49 - 0=firing 1=blocked - OLD FIR_MASK
50	RW	WO_OR	WO_CLEAR	RECOV_MASK050: RECOV Mask for bit50 - 0=firing 1=blocked - OLD FIR_MASK
51	RW	WO_OR	WO_CLEAR	RECOV_MASK051: RECOV Mask for bit51 - 0=firing 1=blocked - OLD FIR_MASK
52	RW	WO_OR	WO_CLEAR	RECOV_MASK052: RECOV Mask for bit52 - 0=firing 1=blocked - OLD FIR_MASK
53	RW	WO_OR	WO_CLEAR	RECOV_MASK053: RECOV Mask for bit53 - 0=firing 1=blocked - OLD FIR_MASK

Special Attention Mask
Addr:	0000000001040042 (SCOM) 0000000001040052 (SCOM1) 0000000001040062 (SCOM2)
Name:	TP.TPCHIP.TPC.SPATTN_MASK
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:35	TP.TPCHIP.TPC.EPS.FIR.COMP.SPATTN_MASK_Q_INST.LATC.L2(0:35) [000000000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0	RW	WO_OR	WO_CLEAR	SPATTN_MASK_UNUSED: Unused SPATTN Mask bit0
1	RW	WO_OR	WO_CLEAR	SPATTN_MASK01: SPATTN Mask for bit1 - 0=firing 1=blocked
2	RW	WO_OR	WO_CLEAR	SPATTN_MASK02: SPATTN Mask for bit2 - 0=firing 1=blocked
3	RW	WO_OR	WO_CLEAR	SPATTN_MASK03: SPATTN Mask for bit3 - 0=firing 1=blocked
4	RW	WO_OR	WO_CLEAR	SPATTN_MASK04: SPATTN Mask for bit4 - 0=firing 1=blocked
5	RW	WO_OR	WO_CLEAR	SPATTN_MASK05: SPATTN Mask for bit5 - 0=firing 1=blocked
6	RW	WO_OR	WO_CLEAR	SPATTN_MASK06: SPATTN Mask for bit6 - 0=firing 1=blocked
7	RW	WO_OR	WO_CLEAR	SPATTN_MASK07: SPATTN Mask for bit7 - 0=firing 1=blocked
8	RW	WO_OR	WO_CLEAR	SPATTN_MASK08: SPATTN Mask for bit8 - 0=firing 1=blocked
9	RW	WO_OR	WO_CLEAR	SPATTN_MASK09: SPATTN Mask for bit9 - 0=firing 1=blocked
10	RW	WO_OR	WO_CLEAR	SPATTN_MASK10: SPATTN Mask for bit10 - 0=firing 1=blocked
11	RW	WO_OR	WO_CLEAR	SPATTN_MASK11: SPATTN Mask for bit11 - 0=firing 1=blocked
12	RW	WO_OR	WO_CLEAR	SPATTN_MASK12: SPATTN Mask for bit12 - 0=firing 1=blocked
13	RW	WO_OR	WO_CLEAR	SPATTN_MASK13: SPATTN Mask for bit13 - 0=firing 1=blocked
14	RW	WO_OR	WO_CLEAR	SPATTN_MASK14: SPATTN Mask for bit14 - 0=firing 1=blocked
15	RW	WO_OR	WO_CLEAR	SPATTN_MASK15: SPATTN Mask for bit15 - 0=firing 1=blocked
16	RW	WO_OR	WO_CLEAR	SPATTN_MASK16: SPATTN Mask for bit16 - 0=firing 1=blocked
17	RW	WO_OR	WO_CLEAR	SPATTN_MASK17: SPATTN Mask for bit17 - 0=firing 1=blocked
18	RW	WO_OR	WO_CLEAR	SPATTN_MASK18: SPATTN Mask for bit18 - 0=firing 1=blocked
19	RW	WO_OR	WO_CLEAR	SPATTN_MASK19: SPATTN Mask for bit19 - 0=firing 1=blocked
20	RW	WO_OR	WO_CLEAR	SPATTN_MASK20: SPATTN Mask for bit20 - 0=firing 1=blocked
21	RW	WO_OR	WO_CLEAR	SPATTN_MASK21: SPATTN Mask for bit21 - 0=firing 1=blocked
22	RW	WO_OR	WO_CLEAR	SPATTN_MASK22: SPATTN Mask for bit22 - 0=firing 1=blocked
23	RW	WO_OR	WO_CLEAR	SPATTN_MASK23: SPATTN Mask for bit23 - 0=firing 1=blocked
24	RW	WO_OR	WO_CLEAR	SPATTN_MASK24: SPATTN Mask for bit24 - 0=firing 1=blocked
25	RW	WO_OR	WO_CLEAR	SPATTN_MASK25: SPATTN Mask for bit25 - 0=firing 1=blocked
26	RW	WO_OR	WO_CLEAR	SPATTN_MASK26: SPATTN Mask for bit26 - 0=firing 1=blocked
27	RW	WO_OR	WO_CLEAR	SPATTN_MASK27: SPATTN Mask for bit27 - 0=firing 1=blocked
28	RW	WO_OR	WO_CLEAR	SPATTN_MASK28: SPATTN Mask for bit28 - 0=firing 1=blocked
29	RW	WO_OR	WO_CLEAR	SPATTN_MASK29: SPATTN Mask for bit29 - 0=firing 1=blocked
30	RW	WO_OR	WO_CLEAR	SPATTN_MASK30: SPATTN Mask for bit30 - 0=firing 1=blocked
31	RW	WO_OR	WO_CLEAR	SPATTN_MASK31: SPATTN Mask for bit31 - 0=firing 1=blocked
32	RW	WO_OR	WO_CLEAR	SPATTN_MASK32: SPATTN Mask for bit32 - 0=firing 1=blocked
33	RW	WO_OR	WO_CLEAR	SPATTN_MASK33: SPATTN Mask for bit33 - 0=firing 1=blocked
34	RW	WO_OR	WO_CLEAR	SPATTN_MASK34: SPATTN Mask for bit34 - 0=firing 1=blocked
35	RW	WO_OR	WO_CLEAR	SPATTN_MASK35: SPATTN Mask for bit35 - 0=firing 1=blocked

Local XSTOP Mask
Addr:	0000000001040043 (SCOM) 0000000001040053 (SCOM1) 0000000001040063 (SCOM2)
Name:	TP.TPCHIP.TPC.LOCAL_XSTOP_MASK
Constant(s):	PERV_1_LOCAL_XSTOP_MASK
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.TPC.EPS.FIR.COMP.LXSTOP_MASK_Q_INST.LATC.L2(0:15) [0000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0	RW	WO_OR	WO_CLEAR	LOCAL_XSTOP_MASK_UNUSED: Unused Local XSTOP Mask bit0
1	RW	WO_OR	WO_CLEAR	LOCAL_XSTOP_MASK01: Local XSTOP Mask for bit1 - 0=firing 1=blocked
2	RW	WO_OR	WO_CLEAR	LOCAL_XSTOP_MASK02: Local XSTOP Mask for bit2 - 0=firing 1=blocked
3	RW	WO_OR	WO_CLEAR	LOCAL_XSTOP_MASK03: Local XSTOP Mask for bit3 - 0=firing 1=blocked
4	RW	WO_OR	WO_CLEAR	LOCAL_XSTOP_MASK04: Local XSTOP Mask for bit4 - 0=firing 1=blocked
5	RW	WO_OR	WO_CLEAR	LOCAL_XSTOP_MASK05: Local XSTOP Mask for bit5 - 0=firing 1=blocked
6	RW	WO_OR	WO_CLEAR	LOCAL_XSTOP_MASK06: Local XSTOP Mask for bit6 - 0=firing 1=blocked
7	RW	WO_OR	WO_CLEAR	LOCAL_XSTOP_MASK07: Local XSTOP Mask for bit7 - 0=firing 1=blocked
8	RW	WO_OR	WO_CLEAR	LOCAL_XSTOP_MASK08: Local XSTOP Mask for bit8 - 0=firing 1=blocked
9	RW	WO_OR	WO_CLEAR	LOCAL_XSTOP_MASK09: Local XSTOP Mask for bit9 - 0=firing 1=blocked
10	RW	WO_OR	WO_CLEAR	LOCAL_XSTOP_MASK10: Local XSTOP Mask for bit10 - 0=firing 1=blocked
11	RW	WO_OR	WO_CLEAR	LOCAL_XSTOP_MASK11: Local XSTOP Mask for bit11 - 0=firing 1=blocked
12	RW	WO_OR	WO_CLEAR	LOCAL_XSTOP_MASK12: Local XSTOP Mask for bit12 - 0=firing 1=blocked
13	RW	WO_OR	WO_CLEAR	LOCAL_XSTOP_MASK13: Local XSTOP Mask for bit13 - 0=firing 1=blocked
14	RW	WO_OR	WO_CLEAR	LOCAL_XSTOP_MASK14: Local XSTOP Mask for bit14 - 0=firing 1=blocked
15	RW	WO_OR	WO_CLEAR	LOCAL_XSTOP_MASK15: Local XSTOP Mask for bit15 - 0=firing 1=blocked

Host Attention Mask
Addr:	0000000001040044 (SCOM) 0000000001040054 (SCOM1) 0000000001040064 (SCOM2)
Name:	TP.TPCHIP.TPC.HOSTATTN_MASK
Constant(s):	PERV_1_HOSTATTN_MASK
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:53	TP.TPCHIP.TPC.EPS.FIR.COMP.HOSTATTN_MASK_Q_INST.LATC.L2(0:53) [000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK_UNUSED: Unused HOSTATTN Mask bit0
1	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK01: HOSTATTN Mask for bit1 - 0=firing 1=blocked
2	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK02: HOSTATTN Mask for bit2 - 0=firing 1=blocked
3	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK03: HOSTATTN Mask for bit3 - 0=firing 1=blocked
4	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK04: HOSTATTN Mask for bit4 - 0=firing 1=blocked
5	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK05: HOSTATTN Mask for bit5 - 0=firing 1=blocked
6	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK06: HOSTATTN Mask for bit6 - 0=firing 1=blocked
7	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK07: HOSTATTN Mask for bit7 - 0=firing 1=blocked
8	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK08: HOSTATTN Mask for bit8 - 0=firing 1=blocked
9	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK09: HOSTATTN Mask for bit9 - 0=firing 1=blocked
10	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK10: HOSTATTN Mask for bit10 - 0=firing 1=blocked
11	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK11: HOSTATTN Mask for bit11 - 0=firing 1=blocked
12	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK12: HOSTATTN Mask for bit12 - 0=firing 1=blocked
13	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK13: HOSTATTN Mask for bit13 - 0=firing 1=blocked
14	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK14: HOSTATTN Mask for bit14 - 0=firing 1=blocked
15	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK15: HOSTATTN Mask for bit15 - 0=firing 1=blocked
16	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK16: HOSTATTN Mask for bit16 - 0=firing 1=blocked
17	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK17: HOSTATTN Mask for bit17 - 0=firing 1=blocked
18	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK18: HOSTATTN Mask for bit18 - 0=firing 1=blocked
19	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK19: HOSTATTN Mask for bit19 - 0=firing 1=blocked
20	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK20: HOSTATTN Mask for bit20 - 0=firing 1=blocked
21	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK21: HOSTATTN Mask for bit21 - 0=firing 1=blocked
22	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK22: HOSTATTN Mask for bit22 - 0=firing 1=blocked
23	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK23: HOSTATTN Mask for bit23 - 0=firing 1=blocked
24	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK24: HOSTATTN Mask for bit24 - 0=firing 1=blocked
25	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK25: HOSTATTN Mask for bit25 - 0=firing 1=blocked
26	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK26: HOSTATTN Mask for bit26 - 0=firing 1=blocked
27	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK27: HOSTATTN Mask for bit27 - 0=firing 1=blocked
28	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK28: HOSTATTN Mask for bit28 - 0=firing 1=blocked
29	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK29: HOSTATTN Mask for bit29 - 0=firing 1=blocked
30	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK30: HOSTATTN Mask for bit30 - 0=firing 1=blocked
31	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK31: HOSTATTN Mask for bit31 - 0=firing 1=blocked
32	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK32: HOSTATTN Mask for bit32 - 0=firing 1=blocked
33	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK33: HOSTATTN Mask for bit33 - 0=firing 1=blocked
34	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK34: HOSTATTN Mask for bit34 - 0=firing 1=blocked
35	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK35: HOSTATTN Mask for bit35 - 0=firing 1=blocked
36	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK36: HOSTATTN Mask for bit36 - 0=firing 1=blocked
37	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK37: HOSTATTN Mask for bit37 - 0=firing 1=blocked
38	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK38: HOSTATTN Mask for bit38 - 0=firing 1=blocked
39	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK39: HOSTATTN Mask for bit39 - 0=firing 1=blocked
40	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK40: HOSTATTN Mask for bit40 - 0=firing 1=blocked
41	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK41: HOSTATTN Mask for bit41 - 0=firing 1=blocked
42	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK42: HOSTATTN Mask for bit42 - 0=firing 1=blocked
43	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK43: HOSTATTN Mask for bit43 - 0=firing 1=blocked
44	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK44: HOSTATTN Mask for bit44 - 0=firing 1=blocked
45	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK45: HOSTATTN Mask for bit45 - 0=firing 1=blocked
46	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK46: HOSTATTN Mask for bit46 - 0=firing 1=blocked
47	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK47: HOSTATTN Mask for bit47 - 0=firing 1=blocked
48	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK48: HOSTATTN Mask for bit48 - 0=firing 1=blocked
49	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK49: HOSTATTN Mask for bit49 - 0=firing 1=blocked
50	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK50: HOSTATTN Mask for bit50 - 0=firing 1=blocked
51	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK51: HOSTATTN Mask for bit51 - 0=firing 1=blocked
52	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK52: HOSTATTN Mask for bit52 - 0=firing 1=blocked
53	RW	WO_OR	WO_CLEAR	HOSTATTN_MASK53: HOSTATTN Mask for bit53 - 0=firing 1=blocked

Any Local Error Mask - to PCB (old SUMMARY MASK)
Addr:	0000000001040080 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.FIR.ANY_LOCAL_ERR_MASK
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:4	TP.TPCHIP.TPC.EPS.FIR.COMP.ANY_LOCAL_ERR_MASK_Q_INST.LATC.L2(0:4) [00000]
Bit(s)	SCOM			Dial: Description
0	RW			MASK_XSTOP_TO_PCB: mask XSTOP to pcb - 1=blocking
1	RW			MASK_RECOV_TO_PCB: mask RECOV to pcb - 1=blocking
2	RW			MASK_SPATTN_TO_PCB: mask SPATTN to pcb - 1=blocking
3	RW			MASK_LOCAL_XSTOP_TO_PCB: mask LOCAL XSTOP to pcb - 1=blocking
4	RW			MASK_HOSTATTN_TO_PCB: mask HOSTATTN to pcb - 1=blocking

Clockstop on XSTOP Mask1 Reg - to CC XSTOP1
Addr:	0000000001040081 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.FIR.CLKSTOP_ON_XSTOP_MASK1
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.TPC.EPS.FIR.COMP.CLKSTOP_ON_XSTOP_MASK1_Q_INST.LATC.L2(0:26) [000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			CLKSTOP_MASK1_XSTOP_ERR: any xstop triggers clockstop using ClockControl XSTOP1
1	RW			CLKSTOP_MASK1_RECOV_ERR: any recov triggers clockstop using ClockControl XSTOP1
2	RW			CLKSTOP_MASK1_SPATTN_ERR: any spattn triggers clockstop using ClockControl XSTOP1
3	RW			CLKSTOP_MASK1_LXSTOP_ERR: any xstop triggers clockstop using ClockControl XSTOP1
4	RW			CLKSTOP_MASK1_HOSTATTN_ERR: any hostattn triggers clockstop using ClockControl XSTOP1
5	RW			CLKSTOP_MASK1_SYS_XSTOP_ERR: system xstop triggers clockstop using ClockControl XSTOP1
6	RW			CLKSTOP_MASK1_SYS_XSTOP_STAGED_ERR: oob7 -system xstop staged triggers Clockstop using ClockControl XSTOP1
7	RW			CLKSTOP_MASK1_DBG_TRIG_ERR: dbg triggers Clockstop using ClockControl XSTOP1
8	RW			CLKSTOP_MASK1_UNUSED08: Unused
9	RW			CLKSTOP_MASK1_UNUSED09: Unused
10	RW			CLKSTOP_MASK1_UNUSED10: Unused
11	RW			CLKSTOP_MASK1_UNUSED11: Unused
12	RW			CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP01: Local XSTOP bit 1 triggers Clockstop using ClockControl XSTOP1
13	RW			CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP02: Local XSTOP bit 2 triggers Clockstop using ClockControl XSTOP1
14	RW			CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP03: Local XSTOP bit 3 triggers Clockstop using ClockControl XSTOP1
15	RW			CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP04: Local XSTOP bit 4 triggers Clockstop using ClockControl XSTOP1
16	RW			CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP05: Local XSTOP bit 5 triggers Clockstop using ClockControl XSTOP1
17	RW			CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP06: Local XSTOP bit 6 triggers Clockstop using ClockControl XSTOP1
18	RW			CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP07: Local XSTOP bit 7 triggers Clockstop using ClockControl XSTOP1
19	RW			CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP08: Local XSTOP bit 8 triggers Clockstop using ClockControl XSTOP1
20	RW			CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP09: Local XSTOP bit 9 triggers Clockstop using ClockControl XSTOP1
21	RW			CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP10: Local XSTOP bit 10 triggers Clockstop using ClockControl XSTOP1
22	RW			CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP11: Local XSTOP bit 11 triggers Clockstop using ClockControl XSTOP1
23	RW			CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP12: Local XSTOP bit 12 triggers Clockstop using ClockControl XSTOP1
24	RW			CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP13: Local XSTOP bit 13 triggers Clockstop using ClockControl XSTOP1
25	RW			CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP14: Local XSTOP bit 14 triggers Clockstop using ClockControl XSTOP1
26	RW			CLKSTOP_MASK1_UNIT_TC_FIR_LOCAL_XSTOP15: Local XSTOP bit 15 triggers Clockstop using ClockControl XSTOP1

Clockstop on XSTOP Mask2 Reg - to CC XSTOP2
Addr:	0000000001040082 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.FIR.CLKSTOP_ON_XSTOP_MASK2
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.TPC.EPS.FIR.COMP.CLKSTOP_ON_XSTOP_MASK2_Q_INST.LATC.L2(0:26) [000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			CLKSTOP_MASK2_XSTOP_ERR: any xstop triggers clockstop using ClockControl XSTOP2
1	RW			CLKSTOP_MASK2_RECOV_ERR: any recov triggers clockstop using ClockControl XSTOP2
2	RW			CLKSTOP_MASK2_SPATTN_ERR: any spattn triggers clockstop using ClockControl XSTOP2
3	RW			CLKSTOP_MASK2_LXSTOP_ERR: any xstop triggers clockstop using ClockControl XSTOP2
4	RW			CLKSTOP_MASK2_HOSTATTN_ERR: any hostattn triggers clockstop using ClockControl XSTOP2
5	RW			CLKSTOP_MASK2_SYS_XSTOP_ERR: system xstop triggers clockstop using ClockControl XSTOP2
6	RW			CLKSTOP_MASK2_SYS_XSTOP_STAGED_ERR: oob7 -system xstop staged triggers Clockstop using ClockControl XSTOP2
7	RW			CLKSTOP_MASK2_DBG_TRIG_ERR: dbg triggers Clockstop using ClockControl XSTOP2
8	RW			CLKSTOP_MASK2_UNUSED08: Unused
9	RW			CLKSTOP_MASK2_UNUSED09: Unused
10	RW			CLKSTOP_MASK2_UNUSED20: Unused
11	RW			CLKSTOP_MASK2_UNUSED22: Unused
12	RW			CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP01: Local XSTOP bit 1 triggers Clockstop using ClockControl XSTOP2
13	RW			CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP02: Local XSTOP bit 2 triggers Clockstop using ClockControl XSTOP2
14	RW			CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP03: Local XSTOP bit 3 triggers Clockstop using ClockControl XSTOP2
15	RW			CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP04: Local XSTOP bit 4 triggers Clockstop using ClockControl XSTOP2
16	RW			CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP05: Local XSTOP bit 5 triggers Clockstop using ClockControl XSTOP2
17	RW			CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP06: Local XSTOP bit 6 triggers Clockstop using ClockControl XSTOP2
18	RW			CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP07: Local XSTOP bit 7 triggers Clockstop using ClockControl XSTOP2
19	RW			CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP08: Local XSTOP bit 8 triggers Clockstop using ClockControl XSTOP2
20	RW			CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP09: Local XSTOP bit 9 triggers Clockstop using ClockControl XSTOP2
21	RW			CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP010: Local XSTOP bit 10 triggers Clockstop using ClockControl XSTOP2
22	RW			CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP011: Local XSTOP bit 11 triggers Clockstop using ClockControl XSTOP2
23	RW			CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP012: Local XSTOP bit 12 triggers Clockstop using ClockControl XSTOP2
24	RW			CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP013: Local XSTOP bit 13 triggers Clockstop using ClockControl XSTOP2
25	RW			CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP014: Local XSTOP bit 14 triggers Clockstop using ClockControl XSTOP2
26	RW			CLKSTOP_MASK2_UNIT_TC_FIR_LOCAL_XSTOP015: Local XSTOP bit 15 triggers Clockstop using ClockControl XSTOP2

Clockstop on XSTOP Mask3 Reg - to CC XSTOP3
Addr:	0000000001040083 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.FIR.CLKSTOP_ON_XSTOP_MASK3
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.TPC.EPS.FIR.COMP.CLKSTOP_ON_XSTOP_MASK3_Q_INST.LATC.L2(0:26) [000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			CLKSTOP_MASK3_XSTOP_ERR: any xstop triggers clockstop using ClockControl XSTOP3
1	RW			CLKSTOP_MASK3_RECOV_ERR: any recov triggers clockstop using ClockControl XSTOP3
2	RW			CLKSTOP_MASK3_SPATTN_ERR: any spattn triggers clockstop using ClockControl XSTOP3
3	RW			CLKSTOP_MASK3_LXSTOP_ERR: any xstop triggers clockstop using ClockControl XSTOP3
4	RW			CLKSTOP_MASK3_HOSTATTN_ERR: any hostattn triggers clockstop using ClockControl XSTOP3
5	RW			CLKSTOP_MASK3_SYS_XSTOP_ERR: system xstop triggers clockstop using ClockControl XSTOP3
6	RW			CLKSTOP_MASK3_SYS_XSTOP_STAGED_ERR: oob7 -system xstop staged triggers Clockstop using ClockControl XSTOP3
7	RW			CLKSTOP_MASK3_DBG_TRIG_ERR: dbg triggers Clockstop using ClockControl XSTOP3
8	RW			CLKSTOP_MASK3_UNUSED08: Unused
9	RW			CLKSTOP_MASK3_UNUSED09: Unused
10	RW			CLKSTOP_MASK3_UNUSED10: Unused
11	RW			CLKSTOP_MASK3_UNUSED11: Unused
12	RW			CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP01: Local XSTOP bit 1 triggers Clockstop using ClockControl XSTOP3
13	RW			CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP02: Local XSTOP bit 2 triggers Clockstop using ClockControl XSTOP3
14	RW			CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP03: Local XSTOP bit 3 triggers Clockstop using ClockControl XSTOP3
15	RW			CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP04: Local XSTOP bit 4 triggers Clockstop using ClockControl XSTOP3
16	RW			CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP05: Local XSTOP bit 5 triggers Clockstop using ClockControl XSTOP3
17	RW			CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP06: Local XSTOP bit 6 triggers Clockstop using ClockControl XSTOP3
18	RW			CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP07: Local XSTOP bit 7 triggers Clockstop using ClockControl XSTOP3
19	RW			CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP08: Local XSTOP bit 8 triggers Clockstop using ClockControl XSTOP3
20	RW			CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP09: Local XSTOP bit 9 triggers Clockstop using ClockControl XSTOP3
21	RW			CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP010: Local XSTOP bit 10 triggers Clockstop using ClockControl XSTOP3
22	RW			CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP011: Local XSTOP bit 11 triggers Clockstop using ClockControl XSTOP3
23	RW			CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP012: Local XSTOP bit 12 triggers Clockstop using ClockControl XSTOP3
24	RW			CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP013: Local XSTOP bit 13 triggers Clockstop using ClockControl XSTOP3
25	RW			CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP014: Local XSTOP bit 14 triggers Clockstop using ClockControl XSTOP3
26	RW			CLKSTOP_MASK3_UNIT_TC_FIR_LOCAL_XSTOP015: Local XSTOP bit 15 triggers Clockstop using ClockControl XSTOP3

Clockstop on XSTOP Mask4 Reg - to CC XSTOP4
Addr:	0000000001040084 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.FIR.CLKSTOP_ON_XSTOP_MASK4
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.TPC.EPS.FIR.COMP.CLKSTOP_ON_XSTOP_MASK4_Q_INST.LATC.L2(0:26) [000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			CLKSTOP_MASK4_XSTOP_ERR: any xstop triggers clockstop using ClockControl XSTOP4
1	RW			CLKSTOP_MASK4_RECOV_ERR: any recov triggers clockstop using ClockControl XSTOP4
2	RW			CLKSTOP_MASK4_SPATTN_ERR: any spattn triggers clockstop using ClockControl XSTOP4
3	RW			CLKSTOP_MASK4_LXSTOP_ERR: any xstop triggers clockstop using ClockControl XSTOP4
4	RW			CLKSTOP_MASK4_HOSTATTN_ERR: any hostattn triggers clockstop using ClockControl XSTOP4
5	RW			CLKSTOP_MASK4_SYS_XSTOP_ERR: system xstop triggers clockstop using ClockControl XSTOP4
6	RW			CLKSTOP_MASK4_SYS_XSTOP_STAGED_ERR: oob7 -system xstop staged triggers Clockstop using ClockControl XSTOP4
7	RW			CLKSTOP_MASK4_DBG_TRIG_ERR: dbg triggers Clockstop using ClockControl XSTOP4
8	RW			CLKSTOP_MASK4_UNUSED08: Unused
9	RW			CLKSTOP_MASK4_UNUSED09: Unused
10	RW			CLKSTOP_MASK4_UNUSED10: Unused
11	RW			CLKSTOP_MASK4_UNUSED11: Unused
12	RW			CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP01: Local XSTOP bit 1 triggers Clockstop using ClockControl XSTOP4
13	RW			CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP02: Local XSTOP bit 2 triggers Clockstop using ClockControl XSTOP4
14	RW			CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP03: Local XSTOP bit 3 triggers Clockstop using ClockControl XSTOP4
15	RW			CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP04: Local XSTOP bit 4 triggers Clockstop using ClockControl XSTOP4
16	RW			CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP05: Local XSTOP bit 5 triggers Clockstop using ClockControl XSTOP4
17	RW			CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP06: Local XSTOP bit 6 triggers Clockstop using ClockControl XSTOP4
18	RW			CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP07: Local XSTOP bit 7 triggers Clockstop using ClockControl XSTOP4
19	RW			CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP08: Local XSTOP bit 8 triggers Clockstop using ClockControl XSTOP4
20	RW			CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP09: Local XSTOP bit 9 triggers Clockstop using ClockControl XSTOP4
21	RW			CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP10: Local XSTOP bit 10 triggers Clockstop using ClockControl XSTOP4
22	RW			CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP11: Local XSTOP bit 11 triggers Clockstop using ClockControl XSTOP4
23	RW			CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP12: Local XSTOP bit 12 triggers Clockstop using ClockControl XSTOP4
24	RW			CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP13: Local XSTOP bit 13 triggers Clockstop using ClockControl XSTOP4
25	RW			CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP14: Local XSTOP bit 14 triggers Clockstop using ClockControl XSTOP4
26	RW			CLKSTOP_MASK4_UNIT_TC_FIR_LOCAL_XSTOP15: Local XSTOP bit 15 triggers Clockstop using ClockControl XSTOP4

Clockstop on XSTOP Mask5 Reg - to CC XSTOP5
Addr:	0000000001040085 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.FIR.CLKSTOP_ON_XSTOP_MASK5
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:26	TP.TPCHIP.TPC.EPS.FIR.COMP.CLKSTOP_ON_XSTOP_MASK5_Q_INST.LATC.L2(0:26) [000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			CLKSTOP_MASK5_XSTOP_ERR: any xstop triggers clockstop using ClockControl XSTOP5
1	RW			CLKSTOP_MASK5_RECOV_ERR: any recov triggers clockstop using ClockControl XSTOP5
2	RW			CLKSTOP_MASK5_SPATTN_ERR: any spattn triggers clockstop using ClockControl XSTOP5
3	RW			CLKSTOP_MASK5_LXSTOP_ERR: any xstop triggers clockstop using ClockControl XSTOP5
4	RW			CLKSTOP_MASK5_HOSTATTN_ERR: any hostattn triggers clockstop using ClockControl XSTOP5
5	RW			CLKSTOP_MASK5_SYS_XSTOP_ERR: system xstop triggers clockstop using ClockControl XSTOP5
6	RW			CLKSTOP_MASK5_SYS_XSTOP_STAGED_ERR: oob7 -system xstop staged triggers Clockstop using ClockControl XSTOP5
7	RW			CLKSTOP_MASK5_DBG_TRIG_ERR: dbg triggers Clockstop using ClockControl XSTOP5
8	RW			CLKSTOP_MASK5_UNUSED08: Unused
9	RW			CLKSTOP_MASK5_UNUSED09: Unused
10	RW			CLKSTOP_MASK5_UNUSED10: Unused
11	RW			CLKSTOP_MASK5_UNUSED11: Unused
12	RW			CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP01: Local XSTOP bit 1 triggers Clockstop using ClockControl XSTOP5
13	RW			CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP02: Local XSTOP bit 2 triggers Clockstop using ClockControl XSTOP5
14	RW			CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP03: Local XSTOP bit 3 triggers Clockstop using ClockControl XSTOP5
15	RW			CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP04: Local XSTOP bit 4 triggers Clockstop using ClockControl XSTOP5
16	RW			CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP05: Local XSTOP bit 5 triggers Clockstop using ClockControl XSTOP5
17	RW			CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP06: Local XSTOP bit 6 triggers Clockstop using ClockControl XSTOP5
18	RW			CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP07: Local XSTOP bit 7 triggers Clockstop using ClockControl XSTOP5
19	RW			CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP08: Local XSTOP bit 8 triggers Clockstop using ClockControl XSTOP5
20	RW			CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP09: Local XSTOP bit 9 triggers Clockstop using ClockControl XSTOP5
21	RW			CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP10: Local XSTOP bit 10 triggers Clockstop using ClockControl XSTOP5
22	RW			CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP11: Local XSTOP bit 11 triggers Clockstop using ClockControl XSTOP5
23	RW			CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP12: Local XSTOP bit 12 triggers Clockstop using ClockControl XSTOP5
24	RW			CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP13: Local XSTOP bit 13 triggers Clockstop using ClockControl XSTOP5
25	RW			CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP14: Local XSTOP bit 14 triggers Clockstop using ClockControl XSTOP5
26	RW			CLKSTOP_MASK5_UNIT_TC_FIR_LOCAL_XSTOP15: Local XSTOP bit 15 triggers Clockstop using ClockControl XSTOP5

Mode Register
Addr:	0000000001040088 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.FIR.MODE_REG
Constant(s):	PERV_1_MODE_REG
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.TPC.EPS.FIR.COMP.MODE_REG_Q_INST.LATC.L2(0:15) [0000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			XSTOP_LOCK_XSTOP: XSTOP will lock XSTOP register - default = 1
1	RW			XSTOP_LOCK_RECOV: XSTOP will lock RECOV register - default = 1
2	RW			XSTOP_LOCK_SPATTN: XSTOP will lock SPATTN register - default = 0
3	RW			XSTOP_LOCK_LXSTOP: XSTOP will lock LXSTOP register - default = 0
4	RW			XSTOP_LOCK_HOSTATTN: XSTOP will lock HOSTATTN register - default = 0
5	RW			MODE_REG05: unused
6	RW			DISABLE_IOPB_ERR: disable_iopb_err XSTOP trigger to IO/PB
7	RW			MODE_REG07: unused
8	RW			MODE_REG08: unused
9	RW			MASK_DIRECT_ERROR: mask direct error XSTOP trigger to Core
10	RW			MODE_REG10: unused
11	RW			MODE_REG11: unused
12	RW			MODE_REG12: unused
13	RW			MODE_REG13: unused
14	RW			MODE_REG14: unused
15	RW			MODE_REG15: unused

Local FIR
Addr:	0000000001040100 (SCOM) 0000000001040101 (SCOM1) 0000000001040102 (SCOM2)
Name:	TP.TPCHIP.TPC.LOCAL_FIR
Constant(s):	PERV_1_LOCAL_FIR
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.TPC.EPS.FIR.LFIR.LOCALFIR.FIR.FIR.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0	RWX	WOX_AND	WOX_OR	LFIR_ERROR_CFIR: CFIR - Parity or PCB access error TYPE:RECOV CLEAR:only LFIR
1	RWX	WOX_AND	WOX_OR	LFIR_ERROR_CPLT_CTRL: CPLT_CTRL - PCB access error TYPE:RECOV CLEAR:by next PCB req
2	RWX	WOX_AND	WOX_OR	LFIR_ERROR_CC_PCB: CC - PCB access error TYPE:RECOV READ STATUS:nn03000F CLEAR:write 0 to nn03000F
3	RWX	WOX_AND	WOX_OR	LFIR_ERROR_CC_OTHERS: CC - Clock Control Error TYPE:RECOV READ STATUS:nn03000F CLEAR:write 0 to nn03000F
4	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN04: PSC - PSCOM access error TYPE:RECOV READ STATUS:nn010001 CLEAR:write 0 to nn010001
5	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN05: PSC - internal or ring interface error TYPE:RECOV READ STATUS:nn010001 CLEAR:write 0 to nn010001
6	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN06: THERM - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out TYPE:RECOV - MASK afterwards READ STATUS:nn050013 CLEAR:only scan0
7	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN07: THERM - pcb error TYPE:RECOV CLEAR:by next PCB req
8	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN08: THERMTRIP - Critical temperature indicator TYPE:MASKED (unused) CLEAR:only LFIR
9	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN09: THERMTRIP - Fatal temperature indicator TYPE:MASKED (unused) CLEAR:only LFIR
10	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN10: VOLTTRIP - Voltage sense error TYPE:MASKED (unused) CLEAR:only LFIR
11	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN11: DBG - scom parity fail TYPE:RECOV CLEAR:by next SCOM req
12	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN12: reserved TYPE:MASKED (unused) CLEAR:only LFIR
13	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN13: reserved TYPE:MASKED (unused) CLEAR:only LFIR
14	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN14: reserved TYPE:MASKED (unused) CLEAR:only LFIR
15	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN15: reserved TYPE:MASKED (unused) CLEAR:only LFIR
16	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN16: reserved TYPE:MASKED (unused) CLEAR:only LFIR
17	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN17: reserved TYPE:MASKED (unused) CLEAR:only LFIR
18	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN18: reserved TYPE:MASKED (unused) CLEAR:only LFIR
19	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN19: reserved TYPE:MASKED (unused) CLEAR:only LFIR
20	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN20: Trace00 - scom parity err TYPE:RECOV CLEAR:by next SCOM req
21	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN21: ITR - FMU error TYPE:MASKED CLEAR:scan0
22	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN22: ITR - PCB error TYPE:RECOV CLEAR:by next PCB req
23	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN23: PCB Master - timeout TYPE:RECOV READ STATUS:000F001F CLEAR:write 0 to 000F001F
24	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN24: I2CM - Parity errors TYPE:RECOV READ STATUS:ring dump CLEAR:write 0 to A0001
25	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN25: TOD - any error TYPE:RECOV READ STATUS:00040030 CLEAR:write 0 to 00040030
26	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN26: TOD - access error PIB TYPE:RECOV READ STATUS:00040030 CLEAR:write 0 to 00040030
27	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN27: TOD - unused tie0 TYPE:RECOV CLEAR:only LFIR
28	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN28: Error reported from one or more PCB Slaves TYPE:MASKED - PLL lock/unlock READ STATUS:nn0F001F CLEAR:write 0 to nn0F001F
29	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN29: SBE - PPE int hardware error TYPE:MASKED (handled by SBE) CLEAR:only LFIR
30	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN30: SBE - PPE ext hardware error TYPE:MASKED (handled by SBE) CLEAR:only LFIR
31	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN31: SBE- PPE code error TYPE:MASKED (handled by SBE) CLEAR:only LFIR
32	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN32: SBE - PPE debug code breakpoint TYPE:MASKED (debug) CLEAR:only LFIR
33	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN33: SBE - PPE in halted state TYPE:MASKED (Status) CLEAR:only LFIR
34	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN34: SBE - PPE watchdog timeout TYPE:MASKED (handled by SBE) CLEAR:only LFIR
35	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN35: SBE - unused tie0 TYPE:MASKED (unused) CLEAR:only LFIR
36	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN36: SBE - unused tie0 TYPE:MASKED (unused) CLEAR:only LFIR
37	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN37: SBE - PPE triggers DBG TYPE:MASKED (debug) CLEAR:only LFIR
38	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN38: OTP - SCOM access errors & single ecc correctable errors TYPE:RECOV READ STATUS:x010002 CLEAR:by next SCOM req
39	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN39: TPIO External Trigger TYPE:MASKED CLEAR:
40	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN40: PCB Master - Multicast group member count underrun (MC misconfig) TYPE:RECOV READ STATUS:000F001F CLEAR:write 0 to 000F001F
41	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN41: PCB Master - Parity ERR TYPE:RECOV READ STATUS:000F001F CLEAR:write 0 to 000F001F
42	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN42: RCS - OSC0 Error TYPE:RECOV CLEAR:only LFIR
43	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN43: RCS - OSC1 Error TYPE:RECOV CLEAR:only LFIR
44	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN44: RCS - Up/down counter A unlock TYPE:RECOV CLEAR:only LFIR
45	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN45: RCS - Up/down counter B unlock TYPE:RECOV CLEAR:only LFIR
46	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN46: PIBMEM TYPE:RECOV CLEAR:only LFIR
47	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN47: PIBMEM TYPE:RECOV CLEAR:only LFIR
48	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN48: OTP - ECC UE or CE count overflow TYPE:RECOV READ STATUS:x010002 CLEAR:by next SCOM req
49	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN49: Nest DPLL: DCO empty TYPE:MASKED (Status,debug) CLEAR:
50	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN50: Nest DPLL: DCO full TYPE:MASKED (Status,debug) CLEAR:
51	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN51: Nest DPLL: internal error TYPE:MASKED (unused) CLEAR:only LFIR
52	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN52: PAU DPLL: DCO empty TYPE:MASKED (Status,debug) CLEAR:
53	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN53: PAU DPLL: DCO full TYPE:MASKED (Status,debug) CLEAR:
54	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN54: PAU DPLL: internal error TYPE:MASKED (unused) CLEAR:only LFIR
55	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN55: SPI Master 0 Err TYPE:RECOV READ STATUS:all SPI regs CLEAR:re-write SPI regs
56	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN56: SPI Master 1 Err TYPE:RECOV READ STATUS:all SPI regs CLEAR:re-write SPI regs
57	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN57: SPI Master 2 Err TYPE:RECOV READ STATUS:all SPI regs CLEAR:re-write SPI regs
58	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN58: SPI Master 3 Err TYPE:RECOV READ STATUS:all SPI regs CLEAR:re-write SPI regs
59	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN59: SPI Master 4 Err TYPE:RECOV READ STATUS:all SPI regs CLEAR:re-write SPI regs
60	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN60: unused TYPE:MASKED (unused) CLEAR:only LFIR
61	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN61: unused TYPE:MASKED (unused) CLEAR:only LFIR
62	RWX	WOX_AND	WOX_OR	LFIR_ERROR_IN62: unused TYPE:MASKED (unused) CLEAR:only LFIR
63	RWX	WOX_AND	WOX_OR	LFIR_ERROR_EXT_LOCAL_XSTOP: ext_local_xstop TYPE:MASKED (unused) CLEAR:

Local FIR Mask
Addr:	0000000001040103 (SCOM) 0000000001040104 (SCOM1) 0000000001040105 (SCOM2)
Name:	TP.TPCHIP.TPC.EPS.FIR.LOCAL_FIR_MASK
Constant(s):	PERV_1_LOCAL_FIR_MASK
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.TPC.EPS.FIR.LFIR.LOCALFIR.FIR.FIR_MASK.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0	RW	WO_AND	WO_OR	LFIR_MASK00: MASK
1	RW	WO_AND	WO_OR	LFIR_MASK01: MASK
2	RW	WO_AND	WO_OR	LFIR_MASK02: MASK
3	RW	WO_AND	WO_OR	LFIR_MASK03: MASK
4	RW	WO_AND	WO_OR	LFIR_MASK04: MASK
5	RW	WO_AND	WO_OR	LFIR_MASK05: MASK
6	RW	WO_AND	WO_OR	LFIR_MASK06: MASK
7	RW	WO_AND	WO_OR	LFIR_MASK07: MASK
8	RW	WO_AND	WO_OR	LFIR_MASK08: MASK
9	RW	WO_AND	WO_OR	LFIR_MASK09: MASK
10	RW	WO_AND	WO_OR	LFIR_MASK10: MASK
11	RW	WO_AND	WO_OR	LFIR_MASK11: MASK
12	RW	WO_AND	WO_OR	LFIR_MASK12: MASK
13	RW	WO_AND	WO_OR	LFIR_MASK13: MASK
14	RW	WO_AND	WO_OR	LFIR_MASK14: MASK
15	RW	WO_AND	WO_OR	LFIR_MASK15: MASK
16	RW	WO_AND	WO_OR	LFIR_MASK16: MASK
17	RW	WO_AND	WO_OR	LFIR_MASK17: MASK
18	RW	WO_AND	WO_OR	LFIR_MASK18: MASK
19	RW	WO_AND	WO_OR	LFIR_MASK19: MASK
20	RW	WO_AND	WO_OR	LFIR_MASK20: MASK
21	RW	WO_AND	WO_OR	LFIR_MASK21: MASK
22	RW	WO_AND	WO_OR	LFIR_MASK22: MASK
23	RW	WO_AND	WO_OR	LFIR_MASK23: MASK
24	RW	WO_AND	WO_OR	LFIR_MASK24: MASK
25	RW	WO_AND	WO_OR	LFIR_MASK25: MASK
26	RW	WO_AND	WO_OR	LFIR_MASK26: MASK
27	RW	WO_AND	WO_OR	LFIR_MASK27: MASK
28	RW	WO_AND	WO_OR	LFIR_MASK28: MASK
29	RW	WO_AND	WO_OR	LFIR_MASK29: MASK
30	RW	WO_AND	WO_OR	LFIR_MASK30: MASK
31	RW	WO_AND	WO_OR	LFIR_MASK31: MASK
32	RW	WO_AND	WO_OR	LFIR_MASK32: MASK
33	RW	WO_AND	WO_OR	LFIR_MASK33: MASK
34	RW	WO_AND	WO_OR	LFIR_MASK34: MASK
35	RW	WO_AND	WO_OR	LFIR_MASK35: MASK
36	RW	WO_AND	WO_OR	LFIR_MASK36: MASK
37	RW	WO_AND	WO_OR	LFIR_MASK37: MASK
38	RW	WO_AND	WO_OR	LFIR_MASK38: MASK
39	RW	WO_AND	WO_OR	LFIR_MASK39: MASK
40	RW	WO_AND	WO_OR	LFIR_MASK40: MASK
41	RW	WO_AND	WO_OR	LFIR_MASK41: MASK
42	RW	WO_AND	WO_OR	LFIR_MASK42: MASK
43	RW	WO_AND	WO_OR	LFIR_MASK43: MASK
44	RW	WO_AND	WO_OR	LFIR_MASK44: MASK
45	RW	WO_AND	WO_OR	LFIR_MASK45: MASK
46	RW	WO_AND	WO_OR	LFIR_MASK46: MASK
47	RW	WO_AND	WO_OR	LFIR_MASK47: MASK
48	RW	WO_AND	WO_OR	LFIR_MASK48: MASK
49	RW	WO_AND	WO_OR	LFIR_MASK49: MASK
50	RW	WO_AND	WO_OR	LFIR_MASK50: MASK
51	RW	WO_AND	WO_OR	LFIR_MASK51: MASK
52	RW	WO_AND	WO_OR	LFIR_MASK52: MASK
53	RW	WO_AND	WO_OR	LFIR_MASK53: MASK
54	RW	WO_AND	WO_OR	LFIR_MASK54: MASK
55	RW	WO_AND	WO_OR	LFIR_MASK55: MASK
56	RW	WO_AND	WO_OR	LFIR_MASK56: MASK
57	RW	WO_AND	WO_OR	LFIR_MASK57: MASK
58	RW	WO_AND	WO_OR	LFIR_MASK58: MASK
59	RW	WO_AND	WO_OR	LFIR_MASK59: MASK
60	RW	WO_AND	WO_OR	LFIR_MASK60: MASK
61	RW	WO_AND	WO_OR	LFIR_MASK61: MASK
62	RW	WO_AND	WO_OR	LFIR_MASK62: MASK
63	RW	WO_AND	WO_OR	LFIR_MASK63: MASK

Local FIR Action0
Addr:	0000000001040106 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.FIR.LOCAL_FIR_ACTION0
Constant(s):	PERV_1_LOCAL_FIR_ACTION0
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.TPC.EPS.FIR.LFIR.LOCALFIR.FIR.DO_ACTION0.FIR_ACTION0.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			FIR_ACTION0_IN00: ACTION0
1	RW			FIR_ACTION0_IN01: ACTION0
2	RW			FIR_ACTION0_IN02: ACTION0
3	RW			FIR_ACTION0_IN03: ACTION0
4	RW			FIR_ACTION0_IN04: ACTION0
5	RW			FIR_ACTION0_IN05: ACTION0
6	RW			FIR_ACTION0_IN06: ACTION0
7	RW			FIR_ACTION0_IN07: ACTION0
8	RW			FIR_ACTION0_IN08: ACTION0
9	RW			FIR_ACTION0_IN09: ACTION0
10	RW			FIR_ACTION0_IN10: ACTION0
11	RW			FIR_ACTION0_IN11: ACTION0
12	RW			FIR_ACTION0_IN12: ACTION0
13	RW			FIR_ACTION0_IN13: ACTION0
14	RW			FIR_ACTION0_IN14: ACTION0
15	RW			FIR_ACTION0_IN15: ACTION0
16	RW			FIR_ACTION0_IN16: ACTION0
17	RW			FIR_ACTION0_IN17: ACTION0
18	RW			FIR_ACTION0_IN18: ACTION0
19	RW			FIR_ACTION0_IN19: ACTION0
20	RW			FIR_ACTION0_IN20: ACTION0
21	RW			FIR_ACTION0_IN21: ACTION0
22	RW			FIR_ACTION0_IN22: ACTION0
23	RW			FIR_ACTION0_IN23: ACTION0
24	RW			FIR_ACTION0_IN24: ACTION0
25	RW			FIR_ACTION0_IN25: ACTION0
26	RW			FIR_ACTION0_IN26: ACTION0
27	RW			FIR_ACTION0_IN27: ACTION0
28	RW			FIR_ACTION0_IN28: ACTION0
29	RW			FIR_ACTION0_IN29: ACTION0
30	RW			FIR_ACTION0_IN30: ACTION0
31	RW			FIR_ACTION0_IN31: ACTION0
32	RW			FIR_ACTION0_IN32: ACTION0
33	RW			FIR_ACTION0_IN33: ACTION0
34	RW			FIR_ACTION0_IN34: ACTION0
35	RW			FIR_ACTION0_IN35: ACTION0
36	RW			FIR_ACTION0_IN36: ACTION0
37	RW			FIR_ACTION0_IN37: ACTION0
38	RW			FIR_ACTION0_IN38: ACTION0
39	RW			FIR_ACTION0_IN39: ACTION0
40	RW			FIR_ACTION0_IN40: ACTION0
41	RW			FIR_ACTION0_IN41: ACTION0
42	RW			FIR_ACTION0_IN42: ACTION0
43	RW			FIR_ACTION0_IN43: ACTION0
44	RW			FIR_ACTION0_IN44: ACTION0
45	RW			FIR_ACTION0_IN45: ACTION0
46	RW			FIR_ACTION0_IN46: ACTION0
47	RW			FIR_ACTION0_IN47: ACTION0
48	RW			FIR_ACTION0_IN48: ACTION0
49	RW			FIR_ACTION0_IN49: ACTION0
50	RW			FIR_ACTION0_IN50: ACTION0
51	RW			FIR_ACTION0_IN51: ACTION0
52	RW			FIR_ACTION0_IN52: ACTION0
53	RW			FIR_ACTION0_IN53: ACTION0
54	RW			FIR_ACTION0_IN54: ACTION0
55	RW			FIR_ACTION0_IN55: ACTION0
56	RW			FIR_ACTION0_IN56: ACTION0
57	RW			FIR_ACTION0_IN57: ACTION0
58	RW			FIR_ACTION0_IN58: ACTION0
59	RW			FIR_ACTION0_IN59: ACTION0
60	RW			FIR_ACTION0_IN60: ACTION0
61	RW			FIR_ACTION0_IN61: ACTION0
62	RW			FIR_ACTION0_IN62: ACTION0
63	RW			FIR_ACTION0_IN63: ACTION0

Local FIR Action1
Addr:	0000000001040107 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.FIR.LOCAL_FIR_ACTION1
Constant(s):	PERV_1_LOCAL_FIR_ACTION1
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.TPC.EPS.FIR.LFIR.LOCALFIR.FIR.DO_ACTION1.FIR_ACTION1.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			FIR_ACTION1_IN00: ACTION1
1	RW			FIR_ACTION1_IN01: ACTION1
2	RW			FIR_ACTION1_IN02: ACTION1
3	RW			FIR_ACTION1_IN03: ACTION1
4	RW			FIR_ACTION1_IN04: ACTION1
5	RW			FIR_ACTION1_IN05: ACTION1
6	RW			FIR_ACTION1_IN06: ACTION1
7	RW			FIR_ACTION1_IN07: ACTION1
8	RW			FIR_ACTION1_IN08: ACTION1
9	RW			FIR_ACTION1_IN09: ACTION1
10	RW			FIR_ACTION1_IN10: ACTION1
11	RW			FIR_ACTION1_IN11: ACTION1
12	RW			FIR_ACTION1_IN12: ACTION1
13	RW			FIR_ACTION1_IN13: ACTION1
14	RW			FIR_ACTION1_IN14: ACTION1
15	RW			FIR_ACTION1_IN15: ACTION1
16	RW			FIR_ACTION1_IN16: ACTION1
17	RW			FIR_ACTION1_IN17: ACTION1
18	RW			FIR_ACTION1_IN18: ACTION1
19	RW			FIR_ACTION1_IN19: ACTION1
20	RW			FIR_ACTION1_IN20: ACTION1
21	RW			FIR_ACTION1_IN21: ACTION1
22	RW			FIR_ACTION1_IN22: ACTION1
23	RW			FIR_ACTION1_IN23: ACTION1
24	RW			FIR_ACTION1_IN24: ACTION1
25	RW			FIR_ACTION1_IN25: ACTION1
26	RW			FIR_ACTION1_IN26: ACTION1
27	RW			FIR_ACTION1_IN27: ACTION1
28	RW			FIR_ACTION1_IN28: ACTION1
29	RW			FIR_ACTION1_IN29: ACTION1
30	RW			FIR_ACTION1_IN30: ACTION1
31	RW			FIR_ACTION1_IN31: ACTION1
32	RW			FIR_ACTION1_IN32: ACTION1
33	RW			FIR_ACTION1_IN33: ACTION1
34	RW			FIR_ACTION1_IN34: ACTION1
35	RW			FIR_ACTION1_IN35: ACTION1
36	RW			FIR_ACTION1_IN36: ACTION1
37	RW			FIR_ACTION1_IN37: ACTION1
38	RW			FIR_ACTION1_IN38: ACTION1
39	RW			FIR_ACTION1_IN39: ACTION1
40	RW			FIR_ACTION1_IN40: ACTION1
41	RW			FIR_ACTION1_IN41: ACTION1
42	RW			FIR_ACTION1_IN42: ACTION1
43	RW			FIR_ACTION1_IN43: ACTION1
44	RW			FIR_ACTION1_IN44: ACTION1
45	RW			FIR_ACTION1_IN45: ACTION1
46	RW			FIR_ACTION1_IN46: ACTION1
47	RW			FIR_ACTION1_IN47: ACTION1
48	RW			FIR_ACTION1_IN48: ACTION1
49	RW			FIR_ACTION1_IN49: ACTION1
50	RW			FIR_ACTION1_IN50: ACTION1
51	RW			FIR_ACTION1_IN51: ACTION1
52	RW			FIR_ACTION1_IN52: ACTION1
53	RW			FIR_ACTION1_IN53: ACTION1
54	RW			FIR_ACTION1_IN54: ACTION1
55	RW			FIR_ACTION1_IN55: ACTION1
56	RW			FIR_ACTION1_IN56: ACTION1
57	RW			FIR_ACTION1_IN57: ACTION1
58	RW			FIR_ACTION1_IN58: ACTION1
59	RW			FIR_ACTION1_IN59: ACTION1
60	RW			FIR_ACTION1_IN60: ACTION1
61	RW			FIR_ACTION1_IN61: ACTION1
62	RW			FIR_ACTION1_IN62: ACTION1
63	RW			FIR_ACTION1_IN63: ACTION1

Local FIR WOF
Addr:	0000000001040108 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.FIR.LOCAL_FIR_WOF
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.TPC.EPS.FIR.LFIR.LOCALFIR.FIR.WOF_LAT_YES.WOF.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW_WCLRPART			FIR_WOF_IN00: WOF
1	RW_WCLRPART			FIR_WOF_IN01: WOF
2	RW_WCLRPART			FIR_WOF_IN02: WOF
3	RW_WCLRPART			FIR_WOF_IN03: WOF
4	RW_WCLRPART			FIR_WOF_IN04: WOF
5	RW_WCLRPART			FIR_WOF_IN05: WOF
6	RW_WCLRPART			FIR_WOF_IN06: WOF
7	RW_WCLRPART			FIR_WOF_IN07: WOF
8	RW_WCLRPART			FIR_WOF_IN08: WOF
9	RW_WCLRPART			FIR_WOF_IN09: WOF
10	RW_WCLRPART			FIR_WOF_IN10: WOF
11	RW_WCLRPART			FIR_WOF_IN11: WOF
12	RW_WCLRPART			FIR_WOF_IN12: WOF
13	RW_WCLRPART			FIR_WOF_IN13: WOF
14	RW_WCLRPART			FIR_WOF_IN14: WOF
15	RW_WCLRPART			FIR_WOF_IN15: WOF
16	RW_WCLRPART			FIR_WOF_IN16: WOF
17	RW_WCLRPART			FIR_WOF_IN17: WOF
18	RW_WCLRPART			FIR_WOF_IN18: WOF
19	RW_WCLRPART			FIR_WOF_IN19: WOF
20	RW_WCLRPART			FIR_WOF_IN20: WOF
21	RW_WCLRPART			FIR_WOF_IN21: WOF
22	RW_WCLRPART			FIR_WOF_IN22: WOF
23	RW_WCLRPART			FIR_WOF_IN23: WOF
24	RW_WCLRPART			FIR_WOF_IN24: WOF
25	RW_WCLRPART			FIR_WOF_IN25: WOF
26	RW_WCLRPART			FIR_WOF_IN26: WOF
27	RW_WCLRPART			FIR_WOF_IN27: WOF
28	RW_WCLRPART			FIR_WOF_IN28: WOF
29	RW_WCLRPART			FIR_WOF_IN29: WOF
30	RW_WCLRPART			FIR_WOF_IN30: WOF
31	RW_WCLRPART			FIR_WOF_IN31: WOF
32	RW_WCLRPART			FIR_WOF_IN32: WOF
33	RW_WCLRPART			FIR_WOF_IN33: WOF
34	RW_WCLRPART			FIR_WOF_IN34: WOF
35	RW_WCLRPART			FIR_WOF_IN35: WOF
36	RW_WCLRPART			FIR_WOF_IN36: WOF
37	RW_WCLRPART			FIR_WOF_IN37: WOF
38	RW_WCLRPART			FIR_WOF_IN38: WOF
39	RW_WCLRPART			FIR_WOF_IN39: WOF
40	RW_WCLRPART			FIR_WOF_IN40: WOF
41	RW_WCLRPART			FIR_WOF_IN41: WOF
42	RW_WCLRPART			FIR_WOF_IN42: WOF
43	RW_WCLRPART			FIR_WOF_IN43: WOF
44	RW_WCLRPART			FIR_WOF_IN44: WOF
45	RW_WCLRPART			FIR_WOF_IN45: WOF
46	RW_WCLRPART			FIR_WOF_IN46: WOF
47	RW_WCLRPART			FIR_WOF_IN47: WOF
48	RW_WCLRPART			FIR_WOF_IN48: WOF
49	RW_WCLRPART			FIR_WOF_IN49: WOF
50	RW_WCLRPART			FIR_WOF_IN50: WOF
51	RW_WCLRPART			FIR_WOF_IN51: WOF
52	RW_WCLRPART			FIR_WOF_IN52: WOF
53	RW_WCLRPART			FIR_WOF_IN53: WOF
54	RW_WCLRPART			FIR_WOF_IN54: WOF
55	RW_WCLRPART			FIR_WOF_IN55: WOF
56	RW_WCLRPART			FIR_WOF_IN56: WOF
57	RW_WCLRPART			FIR_WOF_IN57: WOF
58	RW_WCLRPART			FIR_WOF_IN58: WOF
59	RW_WCLRPART			FIR_WOF_IN59: WOF
60	RW_WCLRPART			FIR_WOF_IN60: WOF
61	RW_WCLRPART			FIR_WOF_IN61: WOF
62	RW_WCLRPART			FIR_WOF_IN62: WOF
63	RW_WCLRPART			FIR_WOF_IN63: WOF

Local FIR Action2
Addr:	0000000001040109 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.FIR.LOCAL_FIR_ACTION2
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.TPC.EPS.FIR.LFIR.LOCALFIR.FIR.DO_ACTION2.FIR_ACTION2.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	RW			FIR_ACTION2_IN00: ACTION2
1	RW			FIR_ACTION2_IN01: ACTION2
2	RW			FIR_ACTION2_IN02: ACTION2
3	RW			FIR_ACTION2_IN03: ACTION2
4	RW			FIR_ACTION2_IN04: ACTION2
5	RW			FIR_ACTION2_IN05: ACTION2
6	RW			FIR_ACTION2_IN06: ACTION2
7	RW			FIR_ACTION2_IN07: ACTION2
8	RW			FIR_ACTION2_IN08: ACTION2
9	RW			FIR_ACTION2_IN09: ACTION2
10	RW			FIR_ACTION2_IN10: ACTION2
11	RW			FIR_ACTION2_IN11: ACTION2
12	RW			FIR_ACTION2_IN12: ACTION2
13	RW			FIR_ACTION2_IN13: ACTION2
14	RW			FIR_ACTION2_IN14: ACTION2
15	RW			FIR_ACTION2_IN15: ACTION2
16	RW			FIR_ACTION2_IN16: ACTION2
17	RW			FIR_ACTION2_IN17: ACTION2
18	RW			FIR_ACTION2_IN18: ACTION2
19	RW			FIR_ACTION2_IN19: ACTION2
20	RW			FIR_ACTION2_IN20: ACTION2
21	RW			FIR_ACTION2_IN21: ACTION2
22	RW			FIR_ACTION2_IN22: ACTION2
23	RW			FIR_ACTION2_IN23: ACTION2
24	RW			FIR_ACTION2_IN24: ACTION2
25	RW			FIR_ACTION2_IN25: ACTION2
26	RW			FIR_ACTION2_IN26: ACTION2
27	RW			FIR_ACTION2_IN27: ACTION2
28	RW			FIR_ACTION2_IN28: ACTION2
29	RW			FIR_ACTION2_IN29: ACTION2
30	RW			FIR_ACTION2_IN30: ACTION2
31	RW			FIR_ACTION2_IN31: ACTION2
32	RW			FIR_ACTION2_IN32: ACTION2
33	RW			FIR_ACTION2_IN33: ACTION2
34	RW			FIR_ACTION2_IN34: ACTION2
35	RW			FIR_ACTION2_IN35: ACTION2
36	RW			FIR_ACTION2_IN36: ACTION2
37	RW			FIR_ACTION2_IN37: ACTION2
38	RW			FIR_ACTION2_IN38: ACTION2
39	RW			FIR_ACTION2_IN39: ACTION2
40	RW			FIR_ACTION2_IN40: ACTION2
41	RW			FIR_ACTION2_IN41: ACTION2
42	RW			FIR_ACTION2_IN42: ACTION2
43	RW			FIR_ACTION2_IN43: ACTION2
44	RW			FIR_ACTION2_IN44: ACTION2
45	RW			FIR_ACTION2_IN45: ACTION2
46	RW			FIR_ACTION2_IN46: ACTION2
47	RW			FIR_ACTION2_IN47: ACTION2
48	RW			FIR_ACTION2_IN48: ACTION2
49	RW			FIR_ACTION2_IN49: ACTION2
50	RW			FIR_ACTION2_IN50: ACTION2
51	RW			FIR_ACTION2_IN51: ACTION2
52	RW			FIR_ACTION2_IN52: ACTION2
53	RW			FIR_ACTION2_IN53: ACTION2
54	RW			FIR_ACTION2_IN54: ACTION2
55	RW			FIR_ACTION2_IN55: ACTION2
56	RW			FIR_ACTION2_IN56: ACTION2
57	RW			FIR_ACTION2_IN57: ACTION2
58	RW			FIR_ACTION2_IN58: ACTION2
59	RW			FIR_ACTION2_IN59: ACTION2
60	RW			FIR_ACTION2_IN60: ACTION2
61	RW			FIR_ACTION2_IN61: ACTION2
62	RW			FIR_ACTION2_IN62: ACTION2
63	RW			FIR_ACTION2_IN63: ACTION2

DTS Thermal Sensor loop1 Results
Addr:	0000000001050000 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.THERM.WSUB.DTS_RESULT0
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:47	TP.TPCHIP.TPC.EPS.THERM.WSUB.THRESH.COMP.DTS_RESULT_REGQ_INT_INST.LATC.L2(0:47) [000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:15	ROX			DTS_0_RESULT: Calibrated DTS Result of sensor with id 0. EQ x50000: CORE0 ISU EQ x50020: CORE2 ISU N0,N1,PAUE,PAUW: DTS0 AXON,PCI,TP: n/a 0-11 sensor result, 12-13 trip, 14 spare, 15 valid
16:31	ROX			DTS_1_RESULT: Calibrated DTS Result of sensor with id 1. EQ x50000: CORE0 VSU EQ x50020: CORE2 VSU N0,N1,PAUE,PAUW: n/a AXON,PCI,TP: n/a 0-11 sensor result, 12-13 trip, 14 spare, 15 valid .
32:47	ROX			DTS_2_RESULT: Calibrated DTS Result of sensor with id 2. EQ x50000: CORE0 L3 EQ x50020: CORE2 L3 N0,N1,PAUE,PAUW: n/a AXON,PCI,TP: n/a 0-11 sensor result, 12-13 trip, 14 spare, 15 valid .
48:63	RO			constant=0b0000000000000000

DTS Thermal Sensor loop2 Results
Addr:	0000000001050001 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.THERM.WSUB.DTS_RESULT1
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:47	TP.TPCHIP.TPC.EPS.THERM.WSUB.THRESH.COMP.DTS_RESULT_REGQ_INT_INST.LATC.L2(48:95) [000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:15	ROX			DTS_4_RESULT: Calibrated DTS Result of sensor with id 4. EQ x50001: CORE1 ISU EQ x50021: CORE3 ISU N0,N1,PAUE,PAUW: n/a AXON,PCI,TP: n/a 0-11 sensor result, 12-13 trip, 14 spare, 15 valid .
16:31	ROX			DTS_5_RESULT: Calibrated DTS Result of sensor with id 5. EQ x50001: CORE1 VSU EQ x50021: CORE3 VSU N0,N1,PAUE,PAUW: n/a AXON,PCI,TP: n/a 0-11 sensor result, 12-13 trip, 14 spare, 15 valid .
32:47	ROX			DTS_6_RESULT: Calibrated DTS Result of sensor with id 6. EQ x50001: CORE1 L3 EQ x50021: CORE3 L3 N0,N1,PAUE,PAUW: n/a AXON,PCI,TP: n/a 0-11 sensor result, 12-13 trip, 14 spare, 15 valid .
48:63	RO			constant=0b0000000000000000

DTS Thermal Sensor loop3 Results
Addr:	0000000001050002 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.THERM.WSUB.DTS_RESULT2
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:15	TP.TPCHIP.TPC.EPS.THERM.WSUB.THRESH.COMP.DTS_RESULT_REGQ_INT_INST.LATC.L2(96:111) [0000000000000000]
Bit(s)	SCOM			Dial: Description
0:15	ROX			DTS_8_RESULT: Calibrated DTS Result of sensor with id 8. EQ x50002: Racetrack EQ x50022: n/a N0,N1,PAUE,PAUW: n/a AXON,PCI,TP: n/a 0-11 sensor result, 12-13 trip, 14 spare, 15 valid .
16:63	RO			constant=0b000000000000000000000000000000000000000000000000

DTS Trace Results
Addr:	0000000001050003 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.THERM.WSUB.DTS_TRC_RESULT
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:43	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.PCB.TIMESTAMP_COUNT_REG_LT_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000]
	44	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.PCB.TIMESTAMP_OVERFLOW_ERR_LT_INST.LATC.L2(0) [0]
	48:63	TP.TPCHIP.TPC.EPS.THERM.WSUB.THRESH.COMP.DTS_RESULT_REGQ_INT_INST.LATC.L2(16:31) [0000000000000000]
Bit(s)	SCOM			Dial: Description
0:43	ROX			TIMESTAMP_COUNTER_VALUE: Time stamp counter value during DTS trace mode.
44	ROX			TIMESTAMP_COUNTER_OVERFLOW_ERR: Over flow error bit of the time stamp counter value during DTS trace mode.
45:47	RO			constant=0b000
48:63	ROX			DTS_1_RESULT: Calibrated DTS Result of sensor with id 1. EQ x50000: CORE0 VSU EQ x50020: CORE2 VSU N0,N1,PAUE,PAUW: n/a AXON,PCI,TP: n/a 0-11 sensor result, 12-13 trip, 14 spare, 15 valid .

CPM & DTS enables and cntl's
Addr:	000000000105000F (SCOM)
Name:	TP.TPCHIP.TPC.EPS.THERM.WSUB.THERM_MODE_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:19	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.COMP.THERM_MODEREG_LT_0_INST.LATC.L2(0:19) [00000000000000000000]
	20:22	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.COMP.THERM_DTS_ENABLE_INTQ_INST.LATC.L2(0:2) [000]
	24:26	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.COMP.THERM_DTS_ENABLE_INTQ_INST.LATC.L2(3:5) [000]
	28	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.COMP.THERM_DTS_ENABLE_INTQ_INST.LATC.L2(6) [0]
Bit(s)	SCOM			Dial: Description
0	RW			THERM_DIS_CPM_BUBBLE_CORR: critical path result bubble correction active
1	RW			THERM_FORCE_THRES_ACT: force tpc_therm_thres_mac clock gating off and activates clocks
2:4	RW			THERM_THRES_TRIP_ENA: therm_thres_trip compare enables 1xx: trip0 - warning x1x: trip1 - critical xx1: trip2 - fatal
5	RW			THERM_DTS_SAMPLE_ENA: 0: no dts sampling, 1: dts sampling is enabled and below counter compare match can occur.
6:9	RW			THERM_SAMPLE_PULSE_CNT: A 16 MHz sample pulse is feed into an 18 Bit counter, with the therm_sample_pulse_cnt it is possible to select a highorder bit of the counter to enable a resolutions of sampling dtss between 2.5 us and 80 ms. An edge detection circuit detects the rising edge of the selected counter bit and this triggers a dts sample 0000: 16 ms 0001: 8 ms 0010: 4 ms 0011: 2 ms 0100: 1 ms 0101: 0.5 ms 0110: 250 us 0111: 125 us 1000: 62 .5us 1001: 31.3 us 1010: 15.6 us 1011: 7.8 us 1100: 3.9 us 1101: 2 us 1110: 1 us 1111: 0.5 us
10:11	RW			THERM_THRES_MODE_ENA: forces max or min mode in threshold unit: 00: is off 11: is ilegal 10: max mode 01: min mode
12	RW			DTS_TRIGGER_MODE: unused
13	RW			DTS_TRIGGER_SEL: unused
14	RW			THERM_THRES_OVERFLOW_MASK: 0 - therm_overflow_err will be enabled 1 - therm_overflow_err will be disabled
15	RW			THERM_MODE_UNUSED: unused
16:19	RW			THERM_DTS_READ_SEL: selects which dts result will be provided with pcb read addr_v(3): 0000: DTS 0 0001: DTS 1 0010: DTS 2 0100: DTS 4 0101: DTS 5 0110: DTS 6 1000: DTS 8 1111: Worst Case Sensor
20:22	RW			THERM_DTS_ENABLE_L1: loop1 dts enables: If there is only a single DTS enabled, it has to be the first DTS in a loop - here DTS 0 1xxx: DTS 0 available x1xx: DTS 1 available xx1x: DTS 2 available
23	RO			constant=0b0
24:26	RW			THERM_DTS_ENABLE_L2: loop2 dts enables: If there is only a single DTS enabled, it has to be the first DTS in a loop - here DTS 4 1xxx: DTS 4 available x1xx: DTS 5 available xx1x: DTS 6 available
27	RO			constant=0b0
28	RW			THERM_DTS_ENABLE_L3: dts enables: If there is only a single DTS enabled, it has to be the first DTS in a loop - here DTS 8 1xxx: DTS 8 available
29:36	RO			constant=0b00000000

Skitter Control Register
Addr:	0000000001050010 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.THERM.WSUB.SKITTER_MODE_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.SKIT.SKITTER_MODEREG_LT_0_INST.LATC.L2(0:7) [00000000]
	8:9	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.SKIT.SKITTER_MODEREG_LT_8_INST.LATC.L2(8:9) [00]
	44	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.SKIT.SKITTER_HOLD_SAMPLE_LT_INST.LATC.L2(0) [0]
	45	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.SKIT.SKITTER_DATA_V_LT_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	RW			SKITTER_HOLD_SAMPLE: forces skitter to hold current sample
1	RW			DISABLE_SKITTER_STICKINESS: if '0' accumulation mode, '1' samples new value each cycle and resets sticky value
2:3	RW			SKITTER_MODE_UNUSED1: unused
4:5	RW			SKITTER_HOLD_DBGTRIG_SEL: bit0: hold_on_trigger0 bit1: _on_trigger1
6:7	RW			SKITTER_RESET_TRIG_SEL: bit0: reset_sticky_on_trigger0 bit1: reset_sticky_on_trigger1
8:9	RW			SKITTER_SAMPLE_GUTS: selects guts to measure: 00: guts1 01: guts2 10: guts3 11: guts4
10:43	RO			constant=0b0000000000000000000000000000000000
44	ROX			SKITTER_HOLD_SAMPLE_WITH_TRIGGER: forces skitter to hold current sample on dbg trigger, this has highest priority
45	ROX			SKITTER_DATA_V_LT: if '1' the data requested by a skitter force read register has finished and data is present in skitter data register in the collector macro. The data be read by any combination of V25/V26/V27 pcb reads

Error Injection Control Register
Addr:	0000000001050011 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.THERM.WSUB.INJECT_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:3	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.COMP.INJECT_REG_LT_INST.LATC.L2(0:3) [0000]
Bit(s)	SCOM			Dial: Description
0:1	RW			THERM_INJECT_TRIP: 00: no injection 01: warning trip level injection 10: crtical trip level injection 11: fatal trip level injection
2:3	RW			THERM_INJECT_MODE: 00: no injection 01: injection on the next dts sample 10: solid injection for the next dts samples till bit setting changes 11: not used

Control / Force Reset Register
Addr:	0000000001050012 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.THERM.WSUB.CONTROL_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	12	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.COMP.F_SHIFT_SENSOR [X]
Bit(s)	SCOM			Dial: Description
0	WO_1P			reset_trip_history
1	WO_1P			reset_sample_pulse_cnt
2	WO_1P			f_reset_cpm_rd
3	WO_1P			f_reset_cpm_wr
4	WO_1P			reset_sample_dts
5	WO_1P			force_sample_dts
6	WO_1P			force_sample_dts_interruptible
7	WO_1P			force_reset_thres_l1results
8	WO_1P			force_reset_thres_l2results
9	WO_1P			force_reset_thres_l3results
10	WO_1P			force_measure_volt_interruptible
11	WO_1P			force_reset_measure_volt
12	WO_1P			force_shift_sensor

Thermal Error Status Register
Addr:	0000000001050013 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.THERM.WSUB.ERR_STATUS_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:1	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.COMP.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(0:1) [00]
	2:3	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.SKIT.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(0:1) [00]
	4	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.PCB.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(0) [0]
	5	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.COMP.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(2) [0]
	6	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.SKIT.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(3) [0]
	7	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.PCB.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(1) [0]
	8	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.COMP.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(7) [0]
	9	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.COMP.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(3) [0]
	10	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.COMP.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(12) [0]
	11:13	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.COMP.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(8:10) [000]
	14	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.SKIT.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(2) [0]
	15	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.PCB.CERR0.HOLD_LATCH_INST.HOLD.LATC.L2(2) [0]
	40:43	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.PCB.COUNT_STATE_LT_INST.LATC.L2(0:3) [0000]
	44:46	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.COMP.RUN_STATE_LT_INST.LATC.L2(0:2) [000]
	47	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.COMP.SHIFT_DTS_LT_INST.LATC.L2(0) [0]
	48	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.COMP.SHIFT_VOLT_LT_INST.LATC.L2(0) [0]
	49:50	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.COMP.READ_STATE_LT_INST.LATC.L2(0:1) [00]
	51:54	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.COMP.WRITE_STATE_LT_INST.LATC.L2(0:3) [0000]
	55	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.COMP.SAMPLE_DTS_LT_INST.LATC.L2(0) [0]
	56	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.COMP.MEASURE_VOLT_LT_INST.LATC.L2(0) [0]
	57	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.COMP.READ_CPM_LT_INST.LATC.L2(0) [0]
	58	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.COMP.WRITE_CPM_LT_INST.LATC.L2(0) [0]
	59	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.PWR_STATUS(15) [0]
Bit(s)	SCOM			Dial: Description
0	ROX			serial_shiftcnt_modereg_parity_err_hold
1	ROX			therm_modereg_parity_err_hold
2	ROX			skitter_modereg_parity_err_hold
3	ROX			skitter_forcereg_parity_err_hold
4	ROX			scan_init_version_reg_parity_err_hold
5	ROX			volt_modereg_parity_err_hold
6	ROX			skitter_clksrcreg_parity_err_hold
7	ROX			count_state_err_hold
8	ROX			run_state_err_hold
9	ROX			thres_therm_state_err_hold
10	ROX			thres_therm_overflow_err_hold
11	ROX			shifter_parity_err_hold
12	ROX			shifter_valid_err_hold
13	ROX			timeout_err_hold
14	ROX			f_skitter_err_hold
15	ROX			pcb_err_hold_out
16:39	RO			constant=0b000000000000000000000000
40:43	ROX			count_state_lt
44:46	ROX			run_state_lt
47	ROX			shift_dts_lt
48	ROX			shift_volt_lt
49:50	ROX			read_state_lt
51:54	ROX			write_state_lt
55	ROX			sample_dts_lt
56	ROX			measure_volt_lt
57	ROX			read_cpm_lt
58	ROX			write_cpm_lt
59	ROX			unused
60:63	RO			constant=0b0000

Skitter Force Read Register
Addr:	0000000001050014 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.THERM.WSUB.SKITTER_FORCE_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.SKIT.SKITTER_FORCEREG_LT_0_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	RW			F_SKITTER_READ: Forces the read of that particular skitter

Skitter Clock src control Register
Addr:	0000000001050016 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.THERM.WSUB.SKITTER_CLKSRC_REG
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:2	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.SKIT.SKITTER_CLKSRCREG_LT_0_INST.LATC.L2(0:2) [000]
	36:37	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.SKIT.SKITTER_CLKSRCREG_LT_36_INST.LATC.L2(36:37) [00]
Bit(s)	SCOM			Dial: Description
0:2	RW			SKITTER0_CLKSRC: selects clock to measure: 000: local mesh clock 001: external pin skitter_c1_1_in 010: local d1clk only if d_mode = 1 011: external pin skitter_c1_2_in 100: local lclk only if d_mode = 1 101: external pin skitter_c1_3_in 110: unused 111: external pin skitter_c1_4_in
3:35	RO			constant=0b000000000000000000000000000000000
36:37	RW			SKITTER0_DELAY_SELECT: To select delay to be added between clock source mux and inverter chain(base line delay is 12.2psec) of skitter0. 00 - No delay 01 - 0.6psec 10 - 1.8psec 11 - 5 psec

Skitter Data Register Read Bit0:63
Addr:	0000000001050019 (SCOM)
Name:	TP.TPCHIP.TPC.EPS.THERM.WSUB.SKITTER_DATA0
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.SKIT.SKITTER_DATA_LT_INST.LATC.L2(0:63) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	ROX

Skitter Data Register Read Bit32:95
Addr:	000000000105001A (SCOM)
Name:	TP.TPCHIP.TPC.EPS.THERM.WSUB.SKITTER_DATA1
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.SKIT.SKITTER_DATA_LT_INST.LATC.L2(32:95) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	ROX

Skitter Data Register Read Bit64:127
Addr:	000000000105001B (SCOM)
Name:	TP.TPCHIP.TPC.EPS.THERM.WSUB.SKITTER_DATA2
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:63	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.SKIT.SKITTER_DATA_LT_INST.LATC.L2(64:127) [0000000000000000000000000000000000000000000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0:63	ROX

Timestamp Counter Read
Addr:	000000000105001C (SCOM)
Name:	TP.TPCHIP.TPC.EPS.THERM.WSUB.TIMESTAMP_COUNTER_READ
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:43	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.PCB.TIMESTAMP_COUNT_REG_LT_INST.LATC.L2(0:43) [00000000000000000000000000000000000000000000]
	44	TP.TPCHIP.TPC.EPS.THERM.WSUB.PWR.PCB.TIMESTAMP_OVERFLOW_ERR_LT_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0:43	ROX			TIMESTAMP_COUNTER_VALUE: Time stamp counter value during DTS trace mode.
44	ROX			TIMESTAMP_COUNTER_OVERFLOW_ERR: Over flow error bit of the time stamp counter value during DTS trace mode.

DPLL Frequency Configuration Register
Addr:	0000000001060051 (SCOM)
Name:	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_FREQ
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:15	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_FREQ.CCFG_REG.CCFG_Q_INST.LATC.L2(1:15) [000000000000000]
	17:31	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_FREQ.CCFG_REG.CCFG_Q_INST.LATC.L2(17:31) [000000000000000]
	33:47	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_FREQ.CCFG_REG.CCFG_Q_INST.LATC.L2(33:47) [000000000000000]
Bit(s)	SCOM			Dial: Description
0	RO			constant=0b0
1:11	RW			DPLL_FREQ_FMAX: When DPLL_CTRL (DYNAMIC_SLEW_MODE) = '1, this field contains the requested maximum DPLL frequency target. Otherwise, this field should be set to match the FREQ_MULT field below.
12:15	RW			DPLL_FREQ_HIRES_FMAX: Same description as HIRES_FREQ_MULT below, but for FMAX control.
16	RO			constant=0b0
17:27	RW			DPLL_FREQ_FMULT: Primary DPLL frequency multiplier input, used to define the DPLL frequency target. This value is used in the absence of droop events when DPLL_CTRL[ENABLE_JUMP_PROTECT] = 1 and in the absence of voltage overshoot or undershoot when DPLL_CTRL[DYNAMIC_SLEW_MODE] = 1. The frequency given is FMULT * (REFCLK / DPLL_DIVIDER). With a REFCLK of 133MHz and DPLL_DIVIDER of 8 yields FMULT * 16.667 MHz. This allows a range from 0 to 34 GHz to be set although practical timing limits will not allow this full range to be realized.
28:31	RW			DPLL_FREQ_HIRES_FMULT: This field provides frequency control with a finer resolution (e.g. less than 16.67 Mhz) such that all DPLL inputs can be controlled. To avoid excess jitter, this field should be set to 0x0.
32	RO			constant=0b0
33:43	RW			DPLL_FREQ_FMIN: Minimum DPLL frequency only used in Dynamic DPLL mode when DPLL_CTRL[DYNAMIC_SLEW_MODE] = '1'. Note that this field is NOT honored when DPLL_CTRL[ENABLE_JUMP_PROTECT]='1' and a droop event occurs. Minimum DPLL frequency only used in Dynamic DPLL mode when DPLL_CTRL[DYNAMIC_SLEW_MODE] = '1'. Note that this field is NOT honored when DPLL_CTRL[ENABLE_JUMP_PROTECT]='1' and a droop event occurs.
44:47	RW			DPLL_FREQ_HIRES_FMIN: Same description as HIRES_FREQ_MULT, but for FMIN control.
48:62	RO			constant=0b000000000000000

DPLL Control Register
Addr:	0000000001060052 (SCOM) 0000000001060053 (SCOM1) 0000000001060054 (SCOM2)
Name:	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_CTRL
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:27	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_CTRL.CCFG_REG.CCFG_Q_INST.LATC.L2(0:27) [0000000000000000000000000000]
	33:35	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_CTRL_1.CCFG_REG.CCFG_Q_INST.LATC.L2(0:2) [000]
	37:39	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_CTRL_2.CCFG_REG.CCFG_Q_INST.LATC.L2(0:2) [000]
	41:43	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_CTRL_3.CCFG_REG.CCFG_Q_INST.LATC.L2(0:2) [000]
	45:47	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_CTRL_4.CCFG_REG.CCFG_Q_INST.LATC.L2(0:2) [000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0	RW	WO_CLEAR	WO_OR	DPLL_CTRL_DPLL_LOCK_SEL: DPLL Lock Sensitivity Select 0=faster lock time (for droop protect, parts per thousand) 1=slower lock time (more accurate, parts per million)
1	RW	WO_CLEAR	WO_OR	DPLL_CTRL_ENABLE_JUMP_PROTECT: Allow the DPLL to instantly drop frequency by a configured amount in response to two of the Dynamic Encoded Input bits dynamic_encoded_data(0:1), where bit0 indicates large and bit 1 indicates a small droop event response. Note: This mode must be '0' when DYNAMIC_SLEW_MODE is set to '1'.
2	RW	WO_CLEAR	WO_OR	DPLL_CTRL_FF_BYPASS: Enables frequency filter bypass.
3	RW	WO_CLEAR	WO_OR	DPLL_CTRL_DCO_OVERRIDE: Enables the following two fields to control the DCO manually in a special manufacturing test mode for DPLL characterization.
4	RW	WO_CLEAR	WO_OR	DPLL_CTRL_DCO_INCR: Increments DCO control logic for manufacturing test mode.
5	RW	WO_CLEAR	WO_OR	DPLL_CTRL_DCO_DECR: Decrements DCO control logic for manufacturing test mode.
6:7	RW	WO_CLEAR	WO_OR	DPLL_CTRL_SPARE: Implemented but not used.
8:15	RW	WO_CLEAR	WO_OR	DPLL_CTRL_FF_SLEWRATE_UP: Out of lock slew rate for DPLL to use when increasing frequency (when not performing droop recovery).
16:23	RW	WO_CLEAR	WO_OR	DPLL_CTRL_FF_SLEWRATE_DN: Out of lock slew rate for DPLL to use when decreasing frequency (when not performing droop recovery). Note: previously implemented on P9 as scanonly latches inside DPLL
24	RW	WO_CLEAR	WO_OR	DPLL_CTRL_SPARE2: Implemented but not used.
25	RW	WO_CLEAR	WO_OR	DPLL_CTRL_DYNAMIC_SLEW_MODE: This mode must be '0' when ENABLE_JUMP_PROTECT is set to '1'. When set, use dynamic_encoded_data(0:2) input from the DDS macros to slew the frequency in response to available timing margin: 000: Go down to Fmin as fast as possible (unless FAST_FMIN_DISABLE = 1) 100: Slew down towards Fmin normally 110: Slew up towards Fmax normally 111: Go up to Fmax as fast as possible (unless FAST_FMAX_DISABLE = 1)
26	RW	WO_CLEAR	WO_OR	DPLL_CTRL_FAST_FMAX_DISABLE: When DYNAMIC_SLEW_MODE=1, changes behavior of response to dynamic_encoded_data(0:2) = 111 to avoid overshoot: If below Fmult go up to Fmult as fast as possible, then slew normally up towards Fmax
27	RW	WO_CLEAR	WO_OR	DPLL_CTRL_FAST_FMIN_DISABLE: When DYNAMIC_SLEW_MODE=1, changes behavior of response to dynamic_encoded_data(0:2) = 000 to avoid undershoot: If above Fmult go down to Fmult as fast as possible, then slew normally down towards Fmin
28:32	RO	RO	RO	constant=0b00000
33:35	RW	WO_CLEAR	WO_OR	DPLL_CTRL_JUMP_VALUE_N_L: Large Jump Value in 1/32 (frequency to drop in response to a Large droop starting from a No Droop state) If ENABLE_JUMP_PROTECT is set, this must be a number between 1 and 7.
36	RO	RO	RO	constant=0b0
37:39	RW	WO_CLEAR	WO_OR	DPLL_CTRL_JUMP_VALUE_N_S: Small Jump Value in 1/32 (frequency to drop in response to a Small droop starting from a No Droop state) If ENABLE_JUMP_PROTECT is set, this number must be <= JUMP_VALUE_N_L.
40	RO	RO	RO	constant=0b0
41:43	RW	WO_CLEAR	WO_OR	DPLL_CTRL_JUMP_VALUE_L_S: Large Return Jump Amount in 1/32 (amount of original frequency to recover in response to a Large droop changing to a Small Droop condition) If ENABLE_JUMP_PROTECT is set, this number must be <= JUMP_VALUE_N_L - JUMP_VALUE_S_N.
44	RO	RO	RO	constant=0b0
45:47	RW	WO_CLEAR	WO_OR	DPLL_CTRL_JUMP_VALUE_S_N: Small Return Jump Amount in 1/32 (amount of original frequency to recover in response to a Small droop changing to No Droop condition) If ENABLE_JUMP_PROTECT is set, this number must be <= JUMP_VALUE_N_S.
48:63	RO	RO	RO	constant=0b0000000000000000

DPLL Output Status Register
Addr:	0000000001060055 (SCOM)
Name:	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_STAT
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:16	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_STAT.CCFG_REG.CCFG_Q_INST.LATC.L2(1:16) [0000000000000000]
	60:63	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_STAT.CCFG_REG.CCFG_Q_INST.LATC.L2(60:63) [0000]
Bit(s)	SCOM			Dial: Description
0	RO			constant=0b0
1:11	ROX			DPLL_STAT_FREQOUT: Digital numeric output from the DPLL indicating what full speed frequency it is currently driving on the Core and L2 clock grids. (The L3 grid is driven by this frequency2). This register bits 0:11 are scaled the same as the FMIN and FMAX settings in the DPLL_FREQ register, so the same equation can be used to convert this number to MHz.
12:16	ROX			DPLL_STAT_HIRES_FREQOUT: Higher resolution, extended portion of the frequency output of the DPLL.
17:59	RO			constant=0b0000000000000000000000000000000000000000000
60	ROX			DPLL_STAT_UPDATE_COMPLETE: DPLL output indicating that the internal DPLL save point (jump value for >>home<<) is at the requested FMULT target. Code must poll this in Mode3 to ensure that an FMULT update was accepted.
61	ROX			DPLL_STAT_FREQ_CHANGE: DPLL output indicating that the DPLL is NOT at the requested FMULT target. Code can poll this in Mode2 instead of the LOCK as a faster indication that DPLL has reached its target frequency. Note: this signal is usually the inverse of the LOCK except it will change to zero after a change many refclocks before the LOCK goes active.
62	ROX			DPLL_STAT_BLOCK_ACTIVE: DPLL output indicating that the DPLL is blocking (not sampling) the FMULT target input. Occurs in Mode 3 when a Droop Jump Event or Droop Recovery is in progress.
63	ROX			DPLL_STAT_LOCK: DPLL Lock Indicator (flock output from DPLL). Signal indicating that DPLL is at the requested FMULT target and is stable for a large number of refclock cycles in a row. Only >>stable<< in Mode 2 or in Mode 3 when no Droop Jump Events are present. Only intended to be checked during IPL to ensure the DPLL is operating properly. Will change state whenever a new FMULT is requested and for Modes 3 or 4 in response to dynamic_encoded_data changes (from the Digital Droop Sensors).

DPLL Output Characterization Register
Addr:	0000000001060056 (SCOM)
Name:	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#1.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	2	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#2.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	3	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#3.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	4	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#4.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	5	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#5.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	6	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#6.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	7	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#7.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	8	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#8.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	9	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#9.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	10	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#10.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	11	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#11.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	12	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#12.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	13	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#13.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	14	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#14.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	15	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#15.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	16	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#16.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	21	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#21.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	22	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#22.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	23	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#23.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	24	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#24.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	25	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#25.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	26	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#26.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	27	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#27.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	28	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#28.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	29	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#29.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	30	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#30.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	31	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#31.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	32	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#32.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	33	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#33.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	34	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#34.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	35	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#35.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	36	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#36.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	41	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#41.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	42	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#42.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	43	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#43.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	44	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#44.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	45	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#45.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	46	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#46.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	47	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#47.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	48	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#48.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	49	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#49.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	50	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#50.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	51	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#51.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	52	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#52.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	53	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#53.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	54	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#54.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	55	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#55.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	56	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR.MAKE_LATCHES#56.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	RO			constant=0b0
1:11	ROX			DPLL_OCHAR_FREQOUT_MAX: Contains the largest value of the DPLL frequency output seen since the last read of this register (updated every cycle). This field is set to FF_MULT_INTG_OUT(0:7) : FF_MULT_FRAC_OUT(0:2) when this register is read or if that value is larger than this field.
12:16	ROX			DPLL_OCHAR_HIRES_FREQOUT_MAX: Contains the largest value of the DPLL frequency output seen since the last read of this register (updated every cycle). This field is set to FF_MULT_FRAC_OUT(3:7) when this register is read or if FF_MULT_INTG_OUT(0:7) : FF_MULT_FRAC_OUT(0:7) is larger than FREQOUT_MAX : HIRES_FREQOUT_MAX.
17:20	RO			constant=0b0000
21:31	ROX			DPLL_OCHAR_FREQOUT_AVG: Contains a >>Weighted Moving Averag<< of the value seen on the DPLL Frequency Output. On a read, this field is set to the DPLL FF_MULT_INTG_OUT(0:7) : FF_MULT_FRAC_OUT(0:2). Otherwise, this field updates (increments or decrements) based on the signed carryout of the next field.
32:36	ROX			DPLL_OCHAR_HIRES_FREQOUT_AVG: Contains a >>Weighted Moving Averag<< of the value seen on the DPLL Frequency HIRES_FREQ_MULT Input. On a read to this register, this field is set to FF_MULT_FRAC_OUT(3:7). Otherwise, this field increments by 1 if the FF_MULT_INTG_OUT(0:7) : FF_MULT_FRAC_OUT(0:7) is greater than FREQOUT_AVG:HIRES_FREQOUT_AVG or decrements by 1 if the value is less.
37:40	RO			constant=0b0000
41:51	ROX			DPLL_OCHAR_FREQOUT_MIN: Contains the smallest value of the DPLL frequency output seen since the last read of this register (updated every cycle). This field is set to FF_MULT_INTG_OUT(0:7) : FF_MULT_FRAC_OUT(0:2) when this register is read or if that value is smaller than this field.
52:56	ROX			DPLL_OCHAR_HIRES_FREQOUT_MIN: Contains the smallest value of the DPLL frequency output seen since the last read of this register (updated every cycle). This field is set to FF_MULT_FRAC_OUT(3:7) when this register is read or if FF_MULT_INTG_OUT(0:7) : FF_MULT_FRAC_OUT(0:7) is smaller than FREQOUT_MIN : HIRES_FREQOUT_MIN.
57:63	RO			constant=0b0000000

DPLL Input Characterization Register
Addr:	0000000001060057 (SCOM)
Name:	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#1.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	2	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#2.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	3	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#3.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	4	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#4.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	5	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#5.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	6	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#6.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	7	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#7.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	8	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#8.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	9	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#9.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	10	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#10.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	11	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#11.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	12	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#12.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	13	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#13.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	14	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#14.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	15	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#15.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	16	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#16.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	21	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#21.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	22	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#22.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	23	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#23.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	24	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#24.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	25	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#25.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	26	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#26.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	27	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#27.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	28	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#28.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	29	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#29.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	30	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#30.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	31	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#31.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	32	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#32.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	33	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#33.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	34	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#34.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	35	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#35.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	36	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#36.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	41	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#41.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	42	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#42.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	43	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#43.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	44	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#44.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	45	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#45.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	46	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#46.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	47	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#47.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	48	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#48.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	49	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#49.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	50	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#50.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	51	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#51.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	52	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#52.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	53	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#53.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	54	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#54.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	55	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#55.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	56	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR.MAKE_LATCHES#56.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	RO			constant=0b0
1:11	ROX			DPLL_ICHAR_FREQIN_AVG: Contains a >>running average<< of the value of the DPLL Frequency FREQ_MULT Input. On a read to this register, this field is set to DPLL_FREQ[FREQIN]. Otherwise, this field updates (increments or decrements) based on the signed carryout of the next field.
12:16	ROX			DPLL_ICHAR_HIRES_FREQIN_AVG: Contains a>>running average<< of the value of the DPLL Frequency HIRES_FREQ_MULT Input. On a read to this register, this field is set to DPLL_FREQ[HIRES_FREQIN]. Otherwise, this field increments by 1 if the MULT:HIRES_MULT is greater than FREQIN_AVG:HIRES_FREQIN_AVG or decrements by 1 if the value is less.
17:20	RO			constant=0b0000
21:31	ROX			DPLL_ICHAR_FREQIN_MAX: Contains the largest value provided to the DPLL frequency MULT input since the last read of this register. This field is set to DPLL_FREQ[FREQIN] when this register is read or if that field is written with a value larger than this field.
32:36	ROX			DPLL_ICHAR_HIRES_FREQIN_MAX: Contains the largest value of the DPLL frequency output seen since the last read of this register (updated every cycle). This field is set to HIRES_FREQIN when this register is read or if FREQIN:HIRES_FREQIN is larger than FREQIN_MAX : HIRES_FREQIN_MAX.
37:40	RO			constant=0b0000
41:51	ROX			DPLL_ICHAR_FREQIN_MIN: Contains the smallest value of the DPLL frequency MULT input since the last read of this register. This field is set to DPLL_FREQ[FREQIN] when this register is read or if that field is written with a value smaller than this field.
52:56	ROX			DPLL_ICHAR_HIRES_FREQIN_MIN: Contains the smallest value of the DPLL frequency output seen since the last read of this register (updated every cycle). This field is set to HIRES_FREQIN when this register is read or if FREQIN:HIRES_FREQIN is smaller than FREQIN_MIN : HIRES_FREQIN_MIN.
57:63	RO			constant=0b0000000

DPLL Dynamic Encode Characterization Register
Addr:	0000000001060058 (SCOM)
Name:	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ECHAR
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ECHAR.MAKE_LATCHES#1.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	2	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ECHAR.MAKE_LATCHES#2.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	3	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ECHAR.MAKE_LATCHES#3.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	5	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ECHAR.MAKE_LATCHES#5.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	6	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ECHAR.MAKE_LATCHES#6.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	7	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ECHAR.MAKE_LATCHES#7.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	9	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ECHAR.MAKE_LATCHES#9.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	10	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ECHAR.MAKE_LATCHES#10.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	11	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ECHAR.MAKE_LATCHES#11.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	61	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ECHAR.MAKE_LATCHES#61.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	62	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ECHAR.MAKE_LATCHES#62.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	63	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ECHAR.MAKE_LATCHES#63.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	RO			constant=0b0
1:3	ROX			DPLL_ECHAR_DYNAMIC_ENCODED_DATA: Directly sampled value of the async dynamic_encoded_data(0:2) input signals feeding the DPLL input, after going through metastability latches in this macro.
4	RO			constant=0b0
5:7	ROX			DPLL_ECHAR_MIN_ENCODED_DATA: Minimum (worst case) value since the last time this register was read. This field is AND'd with dynamic_encoded_data(0:2) every cycle. This field is written with DYNAMIC_ENCODED_DATA on register read.
8	RO			constant=0b0
9:11	ROX			DPLL_ECHAR_MAX_ENCODED_DATA: Maximum (best case) value since the last time this register was read. This field is OR'd with dynamic_encoded_data(0:2) every cycle. This field is written with DYNAMIC_ENCODED_DATA on register read.
12:60	RO			constant=0b0000000000000000000000000000000000000000000000000
61:63	RW			DPLL_ECHAR_INVERTED_DYNAMIC_ENCODE_INJECT: The inverted value (one's complement) of this field is sent out of this macro to be AND'd with the dynamic_encoded_data(0:2) from the Cores before feeding the DPLL input of that same name.

DPLL_TEST_SEL_REG
Addr:	0000000001060059 (SCOM)
Name:	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_TESTSEL
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_TESTSEL.CCFG_REG.CCFG_Q_INST.LATC.L2(0:7) [00000000]
Bit(s)	SCOM			Dial: Description
0:7	RW			DPLL_TESTSEL_TEST_SEL: Static Control of the DPLL TEST_SEL (0..7) inputs

PFET Status Register
Addr:	0000000001060080 (SCOM)
Name:	TP.TPCHIP.TPC.DPLL_CNTL.MISC.REGS.MISC_PFET
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:25	TP.TPCHIP.TPC.DPLL_CNTL.MISC.REGS.MISC_PFET.CCFG_REG.CCFG_Q_INST.LATC.L2(0:25) [00000000000000000000000000]
Bit(s)	SCOM			Dial: Description
0	ROX			EMO3_VDD_PFETS_DISABLED_SENSE_OUT_DC: EMO3 PFETs are fully turned off
1	ROX			EMO3_VDD_PFETS_ENABLED_SENSE_OUT_DC: EMO3 PFETs are fully turned on
2	ROX			EMO2_VDD_PFETS_DISABLED_SENSE_OUT_DC: EMO2 PFETs are fully turned off
3	ROX			EMO2_VDD_PFETS_ENABLED_SENSE_OUT_DC: EMO2 PFETs are fully turned on
4	ROX			EMO1_VDD_PFETS_DISABLED_SENSE_OUT_DC: EMO1 PFETs are fully turned off
5	ROX			EMO1_VDD_PFETS_ENABLED_SENSE_OUT_DC: EMO1 PFETs are fully turned on
6	ROX			EMO0_VDD_PFETS_DISABLED_SENSE_OUT_DC: EMO0 PFETs are fully turned off
7	ROX			EMO0_VDD_PFETS_ENABLED_SENSE_OUT_DC: EMO0 PFETs are fully turned on
8	ROX			PAU0_VDD_PFETS_DISABLED_SENSE_OUT_DC: PAU0 PFETs are fully turned off
9	ROX			PAU0_VDD_PFETS_ENABLED_SENSE_OUT_DC: PAU0 PFETs are fully turned on
10	ROX			PAU3_VDD_PFETS_DISABLED_SENSE_OUT_DC: PAU3 PFETs are fully turned off
11	ROX			PAU3_VDD_PFETS_ENABLED_SENSE_OUT_DC: PAU3 PFETs are fully turned on
12	ROX			PAU4_VDD_PFETS_DISABLED_SENSE_OUT_DC: PAU4 PFETs are fully turned off
13	ROX			PAU4_VDD_PFETS_ENABLED_SENSE_OUT_DC: PAU4 PFETs are fully turned on
14	ROX			PAU5_VDD_PFETS_DISABLED_SENSE_OUT_DC: PAU5 PFETs are fully turned off
15	ROX			PAU5_VDD_PFETS_ENABLED_SENSE_OUT_DC: PAU5 PFETs are fully turned on
16	ROX			PAU6_VDD_PFETS_DISABLED_SENSE_OUT_DC: PAU6 PFETs are fully turned off
17	ROX			PAU6_VDD_PFETS_ENABLED_SENSE_OUT_DC: PAU6 PFETs are fully turned on
18	ROX			PAU7_VDD_PFETS_DISABLED_SENSE_OUT_DC: PAU7 PFETs are fully turned off
19	ROX			PAU7_VDD_PFETS_ENABLED_SENSE_OUT_DC: PAU7 PFETs are fully turned on
20	ROX			PCIE1_VDD_PFETS_DISABLED_SENSE_OUT_DC: PCIE1 PFETs are fully turned off
21	ROX			PCIE1_VDD_PFETS_ENABLED_SENSE_OUT_DC: PCIE1 PFETs are fully turned on
22	ROX			PCIE0_VDD_PFETS_DISABLED_SENSE_OUT_DC: PCIE0 PFETs are fully turned off
23	ROX			PCIE0_VDD_PFETS_ENABLED_SENSE_OUT_DC: PCIE0 PFETs are fully turned on
24	ROX			NMMU_VDD_PFETS_DISABLED_SENSE_OUT_DC: NMMU PFETs are fully turned off
25	ROX			NMMU_VDD_PFETS_ENABLED_SENSE_OUT_DC: NMMU PFETs are fully turned on
26:63	RO			constant=0b00000000000000000000000000000000000000

DPLL Frequency Configuration Register
Addr:	0000000001060151 (SCOM)
Name:	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_FREQ
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:15	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_FREQ.CCFG_REG.CCFG_Q_INST.LATC.L2(1:15) [000000000000000]
	17:31	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_FREQ.CCFG_REG.CCFG_Q_INST.LATC.L2(17:31) [000000000000000]
	33:47	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_FREQ.CCFG_REG.CCFG_Q_INST.LATC.L2(33:47) [000000000000000]
Bit(s)	SCOM			Dial: Description
0	RO			constant=0b0
1:11	RW			DPLL_FREQ_FMAX: When DPLL_CTRL (DYNAMIC_SLEW_MODE) = '1, this field contains the requested maximum DPLL frequency target. Otherwise, this field should be set to match the FREQ_MULT field below.
12:15	RW			DPLL_FREQ_HIRES_FMAX: Same description as HIRES_FREQ_MULT below, but for FMAX control.
16	RO			constant=0b0
17:27	RW			DPLL_FREQ_FMULT: Primary DPLL frequency multiplier input, used to define the DPLL frequency target. This value is used in the absence of droop events when DPLL_CTRL[ENABLE_JUMP_PROTECT] = 1 and in the absence of voltage overshoot or undershoot when DPLL_CTRL[DYNAMIC_SLEW_MODE] = 1. The frequency given is FMULT * (REFCLK / DPLL_DIVIDER). With a REFCLK of 133MHz and DPLL_DIVIDER of 8 yields FMULT * 16.667 MHz. This allows a range from 0 to 34 GHz to be set although practical timing limits will not allow this full range to be realized.
28:31	RW			DPLL_FREQ_HIRES_FMULT: This field provides frequency control with a finer resolution (e.g. less than 16.67 Mhz) such that all DPLL inputs can be controlled. To avoid excess jitter, this field should be set to 0x0.
32	RO			constant=0b0
33:43	RW			DPLL_FREQ_FMIN: Minimum DPLL frequency only used in Dynamic DPLL mode when DPLL_CTRL[DYNAMIC_SLEW_MODE] = '1'. Note that this field is NOT honored when DPLL_CTRL[ENABLE_JUMP_PROTECT]='1' and a droop event occurs. Minimum DPLL frequency only used in Dynamic DPLL mode when DPLL_CTRL[DYNAMIC_SLEW_MODE] = '1'. Note that this field is NOT honored when DPLL_CTRL[ENABLE_JUMP_PROTECT]='1' and a droop event occurs.
44:47	RW			DPLL_FREQ_HIRES_FMIN: Same description as HIRES_FREQ_MULT, but for FMIN control.
48:62	RO			constant=0b000000000000000

DPLL Control Register
Addr:	0000000001060152 (SCOM) 0000000001060153 (SCOM1) 0000000001060154 (SCOM2)
Name:	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_CTRL
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:27	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_CTRL.CCFG_REG.CCFG_Q_INST.LATC.L2(0:27) [0000000000000000000000000000]
	33:35	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_CTRL_1.CCFG_REG.CCFG_Q_INST.LATC.L2(0:2) [000]
	37:39	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_CTRL_2.CCFG_REG.CCFG_Q_INST.LATC.L2(0:2) [000]
	41:43	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_CTRL_3.CCFG_REG.CCFG_Q_INST.LATC.L2(0:2) [000]
	45:47	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_CTRL_4.CCFG_REG.CCFG_Q_INST.LATC.L2(0:2) [000]
Bit(s)	SCOM	SCOM1	SCOM2	Dial: Description
0	RW	WO_CLEAR	WO_OR	DPLL_CTRL_DPLL_LOCK_SEL: DPLL Lock Sensitivity Select 0=faster lock time (for droop protect, parts per thousand) 1=slower lock time (more accurate, parts per million)
1	RW	WO_CLEAR	WO_OR	DPLL_CTRL_ENABLE_JUMP_PROTECT: Allow the DPLL to instantly drop frequency by a configured amount in response to two of the Dynamic Encoded Input bits dynamic_encoded_data(0:1), where bit0 indicates large and bit 1 indicates a small droop event response. Note: This mode must be '0' when DYNAMIC_SLEW_MODE is set to '1'.
2	RW	WO_CLEAR	WO_OR	DPLL_CTRL_FF_BYPASS: Enables frequency filter bypass.
3	RW	WO_CLEAR	WO_OR	DPLL_CTRL_DCO_OVERRIDE: Enables the following two fields to control the DCO manually in a special manufacturing test mode for DPLL characterization.
4	RW	WO_CLEAR	WO_OR	DPLL_CTRL_DCO_INCR: Increments DCO control logic for manufacturing test mode.
5	RW	WO_CLEAR	WO_OR	DPLL_CTRL_DCO_DECR: Decrements DCO control logic for manufacturing test mode.
6:7	RW	WO_CLEAR	WO_OR	DPLL_CTRL_SPARE: Implemented but not used.
8:15	RW	WO_CLEAR	WO_OR	DPLL_CTRL_FF_SLEWRATE_UP: Out of lock slew rate for DPLL to use when increasing frequency (when not performing droop recovery).
16:23	RW	WO_CLEAR	WO_OR	DPLL_CTRL_FF_SLEWRATE_DN: Out of lock slew rate for DPLL to use when decreasing frequency (when not performing droop recovery). Note: previously implemented on P9 as scanonly latches inside DPLL
24	RW	WO_CLEAR	WO_OR	DPLL_CTRL_SPARE2: Implemented but not used.
25	RW	WO_CLEAR	WO_OR	DPLL_CTRL_DYNAMIC_SLEW_MODE: This mode must be '0' when ENABLE_JUMP_PROTECT is set to '1'. When set, use dynamic_encoded_data(0:2) input from the DDS macros to slew the frequency in response to available timing margin: 000: Go down to Fmin as fast as possible (unless FAST_FMIN_DISABLE = 1) 100: Slew down towards Fmin normally 110: Slew up towards Fmax normally 111: Go up to Fmax as fast as possible (unless FAST_FMAX_DISABLE = 1)
26	RW	WO_CLEAR	WO_OR	DPLL_CTRL_FAST_FMAX_DISABLE: When DYNAMIC_SLEW_MODE=1, changes behavior of response to dynamic_encoded_data(0:2) = 111 to avoid overshoot: If below Fmult go up to Fmult as fast as possible, then slew normally up towards Fmax
27	RW	WO_CLEAR	WO_OR	DPLL_CTRL_FAST_FMIN_DISABLE: When DYNAMIC_SLEW_MODE=1, changes behavior of response to dynamic_encoded_data(0:2) = 000 to avoid undershoot: If above Fmult go down to Fmult as fast as possible, then slew normally down towards Fmin
28:32	RO	RO	RO	constant=0b00000
33:35	RW	WO_CLEAR	WO_OR	DPLL_CTRL_JUMP_VALUE_N_L: Large Jump Value in 1/32 (frequency to drop in response to a Large droop starting from a No Droop state) If ENABLE_JUMP_PROTECT is set, this must be a number between 1 and 7.
36	RO	RO	RO	constant=0b0
37:39	RW	WO_CLEAR	WO_OR	DPLL_CTRL_JUMP_VALUE_N_S: Small Jump Value in 1/32 (frequency to drop in response to a Small droop starting from a No Droop state) If ENABLE_JUMP_PROTECT is set, this number must be <= JUMP_VALUE_N_L.
40	RO	RO	RO	constant=0b0
41:43	RW	WO_CLEAR	WO_OR	DPLL_CTRL_JUMP_VALUE_L_S: Large Return Jump Amount in 1/32 (amount of original frequency to recover in response to a Large droop changing to a Small Droop condition) If ENABLE_JUMP_PROTECT is set, this number must be <= JUMP_VALUE_N_L - JUMP_VALUE_S_N.
44	RO	RO	RO	constant=0b0
45:47	RW	WO_CLEAR	WO_OR	DPLL_CTRL_JUMP_VALUE_S_N: Small Return Jump Amount in 1/32 (amount of original frequency to recover in response to a Small droop changing to No Droop condition) If ENABLE_JUMP_PROTECT is set, this number must be <= JUMP_VALUE_N_S.
48:63	RO	RO	RO	constant=0b0000000000000000

DPLL Output Status Register
Addr:	0000000001060155 (SCOM)
Name:	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_STAT
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1:16	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_STAT.CCFG_REG.CCFG_Q_INST.LATC.L2(1:16) [0000000000000000]
	60:63	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_STAT.CCFG_REG.CCFG_Q_INST.LATC.L2(60:63) [0000]
Bit(s)	SCOM			Dial: Description
0	RO			constant=0b0
1:11	ROX			DPLL_STAT_FREQOUT: Digital numeric output from the DPLL indicating what full speed frequency it is currently driving on the Core and L2 clock grids. (The L3 grid is driven by this frequency2). This register bits 0:11 are scaled the same as the FMIN and FMAX settings in the DPLL_FREQ register, so the same equation can be used to convert this number to MHz.
12:16	ROX			DPLL_STAT_HIRES_FREQOUT: Higher resolution, extended portion of the frequency output of the DPLL.
17:59	RO			constant=0b0000000000000000000000000000000000000000000
60	ROX			DPLL_STAT_UPDATE_COMPLETE: DPLL output indicating that the internal DPLL save point (jump value for >>home<<) is at the requested FMULT target. Code must poll this in Mode3 to ensure that an FMULT update was accepted.
61	ROX			DPLL_STAT_FREQ_CHANGE: DPLL output indicating that the DPLL is NOT at the requested FMULT target. Code can poll this in Mode2 instead of the LOCK as a faster indication that DPLL has reached its target frequency. Note: this signal is usually the inverse of the LOCK except it will change to zero after a change many refclocks before the LOCK goes active.
62	ROX			DPLL_STAT_BLOCK_ACTIVE: DPLL output indicating that the DPLL is blocking (not sampling) the FMULT target input. Occurs in Mode 3 when a Droop Jump Event or Droop Recovery is in progress.
63	ROX			DPLL_STAT_LOCK: DPLL Lock Indicator (flock output from DPLL). Signal indicating that DPLL is at the requested FMULT target and is stable for a large number of refclock cycles in a row. Only >>stable<< in Mode 2 or in Mode 3 when no Droop Jump Events are present. Only intended to be checked during IPL to ensure the DPLL is operating properly. Will change state whenever a new FMULT is requested and for Modes 3 or 4 in response to dynamic_encoded_data changes (from the Digital Droop Sensors).

DPLL Output Characterization Register
Addr:	0000000001060156 (SCOM)
Name:	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#1.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	2	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#2.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	3	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#3.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	4	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#4.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	5	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#5.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	6	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#6.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	7	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#7.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	8	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#8.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	9	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#9.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	10	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#10.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	11	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#11.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	12	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#12.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	13	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#13.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	14	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#14.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	15	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#15.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	16	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#16.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	21	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#21.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	22	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#22.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	23	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#23.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	24	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#24.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	25	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#25.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	26	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#26.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	27	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#27.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	28	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#28.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	29	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#29.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	30	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#30.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	31	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#31.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	32	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#32.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	33	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#33.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	34	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#34.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	35	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#35.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	36	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#36.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	41	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#41.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	42	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#42.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	43	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#43.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	44	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#44.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	45	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#45.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	46	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#46.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	47	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#47.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	48	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#48.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	49	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#49.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	50	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#50.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	51	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#51.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	52	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#52.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	53	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#53.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	54	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#54.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	55	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#55.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	56	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR.MAKE_LATCHES#56.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	RO			constant=0b0
1:11	ROX			DPLL_OCHAR_FREQOUT_MAX: Contains the largest value of the DPLL frequency output seen since the last read of this register (updated every cycle). This field is set to FF_MULT_INTG_OUT(0:7) : FF_MULT_FRAC_OUT(0:2) when this register is read or if that value is larger than this field.
12:16	ROX			DPLL_OCHAR_HIRES_FREQOUT_MAX: Contains the largest value of the DPLL frequency output seen since the last read of this register (updated every cycle). This field is set to FF_MULT_FRAC_OUT(3:7) when this register is read or if FF_MULT_INTG_OUT(0:7) : FF_MULT_FRAC_OUT(0:7) is larger than FREQOUT_MAX : HIRES_FREQOUT_MAX.
17:20	RO			constant=0b0000
21:31	ROX			DPLL_OCHAR_FREQOUT_AVG: Contains a >>Weighted Moving Averag<< of the value seen on the DPLL Frequency Output. On a read, this field is set to the DPLL FF_MULT_INTG_OUT(0:7) : FF_MULT_FRAC_OUT(0:2). Otherwise, this field updates (increments or decrements) based on the signed carryout of the next field.
32:36	ROX			DPLL_OCHAR_HIRES_FREQOUT_AVG: Contains a >>Weighted Moving Averag<< of the value seen on the DPLL Frequency HIRES_FREQ_MULT Input. On a read to this register, this field is set to FF_MULT_FRAC_OUT(3:7). Otherwise, this field increments by 1 if the FF_MULT_INTG_OUT(0:7) : FF_MULT_FRAC_OUT(0:7) is greater than FREQOUT_AVG:HIRES_FREQOUT_AVG or decrements by 1 if the value is less.
37:40	RO			constant=0b0000
41:51	ROX			DPLL_OCHAR_FREQOUT_MIN: Contains the smallest value of the DPLL frequency output seen since the last read of this register (updated every cycle). This field is set to FF_MULT_INTG_OUT(0:7) : FF_MULT_FRAC_OUT(0:2) when this register is read or if that value is smaller than this field.
52:56	ROX			DPLL_OCHAR_HIRES_FREQOUT_MIN: Contains the smallest value of the DPLL frequency output seen since the last read of this register (updated every cycle). This field is set to FF_MULT_FRAC_OUT(3:7) when this register is read or if FF_MULT_INTG_OUT(0:7) : FF_MULT_FRAC_OUT(0:7) is smaller than FREQOUT_MIN : HIRES_FREQOUT_MIN.
57:63	RO			constant=0b0000000

DPLL Input Characterization Register
Addr:	0000000001060157 (SCOM)
Name:	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#1.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	2	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#2.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	3	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#3.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	4	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#4.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	5	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#5.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	6	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#6.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	7	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#7.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	8	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#8.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	9	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#9.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	10	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#10.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	11	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#11.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	12	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#12.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	13	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#13.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	14	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#14.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	15	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#15.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	16	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#16.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	21	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#21.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	22	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#22.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	23	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#23.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	24	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#24.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	25	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#25.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	26	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#26.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	27	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#27.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	28	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#28.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	29	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#29.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	30	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#30.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	31	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#31.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	32	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#32.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	33	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#33.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	34	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#34.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	35	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#35.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	36	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#36.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	41	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#41.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	42	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#42.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	43	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#43.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	44	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#44.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	45	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#45.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	46	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#46.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	47	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#47.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	48	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#48.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	49	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#49.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	50	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#50.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	51	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#51.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	52	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#52.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	53	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#53.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	54	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#54.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	55	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#55.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	56	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR.MAKE_LATCHES#56.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	RO			constant=0b0
1:11	ROX			DPLL_ICHAR_FREQIN_AVG: Contains a >>running average<< of the value of the DPLL Frequency FREQ_MULT Input. On a read to this register, this field is set to DPLL_FREQ[FREQIN]. Otherwise, this field updates (increments or decrements) based on the signed carryout of the next field.
12:16	ROX			DPLL_ICHAR_HIRES_FREQIN_AVG: Contains a>>running average<< of the value of the DPLL Frequency HIRES_FREQ_MULT Input. On a read to this register, this field is set to DPLL_FREQ[HIRES_FREQIN]. Otherwise, this field increments by 1 if the MULT:HIRES_MULT is greater than FREQIN_AVG:HIRES_FREQIN_AVG or decrements by 1 if the value is less.
17:20	RO			constant=0b0000
21:31	ROX			DPLL_ICHAR_FREQIN_MAX: Contains the largest value provided to the DPLL frequency MULT input since the last read of this register. This field is set to DPLL_FREQ[FREQIN] when this register is read or if that field is written with a value larger than this field.
32:36	ROX			DPLL_ICHAR_HIRES_FREQIN_MAX: Contains the largest value of the DPLL frequency output seen since the last read of this register (updated every cycle). This field is set to HIRES_FREQIN when this register is read or if FREQIN:HIRES_FREQIN is larger than FREQIN_MAX : HIRES_FREQIN_MAX.
37:40	RO			constant=0b0000
41:51	ROX			DPLL_ICHAR_FREQIN_MIN: Contains the smallest value of the DPLL frequency MULT input since the last read of this register. This field is set to DPLL_FREQ[FREQIN] when this register is read or if that field is written with a value smaller than this field.
52:56	ROX			DPLL_ICHAR_HIRES_FREQIN_MIN: Contains the smallest value of the DPLL frequency output seen since the last read of this register (updated every cycle). This field is set to HIRES_FREQIN when this register is read or if FREQIN:HIRES_FREQIN is smaller than FREQIN_MIN : HIRES_FREQIN_MIN.
57:63	RO			constant=0b0000000

DPLL Dynamic Encode Characterization Register
Addr:	0000000001060158 (SCOM)
Name:	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ECHAR
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	1	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ECHAR.MAKE_LATCHES#1.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	2	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ECHAR.MAKE_LATCHES#2.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	3	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ECHAR.MAKE_LATCHES#3.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	5	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ECHAR.MAKE_LATCHES#5.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	6	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ECHAR.MAKE_LATCHES#6.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	7	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ECHAR.MAKE_LATCHES#7.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	9	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ECHAR.MAKE_LATCHES#9.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	10	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ECHAR.MAKE_LATCHES#10.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	11	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ECHAR.MAKE_LATCHES#11.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	61	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ECHAR.MAKE_LATCHES#61.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	62	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ECHAR.MAKE_LATCHES#62.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
	63	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ECHAR.MAKE_LATCHES#63.MY_LATCHES.PCB_REG_Q_INST.LATC.L2(0) [0]
Bit(s)	SCOM			Dial: Description
0	RO			constant=0b0
1:3	ROX			DPLL_ECHAR_DYNAMIC_ENCODED_DATA: Directly sampled value of the async dynamic_encoded_data(0:2) input signals feeding the DPLL input, after going through metastability latches in this macro.
4	RO			constant=0b0
5:7	ROX			DPLL_ECHAR_MIN_ENCODED_DATA: Minimum (worst case) value since the last time this register was read. This field is AND'd with dynamic_encoded_data(0:2) every cycle. This field is written with DYNAMIC_ENCODED_DATA on register read.
8	RO			constant=0b0
9:11	ROX			DPLL_ECHAR_MAX_ENCODED_DATA: Maximum (best case) value since the last time this register was read. This field is OR'd with dynamic_encoded_data(0:2) every cycle. This field is written with DYNAMIC_ENCODED_DATA on register read.
12:60	RO			constant=0b0000000000000000000000000000000000000000000000000
61:63	RW			DPLL_ECHAR_INVERTED_DYNAMIC_ENCODE_INJECT: The inverted value (one's complement) of this field is sent out of this macro to be AND'd with the dynamic_encoded_data(0:2) from the Cores before feeding the DPLL input of that same name.

DPLL_TEST_SEL_REG
Addr:	0000000001060159 (SCOM)
Name:	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_TESTSEL
Constant(s):
Comments:
SelectedAttributes:
Latches	Bits	Latch Name [flushval]
	0:7	TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_TESTSEL.CCFG_REG.CCFG_Q_INST.LATC.L2(0:7) [00000000]
Bit(s)	SCOM			Dial: Description
0:7	RW			DPLL_TESTSEL_TEST_SEL: Static Control of the DPLL TEST_SEL (0..7) inputs

Address listing
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00000000000004A0 TP.TPVSB.FSI.W.FSI_SLAVE.PEEK4A0
00000000000004A4 TP.TPVSB.FSI.W.FSI_SLAVE.PEEK4A4
00000000000004B0 TP.TPVSB.FSI.W.FSI_SLAVE.PEEK4B0
00000000000004B4 TP.TPVSB.FSI.W.FSI_SLAVE.PEEK4B4
0000000000000800 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SMODE
0000000000000800 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SMODE
0000000000000804 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SDMA
0000000000000804 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SDMA
0000000000000808 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SCISC
0000000000000808 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SISC
0000000000000808 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SCISC
0000000000000808 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SISC
000000000000080C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SISM
000000000000080C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SISM
0000000000000810 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SISS
0000000000000810 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SSISM
0000000000000810 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SISS
0000000000000810 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SSISM
0000000000000814 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SCISM
0000000000000814 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SSTAT
0000000000000814 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SCISM
0000000000000814 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SSTAT
0000000000000818 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SI1M
0000000000000818 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SI1M
000000000000081C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SI1S
000000000000081C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SSI1M
000000000000081C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SI1S
000000000000081C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SSI1M
0000000000000820 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SCI1M
0000000000000820 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SIC
0000000000000820 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SCI1M
0000000000000820 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SIC
0000000000000824 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SI2M
0000000000000824 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SI2M
0000000000000828 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SI2S
0000000000000828 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SSI2M
0000000000000828 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SI2S
0000000000000828 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SSI2M
000000000000082C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SCI2CM
000000000000082C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SCMDT
000000000000082C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SCI2CM
000000000000082C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SCMDT
0000000000000830 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SDATA
0000000000000830 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SLBUS
0000000000000830 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SDATA
0000000000000830 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SLBUS
0000000000000834 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SLASTD_SRES
0000000000000834 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SLASTD_SRES
0000000000000838 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SMBL
0000000000000838 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SMBL
000000000000083C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SOML
000000000000083C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SSMBL
000000000000083C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SOML
000000000000083C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SSMBL
0000000000000840 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SCMBL
0000000000000840 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SNML
0000000000000840 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SCMBL
0000000000000840 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SNML
0000000000000844 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SMBR
0000000000000844 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SMBR
0000000000000848 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SOMR
0000000000000848 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SSMBR
0000000000000848 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SOMR
0000000000000848 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SSMBR
000000000000084C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SCMBR
000000000000084C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SNMR
000000000000084C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SCMBR
000000000000084C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SNMR
0000000000000850 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SCRSIC0
0000000000000850 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SCRSIC0
0000000000000854 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SCRSIC4
0000000000000854 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SCRSIC4
0000000000000858 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SCRSIM0
0000000000000858 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SCRSIM0
000000000000085C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SCRSIM4
000000000000085C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SCRSIM4
0000000000000860 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SCRSIS0
0000000000000860 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SCRSIS0
0000000000000864 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SCRSIS4
0000000000000864 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SCRSIS4
0000000000000868 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SRSIC0
0000000000000868 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SRSIC0
000000000000086C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SRSIC4
000000000000086C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SRSIC4
0000000000000870 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SRSIM0
0000000000000870 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SRSIM0
0000000000000874 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SRSIM4
0000000000000874 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SRSIM4
0000000000000878 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SRSIS0
0000000000000878 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SRSIS0
000000000000087C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_SRSIS4
000000000000087C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_SRSIS4
0000000000000900 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_LLMOD
0000000000000900 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_LLMOD
0000000000000904 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_LLSTAT
0000000000000904 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_B_LLSTAT
0000000000000C00 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MMODE
0000000000003000 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MMODE
0000000000000C01 TP.TPVSB.FSI.W.FSI_SHIFT.COMMAND_REGISTER
0000000000000C04 TP.TPVSB.FSI.W.FSI_SHIFT.COMMAND_REGISTER
0000000000000C01 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MDLYR
0000000000003004 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MDLYR
0000000000000C02 TP.TPVSB.FSI.W.FSI_SHIFT.FRONT_END_LENGTH_REGISTER
0000000000000C08 TP.TPVSB.FSI.W.FSI_SHIFT.FRONT_END_LENGTH_REGISTER
0000000000000C02 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MCRSP0
0000000000003008 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MCRSP0
0000000000000C03 TP.TPVSB.FSI.W.FSI_SHIFT.READ_BUFFER
0000000000000C0C TP.TPVSB.FSI.W.FSI_SHIFT.READ_BUFFER
0000000000000C03 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MCRSP1
000000000000300C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MCRSP1
0000000000000C04 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MENP0
0000000000003010 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MENP0
0000000000000C05 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MENP1
0000000000003014 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MENP1
0000000000000C06 TP.TPVSB.FSI.W.FSI_SHIFT.RESET
0000000000000C18 TP.TPVSB.FSI.W.FSI_SHIFT.RESET
0000000000000C06 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MLEVP0
0000000000003018 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MLEVP0
0000000000000C06 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSENP0
0000000000003018 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSENP0
0000000000000C07 TP.TPVSB.FSI.W.FSI_SHIFT.RESET_ERRORS
0000000000000C1C TP.TPVSB.FSI.W.FSI_SHIFT.RESET_ERRORS
0000000000000C07 TP.TPVSB.FSI.W.FSI_SHIFT.STATUS
0000000000000C1C TP.TPVSB.FSI.W.FSI_SHIFT.STATUS
0000000000000C07 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MLEVP1
000000000000301C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MLEVP1
0000000000000C08 TP.TPVSB.FSI.W.FSI_SHIFT.EXTENDED_STATUS
0000000000000C20 TP.TPVSB.FSI.W.FSI_SHIFT.EXTENDED_STATUS
0000000000000C08 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MCENP0
0000000000003020 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MCENP0
0000000000000C08 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MREFP0
0000000000003020 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MREFP0
0000000000000C09 TP.TPVSB.FSI.W.FSI_SHIFT.CHIP_ID
0000000000000C24 TP.TPVSB.FSI.W.FSI_SHIFT.CHIP_ID
0000000000000C09 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MREFP1
0000000000003024 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MREFP1
0000000000000C0C TP.TPVSB.FSI.W.FSI_SHIFT.COMPLEMENT_MASK
0000000000000C30 TP.TPVSB.FSI.W.FSI_SHIFT.COMPLEMENT_MASK
0000000000000C0C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSIEP0
0000000000003030 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSIEP0
0000000000000C0D TP.TPVSB.FSI.W.FSI_SHIFT.TRUE_MASK
0000000000000C34 TP.TPVSB.FSI.W.FSI_SHIFT.TRUE_MASK
0000000000000C0D TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSIEP1
0000000000003034 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSIEP1
0000000000000C0E TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSIEP2
0000000000003038 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSIEP2
0000000000000C0F TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSIEP3
000000000000303C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSIEP3
0000000000000C10 TP.TPVSB.FSI.W.FSI_SHIFT.SHIFT_CONTROL_REGISTER_2
0000000000000C40 TP.TPVSB.FSI.W.FSI_SHIFT.SHIFT_CONTROL_REGISTER_2
0000000000000C10 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSIEP4
0000000000003040 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSIEP4
0000000000000C11 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSIEP5
0000000000003044 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSIEP5
0000000000000C12 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSIEP6
0000000000003048 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSIEP6
0000000000000C13 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSIEP7
000000000000304C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSIEP7
0000000000000C14 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MAESP0
0000000000003050 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MAESP0
0000000000000C14 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSSIEP0
0000000000003050 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSSIEP0
0000000000000C15 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MAESP1
0000000000003054 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MAESP1
0000000000000C16 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MAESP2
0000000000003058 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MAESP2
0000000000000C17 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MAESP3
000000000000305C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MAESP3
0000000000000C18 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MAESP4
0000000000003060 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MAESP4
0000000000000C19 TP.TPVSB.FSI.W.FSI_SHIFT.DMA_MODE_REGISTER
0000000000000C64 TP.TPVSB.FSI.W.FSI_SHIFT.DMA_MODE_REGISTER
0000000000000C19 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MAESP5
0000000000003064 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MAESP5
0000000000000C1A TP.TPVSB.FSI.W.FSI_SHIFT.DMA_STAT_COMP_MASK_REGISTER
0000000000000C68 TP.TPVSB.FSI.W.FSI_SHIFT.DMA_STAT_COMP_MASK_REGISTER
0000000000000C1A TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MAESP6
0000000000003068 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MAESP6
0000000000000C1B TP.TPVSB.FSI.W.FSI_SHIFT.DMA_OP_BLOCKSIZE_REGISTER
0000000000000C6C TP.TPVSB.FSI.W.FSI_SHIFT.DMA_OP_BLOCKSIZE_REGISTER
0000000000000C1B TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MAESP7
000000000000306C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MAESP7
0000000000000C1C TP.TPVSB.FSI.W.FSI_SHIFT.DMA_REM_SIZE_REGISTER
0000000000000C70 TP.TPVSB.FSI.W.FSI_SHIFT.DMA_REM_SIZE_REGISTER
0000000000000C1C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MAEB
0000000000003070 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MAEB
0000000000000C1C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MCSIEP0
0000000000003070 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MCSIEP0
0000000000000C1D TP.TPVSB.FSI.W.FSI_SHIFT.DMA_PIB_SND_BUFFER0_REGISTER
0000000000000C74 TP.TPVSB.FSI.W.FSI_SHIFT.DMA_PIB_SND_BUFFER0_REGISTER
0000000000000C1D TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MVER
0000000000003074 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MVER
0000000000000C1E TP.TPVSB.FSI.W.FSI_SHIFT.DMA_PIB_SND_BUFFER1_REGISTER
0000000000000C78 TP.TPVSB.FSI.W.FSI_SHIFT.DMA_PIB_SND_BUFFER1_REGISTER
0000000000000C1F TP.TPVSB.FSI.W.FSI_SHIFT.DMA_PIB_RCV_BUFFER0_REGISTER
0000000000000C7C TP.TPVSB.FSI.W.FSI_SHIFT.DMA_PIB_RCV_BUFFER0_REGISTER
0000000000000C20 TP.TPVSB.FSI.W.FSI_SHIFT.DMA_PIB_RCV_BUFFER1_REGISTER
0000000000000C80 TP.TPVSB.FSI.W.FSI_SHIFT.DMA_PIB_RCV_BUFFER1_REGISTER
0000000000000C21 TP.TPVSB.FSI.W.FSI_SHIFT.DMA_ERROR_PTR_REGISTER
0000000000000C84 TP.TPVSB.FSI.W.FSI_SHIFT.DMA_ERROR_PTR_REGISTER
0000000000000C22 TP.TPVSB.FSI.W.FSI_SHIFT.DMA_SCOM_CMD_REGISTER
0000000000000C88 TP.TPVSB.FSI.W.FSI_SHIFT.DMA_SCOM_CMD_REGISTER
0000000000000C34 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MRESP0
00000000000030D0 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MRESP0
0000000000000C34 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSTAP0
00000000000030D0 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSTAP0
0000000000000C35 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MRESP1
00000000000030D4 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MRESP1
0000000000000C35 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSTAP1
00000000000030D4 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSTAP1
0000000000000C36 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MRESP2
00000000000030D8 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MRESP2
0000000000000C36 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSTAP2
00000000000030D8 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSTAP2
0000000000000C37 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MRESP3
00000000000030DC TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MRESP3
0000000000000C37 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSTAP3
00000000000030DC TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSTAP3
0000000000000C38 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MRESP4
00000000000030E0 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MRESP4
0000000000000C38 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSTAP4
00000000000030E0 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSTAP4
0000000000000C39 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MRESP5
00000000000030E4 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MRESP5
0000000000000C39 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSTAP5
00000000000030E4 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSTAP5
0000000000000C3A TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MRESP6
00000000000030E8 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MRESP6
0000000000000C3A TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSTAP6
00000000000030E8 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSTAP6
0000000000000C3B TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MRESP7
00000000000030EC TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MRESP7
0000000000000C3B TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSTAP7
00000000000030EC TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSTAP7
0000000000000C74 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MESRB0
00000000000031D0 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MESRB0
0000000000000C74 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MRESB0
00000000000031D0 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MRESB0
0000000000000C75 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSCSB0
00000000000031D4 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MSCSB0
0000000000000C76 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MATRB0
00000000000031D8 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MATRB0
0000000000000C77 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MDTRB0
00000000000031DC TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MDTRB0
0000000000000CB8 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MECTRL
00000000000032E0 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_0_MECTRL
0000000000000D00 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MMODE
0000000000003400 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MMODE
0000000000000D01 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MDLYR
0000000000003404 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MDLYR
0000000000000D02 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MCRSP0
0000000000003408 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MCRSP0
0000000000000D03 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MCRSP1
000000000000340C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MCRSP1
0000000000000D04 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MENP0
0000000000003410 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MENP0
0000000000000D05 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MENP1
0000000000003414 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MENP1
0000000000000D06 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MLEVP0
0000000000003418 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MLEVP0
0000000000000D06 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSENP0
0000000000003418 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSENP0
0000000000000D07 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MLEVP1
000000000000341C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MLEVP1
0000000000000D08 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MCENP0
0000000000003420 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MCENP0
0000000000000D08 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MREFP0
0000000000003420 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MREFP0
0000000000000D09 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MREFP1
0000000000003424 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MREFP1
0000000000000D0C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSIEP0
0000000000003430 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSIEP0
0000000000000D0D TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSIEP1
0000000000003434 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSIEP1
0000000000000D0E TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSIEP2
0000000000003438 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSIEP2
0000000000000D0F TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSIEP3
000000000000343C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSIEP3
0000000000000D10 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSIEP4
0000000000003440 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSIEP4
0000000000000D11 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSIEP5
0000000000003444 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSIEP5
0000000000000D12 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSIEP6
0000000000003448 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSIEP6
0000000000000D13 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSIEP7
000000000000344C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSIEP7
0000000000000D14 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MAESP0
0000000000003450 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MAESP0
0000000000000D14 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSSIEP0
0000000000003450 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSSIEP0
0000000000000D15 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MAESP1
0000000000003454 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MAESP1
0000000000000D16 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MAESP2
0000000000003458 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MAESP2
0000000000000D17 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MAESP3
000000000000345C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MAESP3
0000000000000D18 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MAESP4
0000000000003460 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MAESP4
0000000000000D19 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MAESP5
0000000000003464 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MAESP5
0000000000000D1A TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MAESP6
0000000000003468 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MAESP6
0000000000000D1B TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MAESP7
000000000000346C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MAESP7
0000000000000D1C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MAEB
0000000000003470 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MAEB
0000000000000D1C TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MCSIEP0
0000000000003470 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MCSIEP0
0000000000000D1D TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MVER
0000000000003474 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MVER
0000000000000D34 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MRESP0
00000000000034D0 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MRESP0
0000000000000D34 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSTAP0
00000000000034D0 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSTAP0
0000000000000D35 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MRESP1
00000000000034D4 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MRESP1
0000000000000D35 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSTAP1
00000000000034D4 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSTAP1
0000000000000D36 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MRESP2
00000000000034D8 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MRESP2
0000000000000D36 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSTAP2
00000000000034D8 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSTAP2
0000000000000D37 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MRESP3
00000000000034DC TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MRESP3
0000000000000D37 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSTAP3
00000000000034DC TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSTAP3
0000000000000D38 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MRESP4
00000000000034E0 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MRESP4
0000000000000D38 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSTAP4
00000000000034E0 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSTAP4
0000000000000D39 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MRESP5
00000000000034E4 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MRESP5
0000000000000D39 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSTAP5
00000000000034E4 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSTAP5
0000000000000D3A TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MRESP6
00000000000034E8 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MRESP6
0000000000000D3A TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSTAP6
00000000000034E8 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSTAP6
0000000000000D3B TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MRESP7
00000000000034EC TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MRESP7
0000000000000D3B TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSTAP7
00000000000034EC TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSTAP7
0000000000000D74 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MESRB0
00000000000035D0 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MESRB0
0000000000000D74 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MRESB0
00000000000035D0 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MRESB0
0000000000000D75 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSCSB0
00000000000035D4 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MSCSB0
0000000000000D76 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MATRB0
00000000000035D8 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MATRB0
0000000000000D77 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MDTRB0
00000000000035DC TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MDTRB0
0000000000000DB8 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MECTRL
00000000000036E0 TP.TPVSB.FSI.W.FSI_SLAVE.FSI_A_MST_1_MECTRL
0000000000001000 TP.TPVSB.FSI.W.FSI2PIB.DATA_REGISTER_0
0000000000001001 TP.TPVSB.FSI.W.FSI2PIB.DATA_REGISTER_1
0000000000001004 TP.TPVSB.FSI.W.FSI2PIB.DATA_REGISTER_1
0000000000001002 TP.TPVSB.FSI.W.FSI2PIB.COMMAND_REGISTER
0000000000001008 TP.TPVSB.FSI.W.FSI2PIB.COMMAND_REGISTER
0000000000001006 TP.TPVSB.FSI.W.FSI2PIB.RESET
0000000000001018 TP.TPVSB.FSI.W.FSI2PIB.RESET
0000000000001007 TP.TPVSB.FSI.W.FSI2PIB.SET_PIB_RESET
000000000000101C TP.TPVSB.FSI.W.FSI2PIB.SET_PIB_RESET
0000000000001007 TP.TPVSB.FSI.W.FSI2PIB.STATUS
000000000000101C TP.TPVSB.FSI.W.FSI2PIB.STATUS
000000000000100A TP.TPVSB.FSI.W.FSI2PIB.CHIPID
0000000000001028 TP.TPVSB.FSI.W.FSI2PIB.CHIPID
000000000000100B TP.TPVSB.FSI.W.FSI2PIB.INTERRUPT
000000000000102C TP.TPVSB.FSI.W.FSI2PIB.INTERRUPT
000000000000100C TP.TPVSB.FSI.W.FSI2PIB.COMPLEMENT_MASK
0000000000001030 TP.TPVSB.FSI.W.FSI2PIB.COMPLEMENT_MASK
000000000000100D TP.TPVSB.FSI.W.FSI2PIB.TRUE_MASK
0000000000001034 TP.TPVSB.FSI.W.FSI2PIB.TRUE_MASK
0000000000001400 TP.TPVSB.FSI.W.FSI2PIB.SCPSIZE
0000000000001401 TP.TPVSB.FSI.W.FSI2PIB.FSISCRPD1
0000000000001404 TP.TPVSB.FSI.W.FSI2PIB.FSISCRPD1
0000000000001402 TP.TPVSB.FSI.W.FSI2PIB.FSISCRPD2
0000000000001408 TP.TPVSB.FSI.W.FSI2PIB.FSISCRPD2
0000000000001403 TP.TPVSB.FSI.W.FSI2PIB.FSISCRPD3
000000000000140C TP.TPVSB.FSI.W.FSI2PIB.FSISCRPD3
0000000000001800 TP.TPVSB.FSI.W.FSI_I2C.FIFO1_REGISTER_READ_A
0000000000001801 TP.TPVSB.FSI.W.FSI_I2C.COMMAND_REGISTER_A
0000000000001802 TP.TPVSB.FSI.W.FSI_I2C.MODE_REGISTER_A
0000000000001803 TP.TPVSB.FSI.W.FSI_I2C.WATER_MARK_REGISTER_A
0000000000001804 TP.TPVSB.FSI.W.FSI_I2C.INTERRUPT_MASK_REGISTER_A
0000000000001805 TP.TPVSB.FSI.W.FSI_I2C.INTERRUPT_MASK_REGISTER_A
0000000000001806 TP.TPVSB.FSI.W.FSI_I2C.INTERRUPT_MASK_REGISTER_A
0000000000001804 TP.TPVSB.FSI.W.FSI_I2C.INTERRUPT_MASK_REGISTER_READ_A
0000000000001805 TP.TPVSB.FSI.W.FSI_I2C.INTERRUPT_COND_A
0000000000001806 TP.TPVSB.FSI.W.FSI_I2C.INTERRUPTS_A
0000000000001807 TP.TPVSB.FSI.W.FSI_I2C.IMM_RESET_I2C_A
0000000000001807 TP.TPVSB.FSI.W.FSI_I2C.STATUS_REGISTER_ENGINE_A
0000000000001808 TP.TPVSB.FSI.W.FSI_I2C.EXTENDED_STATUS_A
0000000000001808 TP.TPVSB.FSI.W.FSI_I2C.IMM_RESET_ERR_A
0000000000001809 TP.TPVSB.FSI.W.FSI_I2C.IMM_SET_S_SCL_A
0000000000001809 TP.TPVSB.FSI.W.FSI_I2C.RESIDUAL_FRONT_END_BACK_END_LENGTH_A
000000000000180A TP.TPVSB.FSI.W.FSI_I2C.I2C_BUSY_REGISTER_A
000000000000180B TP.TPVSB.FSI.W.FSI_I2C.IMM_RESET_S_SCL_A
000000000000180C TP.TPVSB.FSI.W.FSI_I2C.IMM_SET_S_SDA_A
000000000000180D TP.TPVSB.FSI.W.FSI_I2C.IMM_RESET_S_SDA_A
0000000000001C00 TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.DATA_REGISTER_0
0000000000001C01 TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.DATA_REGISTER_1
0000000000001C04 TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.DATA_REGISTER_1
0000000000001C02 TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.COMMAND_REGISTER
0000000000001C08 TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.COMMAND_REGISTER
0000000000001C06 TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.RESET
0000000000001C18 TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.RESET
0000000000001C07 TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.SET_PIB_RESET
0000000000001C1C TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.SET_PIB_RESET
0000000000001C07 TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.STATUS
0000000000001C1C TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.STATUS
0000000000001C0B TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.INTERRUPT
0000000000001C2C TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.INTERRUPT
0000000000001C0C TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.COMPLEMENT_MASK
0000000000001C30 TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.COMPLEMENT_MASK
0000000000001C0D TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.TRUE_MASK
0000000000001C34 TP.TPVSB.FSI.W.FSI_SPIMC.FSI2SPI.TRUE_MASK
0000000000002400 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_UPFIFO_DATA_IN
0000000000002401 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_UPFIFO_STATUS
0000000000002404 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_UPFIFO_STATUS
00000000000B0001 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_UPFIFO_STATUS
0000000000002402 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_UPFIFO_SIG_EOT
0000000000002408 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_UPFIFO_SIG_EOT
0000000000002403 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_UPFIFO_REQ_RESET
000000000000240C TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_UPFIFO_REQ_RESET
0000000000002410 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_DNFIFO_DATA_OUT
0000000000002440 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_DNFIFO_DATA_OUT
0000000000002411 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_DOWNFIFO_STATUS
0000000000002444 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_DOWNFIFO_STATUS
00000000000B0011 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_DOWNFIFO_STATUS
0000000000002414 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_DOWNFIFO_RESET
0000000000002450 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_DOWNFIFO_RESET
0000000000002415 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_DOWNFIFO_ACK_EOT
0000000000002454 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_DOWNFIFO_ACK_EOT
0000000000002416 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_DOWNFIFO_MTC
0000000000002458 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_DOWNFIFO_MTC
00000000000B0016 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_DOWNFIFO_MTC
0000000000002420 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HUPFIFO_DATA_IN
0000000000002480 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HUPFIFO_DATA_IN
0000000000002421 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HUPFIFO_STATUS
0000000000002484 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HUPFIFO_STATUS
00000000000B0021 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HUPFIFO_STATUS
0000000000002422 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HUPFIFO_SIG_EOT
0000000000002488 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HUPFIFO_SIG_EOT
0000000000002423 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HUPFIFO_REQ_RESET
000000000000248C TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HUPFIFO_REQ_RESET
0000000000002430 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HDNFIFO_DATA_OUT
00000000000024C0 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HDNFIFO_DATA_OUT
0000000000002431 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HDOWNFIFO_STATUS
00000000000024C4 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HDOWNFIFO_STATUS
00000000000B0031 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HDOWNFIFO_STATUS
0000000000002434 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HDOWNFIFO_RESET
00000000000024D0 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HDOWNFIFO_RESET
0000000000002435 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HDOWNFIFO_ACK_EOT
00000000000024D4 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HDOWNFIFO_ACK_EOT
0000000000002436 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HDOWNFIFO_MTC
00000000000024D8 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HDOWNFIFO_MTC
00000000000B0036 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HDOWNFIFO_MTC
0000000000002470 TP.TPVSB.FSI.W.FSI_SBE_FIFO.SBE2FSI_INTR_STATUS
00000000000025C0 TP.TPVSB.FSI.W.FSI_SBE_FIFO.SBE2FSI_INTR_STATUS
00000000000B0070 TP.TPVSB.FSI.W.FSI_SBE_FIFO.SBE2FSI_INTR_STATUS
0000000000002472 TP.TPVSB.FSI.W.FSI_SBE_FIFO.SBE2FSI_INTR_CLEAR
00000000000025C8 TP.TPVSB.FSI.W.FSI_SBE_FIFO.SBE2FSI_INTR_CLEAR
0000000000002801 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBS_CS
0000000000002804 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBS_CS
0000000000050001 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBS_CS
0000000000002802 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBS_TR
0000000000002808 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBS_TR
0000000000050002 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBS_TR
0000000000002803 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBS_EL
000000000000280C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBS_EL
0000000000050003 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBS_EL
0000000000002804 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBS_ENVSTAT
0000000000002810 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBS_ENVSTAT
0000000000050004 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBS_ENVSTAT
0000000000002805 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBS_TR_HIST
0000000000002814 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBS_TR_HIST
0000000000050005 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBS_TR_HIST
0000000000002806 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBS_EL_HIST
0000000000002818 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBS_EL_HIST
0000000000050006 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBS_EL_HIST
0000000000002808 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SB_CS
0000000000002820 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SB_CS
0000000000050008 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SB_CS
0000000000002809 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SB_MSG
0000000000002824 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SB_MSG
0000000000050009 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SB_MSG
000000000000280B TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBS_STAT
000000000000282C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBS_STAT
000000000005000B TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.CBS_STAT
0000000000002810 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL0
0000000000002840 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL0
0000000000050010 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL0
0000000000002811 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL1
0000000000002844 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL1
0000000000050011 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL1
0000000000002812 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL2
0000000000002848 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL2
0000000000050012 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL2
0000000000002813 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL3
000000000000284C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL3
0000000000050013 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL3
0000000000002814 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL4
0000000000002850 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL4
0000000000050014 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL4
0000000000002815 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL5
0000000000002854 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL5
0000000000050015 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL5
0000000000002816 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL6
0000000000002858 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL6
0000000000050016 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL6
0000000000002817 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL7
000000000000285C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL7
0000000000050017 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL7
0000000000002818 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL8
0000000000002860 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL8
0000000000050018 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL8
000000000000281A TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL0
0000000000002868 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL0
000000000005001A TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL0
000000000000281B TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL1
000000000000286C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL1
000000000005001B TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL1
000000000000281D TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SNS1LTH
0000000000002874 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SNS1LTH
000000000005001D TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SNS1LTH
000000000000281E TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SNS2LTH
0000000000002878 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SNS2LTH
000000000005001E TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SNS2LTH
000000000000281F TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPWRP
000000000000287C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPWRP
000000000005001F TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.GPWRP
0000000000002821 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_HEADER_COMMAND_0_A
0000000000002884 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_HEADER_COMMAND_0_A
0000000000050021 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_HEADER_COMMAND_0_A
0000000000002822 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_HEADER_COMMAND_1_A
0000000000002888 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_HEADER_COMMAND_1_A
0000000000050022 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_HEADER_COMMAND_1_A
0000000000002823 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_HEADER_COMMAND_2_A
000000000000288C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_HEADER_COMMAND_2_A
0000000000050023 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_HEADER_COMMAND_2_A
0000000000002824 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.DOORBELL_STATUS_CONTROL_1A
0000000000002890 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.DOORBELL_STATUS_CONTROL_1A
0000000000050020 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.DOORBELL_STATUS_CONTROL_1A
0000000000002825 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_HEADER_COMMAND_0_B
0000000000002894 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_HEADER_COMMAND_0_B
0000000000050025 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_HEADER_COMMAND_0_B
0000000000002826 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_HEADER_COMMAND_1_B
0000000000002898 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_HEADER_COMMAND_1_B
0000000000050026 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_HEADER_COMMAND_1_B
0000000000002827 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_HEADER_COMMAND_2_B
000000000000289C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_HEADER_COMMAND_2_B
0000000000050027 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_HEADER_COMMAND_2_B
0000000000002829 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_2_HEADER_COMMAND_0_A
00000000000028A4 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_2_HEADER_COMMAND_0_A
0000000000050029 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_2_HEADER_COMMAND_0_A
000000000000282A TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_2_HEADER_COMMAND_1_A
00000000000028A8 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_2_HEADER_COMMAND_1_A
000000000005002A TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_2_HEADER_COMMAND_1_A
000000000000282B TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_2_HEADER_COMMAND_2_A
00000000000028AC TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_2_HEADER_COMMAND_2_A
000000000005002B TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_2_HEADER_COMMAND_2_A
000000000000282C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.DOORBELL_STATUS_CONTROL_2A
00000000000028B0 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.DOORBELL_STATUS_CONTROL_2A
0000000000050028 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.DOORBELL_STATUS_CONTROL_2A
000000000000282D TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_2_HEADER_COMMAND_0_B
00000000000028B4 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_2_HEADER_COMMAND_0_B
000000000005002D TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_2_HEADER_COMMAND_0_B
000000000000282E TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_2_HEADER_COMMAND_1_B
00000000000028B8 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_2_HEADER_COMMAND_1_B
000000000005002E TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_2_HEADER_COMMAND_1_B
000000000000282F TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_2_HEADER_COMMAND_2_B
00000000000028BC TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_2_HEADER_COMMAND_2_B
000000000005002F TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_2_HEADER_COMMAND_2_B
0000000000002830 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS
00000000000028C0 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS
0000000000050030 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS
0000000000002831 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS
00000000000028C4 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS
0000000000050031 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS
0000000000002832 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_SLAVE_A_DOORBELL_INTERRUPT
00000000000028C8 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_SLAVE_A_DOORBELL_INTERRUPT
0000000000050032 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_SLAVE_A_DOORBELL_INTERRUPT
0000000000002833 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1
00000000000028CC TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1
0000000000050033 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1
0000000000050034 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1
0000000000002835 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_SLAVE_B_DOORBELL_INTERRUPT
00000000000028D4 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_SLAVE_B_DOORBELL_INTERRUPT
0000000000050035 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_SLAVE_B_DOORBELL_INTERRUPT
0000000000002836 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1
0000000000002837 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1
00000000000028D8 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1
0000000000050036 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1
0000000000002838 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_1
00000000000028E0 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_1
0000000000050038 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_1
0000000000002839 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_2
00000000000028E4 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_2
0000000000050039 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_2
000000000000283A TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_3
00000000000028E8 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_3
000000000005003A TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_3
000000000000283B TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_4
00000000000028EC TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_4
000000000005003B TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_4
000000000000283C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_5
00000000000028F0 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_5
000000000005003C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_5
000000000000283D TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_6
00000000000028F4 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_6
000000000005003D TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_6
000000000000283E TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_7
00000000000028F8 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_7
000000000005003E TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_7
000000000000283F TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_8
00000000000028FC TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_8
000000000005003F TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_8
0000000000002840 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_0
0000000000002900 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_0
0000000000050040 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_0
0000000000002841 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_1
0000000000002904 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_1
0000000000050041 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_1
0000000000002842 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_2
0000000000002908 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_2
0000000000050042 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_2
0000000000002843 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_3
000000000000290C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_3
0000000000050043 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_3
0000000000002844 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_4
0000000000002910 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_4
0000000000050044 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_4
0000000000002845 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_5
0000000000002914 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_5
0000000000050045 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_5
0000000000002846 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_6
0000000000002918 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_6
0000000000050046 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_6
0000000000002847 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_7
000000000000291C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_7
0000000000050047 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_7
0000000000002848 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_8
0000000000002920 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_8
0000000000050048 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_8
0000000000002849 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_9
0000000000002924 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_9
0000000000050049 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_9
000000000000284A TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_10
0000000000002928 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_10
000000000005004A TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_10
000000000000284B TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_11
000000000000292C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_11
000000000005004B TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_11
000000000000284C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_12
0000000000002930 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_12
000000000005004C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_12
000000000000284D TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_13
0000000000002934 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_13
000000000005004D TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_13
000000000000284E TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_14
0000000000002938 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_14
000000000005004E TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_14
000000000000284F TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_15
000000000000293C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_15
000000000005004F TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1A_DATA_AREA_15
0000000000002880 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_0
0000000000002A00 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_0
0000000000050080 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_0
0000000000002881 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_1
0000000000002A04 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_1
0000000000050081 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_1
0000000000002882 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_2
0000000000002A08 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_2
0000000000050082 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_2
0000000000002883 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_3
0000000000002A0C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_3
0000000000050083 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_3
0000000000002884 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_4
0000000000002A10 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_4
0000000000050084 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_4
0000000000002885 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_5
0000000000002A14 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_5
0000000000050085 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_5
0000000000002886 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_6
0000000000002A18 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_6
0000000000050086 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_6
0000000000002887 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_7
0000000000002A1C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_7
0000000000050087 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_7
0000000000002888 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_8
0000000000002A20 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_8
0000000000050088 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_8
0000000000002889 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_9
0000000000002A24 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_9
0000000000050089 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_9
000000000000288A TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_10
0000000000002A28 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_10
000000000005008A TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_10
000000000000288B TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_11
0000000000002A2C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_11
000000000005008B TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_11
000000000000288C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_12
0000000000002A30 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_12
000000000005008C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_12
000000000000288D TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_13
0000000000002A34 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_13
000000000005008D TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_13
000000000000288E TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_14
0000000000002A38 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_14
000000000005008E TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_14
000000000000288F TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_15
0000000000002A3C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_15
000000000005008F TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M1B_DATA_AREA_15
00000000000028C0 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_0
0000000000002B00 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_0
00000000000500C0 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_0
00000000000028C1 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_1
0000000000002B04 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_1
00000000000500C1 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_1
00000000000028C2 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_2
0000000000002B08 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_2
00000000000500C2 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_2
00000000000028C3 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_3
0000000000002B0C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_3
00000000000500C3 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_3
00000000000028C4 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_4
0000000000002B10 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_4
00000000000500C4 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_4
00000000000028C5 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_5
0000000000002B14 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_5
00000000000500C5 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_5
00000000000028C6 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_6
0000000000002B18 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_6
00000000000500C6 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_6
00000000000028C7 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_7
0000000000002B1C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_7
00000000000500C7 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_7
00000000000028C8 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_8
0000000000002B20 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_8
00000000000500C8 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_8
00000000000028C9 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_9
0000000000002B24 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_9
00000000000500C9 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_9
00000000000028CA TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_10
0000000000002B28 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_10
00000000000500CA TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_10
00000000000028CB TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_11
0000000000002B2C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_11
00000000000500CB TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_11
00000000000028CC TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_12
0000000000002B30 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_12
00000000000500CC TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_12
00000000000028CD TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_13
0000000000002B34 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_13
00000000000500CD TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_13
00000000000028CE TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_14
0000000000002B38 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_14
00000000000500CE TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_14
00000000000028CF TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_15
0000000000002B3C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_15
00000000000500CF TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2A_DATA_AREA_15
0000000000002900 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_0
0000000000002C00 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_0
0000000000050100 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_0
0000000000002901 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_1
0000000000002C04 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_1
0000000000050101 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_1
0000000000002902 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_2
0000000000002C08 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_2
0000000000050102 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_2
0000000000002903 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_3
0000000000002C0C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_3
0000000000050103 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_3
0000000000002904 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_4
0000000000002C10 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_4
0000000000050104 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_4
0000000000002905 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_5
0000000000002C14 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_5
0000000000050105 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_5
0000000000002906 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_6
0000000000002C18 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_6
0000000000050106 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_6
0000000000002907 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_7
0000000000002C1C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_7
0000000000050107 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_7
0000000000002908 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_8
0000000000002C20 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_8
0000000000050108 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_8
0000000000002909 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_9
0000000000002C24 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_9
0000000000050109 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_9
000000000000290A TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_10
0000000000002C28 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_10
000000000005010A TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_10
000000000000290B TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_11
0000000000002C2C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_11
000000000005010B TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_11
000000000000290C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_12
0000000000002C30 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_12
000000000005010C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_12
000000000000290D TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_13
0000000000002C34 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_13
000000000005010D TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_13
000000000000290E TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_14
0000000000002C38 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_14
000000000005010E TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_14
000000000000290F TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_15
0000000000002C3C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_15
000000000005010F TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.M2B_DATA_AREA_15
0000000000002910 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL0_COPY
0000000000002C40 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL0_COPY
0000000000050110 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL0_COPY
0000000000002911 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL1_COPY
0000000000002C44 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL1_COPY
0000000000050111 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL1_COPY
0000000000002912 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL2_COPY
0000000000002C48 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL2_COPY
0000000000050112 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL2_COPY
0000000000002913 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL3_COPY
0000000000002C4C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL3_COPY
0000000000050113 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL3_COPY
0000000000002914 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL4_COPY
0000000000002C50 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL4_COPY
0000000000050114 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL4_COPY
0000000000002915 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL5_COPY
0000000000002C54 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL5_COPY
0000000000050115 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL5_COPY
0000000000002916 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL6_COPY
0000000000002C58 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL6_COPY
0000000000050116 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL6_COPY
0000000000002917 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL7_COPY
0000000000002C5C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL7_COPY
0000000000050117 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL7_COPY
0000000000002918 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL8_COPY
0000000000002C60 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL8_COPY
0000000000050118 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL8_COPY
000000000000291A TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL0_COPY
0000000000002C68 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL0_COPY
000000000005011A TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL0_COPY
000000000000291B TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL1_COPY
0000000000002C6C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL1_COPY
000000000005011B TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL1_COPY
0000000000002920 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL0_SET
0000000000002C80 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL0_SET
0000000000050120 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL0_SET
0000000000002921 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL1_SET
0000000000002C84 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL1_SET
0000000000050121 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL1_SET
0000000000002922 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL2_SET
0000000000002C88 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL2_SET
0000000000050122 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL2_SET
0000000000002923 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL3_SET
0000000000002C8C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL3_SET
0000000000050123 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL3_SET
0000000000002924 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL4_SET
0000000000002C90 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL4_SET
0000000000050124 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL4_SET
0000000000002925 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL5_SET
0000000000002C94 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL5_SET
0000000000050125 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL5_SET
0000000000002926 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL6_SET
0000000000002C98 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL6_SET
0000000000050126 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL6_SET
0000000000002927 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL7_SET
0000000000002C9C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL7_SET
0000000000050127 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL7_SET
0000000000002928 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL8_SET
0000000000002CA0 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL8_SET
0000000000050128 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL8_SET
000000000000292A TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL0_SET
0000000000002CA8 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL0_SET
000000000005012A TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL0_SET
000000000000292B TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL1_SET
0000000000002CAC TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL1_SET
000000000005012B TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL1_SET
0000000000002930 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL0_CLEAR
0000000000002CC0 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL0_CLEAR
0000000000050130 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL0_CLEAR
0000000000002931 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL1_CLEAR
0000000000002CC4 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL1_CLEAR
0000000000050131 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL1_CLEAR
0000000000002932 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL2_CLEAR
0000000000002CC8 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL2_CLEAR
0000000000050132 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL2_CLEAR
0000000000002933 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL3_CLEAR
0000000000002CCC TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL3_CLEAR
0000000000050133 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL3_CLEAR
0000000000002934 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL4_CLEAR
0000000000002CD0 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL4_CLEAR
0000000000050134 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL4_CLEAR
0000000000002935 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL5_CLEAR
0000000000002CD4 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL5_CLEAR
0000000000050135 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL5_CLEAR
0000000000002936 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL6_CLEAR
0000000000002CD8 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL6_CLEAR
0000000000050136 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL6_CLEAR
0000000000002937 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL7_CLEAR
0000000000002CDC TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL7_CLEAR
0000000000050137 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL7_CLEAR
0000000000002938 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL8_CLEAR
0000000000002CE0 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL8_CLEAR
0000000000050138 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRL8_CLEAR
000000000000293A TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL0_CLEAR
0000000000002CE8 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL0_CLEAR
000000000005013A TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL0_CLEAR
000000000000293B TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL1_CLEAR
0000000000002CEC TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL1_CLEAR
000000000005013B TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRL1_CLEAR
0000000000002940 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.RCS_EL0
0000000000002D00 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.RCS_EL0
0000000000050140 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.RCS_EL0
0000000000002941 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.RCS_EL1
0000000000002D04 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.RCS_EL1
0000000000050141 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.RCS_EL1
0000000000002942 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.RCS_EL2
0000000000002D08 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.RCS_EL2
0000000000050142 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.RCS_EL2
0000000000002943 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.RCS_EL3
0000000000002D0C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.RCS_EL3
0000000000050143 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.RCS_EL3
0000000000002980 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_9
0000000000002E00 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_9
0000000000050180 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_9
0000000000002981 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_10
0000000000002E04 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_10
0000000000050181 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_10
0000000000002982 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_11
0000000000002E08 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_11
0000000000050182 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_11
0000000000002983 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_12
0000000000002E0C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_12
0000000000050183 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_12
0000000000002984 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_13
0000000000002E10 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_13
0000000000050184 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_13
0000000000002985 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_14
0000000000002E14 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_14
0000000000050185 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_14
0000000000002986 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_15
0000000000002E18 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_15
0000000000050186 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_15
0000000000002987 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_16
0000000000002E1C TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_16
0000000000050187 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.SCRATCH_REGISTER_16
0000000000010000 TP.TPCHIP.PIB.OTP.OTPC_M.COMMAND_REGISTER
0000000000010001 TP.TPCHIP.PIB.OTP.OTPC_M.RESET_REGISTER
0000000000010002 TP.TPCHIP.PIB.OTP.OTPC_M.STATUS_REGISTER
0000000000010003 TP.TPCHIP.PIB.OTP.OTPC_M.DATA_REGISTER
0000000000010005 TP.TPCHIP.PIB.OTP.OTPC_M.SECURITY_SWITCH_REGISTER
0000000000010006 TP.TPCHIP.PIB.OTP.OTPC_M.SECURITY_SWITCH_REGISTER
0000000000010008 TP.TPCHIP.PIB.OTP.OTPC_M.MODE_REGISTER
0000000000010009 TP.TPCHIP.PIB.OTP.OTPC_M.EXPORT_REGL_STATUS
000000000001000E TP.TPCHIP.PIB.OTP.OTPC_M.EXPORT_REGL_CTRL
0000000000010010 TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG0
0000000000010011 TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG1
0000000000010012 TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG2
0000000000010013 TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG3
0000000000010014 TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG4
0000000000010015 TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG5
0000000000010016 TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG6
0000000000010017 TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG7
0000000000010018 TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG8
0000000000010019 TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG9
000000000001001A TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG10
000000000001001B TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG11
000000000001001C TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG12
000000000001001D TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG13
000000000001001E TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG14
000000000001001F TP.TPCHIP.PIB.OTP.OTPC_M.MEASURE_REG15
0000000000010020 TP.TPCHIP.PIB.OTP.OTPC_M.I2CM_SLVID_CONFIG_REG_B
0000000000010021 TP.TPCHIP.PIB.OTP.OTPC_M.I2CM_SLVID_CONFIG_REG_C
0000000000010022 TP.TPCHIP.PIB.OTP.OTPC_M.I2CM_SLVID_CONFIG_REG_E
0000000000018000 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG0
0000000000018001 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG1
0000000000018002 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG2
0000000000018003 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG3
0000000000018004 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG4
0000000000018005 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG5
0000000000018006 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG6
0000000000018007 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG7
0000000000018008 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG8
0000000000018009 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG9
000000000001800A TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG10
000000000001800B TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG11
000000000001800C TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG12
000000000001800D TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG13
000000000001800E TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG14
000000000001800F TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG15
0000000000018010 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG16
0000000000018011 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG17
0000000000018012 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG18
0000000000018013 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG19
0000000000018014 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG20
0000000000018015 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG21
0000000000018016 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG22
0000000000018017 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG23
0000000000018018 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG24
0000000000018019 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG25
000000000001801A TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG26
000000000001801B TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG27
000000000001801C TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG28
000000000001801D TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG29
000000000001801E TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG30
000000000001801F TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG31
0000000000018020 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG32
0000000000018021 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG33
0000000000018022 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG34
0000000000018023 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG35
0000000000018024 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG36
0000000000018025 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG37
0000000000018026 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG38
0000000000018027 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG39
0000000000018028 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG40
0000000000018029 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG41
000000000001802A TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG42
000000000001802B TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG43
000000000001802C TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG44
000000000001802D TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG45
000000000001802E TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG46
000000000001802F TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG47
0000000000018030 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG48
0000000000018031 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG49
0000000000018032 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG50
0000000000018033 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG51
0000000000018034 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG52
0000000000018035 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG53
0000000000018036 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG54
0000000000018037 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG55
0000000000018038 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG56
0000000000018039 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG57
000000000001803A TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG58
000000000001803B TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG59
000000000001803C TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG60
000000000001803D TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG61
000000000001803E TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG62
000000000001803F TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG63
0000000000018040 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG64
0000000000018041 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG65
0000000000018042 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG66
0000000000018043 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG67
0000000000018044 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG68
0000000000018045 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG69
0000000000018046 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG70
0000000000018047 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG71
0000000000018048 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG72
0000000000018049 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG73
000000000001804A TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG74
000000000001804B TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG75
000000000001804C TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG76
000000000001804D TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG77
000000000001804E TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG78
000000000001804F TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG79
0000000000018050 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG80
0000000000018051 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG81
0000000000018052 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG82
0000000000018053 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG83
0000000000018054 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG84
0000000000018055 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG85
0000000000018056 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG86
0000000000018057 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG87
0000000000018058 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG88
0000000000018059 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG89
000000000001805A TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG90
000000000001805B TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG91
000000000001805C TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG92
000000000001805D TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG93
000000000001805E TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG94
000000000001805F TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG95
0000000000018060 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG96
0000000000018061 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG97
0000000000018062 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG98
0000000000018063 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG99
0000000000018064 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG100
0000000000018065 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG101
0000000000018066 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG102
0000000000018067 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG103
0000000000018068 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG104
0000000000018069 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG105
000000000001806A TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG106
000000000001806B TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG107
000000000001806C TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG108
000000000001806D TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG109
000000000001806E TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG110
000000000001806F TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG111
0000000000018070 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG112
0000000000018071 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG113
0000000000018072 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG114
0000000000018073 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG115
0000000000018074 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG116
0000000000018075 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG117
0000000000018076 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG118
0000000000018077 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG119
0000000000018078 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG120
0000000000018079 TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG121
000000000001807A TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG122
000000000001807B TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG123
000000000001807C TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG124
000000000001807D TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG125
000000000001807E TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG126
000000000001807F TP.TPCHIP.OTPROM.SINGLE_OTP_ROM.OTPROM.ROM_REG127
0000000000020000 TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.CMD_WRDAT
0000000000020001 TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.STAT_RDDAT_ERRES
0000000000020002 TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.LSTAT
0000000000020004 TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.RESET
0000000000020005 TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.CRSIC
0000000000020006 TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.CRSIM
0000000000020007 TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.CRSIS
0000000000020008 TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.RSIC
0000000000020009 TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.RSIM
000000000002000A TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#0.P.RSIS
0000000000020010 TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.CMD_WRDAT
0000000000020011 TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.STAT_RDDAT_ERRES
0000000000020012 TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.LSTAT
0000000000020014 TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.RESET
0000000000020015 TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.CRSIC
0000000000020016 TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.CRSIM
0000000000020017 TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.CRSIS
0000000000020018 TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.RSIC
0000000000020019 TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.RSIM
000000000002001A TP.TPVSB.FSI.W.FSI_SLAVE.CMFSI_INCLUDE.MFSI_A.PIB2OPB.COMP.P#1.P.RSIS
0000000000040000 TP.TPCHIP.PIB.TOD.TOD_M_PATH_CTRL_REG
0000000000040001 TP.TPCHIP.PIB.TOD.TOD_PRI_PORT_0_CTRL_REG
0000000000040002 TP.TPCHIP.PIB.TOD.TOD_PRI_PORT_1_CTRL_REG
0000000000040003 TP.TPCHIP.PIB.TOD.TOD_SEC_PORT_0_CTRL_REG
0000000000040004 TP.TPCHIP.PIB.TOD.TOD_SEC_PORT_1_CTRL_REG
0000000000040005 TP.TPCHIP.PIB.TOD.TOD_S_PATH_CTRL_REG
0000000000040006 TP.TPCHIP.PIB.TOD.TOD_I_PATH_CTRL_REG
0000000000040007 TP.TPCHIP.PIB.TOD.TOD_PSS_MSS_CTRL_REG
0000000000040008 TP.TPCHIP.PIB.TOD.TOD_PSS_MSS_STATUS_REG
0000000000040009 TP.TPCHIP.PIB.TOD.TOD_M_PATH_STATUS_REG
000000000004000A TP.TPCHIP.PIB.TOD.TOD_S_PATH_STATUS_REG
000000000004000B TP.TPCHIP.PIB.TOD.TOD_MISC_RESET_REG
000000000004000C TP.TPCHIP.PIB.TOD.TOD_PROBE_SELECT_REG
000000000004000D TP.TPCHIP.PIB.TOD.TOD_TIMER_REG
000000000004000E TP.TPCHIP.PIB.TOD.TOD_M_PATH_0_STEP_STEER_REG
000000000004000F TP.TPCHIP.PIB.TOD.TOD_M_PATH_1_STEP_STEER_REG
0000000000040010 TP.TPCHIP.PIB.TOD.TOD_CHIP_CTRL_REG
0000000000040011 TP.TPCHIP.PIB.TOD.TOD_TX_TTYPE_0_REG
0000000000040012 TP.TPCHIP.PIB.TOD.TOD_TX_TTYPE_1_REG
0000000000040013 TP.TPCHIP.PIB.TOD.TOD_TX_TTYPE_2_REG
0000000000040014 TP.TPCHIP.PIB.TOD.TOD_TX_TTYPE_3_REG
0000000000040015 TP.TPCHIP.PIB.TOD.TOD_TX_TTYPE_4_REG
0000000000040016 TP.TPCHIP.PIB.TOD.TOD_TX_TTYPE_5_REG
0000000000040017 TP.TPCHIP.PIB.TOD.TOD_MOVE_TOD_TO_TB_REG
0000000000040018 TP.TPCHIP.PIB.TOD.TOD_LOAD_TOD_MOD_REG
000000000004001D TP.TPCHIP.PIB.TOD.TOD_TRACE_DATA_1_REG
000000000004001E TP.TPCHIP.PIB.TOD.TOD_TRACE_DATA_2_REG
000000000004001F TP.TPCHIP.PIB.TOD.TOD_TRACE_DATA_3_REG
0000000000040020 TP.TPCHIP.PIB.TOD.TOD_VALUE_REG
0000000000040021 TP.TPCHIP.PIB.TOD.TOD_LOAD_TOD_REG
0000000000040022 TP.TPCHIP.PIB.TOD.TOD_START_TOD_REG
0000000000040023 TP.TPCHIP.PIB.TOD.TOD_LOW_ORDER_STEP_REG
0000000000040024 TP.TPCHIP.PIB.TOD.TOD_FSM_REG
0000000000040027 TP.TPCHIP.PIB.TOD.TOD_TX_TTYPE_CTRL_REG
0000000000040029 TP.TPCHIP.PIB.TOD.TOD_RX_TTYPE_CTRL_REG
0000000000040030 TP.TPCHIP.PIB.TOD.TOD_ERROR_REG
0000000000040031 TP.TPCHIP.PIB.TOD.TOD_ERROR_INJECT_REG
0000000000040032 TP.TPCHIP.PIB.TOD.TOD_ERROR_MASK_REG
0000000000040033 TP.TPCHIP.PIB.TOD.TOD_ERROR_ROUTING_REG
0000000000050190 TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.I2CDEVICEID_REGISTER
0000000000060000 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPETSEL
00000000C0000000 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPETSEL
0000000000060001 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEIVPR
00000000C0000008 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEIVPR
0000000000060002 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEDBG
00000000C0000010 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEDBG
0000000000060004 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEMACR
00000000C0000020 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEMACR
0000000000060005 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPESWPR0
00000000C0000028 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPESWPR0
0000000000060006 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPESWPR1
00000000C0000030 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPESWPR1
0000000000060010 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIXCR
00000000C0000080 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIXCR
0000000000060011 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIRAMRA
00000000C0000088 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIRAMRA
0000000000060012 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIRAMGA
00000000C0000090 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIRAMGA
0000000000060013 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIRAMDBG
00000000C0000098 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIRAMDBG
0000000000060014 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIRAMEDR
00000000C00000A0 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIRAMEDR
0000000000060015 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIDBGPRO
00000000C00000A8 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIDBGPRO
0000000000060016 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXISIB
00000000C00000B0 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXISIB
0000000000060017 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIMEM
00000000C00000B8 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIMEM
0000000000060018 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXISGB
00000000C00000C0 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXISGB
0000000000060019 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIICAC
00000000C00000C8 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIICAC
000000000006001A TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIDCAC
00000000C00000D0 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIDCAC
000000000006001F TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIDBGINF
00000000C00000F8 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIDBGINF
0000000000060020 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEOXIXCR
00000000C0000100 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEOXIXCR
0000000000060021 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIXSR
00000000C0000108 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIXSR
0000000000060022 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXISPRG0
00000000C0000110 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXISPRG0
0000000000060023 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIEDR
00000000C0000118 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIEDR
0000000000060024 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIIR
00000000C0000120 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIIR
0000000000060025 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIIAR
00000000C0000128 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIIAR
0000000000060026 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXISIBU
00000000C0000130 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXISIBU
0000000000060027 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXISIBL
00000000C0000138 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXISIBL
0000000000060028 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIMEMU
00000000C0000140 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIMEMU
0000000000060029 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIMEML
00000000C0000148 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIMEML
000000000006002A TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXISGBU
00000000C0000150 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXISGBU
000000000006002B TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXISGBL
00000000C0000158 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXISGBL
000000000006002C TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIICACU
00000000C0000160 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIICACU
000000000006002D TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIICACL
00000000C0000168 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIICACL
000000000006002E TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIDCACU
00000000C0000170 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIDCACU
000000000006002F TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIDCACL
00000000C0000178 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIDCACL
0000000000060030 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXISRR0
00000000C0000180 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXISRR0
0000000000060031 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXILR
00000000C0000188 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXILR
0000000000060032 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXICTR
00000000C0000190 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXICTR
0000000000060040 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR0
00000000C0000200 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR0
0000000000060041 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR1
00000000C0000208 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR1
0000000000060042 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR2
00000000C0000210 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR2
0000000000060043 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR3
00000000C0000218 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR3
0000000000060044 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR4
00000000C0000220 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR4
0000000000060045 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR5
00000000C0000228 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR5
0000000000060046 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR6
00000000C0000230 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR6
0000000000060047 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR7
00000000C0000238 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR7
0000000000060048 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR8
00000000C0000240 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR8
0000000000060049 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR9
00000000C0000248 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR9
000000000006004A TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR10
00000000C0000250 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR10
000000000006004B TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR13
00000000C0000258 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR13
000000000006004C TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR28
00000000C0000260 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR28
000000000006004D TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR29
00000000C0000268 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR29
000000000006004E TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR30
00000000C0000270 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR30
000000000006004F TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR31
00000000C0000278 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIGPR31
0000000000060080 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIVDR0
00000000C0000400 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIVDR0
0000000000060081 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIVDR2
00000000C0000408 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIVDR2
0000000000060082 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIVDR4
00000000C0000410 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIVDR4
0000000000060083 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIVDR6
00000000C0000418 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIVDR6
0000000000060084 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIVDR8
00000000C0000420 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIVDR8
0000000000060085 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIVDRX
00000000C0000428 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIVDRX
0000000000060086 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIVDR28
00000000C0000430 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIVDR28
0000000000060087 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIVDR30
00000000C0000438 TP.TPCHIP.OCC.OCI.GPE0.OCB_OCI_GPEXIVDR30
0000000000062000 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPETSEL
00000000C0010000 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPETSEL
0000000000062001 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEIVPR
00000000C0010008 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEIVPR
0000000000062002 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEDBG
00000000C0010010 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEDBG
0000000000062004 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEMACR
00000000C0010020 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEMACR
0000000000062005 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPESWPR0
00000000C0010028 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPESWPR0
0000000000062006 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPESWPR1
00000000C0010030 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPESWPR1
0000000000062010 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIXCR
00000000C0010080 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIXCR
0000000000062011 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIRAMRA
00000000C0010088 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIRAMRA
0000000000062012 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIRAMGA
00000000C0010090 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIRAMGA
0000000000062013 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIRAMDBG
00000000C0010098 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIRAMDBG
0000000000062014 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIRAMEDR
00000000C00100A0 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIRAMEDR
0000000000062015 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIDBGPRO
00000000C00100A8 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIDBGPRO
0000000000062016 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXISIB
00000000C00100B0 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXISIB
0000000000062017 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIMEM
00000000C00100B8 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIMEM
0000000000062018 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXISGB
00000000C00100C0 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXISGB
0000000000062019 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIICAC
00000000C00100C8 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIICAC
000000000006201A TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIDCAC
00000000C00100D0 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIDCAC
000000000006201F TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIDBGINF
00000000C00100F8 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIDBGINF
0000000000062020 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEOXIXCR
00000000C0010100 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEOXIXCR
0000000000062021 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIXSR
00000000C0010108 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIXSR
0000000000062022 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXISPRG0
00000000C0010110 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXISPRG0
0000000000062023 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIEDR
00000000C0010118 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIEDR
0000000000062024 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIIR
00000000C0010120 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIIR
0000000000062025 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIIAR
00000000C0010128 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIIAR
0000000000062026 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXISIBU
00000000C0010130 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXISIBU
0000000000062027 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXISIBL
00000000C0010138 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXISIBL
0000000000062028 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIMEMU
00000000C0010140 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIMEMU
0000000000062029 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIMEML
00000000C0010148 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIMEML
000000000006202A TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXISGBU
00000000C0010150 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXISGBU
000000000006202B TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXISGBL
00000000C0010158 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXISGBL
000000000006202C TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIICACU
00000000C0010160 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIICACU
000000000006202D TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIICACL
00000000C0010168 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIICACL
000000000006202E TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIDCACU
00000000C0010170 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIDCACU
000000000006202F TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIDCACL
00000000C0010178 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIDCACL
0000000000062030 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXISRR0
00000000C0010180 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXISRR0
0000000000062031 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXILR
00000000C0010188 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXILR
0000000000062032 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXICTR
00000000C0010190 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXICTR
0000000000062040 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR0
00000000C0010200 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR0
0000000000062041 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR1
00000000C0010208 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR1
0000000000062042 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR2
00000000C0010210 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR2
0000000000062043 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR3
00000000C0010218 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR3
0000000000062044 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR4
00000000C0010220 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR4
0000000000062045 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR5
00000000C0010228 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR5
0000000000062046 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR6
00000000C0010230 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR6
0000000000062047 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR7
00000000C0010238 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR7
0000000000062048 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR8
00000000C0010240 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR8
0000000000062049 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR9
00000000C0010248 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR9
000000000006204A TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR10
00000000C0010250 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR10
000000000006204B TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR13
00000000C0010258 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR13
000000000006204C TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR28
00000000C0010260 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR28
000000000006204D TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR29
00000000C0010268 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR29
000000000006204E TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR30
00000000C0010270 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR30
000000000006204F TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR31
00000000C0010278 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIGPR31
0000000000062080 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIVDR0
00000000C0010400 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIVDR0
0000000000062081 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIVDR2
00000000C0010408 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIVDR2
0000000000062082 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIVDR4
00000000C0010410 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIVDR4
0000000000062083 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIVDR6
00000000C0010418 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIVDR6
0000000000062084 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIVDR8
00000000C0010420 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIVDR8
0000000000062085 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIVDRX
00000000C0010428 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIVDRX
0000000000062086 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIVDR28
00000000C0010430 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIVDR28
0000000000062087 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIVDR30
00000000C0010438 TP.TPCHIP.OCC.OCI.GPE1.OCB_OCI_GPEXIVDR30
0000000000064000 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPETSEL
00000000C0020000 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPETSEL
0000000000064001 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEIVPR
00000000C0020008 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEIVPR
0000000000064002 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEDBG
00000000C0020010 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEDBG
0000000000064004 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEMACR
00000000C0020020 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEMACR
0000000000064005 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPESWPR0
00000000C0020028 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPESWPR0
0000000000064006 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPESWPR1
00000000C0020030 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPESWPR1
0000000000064010 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIXCR
00000000C0020080 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIXCR
0000000000064011 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIRAMRA
00000000C0020088 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIRAMRA
0000000000064012 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIRAMGA
00000000C0020090 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIRAMGA
0000000000064013 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIRAMDBG
00000000C0020098 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIRAMDBG
0000000000064014 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIRAMEDR
00000000C00200A0 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIRAMEDR
0000000000064015 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIDBGPRO
00000000C00200A8 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIDBGPRO
0000000000064016 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXISIB
00000000C00200B0 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXISIB
0000000000064017 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIMEM
00000000C00200B8 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIMEM
0000000000064018 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXISGB
00000000C00200C0 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXISGB
0000000000064019 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIICAC
00000000C00200C8 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIICAC
000000000006401A TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIDCAC
00000000C00200D0 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIDCAC
000000000006401F TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIDBGINF
00000000C00200F8 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIDBGINF
0000000000064020 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEOXIXCR
00000000C0020100 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEOXIXCR
0000000000064021 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIXSR
00000000C0020108 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIXSR
0000000000064022 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXISPRG0
00000000C0020110 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXISPRG0
0000000000064023 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIEDR
00000000C0020118 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIEDR
0000000000064024 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIIR
00000000C0020120 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIIR
0000000000064025 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIIAR
00000000C0020128 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIIAR
0000000000064026 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXISIBU
00000000C0020130 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXISIBU
0000000000064027 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXISIBL
00000000C0020138 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXISIBL
0000000000064028 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIMEMU
00000000C0020140 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIMEMU
0000000000064029 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIMEML
00000000C0020148 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIMEML
000000000006402A TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXISGBU
00000000C0020150 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXISGBU
000000000006402B TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXISGBL
00000000C0020158 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXISGBL
000000000006402C TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIICACU
00000000C0020160 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIICACU
000000000006402D TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIICACL
00000000C0020168 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIICACL
000000000006402E TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIDCACU
00000000C0020170 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIDCACU
000000000006402F TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIDCACL
00000000C0020178 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIDCACL
0000000000064030 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXISRR0
00000000C0020180 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXISRR0
0000000000064031 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXILR
00000000C0020188 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXILR
0000000000064032 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXICTR
00000000C0020190 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXICTR
0000000000064040 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR0
00000000C0020200 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR0
0000000000064041 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR1
00000000C0020208 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR1
0000000000064042 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR2
00000000C0020210 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR2
0000000000064043 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR3
00000000C0020218 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR3
0000000000064044 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR4
00000000C0020220 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR4
0000000000064045 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR5
00000000C0020228 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR5
0000000000064046 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR6
00000000C0020230 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR6
0000000000064047 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR7
00000000C0020238 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR7
0000000000064048 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR8
00000000C0020240 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR8
0000000000064049 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR9
00000000C0020248 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR9
000000000006404A TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR10
00000000C0020250 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR10
000000000006404B TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR13
00000000C0020258 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR13
000000000006404C TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR28
00000000C0020260 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR28
000000000006404D TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR29
00000000C0020268 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR29
000000000006404E TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR30
00000000C0020270 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR30
000000000006404F TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR31
00000000C0020278 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIGPR31
0000000000064080 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIVDR0
00000000C0020400 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIVDR0
0000000000064081 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIVDR2
00000000C0020408 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIVDR2
0000000000064082 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIVDR4
00000000C0020410 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIVDR4
0000000000064083 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIVDR6
00000000C0020418 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIVDR6
0000000000064084 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIVDR8
00000000C0020420 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIVDR8
0000000000064085 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIVDRX
00000000C0020428 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIVDRX
0000000000064086 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIVDR28
00000000C0020430 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIVDR28
0000000000064087 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIVDR30
00000000C0020438 TP.TPCHIP.OCC.OCI.GPE2.OCB_OCI_GPEXIVDR30
0000000000066000 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPETSEL
00000000C0030000 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPETSEL
0000000000066001 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEIVPR
00000000C0030008 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEIVPR
0000000000066002 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEDBG
00000000C0030010 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEDBG
0000000000066004 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEMACR
00000000C0030020 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEMACR
0000000000066005 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPESWPR0
00000000C0030028 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPESWPR0
0000000000066006 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPESWPR1
00000000C0030030 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPESWPR1
0000000000066010 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIXCR
00000000C0030080 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIXCR
0000000000066011 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIRAMRA
00000000C0030088 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIRAMRA
0000000000066012 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIRAMGA
00000000C0030090 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIRAMGA
0000000000066013 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIRAMDBG
00000000C0030098 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIRAMDBG
0000000000066014 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIRAMEDR
00000000C00300A0 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIRAMEDR
0000000000066015 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIDBGPRO
00000000C00300A8 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIDBGPRO
0000000000066016 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXISIB
00000000C00300B0 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXISIB
0000000000066017 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIMEM
00000000C00300B8 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIMEM
0000000000066018 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXISGB
00000000C00300C0 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXISGB
0000000000066019 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIICAC
00000000C00300C8 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIICAC
000000000006601A TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIDCAC
00000000C00300D0 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIDCAC
000000000006601F TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIDBGINF
00000000C00300F8 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIDBGINF
0000000000066020 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEOXIXCR
00000000C0030100 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEOXIXCR
0000000000066021 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIXSR
00000000C0030108 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIXSR
0000000000066022 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXISPRG0
00000000C0030110 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXISPRG0
0000000000066023 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIEDR
00000000C0030118 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIEDR
0000000000066024 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIIR
00000000C0030120 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIIR
0000000000066025 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIIAR
00000000C0030128 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIIAR
0000000000066026 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXISIBU
00000000C0030130 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXISIBU
0000000000066027 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXISIBL
00000000C0030138 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXISIBL
0000000000066028 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIMEMU
00000000C0030140 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIMEMU
0000000000066029 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIMEML
00000000C0030148 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIMEML
000000000006602A TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXISGBU
00000000C0030150 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXISGBU
000000000006602B TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXISGBL
00000000C0030158 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXISGBL
000000000006602C TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIICACU
00000000C0030160 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIICACU
000000000006602D TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIICACL
00000000C0030168 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIICACL
000000000006602E TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIDCACU
00000000C0030170 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIDCACU
000000000006602F TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIDCACL
00000000C0030178 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIDCACL
0000000000066030 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXISRR0
00000000C0030180 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXISRR0
0000000000066031 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXILR
00000000C0030188 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXILR
0000000000066032 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXICTR
00000000C0030190 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXICTR
0000000000066040 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR0
00000000C0030200 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR0
0000000000066041 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR1
00000000C0030208 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR1
0000000000066042 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR2
00000000C0030210 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR2
0000000000066043 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR3
00000000C0030218 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR3
0000000000066044 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR4
00000000C0030220 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR4
0000000000066045 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR5
00000000C0030228 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR5
0000000000066046 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR6
00000000C0030230 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR6
0000000000066047 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR7
00000000C0030238 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR7
0000000000066048 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR8
00000000C0030240 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR8
0000000000066049 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR9
00000000C0030248 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR9
000000000006604A TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR10
00000000C0030250 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR10
000000000006604B TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR13
00000000C0030258 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR13
000000000006604C TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR28
00000000C0030260 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR28
000000000006604D TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR29
00000000C0030268 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR29
000000000006604E TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR30
00000000C0030270 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR30
000000000006604F TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR31
00000000C0030278 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIGPR31
0000000000066080 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIVDR0
00000000C0030400 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIVDR0
0000000000066081 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIVDR2
00000000C0030408 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIVDR2
0000000000066082 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIVDR4
00000000C0030410 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIVDR4
0000000000066083 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIVDR6
00000000C0030418 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIVDR6
0000000000066084 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIVDR8
00000000C0030420 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIVDR8
0000000000066085 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIVDRX
00000000C0030428 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIVDRX
0000000000066086 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIVDR28
00000000C0030430 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIVDR28
0000000000066087 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIVDR30
00000000C0030438 TP.TPCHIP.OCC.OCI.GPE3.OCB_OCI_GPEXIVDR30
0000000000068000 TP.TPBR.PBA.PBAO.PBAMODE
00000000C0040000 TP.TPBR.PBA.PBAO.PBAMODE
0000000000068001 TP.TPBR.PBA.PBAO.PBASLVRST
00000000C0040008 TP.TPBR.PBA.PBAO.PBASLVRST
0000000000068004 TP.TPBR.PBA.PBAO.PBASLVCTL0
00000000C0040020 TP.TPBR.PBA.PBAO.PBASLVCTL0
0000000000068005 TP.TPBR.PBA.PBAO.PBASLVCTL1
00000000C0040028 TP.TPBR.PBA.PBAO.PBASLVCTL1
0000000000068006 TP.TPBR.PBA.PBAO.PBASLVCTL2
00000000C0040030 TP.TPBR.PBA.PBAO.PBASLVCTL2
0000000000068007 TP.TPBR.PBA.PBAO.PBASLVCTL3
00000000C0040038 TP.TPBR.PBA.PBAO.PBASLVCTL3
0000000000068010 TP.TPBR.PBA.PBAO.BCDE_CTL
00000000C0040080 TP.TPBR.PBA.PBAO.BCDE_CTL
0000000000068011 TP.TPBR.PBA.PBAO.BCDE_SET
00000000C0040088 TP.TPBR.PBA.PBAO.BCDE_SET
0000000000068012 TP.TPBR.PBA.PBAO.BCDE_STAT
00000000C0040090 TP.TPBR.PBA.PBAO.BCDE_STAT
0000000000068013 TP.TPBR.PBA.PBAO.BCDE_PBADR
00000000C0040098 TP.TPBR.PBA.PBAO.BCDE_PBADR
0000000000068014 TP.TPBR.PBA.PBAO.BCDE_OCIBAR
00000000C00400A0 TP.TPBR.PBA.PBAO.BCDE_OCIBAR
0000000000068015 TP.TPBR.PBA.PBAO.BCUE_CTL
00000000C00400A8 TP.TPBR.PBA.PBAO.BCUE_CTL
0000000000068016 TP.TPBR.PBA.PBAO.BCUE_SET
00000000C00400B0 TP.TPBR.PBA.PBAO.BCUE_SET
0000000000068017 TP.TPBR.PBA.PBAO.BCUE_STAT
00000000C00400B8 TP.TPBR.PBA.PBAO.BCUE_STAT
0000000000068018 TP.TPBR.PBA.PBAO.BCUE_PBADR
00000000C00400C0 TP.TPBR.PBA.PBAO.BCUE_PBADR
0000000000068019 TP.TPBR.PBA.PBAO.BCUE_OCIBAR
00000000C00400C8 TP.TPBR.PBA.PBAO.BCUE_OCIBAR
000000000006801A TP.TPBR.PBA.PBAO.PBAOCR0
00000000C00400D0 TP.TPBR.PBA.PBAO.PBAOCR0
000000000006801B TP.TPBR.PBA.PBAO.PBAOCR1
00000000C00400D8 TP.TPBR.PBA.PBAO.PBAOCR1
000000000006801C TP.TPBR.PBA.PBAO.PBAOCR2
00000000C00400E0 TP.TPBR.PBA.PBAO.PBAOCR2
000000000006801D TP.TPBR.PBA.PBAO.PBAOCR3
00000000C00400E8 TP.TPBR.PBA.PBAO.PBAOCR3
0000000000068020 TP.TPBR.PBA.PBAO.PBAXSNDTX
00000000C0040100 TP.TPBR.PBA.PBAO.PBAXSNDTX
0000000000068021 TP.TPBR.PBA.PBAO.PBAXCFG
00000000C0040108 TP.TPBR.PBA.PBAO.PBAXCFG
0000000000068022 TP.TPBR.PBA.PBAO.PBAXSNDSTAT
00000000C0040110 TP.TPBR.PBA.PBAO.PBAXSNDSTAT
0000000000068024 TP.TPBR.PBA.PBAO.PBAXRCVSTAT
00000000C0040120 TP.TPBR.PBA.PBAO.PBAXRCVSTAT
0000000000068026 TP.TPBR.PBA.PBAO.PBAXSHBR0
00000000C0040130 TP.TPBR.PBA.PBAO.PBAXSHBR0
0000000000068027 TP.TPBR.PBA.PBAO.PBAXSHCS0
00000000C0040138 TP.TPBR.PBA.PBAO.PBAXSHCS0
0000000000068028 TP.TPBR.PBA.PBAO.PBAXSHINC0
00000000C0040140 TP.TPBR.PBA.PBAO.PBAXSHINC0
000000000006802A TP.TPBR.PBA.PBAO.PBAXSHBR1
00000000C0040150 TP.TPBR.PBA.PBAO.PBAXSHBR1
000000000006802B TP.TPBR.PBA.PBAO.PBAXSHCS1
00000000C0040158 TP.TPBR.PBA.PBAO.PBAXSHCS1
000000000006802C TP.TPBR.PBA.PBAO.PBAXSHINC1
00000000C0040160 TP.TPBR.PBA.PBAO.PBAXSHINC1
0000000000068030 TP.TPBR.PBA.PBAO.PBAXISNDTX
00000000C0040180 TP.TPBR.PBA.PBAO.PBAXISNDTX
0000000000068031 TP.TPBR.PBA.PBAO.PBAXICFG
00000000C0040188 TP.TPBR.PBA.PBAO.PBAXICFG
0000000000068032 TP.TPBR.PBA.PBAO.PBAXISNDSTAT
00000000C0040190 TP.TPBR.PBA.PBAO.PBAXISNDSTAT
0000000000068034 TP.TPBR.PBA.PBAO.PBAXIRCVSTAT
00000000C00401A0 TP.TPBR.PBA.PBAO.PBAXIRCVSTAT
0000000000068036 TP.TPBR.PBA.PBAO.PBAXISHBR0
00000000C00401B0 TP.TPBR.PBA.PBAO.PBAXISHBR0
0000000000068037 TP.TPBR.PBA.PBAO.PBAXISHCS0
00000000C00401B8 TP.TPBR.PBA.PBAO.PBAXISHCS0
0000000000068038 TP.TPBR.PBA.PBAO.PBAXISHINC0
00000000C00401C0 TP.TPBR.PBA.PBAO.PBAXISHINC0
000000000006803A TP.TPBR.PBA.PBAO.PBAXISHBR1
00000000C00401D0 TP.TPBR.PBA.PBAO.PBAXISHBR1
000000000006803B TP.TPBR.PBA.PBAO.PBAXISHCS1
00000000C00401D8 TP.TPBR.PBA.PBAO.PBAXISHCS1
000000000006803C TP.TPBR.PBA.PBAO.PBAXISHINC1
00000000C00401E0 TP.TPBR.PBA.PBAO.PBAXISHINC1
000000000006A001 TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_SRMR
00000000C0050008 TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_SRMR
000000000006A002 TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_SRMAP
00000000C0050010 TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_SRMAP
000000000006A003 TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_SREAR
00000000C0050018 TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_SREAR
000000000006A004 TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_SRBV0
00000000C0050020 TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_SRBV0
000000000006A005 TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_SRBV1
00000000C0050028 TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_SRBV1
000000000006A006 TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_SRBV2
00000000C0050030 TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_SRBV2
000000000006A007 TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_SRBV3
00000000C0050038 TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_SRBV3
000000000006A008 TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_SRCHSW
00000000C0050040 TP.TPCHIP.OCC.SRAM.SRAM_CTL.SRAM_SRCHSW
000000000006C000 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OISR0
000000000006C001 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OISR0
000000000006C002 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OISR0
00000000C0060000 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OISR0
00000000C0060008 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OISR0
00000000C0060010 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OISR0
000000000006C004 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIMR0
000000000006C005 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIMR0
000000000006C006 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIMR0
00000000C0060020 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIMR0
00000000C0060028 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIMR0
00000000C0060030 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIMR0
000000000006C008 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OITR0
000000000006C009 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OITR0
000000000006C00A TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OITR0
00000000C0060040 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OITR0
00000000C0060048 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OITR0
00000000C0060050 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OITR0
000000000006C00C TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIEPR0
000000000006C00D TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIEPR0
000000000006C00E TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIEPR0
00000000C0060060 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIEPR0
00000000C0060068 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIEPR0
00000000C0060070 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIEPR0
000000000006C010 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OINKR0
00000000C0060080 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OINKR0
000000000006C020 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OISR1
000000000006C021 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OISR1
000000000006C022 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OISR1
00000000C0060100 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OISR1
00000000C0060108 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OISR1
00000000C0060110 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OISR1
000000000006C024 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIMR1
000000000006C025 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIMR1
000000000006C026 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIMR1
00000000C0060120 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIMR1
00000000C0060128 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIMR1
00000000C0060130 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIMR1
000000000006C028 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OITR1
000000000006C029 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OITR1
000000000006C02A TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OITR1
00000000C0060140 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OITR1
00000000C0060148 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OITR1
00000000C0060150 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OITR1
000000000006C02C TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIEPR1
000000000006C02D TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIEPR1
000000000006C02E TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIEPR1
00000000C0060160 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIEPR1
00000000C0060168 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIEPR1
00000000C0060170 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIEPR1
000000000006C030 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OINKR1
00000000C0060180 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OINKR1
000000000006C040 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR0A
000000000006C041 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR0A
000000000006C042 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR0A
00000000C0060200 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR0A
00000000C0060208 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR0A
00000000C0060210 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR0A
000000000006C044 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR0B
000000000006C045 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR0B
000000000006C046 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR0B
00000000C0060220 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR0B
00000000C0060228 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR0B
00000000C0060230 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR0B
000000000006C048 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR0C
000000000006C049 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR0C
000000000006C04A TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR0C
00000000C0060240 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR0C
00000000C0060248 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR0C
00000000C0060250 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR0C
000000000006C050 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR1A
000000000006C051 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR1A
000000000006C052 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR1A
00000000C0060280 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR1A
00000000C0060288 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR1A
00000000C0060290 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR1A
000000000006C054 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR1B
000000000006C055 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR1B
000000000006C056 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR1B
00000000C00602A0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR1B
00000000C00602A8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR1B
00000000C00602B0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR1B
000000000006C058 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR1C
000000000006C059 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR1C
000000000006C05A TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR1C
00000000C00602C0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR1C
00000000C00602C8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR1C
00000000C00602D0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OIRR1C
000000000006C060 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ONISR0
00000000C0060300 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ONISR0
000000000006C061 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCISR0
00000000C0060308 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCISR0
000000000006C062 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OUISR0
00000000C0060310 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OUISR0
000000000006C063 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ODISR0
00000000C0060318 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ODISR0
000000000006C064 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_G0ISR0
00000000C0060320 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_G0ISR0
000000000006C065 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_G1ISR0
00000000C0060328 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_G1ISR0
000000000006C066 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_G2ISR0
00000000C0060330 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_G2ISR0
000000000006C067 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_G3ISR0
00000000C0060338 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_G3ISR0
000000000006C070 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ONISR1
00000000C0060380 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ONISR1
000000000006C071 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCISR1
00000000C0060388 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCISR1
000000000006C072 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OUISR1
00000000C0060390 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OUISR1
000000000006C073 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ODISR1
00000000C0060398 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ODISR1
000000000006C074 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_G0ISR1
00000000C00603A0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_G0ISR1
000000000006C075 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_G1ISR1
00000000C00603A8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_G1ISR1
000000000006C076 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_G2ISR1
00000000C00603B0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_G2ISR1
000000000006C077 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_G3ISR1
00000000C00603B8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_G3ISR1
000000000006C080 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCMISC
000000000006C081 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCMISC
000000000006C082 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCMISC
00000000C0060400 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCMISC
00000000C0060408 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCMISC
00000000C0060410 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCMISC
000000000006C083 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OHTMCR
00000000C0060418 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OHTMCR
000000000006C084 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OEHDR
00000000C0060420 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OEHDR
000000000006C085 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCICFG
00000000C0060428 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCICFG
000000000006C086 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSTAT
00000000C0060430 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSTAT
000000000006C08F TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCHBR
00000000C0060478 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCHBR
000000000006C090 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_CCSR
000000000006C091 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_CCSR
000000000006C092 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_CCSR
00000000C0060480 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_CCSR
00000000C0060488 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_CCSR
00000000C0060490 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_CCSR
000000000006C09F TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OTBR
00000000C00604F8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OTBR
000000000006C0A0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCS0
000000000006C0A1 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCS0
000000000006C0A2 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCS0
00000000C0060500 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCS0
00000000C0060508 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCS0
00000000C0060510 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCS0
000000000006C0A3 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCS1
000000000006C0A4 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCS1
000000000006C0A5 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCS1
00000000C0060518 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCS1
00000000C0060520 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCS1
00000000C0060528 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCS1
000000000006C0A6 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCS2
000000000006C0A7 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCS2
000000000006C0A8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCS2
00000000C0060530 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCS2
00000000C0060538 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCS2
00000000C0060540 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCS2
000000000006C0A9 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCS3
000000000006C0AA TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCS3
000000000006C0AB TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCS3
00000000C0060548 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCS3
00000000C0060550 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCS3
00000000C0060558 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCS3
000000000006C0AC TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG0
000000000006C0AD TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG0
000000000006C0AE TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG0
00000000C0060560 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG0
00000000C0060568 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG0
00000000C0060570 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG0
000000000006C0AF TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG1
000000000006C0B0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG1
000000000006C0B1 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG1
00000000C0060578 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG1
00000000C0060580 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG1
00000000C0060588 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG1
000000000006C0B2 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG2
000000000006C0B3 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG2
000000000006C0B4 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG2
00000000C0060590 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG2
00000000C0060598 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG2
00000000C00605A0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG2
000000000006C0B5 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG3
000000000006C0B6 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG3
000000000006C0B7 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG3
00000000C00605A8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG3
00000000C00605B0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG3
00000000C00605B8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG3
000000000006C0B8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG4
000000000006C0B9 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG4
000000000006C0BA TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG4
00000000C00605C0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG4
00000000C00605C8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG4
00000000C00605D0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG4
000000000006C0BB TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG5
000000000006C0BC TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG5
000000000006C0BD TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG5
00000000C00605D8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG5
00000000C00605E0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG5
00000000C00605E8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG5
000000000006C0BE TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG6
000000000006C0BF TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG6
000000000006C0C0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG6
00000000C00605F0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG6
00000000C00605F8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG6
00000000C0060600 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG6
000000000006C0C1 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG7
000000000006C0C2 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG7
000000000006C0C3 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG7
00000000C0060608 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG7
00000000C0060610 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG7
00000000C0060618 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCFLG7
000000000006C100 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OTR0
00000000C0060800 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OTR0
000000000006C101 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OTR1
00000000C0060808 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OTR1
000000000006C180 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_DERP0
00000000C0060C00 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_DERP0
000000000006C181 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_DORP0
00000000C0060C08 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_DORP0
000000000006C182 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_DERP1
00000000C0060C10 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_DERP1
000000000006C183 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_DORP1
00000000C0060C18 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_DORP1
000000000006C184 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_DERP2
00000000C0060C20 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_DERP2
000000000006C185 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_DORP2
00000000C0060C28 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_DORP2
000000000006C186 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_DERP3
00000000C0060C30 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_DERP3
000000000006C187 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_DORP3
00000000C0060C38 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_DORP3
000000000006C200 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLBR0
00000000C0061000 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLBR0
000000000006C201 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLCS0
00000000C0061008 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLCS0
000000000006C202 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLI0
00000000C0061010 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLI0
000000000006C203 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHBR0
00000000C0061018 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHBR0
000000000006C204 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHCS0
00000000C0061020 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHCS0
000000000006C205 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHI0
00000000C0061028 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHI0
000000000006C206 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSES0
00000000C0061030 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSES0
000000000006C208 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWCR0
00000000C0061040 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWCR0
000000000006C20A TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWSR0
00000000C0061050 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWSR0
000000000006C20C TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWSBR0
00000000C0061060 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWSBR0
000000000006C210 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLBR1
00000000C0061080 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLBR1
000000000006C211 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLCS1
00000000C0061088 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLCS1
000000000006C212 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLI1
00000000C0061090 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLI1
000000000006C213 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHBR1
00000000C0061098 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHBR1
000000000006C214 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHCS1
00000000C00610A0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHCS1
000000000006C215 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHI1
00000000C00610A8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHI1
000000000006C216 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSES1
00000000C00610B0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSES1
000000000006C218 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWCR1
00000000C00610C0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWCR1
000000000006C21A TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWSR1
00000000C00610D0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWSR1
000000000006C21C TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWSBR1
00000000C00610E0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWSBR1
000000000006C220 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLBR2
00000000C0061100 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLBR2
000000000006C221 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLCS2
00000000C0061108 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLCS2
000000000006C222 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLI2
00000000C0061110 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLI2
000000000006C223 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHBR2
00000000C0061118 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHBR2
000000000006C224 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHCS2
00000000C0061120 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHCS2
000000000006C225 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHI2
00000000C0061128 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHI2
000000000006C226 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSES2
00000000C0061130 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSES2
000000000006C228 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWCR2
00000000C0061140 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWCR2
000000000006C22A TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWSR2
00000000C0061150 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWSR2
000000000006C22C TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWSBR2
00000000C0061160 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWSBR2
000000000006C230 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLBR3
00000000C0061180 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLBR3
000000000006C231 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLCS3
00000000C0061188 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLCS3
000000000006C232 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLI3
00000000C0061190 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSLI3
000000000006C233 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHBR3
00000000C0061198 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHBR3
000000000006C234 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHCS3
00000000C00611A0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHCS3
000000000006C235 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHI3
00000000C00611A8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSHI3
000000000006C236 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSES3
00000000C00611B0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBSES3
000000000006C238 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWCR3
00000000C00611C0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWCR3
000000000006C23A TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWSR3
00000000C00611D0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWSR3
000000000006C23C TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWSBR3
00000000C00611E0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCBLWSBR3
000000000006C400 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q0
00000000C0062000 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q0
000000000006C401 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q1
00000000C0062008 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q1
000000000006C402 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q2
00000000C0062010 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q2
000000000006C403 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q3
00000000C0062018 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q3
000000000006C404 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q4
00000000C0062020 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q4
000000000006C405 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q5
00000000C0062028 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q5
000000000006C406 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q6
00000000C0062030 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q6
000000000006C407 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q7
00000000C0062038 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q7
000000000006C408 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q0
00000000C0062040 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q0
000000000006C409 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q1
00000000C0062048 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q1
000000000006C40A TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q2
00000000C0062050 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q2
000000000006C40B TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q3
00000000C0062058 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q3
000000000006C40C TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q4
00000000C0062060 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q4
000000000006C40D TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q5
00000000C0062068 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q5
000000000006C40E TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q6
00000000C0062070 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q6
000000000006C40F TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q7
00000000C0062078 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q7
000000000006C410 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q0
00000000C0062080 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q0
000000000006C411 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q1
00000000C0062088 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q1
000000000006C412 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q2
00000000C0062090 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q2
000000000006C413 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q3
00000000C0062098 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q3
000000000006C414 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q4
00000000C00620A0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q4
000000000006C415 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q5
00000000C00620A8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q5
000000000006C416 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q6
00000000C00620B0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q6
000000000006C417 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q7
00000000C00620B8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q7
000000000006C418 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q0
00000000C00620C0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q0
000000000006C419 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q1
00000000C00620C8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q1
000000000006C41A TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q2
00000000C00620D0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q2
000000000006C41B TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q3
00000000C00620D8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q3
000000000006C41C TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q4
00000000C00620E0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q4
000000000006C41D TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q5
00000000C00620E8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q5
000000000006C41E TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q6
00000000C00620F0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q6
000000000006C41F TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q7
00000000C00620F8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q7
000000000006C420 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q0
00000000C0062100 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q0
000000000006C421 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q1
00000000C0062108 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q1
000000000006C422 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q2
00000000C0062110 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q2
000000000006C423 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q3
00000000C0062118 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q3
000000000006C424 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q4
00000000C0062120 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q4
000000000006C425 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q5
00000000C0062128 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q5
000000000006C426 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q6
00000000C0062130 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q6
000000000006C427 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q7
00000000C0062138 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q7
000000000006C428 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q0
00000000C0062140 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q0
000000000006C429 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q1
00000000C0062148 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q1
000000000006C42A TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q2
00000000C0062150 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q2
000000000006C42B TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q3
00000000C0062158 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q3
000000000006C42C TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q4
00000000C0062160 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q4
000000000006C42D TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q5
00000000C0062168 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q5
000000000006C42E TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q6
00000000C0062170 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q6
000000000006C42F TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q7
00000000C0062178 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q7
000000000006C430 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q0
00000000C0062180 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q0
000000000006C431 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q1
00000000C0062188 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q1
000000000006C432 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q2
00000000C0062190 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q2
000000000006C433 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q3
00000000C0062198 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q3
000000000006C434 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q4
00000000C00621A0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q4
000000000006C435 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q5
00000000C00621A8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q5
000000000006C436 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q6
00000000C00621B0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q6
000000000006C437 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q7
00000000C00621B8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q7
000000000006C438 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q0
00000000C00621C0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q0
000000000006C439 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q1
00000000C00621C8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q1
000000000006C43A TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q2
00000000C00621D0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q2
000000000006C43B TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q3
00000000C00621D8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q3
000000000006C43C TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q4
00000000C00621E0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q4
000000000006C43D TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q5
00000000C00621E8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q5
000000000006C43E TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q6
00000000C00621F0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q6
000000000006C43F TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q7
00000000C00621F8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q7
000000000006C440 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C0
00000000C0062200 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C0
000000000006C441 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C1
00000000C0062208 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C1
000000000006C442 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C2
00000000C0062210 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C2
000000000006C443 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C3
00000000C0062218 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C3
000000000006C444 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C4
00000000C0062220 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C4
000000000006C445 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C5
00000000C0062228 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C5
000000000006C446 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C6
00000000C0062230 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C6
000000000006C447 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C7
00000000C0062238 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C7
000000000006C448 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C8
00000000C0062240 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C8
000000000006C449 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C9
00000000C0062248 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C9
000000000006C44A TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C10
00000000C0062250 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C10
000000000006C44B TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C11
00000000C0062258 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C11
000000000006C44C TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C12
00000000C0062260 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C12
000000000006C44D TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C13
00000000C0062268 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C13
000000000006C44E TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C14
00000000C0062270 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C14
000000000006C44F TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C15
00000000C0062278 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C15
000000000006C450 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C16
00000000C0062280 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C16
000000000006C451 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C17
00000000C0062288 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C17
000000000006C452 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C18
00000000C0062290 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C18
000000000006C453 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C19
00000000C0062298 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C19
000000000006C454 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C20
00000000C00622A0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C20
000000000006C455 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C21
00000000C00622A8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C21
000000000006C456 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C22
00000000C00622B0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C22
000000000006C457 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C23
00000000C00622B8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C23
000000000006C458 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C24
00000000C00622C0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C24
000000000006C459 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C25
00000000C00622C8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C25
000000000006C45A TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C26
00000000C00622D0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C26
000000000006C45B TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C27
00000000C00622D8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C27
000000000006C45C TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C28
00000000C00622E0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C28
000000000006C45D TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C29
00000000C00622E8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C29
000000000006C45E TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C30
00000000C00622F0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C30
000000000006C45F TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C31
00000000C00622F8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C31
000000000006C460 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C0
00000000C0062300 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C0
000000000006C461 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C1
00000000C0062308 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C1
000000000006C462 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C2
00000000C0062310 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C2
000000000006C463 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C3
00000000C0062318 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C3
000000000006C464 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C4
00000000C0062320 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C4
000000000006C465 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C5
00000000C0062328 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C5
000000000006C466 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C6
00000000C0062330 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C6
000000000006C467 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C7
00000000C0062338 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C7
000000000006C468 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C8
00000000C0062340 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C8
000000000006C469 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C9
00000000C0062348 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C9
000000000006C46A TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C10
00000000C0062350 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C10
000000000006C46B TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C11
00000000C0062358 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C11
000000000006C46C TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C12
00000000C0062360 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C12
000000000006C46D TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C13
00000000C0062368 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C13
000000000006C46E TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C14
00000000C0062370 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C14
000000000006C46F TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C15
00000000C0062378 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C15
000000000006C470 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C16
00000000C0062380 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C16
000000000006C471 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C17
00000000C0062388 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C17
000000000006C472 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C18
00000000C0062390 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C18
000000000006C473 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C19
00000000C0062398 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C19
000000000006C474 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C20
00000000C00623A0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C20
000000000006C475 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C21
00000000C00623A8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C21
000000000006C476 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C22
00000000C00623B0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C22
000000000006C477 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C23
00000000C00623B8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C23
000000000006C478 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C24
00000000C00623C0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C24
000000000006C479 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C25
00000000C00623C8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C25
000000000006C47A TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C26
00000000C00623D0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C26
000000000006C47B TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C27
00000000C00623D8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C27
000000000006C47C TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C28
00000000C00623E0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C28
000000000006C47D TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C29
00000000C00623E8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C29
000000000006C47E TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C30
00000000C00623F0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C30
000000000006C47F TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C31
00000000C00623F8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C31
000000000006C480 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITASV0
00000000C0062400 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITASV0
000000000006C481 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITASV1
00000000C0062408 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITASV1
000000000006C482 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITASV2
00000000C0062410 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITASV2
000000000006C483 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITASV3
00000000C0062418 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITASV3
000000000006C484 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBSV0
00000000C0062420 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBSV0
000000000006C485 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBSV1
00000000C0062428 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBSV1
000000000006C486 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBSV2
00000000C0062430 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBSV2
000000000006C487 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBSV3
00000000C0062438 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBSV3
000000000006C488 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITCSV
00000000C0062440 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITCSV
000000000006C48C TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITDSV
00000000C0062460 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITDSV
000000000006C490 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITESV
00000000C0062480 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITESV
000000000006C494 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITFSV
00000000C00624A0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITFSV
000000000006C500 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q0RR
00000000C0062800 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q0RR
000000000006C501 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q1RR
00000000C0062808 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q1RR
000000000006C502 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q2RR
00000000C0062810 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q2RR
000000000006C503 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q3RR
00000000C0062818 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q3RR
000000000006C504 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q4RR
00000000C0062820 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q4RR
000000000006C505 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q5RR
00000000C0062828 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q5RR
000000000006C506 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q6RR
00000000C0062830 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q6RR
000000000006C507 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q7RR
00000000C0062838 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0Q7RR
000000000006C508 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q0RR
00000000C0062840 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q0RR
000000000006C509 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q1RR
00000000C0062848 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q1RR
000000000006C50A TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q2RR
00000000C0062850 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q2RR
000000000006C50B TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q3RR
00000000C0062858 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q3RR
000000000006C50C TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q4RR
00000000C0062860 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q4RR
000000000006C50D TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q5RR
00000000C0062868 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q5RR
000000000006C50E TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q6RR
00000000C0062870 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q6RR
000000000006C50F TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q7RR
00000000C0062878 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1Q7RR
000000000006C510 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q0RR
00000000C0062880 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q0RR
000000000006C511 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q1RR
00000000C0062888 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q1RR
000000000006C512 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q2RR
00000000C0062890 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q2RR
000000000006C513 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q3RR
00000000C0062898 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q3RR
000000000006C514 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q4RR
00000000C00628A0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q4RR
000000000006C515 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q5RR
00000000C00628A8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q5RR
000000000006C516 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q6RR
00000000C00628B0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q6RR
000000000006C517 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q7RR
00000000C00628B8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2Q7RR
000000000006C518 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q0RR
00000000C00628C0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q0RR
000000000006C519 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q1RR
00000000C00628C8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q1RR
000000000006C51A TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q2RR
00000000C00628D0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q2RR
000000000006C51B TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q3RR
00000000C00628D8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q3RR
000000000006C51C TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q4RR
00000000C00628E0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q4RR
000000000006C51D TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q5RR
00000000C00628E8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q5RR
000000000006C51E TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q6RR
00000000C00628F0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q6RR
000000000006C51F TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q7RR
00000000C00628F8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3Q7RR
000000000006C520 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q0RR
00000000C0062900 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q0RR
000000000006C521 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q1RR
00000000C0062908 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q1RR
000000000006C522 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q2RR
00000000C0062910 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q2RR
000000000006C523 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q3RR
00000000C0062918 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q3RR
000000000006C524 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q4RR
00000000C0062920 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q4RR
000000000006C525 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q5RR
00000000C0062928 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q5RR
000000000006C526 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q6RR
00000000C0062930 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q6RR
000000000006C527 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q7RR
00000000C0062938 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4Q7RR
000000000006C528 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q0RR
00000000C0062940 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q0RR
000000000006C529 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q1RR
00000000C0062948 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q1RR
000000000006C52A TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q2RR
00000000C0062950 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q2RR
000000000006C52B TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q3RR
00000000C0062958 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q3RR
000000000006C52C TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q4RR
00000000C0062960 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q4RR
000000000006C52D TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q5RR
00000000C0062968 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q5RR
000000000006C52E TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q6RR
00000000C0062970 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q6RR
000000000006C52F TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q7RR
00000000C0062978 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5Q7RR
000000000006C530 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q0RR
00000000C0062980 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q0RR
000000000006C531 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q1RR
00000000C0062988 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q1RR
000000000006C532 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q2RR
00000000C0062990 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q2RR
000000000006C533 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q3RR
00000000C0062998 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q3RR
000000000006C534 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q4RR
00000000C00629A0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q4RR
000000000006C535 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q5RR
00000000C00629A8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q5RR
000000000006C536 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q6RR
00000000C00629B0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q6RR
000000000006C537 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q7RR
00000000C00629B8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6Q7RR
000000000006C538 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q0RR
00000000C00629C0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q0RR
000000000006C539 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q1RR
00000000C00629C8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q1RR
000000000006C53A TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q2RR
00000000C00629D0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q2RR
000000000006C53B TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q3RR
00000000C00629D8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q3RR
000000000006C53C TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q4RR
00000000C00629E0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q4RR
000000000006C53D TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q5RR
00000000C00629E8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q5RR
000000000006C53E TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q6RR
00000000C00629F0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q6RR
000000000006C53F TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q7RR
00000000C00629F8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7Q7RR
000000000006C540 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C0RR
00000000C0062A00 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C0RR
000000000006C541 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C1RR
00000000C0062A08 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C1RR
000000000006C542 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C2RR
00000000C0062A10 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C2RR
000000000006C543 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C3RR
00000000C0062A18 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C3RR
000000000006C544 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C4RR
00000000C0062A20 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C4RR
000000000006C545 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C5RR
00000000C0062A28 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C5RR
000000000006C546 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C6RR
00000000C0062A30 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C6RR
000000000006C547 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C7RR
00000000C0062A38 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C7RR
000000000006C548 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C8RR
00000000C0062A40 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C8RR
000000000006C549 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C9RR
00000000C0062A48 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C9RR
000000000006C54A TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C10RR
00000000C0062A50 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C10RR
000000000006C54B TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C11RR
00000000C0062A58 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C11RR
000000000006C54C TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C12RR
00000000C0062A60 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C12RR
000000000006C54D TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C13RR
00000000C0062A68 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C13RR
000000000006C54E TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C14RR
00000000C0062A70 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C14RR
000000000006C54F TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C15RR
00000000C0062A78 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C15RR
000000000006C550 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C16RR
00000000C0062A80 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C16RR
000000000006C551 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C17RR
00000000C0062A88 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C17RR
000000000006C552 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C18RR
00000000C0062A90 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C18RR
000000000006C553 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C19RR
00000000C0062A98 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C19RR
000000000006C554 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C20RR
00000000C0062AA0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C20RR
000000000006C555 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C21RR
00000000C0062AA8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C21RR
000000000006C556 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C22RR
00000000C0062AB0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C22RR
000000000006C557 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C23RR
00000000C0062AB8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C23RR
000000000006C558 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C24RR
00000000C0062AC0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C24RR
000000000006C559 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C25RR
00000000C0062AC8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C25RR
000000000006C55A TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C26RR
00000000C0062AD0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C26RR
000000000006C55B TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C27RR
00000000C0062AD8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C27RR
000000000006C55C TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C28RR
00000000C0062AE0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C28RR
000000000006C55D TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C29RR
00000000C0062AE8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C29RR
000000000006C55E TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C30RR
00000000C0062AF0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C30RR
000000000006C55F TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C31RR
00000000C0062AF8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8C31RR
000000000006C560 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C0RR
00000000C0062B00 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C0RR
000000000006C561 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C1RR
00000000C0062B08 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C1RR
000000000006C562 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C2RR
00000000C0062B10 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C2RR
000000000006C563 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C3RR
00000000C0062B18 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C3RR
000000000006C564 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C4RR
00000000C0062B20 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C4RR
000000000006C565 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C5RR
00000000C0062B28 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C5RR
000000000006C566 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C6RR
00000000C0062B30 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C6RR
000000000006C567 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C7RR
00000000C0062B38 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C7RR
000000000006C568 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C8RR
00000000C0062B40 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C8RR
000000000006C569 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C9RR
00000000C0062B48 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C9RR
000000000006C56A TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C10RR
00000000C0062B50 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C10RR
000000000006C56B TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C11RR
00000000C0062B58 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C11RR
000000000006C56C TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C12RR
00000000C0062B60 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C12RR
000000000006C56D TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C13RR
00000000C0062B68 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C13RR
000000000006C56E TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C14RR
00000000C0062B70 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C14RR
000000000006C56F TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C15RR
00000000C0062B78 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C15RR
000000000006C570 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C16RR
00000000C0062B80 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C16RR
000000000006C571 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C17RR
00000000C0062B88 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C17RR
000000000006C572 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C18RR
00000000C0062B90 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C18RR
000000000006C573 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C19RR
00000000C0062B98 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C19RR
000000000006C574 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C20RR
00000000C0062BA0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C20RR
000000000006C575 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C21RR
00000000C0062BA8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C21RR
000000000006C576 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C22RR
00000000C0062BB0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C22RR
000000000006C577 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C23RR
00000000C0062BB8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C23RR
000000000006C578 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C24RR
00000000C0062BC0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C24RR
000000000006C579 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C25RR
00000000C0062BC8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C25RR
000000000006C57A TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C26RR
00000000C0062BD0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C26RR
000000000006C57B TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C27RR
00000000C0062BD8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C27RR
000000000006C57C TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C28RR
00000000C0062BE0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C28RR
000000000006C57D TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C29RR
00000000C0062BE8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C29RR
000000000006C57E TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C30RR
00000000C0062BF0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C30RR
000000000006C57F TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C31RR
00000000C0062BF8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9C31RR
000000000006C580 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITASV0RR
00000000C0062C00 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITASV0RR
000000000006C581 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITASV1RR
00000000C0062C08 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITASV1RR
000000000006C582 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITASV2RR
00000000C0062C10 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITASV2RR
000000000006C583 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITASV3RR
00000000C0062C18 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITASV3RR
000000000006C584 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBSV0RR
00000000C0062C20 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBSV0RR
000000000006C585 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBSV1RR
00000000C0062C28 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBSV1RR
000000000006C586 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBSV2RR
00000000C0062C30 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBSV2RR
000000000006C587 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBSV3RR
00000000C0062C38 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBSV3RR
000000000006C588 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITCSVRR
00000000C0062C40 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITCSVRR
000000000006C58C TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITDSVRR
00000000C0062C60 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITDSVRR
000000000006C590 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITESVRR
00000000C0062C80 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITESVRR
000000000006C594 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITFSVRR
00000000C0062CA0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITFSVRR
000000000006C5C0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITIR
00000000C0062E00 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITIR
000000000006C600 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0PRA
000000000006C601 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0PRA
00000000C0063000 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0PRA
00000000C0063008 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT0PRA
000000000006C608 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1PRA
000000000006C609 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1PRA
00000000C0063040 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1PRA
00000000C0063048 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1PRA
000000000006C610 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2PRA
000000000006C611 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2PRA
00000000C0063080 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2PRA
00000000C0063088 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT2PRA
000000000006C618 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3PRA
000000000006C619 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3PRA
00000000C00630C0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3PRA
00000000C00630C8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT3PRA
000000000006C620 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4PRA
000000000006C621 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4PRA
00000000C0063100 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4PRA
00000000C0063108 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT4PRA
000000000006C628 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5PRA
000000000006C629 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5PRA
00000000C0063140 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5PRA
00000000C0063148 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT5PRA
000000000006C630 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6PRA
000000000006C631 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6PRA
00000000C0063180 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6PRA
00000000C0063188 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT6PRA
000000000006C638 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7PRA
000000000006C639 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7PRA
00000000C00631C0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7PRA
00000000C00631C8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT7PRA
000000000006C640 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8PRB
000000000006C641 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8PRB
00000000C0063200 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8PRB
00000000C0063208 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT8PRB
000000000006C660 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9PRB
000000000006C661 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9PRB
00000000C0063300 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9PRB
00000000C0063308 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT9PRB
000000000006C680 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITAPRC
000000000006C681 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITAPRC
00000000C0063400 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITAPRC
00000000C0063408 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITAPRC
000000000006C684 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBPRC
000000000006C685 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBPRC
00000000C0063420 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBPRC
00000000C0063428 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITBPRC
000000000006C688 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITCPRC
000000000006C689 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITCPRC
00000000C0063440 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITCPRC
00000000C0063448 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITCPRC
000000000006C68C TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITDPRC
000000000006C68D TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITDPRC
00000000C0063460 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITDPRC
00000000C0063468 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITDPRC
000000000006C690 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITEPRD
000000000006C691 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITEPRD
00000000C0063480 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITEPRD
00000000C0063488 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITEPRD
000000000006C694 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITFPRD
000000000006C695 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITFPRD
00000000C00634A0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITFPRD
00000000C00634A8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPITFPRD
000000000006C700 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRLF0
00000000C0063800 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRLF0
000000000006C701 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRLS0
00000000C0063808 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRLS0
000000000006C702 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRL10
00000000C0063810 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRL10
000000000006C703 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRL20
00000000C0063818 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRL20
000000000006C706 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SST0A
00000000C0063830 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SST0A
000000000006C707 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCMD0A
00000000C0063838 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCMD0A
000000000006C708 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SWD0A
00000000C0063840 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SWD0A
000000000006C709 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SRD0A
00000000C0063848 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SRD0A
000000000006C716 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SST0B
00000000C00638B0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SST0B
000000000006C717 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCMD0B
00000000C00638B8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCMD0B
000000000006C718 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SWD0B
00000000C00638C0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SWD0B
000000000006C719 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SRD0B
00000000C00638C8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SRD0B
000000000006C720 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRLF1
00000000C0063900 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRLF1
000000000006C721 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRLS1
00000000C0063908 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRLS1
000000000006C722 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRL11
00000000C0063910 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRL11
000000000006C723 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRL21
00000000C0063918 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRL21
000000000006C726 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SST1A
00000000C0063930 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SST1A
000000000006C727 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCMD1A
00000000C0063938 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCMD1A
000000000006C728 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SWD1A
00000000C0063940 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SWD1A
000000000006C729 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SRD1A
00000000C0063948 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SRD1A
000000000006C736 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SST1B
00000000C00639B0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SST1B
000000000006C737 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCMD1B
00000000C00639B8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCMD1B
000000000006C738 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SWD1B
00000000C00639C0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SWD1B
000000000006C739 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SRD1B
00000000C00639C8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SRD1B
000000000006C740 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRLF2
00000000C0063A00 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRLF2
000000000006C741 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRLS2
00000000C0063A08 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRLS2
000000000006C742 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRL12
00000000C0063A10 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRL12
000000000006C743 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRL22
00000000C0063A18 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCTRL22
000000000006C746 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SST2A
00000000C0063A30 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SST2A
000000000006C747 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCMD2A
00000000C0063A38 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCMD2A
000000000006C748 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SWD2A
00000000C0063A40 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SWD2A
000000000006C749 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SRD2A
00000000C0063A48 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SRD2A
000000000006C756 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SST2B
00000000C0063AB0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SST2B
000000000006C757 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCMD2B
00000000C0063AB8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SCMD2B
000000000006C758 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SWD2B
00000000C0063AC0 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SWD2B
000000000006C759 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SRD2B
00000000C0063AC8 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_O2SRD2B
000000000006C780 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_WOFICCTRL
00000000C0063C00 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_WOFICCTRL
000000000006C781 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_WOFICPING
00000000C0063C08 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_WOFICPING
000000000006C782 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_WOFICSTAT
00000000C0063C10 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_WOFICSTAT
000000000006C783 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_WOFICRD
00000000C0063C18 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_WOFICRD
000000000006C784 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_WOFICWD
00000000C0063C20 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_WOFICWD
000000000006C785 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_WOFICDCM1
00000000C0063C28 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_WOFICDCM1
000000000006C786 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_WOFICDCM2
00000000C0063C30 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_WOFICDCM2
000000000006C787 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_WOFICECC
00000000C0063C38 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_WOFICECC
000000000006C800 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_CR0
00000000C0064000 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_CR0
000000000006C801 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_CR1
00000000C0064008 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_CR1
000000000006C802 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_CR2
00000000C0064010 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_CR2
000000000006C803 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_STAT
00000000C0064018 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_STAT
000000000006C804 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_CMD
00000000C0064020 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_CMD
000000000006C805 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_RESET
00000000C0064028 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_RESET
000000000006C810 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_WDATA
00000000C0064080 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_WDATA
000000000006C820 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_RDATA0
00000000C0064100 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_RDATA0
000000000006C821 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_RDATA1
00000000C0064108 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_RDATA1
000000000006C822 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_RDATA2
00000000C0064110 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_RDATA2
000000000006C823 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_RDATA3
00000000C0064118 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_RDATA3
000000000006C824 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_RDATA4
00000000C0064120 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_RDATA4
000000000006C825 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_RDATA5
00000000C0064128 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_RDATA5
000000000006C826 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_RDATA6
00000000C0064130 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_RDATA6
000000000006C827 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_RDATA7
00000000C0064138 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_ADC_RDATA7
000000000006C828 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_P2S_100NS
00000000C0064140 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_P2S_100NS
000000000006C840 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_P2S_CR0
00000000C0064200 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_P2S_CR0
000000000006C841 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_P2S_CR1
00000000C0064208 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_P2S_CR1
000000000006C842 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_P2S_CR2
00000000C0064210 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_P2S_CR2
000000000006C843 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_P2S_STAT
00000000C0064218 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_P2S_STAT
000000000006C844 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_P2S_CMD
00000000C0064220 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_P2S_CMD
000000000006C845 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_P2S_RESET
00000000C0064228 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_P2S_RESET
000000000006C850 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_P2S_WDATA
00000000C0064280 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_P2S_WDATA
000000000006C860 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_P2S_RDATA
00000000C0064300 TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_P2S_RDATA
000000000006D000 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCR
000000000006D001 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCR
000000000006D002 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCR
000000000006D003 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCDBG
000000000006D004 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OJCFG
000000000006D005 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OJCFG
000000000006D006 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OJCFG
000000000006D007 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OJFRST
000000000006D008 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OJIC
000000000006D009 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OJIC
000000000006D00A TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OJIC
000000000006D00B TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OJSTAT
000000000006D00C TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OJTDI
000000000006D00D TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OJTDO
000000000006D010 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBAR0
000000000006D011 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBCSR0
000000000006D012 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBCSR0
000000000006D013 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBCSR0
000000000006D014 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBESR0
000000000006D015 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBDR0
000000000006D030 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBAR1
000000000006D031 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBCSR1
000000000006D032 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBCSR1
000000000006D033 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBCSR1
000000000006D034 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBESR1
000000000006D035 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBDR1
000000000006D050 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBAR2
000000000006D051 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBCSR2
000000000006D052 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBCSR2
000000000006D053 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBCSR2
000000000006D054 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBESR2
000000000006D055 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBDR2
000000000006D070 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBAR3
000000000006D071 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBCSR3
000000000006D072 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBCSR3
000000000006D073 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBCSR3
000000000006D074 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBESR3
000000000006D075 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBDR3
000000000006D110 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OTDCR
000000000006D111 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OPPCINJ
000000000006D200 TP.TPCHIP.OCC.OCI.PLBTO.OCB_PIB_OSTOEAR
000000000006D201 TP.TPCHIP.OCC.OCI.PLBTO.OCB_PIB_OSTOESR
000000000006D202 TP.TPCHIP.OCC.OCI.ARB.OCB_PIB_OREV
000000000006D204 TP.TPCHIP.OCC.OCI.ARB.OCB_PIB_OESR
000000000006D206 TP.TPCHIP.OCC.OCI.ARB.OCB_PIB_OEAR
000000000006D207 TP.TPCHIP.OCC.OCI.ARB.OCB_PIB_OACR
000000000006D210 TP.TPCHIP.OCC.OCI.OCB.OCB_PIB_OCBEAR
0000000000070000 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0_ERROR_INJECT_
0000000000070001 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0_COUNTER
0000000000070002 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0_CONFIG1
0000000000070003 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0_CLOCK_CONFIG
0000000000070004 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0_MEMORY_MAPPING
0000000000070005 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0_TRANSMIT_DATA_REG
0000000000070006 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0_RECEIVE_DATA_REG
0000000000070007 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0_SEQUENCER_OP_REG
0000000000070008 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST0_STATUS_REG
0000000000070020 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1_ERROR_INJECT_
0000000000070021 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1_COUNTER
0000000000070022 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1_CONFIG1
0000000000070023 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1_CLOCK_CONFIG
0000000000070024 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1_MEMORY_MAPPING
0000000000070025 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1_TRANSMIT_DATA_REG
0000000000070026 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1_RECEIVE_DATA_REG
0000000000070027 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1_SEQUENCER_OP_REG
0000000000070028 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST1_STATUS_REG
0000000000070040 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2_ERROR_INJECT_
0000000000070041 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2_COUNTER
0000000000070042 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2_CONFIG1
0000000000070043 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2_CLOCK_CONFIG
0000000000070044 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2_MEMORY_MAPPING
0000000000070045 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2_TRANSMIT_DATA_REG
0000000000070046 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2_RECEIVE_DATA_REG
0000000000070047 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2_SEQUENCER_OP_REG
0000000000070048 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST2_STATUS_REG
0000000000070060 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3_ERROR_INJECT_
0000000000070061 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3_COUNTER
0000000000070062 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3_CONFIG1
0000000000070063 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3_CLOCK_CONFIG
0000000000070064 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3_MEMORY_MAPPING
0000000000070065 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3_TRANSMIT_DATA_REG
0000000000070066 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3_RECEIVE_DATA_REG
0000000000070067 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3_SEQUENCER_OP_REG
0000000000070068 TP.TPVSB.FSI.W.FSI_SPIMC.SPI_PIB.SPIMST3_STATUS_REG
000000000008FFF0 TP.TPCHIP.PIBMEM.PIBMEM.CTRL_MAC.PIBMEM_CONTROL_REGISTER
000000000008FFF1 TP.TPCHIP.PIBMEM.PIBMEM.CTRL_MAC.PIBMEM_ADDRESS_REGISTER
000000000008FFF5 TP.TPCHIP.PIBMEM.PIBMEM.CTRL_MAC.PIBMEM_STATUS_REG
000000000008FFF6 TP.TPCHIP.PIBMEM.PIBMEM.CTRL_MAC.PIBMEM_RESET_REGISTER
000000000008FFF7 TP.TPCHIP.PIBMEM.PIBMEM.CTRL_MAC.PIBMEM_ADDRESS_REGISTER_FA
000000000008FFF8 TP.TPCHIP.PIBMEM.PIBMEM.CTRL_MAC.FIR_MASK_REGISTER
000000000008FFFB TP.TPCHIP.PIBMEM.PIBMEM.CTRL_MAC.ECC_CAPTURE_REG
0000000000090000 TP.TPBR.AD.ALTD_ADDR_REG
0000000000090001 TP.TPBR.AD.ALTD_CMD_REG
0000000000090002 TP.TPBR.AD.ALTD_OPTION_REG
0000000000090003 TP.TPBR.AD.ALTD_STATUS_REG
0000000000090004 TP.TPBR.AD.ALTD_DATA_REG
000000000009000D TP.TPBR.AD.FORCE_ECC_REG
0000000000090010 TP.TPBR.AD.XSCOM_BASE_REG
0000000000090011 TP.TPBR.AD.XSCOM_MODE_REG
0000000000090012 TP.TPBR.AD.XSCOM_LOG_REG
0000000000090013 TP.TPBR.AD.XSCOM_ERR_REG
0000000000090018 TP.TPBR.AD.XSCOM_RCVED_STAT_REG
000000000009001C TP.TPBR.AD.ADS_XSCOM_CMD_REG
000000000009001E TP.TPBR.AD.XSCOM_DAT0_REG
000000000009001F TP.TPBR.AD.XSCOM_DAT1_REG
0000000000090020 TP.TPBR.AD.SND_STAT_REG
0000000000090021 TP.TPBR.AD.SND_MODE_REG
0000000000090022 TP.TPBR.AD.RCV_ERRLOG0_REG
0000000000090028 TP.TPBR.AD.TOD_DATA_SND_REG
0000000000090029 TP.TPBR.AD.TOD_DATA_RCV_REG
000000000009002A TP.TPBR.AD.TOD_CMD_REG
0000000000090030 TP.TPBR.AD.IO_DATA_REG
0000000000090031 TP.TPBR.AD.PIB_CMD_REG
0000000000090032 TP.TPBR.AD.PIB_DATA_REG
0000000000090033 TP.TPBR.AD.PIB_RESET_REG
0000000000090040 TP.TPBR.AD.LPC_BASE_REG
0000000000090041 TP.TPBR.AD.LPC_CMD_REG
0000000000090042 TP.TPBR.AD.LPC_DATA_REG
0000000000090043 TP.TPBR.AD.LPC_STATUS_REG
0000000000090050 TP.TPBR.AD.ADU_HANG_DIV_REG
0000000000090051 TP.TPBR.AD.TOPOID_XLAT_TBL0
0000000000090052 TP.TPBR.AD.TOPOID_XLAT_TBL1
0000000000090053 TP.TPBR.AD.TOPOID_XLAT_TBL2
0000000000090054 TP.TPBR.AD.TOPOID_XLAT_TBL3
00000000000A0000 TP.TPCHIP.PIB.I2CM.CONTROL_REGISTER_B
00000000000A0001 TP.TPCHIP.PIB.I2CM.DATA8TO15_REGISTER_B
00000000000A0001 TP.TPCHIP.PIB.I2CM.RESET_REGISTER_B
00000000000A0002 TP.TPCHIP.PIB.I2CM.STATUS_REGISTER_B
00000000000A0003 TP.TPCHIP.PIB.I2CM.DATA0TO7_REGISTER_B
00000000000A0004 TP.TPCHIP.PIB.I2CM.FIFO1_REGISTER_READ_B
00000000000A0005 TP.TPCHIP.PIB.I2CM.COMMAND_REGISTER_B
00000000000A0006 TP.TPCHIP.PIB.I2CM.MODE_REGISTER_B
00000000000A0007 TP.TPCHIP.PIB.I2CM.WATER_MARK_REGISTER_B
00000000000A0008 TP.TPCHIP.PIB.I2CM.INTERRUPT_MASK_REGISTER_B
00000000000A0009 TP.TPCHIP.PIB.I2CM.INTERRUPT_MASK_REGISTER_B
00000000000A000A TP.TPCHIP.PIB.I2CM.INTERRUPT_MASK_REGISTER_B
00000000000A0008 TP.TPCHIP.PIB.I2CM.INTERRUPT_MASK_REGISTER_READ_B
00000000000A0009 TP.TPCHIP.PIB.I2CM.INTERRUPT_COND_B
00000000000A000A TP.TPCHIP.PIB.I2CM.INTERRUPTS_B
00000000000A000B TP.TPCHIP.PIB.I2CM.IMM_RESET_I2C_B
00000000000A000B TP.TPCHIP.PIB.I2CM.STATUS_REGISTER_ENGINE_B
00000000000A000C TP.TPCHIP.PIB.I2CM.EXTENDED_STATUS_B
00000000000A000C TP.TPCHIP.PIB.I2CM.IMM_RESET_ERR_B
00000000000A000D TP.TPCHIP.PIB.I2CM.IMM_SET_S_SCL_B
00000000000A000D TP.TPCHIP.PIB.I2CM.RESIDUAL_FRONT_END_BACK_END_LENGTH_B
00000000000A000E TP.TPCHIP.PIB.I2CM.I2C_BUSY_REGISTER_B
00000000000A000F TP.TPCHIP.PIB.I2CM.IMM_RESET_S_SCL_B
00000000000A0010 TP.TPCHIP.PIB.I2CM.IMM_SET_S_SDA_B
00000000000A0011 TP.TPCHIP.PIB.I2CM.IMM_RESET_S_SDA_B
00000000000A0012 TP.TPCHIP.PIB.I2CM.FIFO4_REGISTER_READ_B
00000000000A03FE TP.TPCHIP.PIB.I2CM.PIBI2CM_PROTECT_MODE_REG_B
00000000000A03FF TP.TPCHIP.PIB.I2CM.PIBI2CM_ATOMIC_LOCK_REG_B
00000000000A1000 TP.TPCHIP.PIB.I2CM.CONTROL_REGISTER_C
00000000000A1001 TP.TPCHIP.PIB.I2CM.DATA8TO15_REGISTER_C
00000000000A1001 TP.TPCHIP.PIB.I2CM.RESET_REGISTER_C
00000000000A1002 TP.TPCHIP.PIB.I2CM.STATUS_REGISTER_C
00000000000A1003 TP.TPCHIP.PIB.I2CM.DATA0TO7_REGISTER_C
00000000000A1004 TP.TPCHIP.PIB.I2CM.FIFO1_REGISTER_READ_C
00000000000A1005 TP.TPCHIP.PIB.I2CM.COMMAND_REGISTER_C
00000000000A1006 TP.TPCHIP.PIB.I2CM.MODE_REGISTER_C
00000000000A1007 TP.TPCHIP.PIB.I2CM.WATER_MARK_REGISTER_C
00000000000A1008 TP.TPCHIP.PIB.I2CM.INTERRUPT_MASK_REGISTER_C
00000000000A1009 TP.TPCHIP.PIB.I2CM.INTERRUPT_MASK_REGISTER_C
00000000000A100A TP.TPCHIP.PIB.I2CM.INTERRUPT_MASK_REGISTER_C
00000000000A1008 TP.TPCHIP.PIB.I2CM.INTERRUPT_MASK_REGISTER_READ_C
00000000000A1009 TP.TPCHIP.PIB.I2CM.INTERRUPT_COND_C
00000000000A100A TP.TPCHIP.PIB.I2CM.INTERRUPTS_C
00000000000A100B TP.TPCHIP.PIB.I2CM.IMM_RESET_I2C_C
00000000000A100B TP.TPCHIP.PIB.I2CM.STATUS_REGISTER_ENGINE_C
00000000000A100C TP.TPCHIP.PIB.I2CM.EXTENDED_STATUS_C
00000000000A100C TP.TPCHIP.PIB.I2CM.IMM_RESET_ERR_C
00000000000A100D TP.TPCHIP.PIB.I2CM.IMM_SET_S_SCL_C
00000000000A100D TP.TPCHIP.PIB.I2CM.RESIDUAL_FRONT_END_BACK_END_LENGTH_C
00000000000A100E TP.TPCHIP.PIB.I2CM.I2C_BUSY_REGISTER_C
00000000000A100F TP.TPCHIP.PIB.I2CM.IMM_RESET_S_SCL_C
00000000000A1010 TP.TPCHIP.PIB.I2CM.IMM_SET_S_SDA_C
00000000000A1011 TP.TPCHIP.PIB.I2CM.IMM_RESET_S_SDA_C
00000000000A1012 TP.TPCHIP.PIB.I2CM.FIFO4_REGISTER_READ_C
00000000000A13FE TP.TPCHIP.PIB.I2CM.PIBI2CM_PROTECT_MODE_REG_C
00000000000A13FF TP.TPCHIP.PIB.I2CM.PIBI2CM_ATOMIC_LOCK_REG_C
00000000000A2000 TP.TPCHIP.PIB.I2CM.CONTROL_REGISTER_D
00000000000A2001 TP.TPCHIP.PIB.I2CM.DATA8TO15_REGISTER_D
00000000000A2001 TP.TPCHIP.PIB.I2CM.RESET_REGISTER_D
00000000000A2002 TP.TPCHIP.PIB.I2CM.STATUS_REGISTER_D
00000000000A2003 TP.TPCHIP.PIB.I2CM.DATA0TO7_REGISTER_D
00000000000A2004 TP.TPCHIP.PIB.I2CM.FIFO1_REGISTER_READ_D
00000000000A2005 TP.TPCHIP.PIB.I2CM.COMMAND_REGISTER_D
00000000000A2006 TP.TPCHIP.PIB.I2CM.MODE_REGISTER_D
00000000000A2007 TP.TPCHIP.PIB.I2CM.WATER_MARK_REGISTER_D
00000000000A2008 TP.TPCHIP.PIB.I2CM.INTERRUPT_MASK_REGISTER_D
00000000000A2009 TP.TPCHIP.PIB.I2CM.INTERRUPT_MASK_REGISTER_D
00000000000A200A TP.TPCHIP.PIB.I2CM.INTERRUPT_MASK_REGISTER_D
00000000000A2008 TP.TPCHIP.PIB.I2CM.INTERRUPT_MASK_REGISTER_READ_D
00000000000A2009 TP.TPCHIP.PIB.I2CM.INTERRUPT_COND_D
00000000000A200A TP.TPCHIP.PIB.I2CM.INTERRUPTS_D
00000000000A200B TP.TPCHIP.PIB.I2CM.IMM_RESET_I2C_D
00000000000A200B TP.TPCHIP.PIB.I2CM.STATUS_REGISTER_ENGINE_D
00000000000A200C TP.TPCHIP.PIB.I2CM.EXTENDED_STATUS_D
00000000000A200C TP.TPCHIP.PIB.I2CM.IMM_RESET_ERR_D
00000000000A200D TP.TPCHIP.PIB.I2CM.IMM_SET_S_SCL_D
00000000000A200D TP.TPCHIP.PIB.I2CM.RESIDUAL_FRONT_END_BACK_END_LENGTH_D
00000000000A200E TP.TPCHIP.PIB.I2CM.I2C_BUSY_REGISTER_D
00000000000A200F TP.TPCHIP.PIB.I2CM.IMM_RESET_S_SCL_D
00000000000A2010 TP.TPCHIP.PIB.I2CM.IMM_SET_S_SDA_D
00000000000A2011 TP.TPCHIP.PIB.I2CM.IMM_RESET_S_SDA_D
00000000000A2012 TP.TPCHIP.PIB.I2CM.FIFO4_REGISTER_READ_D
00000000000A23FE TP.TPCHIP.PIB.I2CM.PIBI2CM_PROTECT_MODE_REG_D
00000000000A23FF TP.TPCHIP.PIB.I2CM.PIBI2CM_ATOMIC_LOCK_REG_D
00000000000A3000 TP.TPCHIP.PIB.I2CM.CONTROL_REGISTER_E
00000000000A3001 TP.TPCHIP.PIB.I2CM.DATA8TO15_REGISTER_E
00000000000A3001 TP.TPCHIP.PIB.I2CM.RESET_REGISTER_E
00000000000A3002 TP.TPCHIP.PIB.I2CM.STATUS_REGISTER_E
00000000000A3003 TP.TPCHIP.PIB.I2CM.DATA0TO7_REGISTER_E
00000000000A3004 TP.TPCHIP.PIB.I2CM.FIFO1_REGISTER_READ_E
00000000000A3005 TP.TPCHIP.PIB.I2CM.COMMAND_REGISTER_E
00000000000A3006 TP.TPCHIP.PIB.I2CM.MODE_REGISTER_E
00000000000A3007 TP.TPCHIP.PIB.I2CM.WATER_MARK_REGISTER_E
00000000000A3008 TP.TPCHIP.PIB.I2CM.INTERRUPT_MASK_REGISTER_E
00000000000A3009 TP.TPCHIP.PIB.I2CM.INTERRUPT_MASK_REGISTER_E
00000000000A300A TP.TPCHIP.PIB.I2CM.INTERRUPT_MASK_REGISTER_E
00000000000A3008 TP.TPCHIP.PIB.I2CM.INTERRUPT_MASK_REGISTER_READ_E
00000000000A3009 TP.TPCHIP.PIB.I2CM.INTERRUPT_COND_E
00000000000A300A TP.TPCHIP.PIB.I2CM.INTERRUPTS_E
00000000000A300B TP.TPCHIP.PIB.I2CM.IMM_RESET_I2C_E
00000000000A300B TP.TPCHIP.PIB.I2CM.STATUS_REGISTER_ENGINE_E
00000000000A300C TP.TPCHIP.PIB.I2CM.EXTENDED_STATUS_E
00000000000A300C TP.TPCHIP.PIB.I2CM.IMM_RESET_ERR_E
00000000000A300D TP.TPCHIP.PIB.I2CM.IMM_SET_S_SCL_E
00000000000A300D TP.TPCHIP.PIB.I2CM.RESIDUAL_FRONT_END_BACK_END_LENGTH_E
00000000000A300E TP.TPCHIP.PIB.I2CM.I2C_BUSY_REGISTER_E
00000000000A300F TP.TPCHIP.PIB.I2CM.IMM_RESET_S_SCL_E
00000000000A3010 TP.TPCHIP.PIB.I2CM.IMM_SET_S_SDA_E
00000000000A3011 TP.TPCHIP.PIB.I2CM.IMM_RESET_S_SDA_E
00000000000A3012 TP.TPCHIP.PIB.I2CM.FIFO4_REGISTER_READ_E
00000000000A33FE TP.TPCHIP.PIB.I2CM.PIBI2CM_PROTECT_MODE_REG_E
00000000000A33FF TP.TPCHIP.PIB.I2CM.PIBI2CM_ATOMIC_LOCK_REG_E
00000000000B0000 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_UPFIFO_DATA_OUT
00000000000B0004 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_UPFIFO_RESET
00000000000B0005 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_UPFIFO_ACK_EOT
00000000000B0010 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_DOWNFIFO_DATA_IN
00000000000B0012 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_DOWNFIFO_SIG_EOT
00000000000B0013 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_DOWNFIFO_REQ_RESET
00000000000B0020 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HUPFIFO_DATA_OUT
00000000000B0024 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HUPFIFO_RESET
00000000000B0025 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HUPFIFO_ACK_EOT
00000000000B0030 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HDOWNFIFO_DATA_IN
00000000000B0032 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HDOWNFIFO_SIG_EOT
00000000000B0033 TP.TPVSB.FSI.W.FSI_SBE_FIFO.FSB_HDOWNFIFO_REQ_RESET
00000000000B0050 TP.TPVSB.FSI.W.FSI_SBE_FIFO.GPIO_INPUT
00000000000B0051 TP.TPVSB.FSI.W.FSI_SBE_FIFO.GPIO_OUTPUT
00000000000B0052 TP.TPVSB.FSI.W.FSI_SBE_FIFO.GPIO_OUTPUT
00000000000B0053 TP.TPVSB.FSI.W.FSI_SBE_FIFO.GPIO_OUTPUT
00000000000B0054 TP.TPVSB.FSI.W.FSI_SBE_FIFO.GPIO_OUTPUT_EN
00000000000B0057 TP.TPVSB.FSI.W.FSI_SBE_FIFO.GPIO_INT_STATUS
00000000000B0059 TP.TPVSB.FSI.W.FSI_SBE_FIFO.GPIO_MODE
00000000000B005C TP.TPVSB.FSI.W.FSI_SBE_FIFO.GPIO_INT_POLARITY
00000000000B005D TP.TPVSB.FSI.W.FSI_SBE_FIFO.GPIO_INT_ENABLE
00000000000B005E TP.TPVSB.FSI.W.FSI_SBE_FIFO.GPIO_INT_COND
00000000000B0071 TP.TPVSB.FSI.W.FSI_SBE_FIFO.SBE2FSI_INTR_SET
00000000000C0000 TP.TPCHIP.PIB.SPIMC.SPIMST0_ERROR_INJECT_
00000000000C0001 TP.TPCHIP.PIB.SPIMC.SPIMST0_COUNTER
00000000000C0002 TP.TPCHIP.PIB.SPIMC.SPIMST0_CONFIG1
00000000000C0003 TP.TPCHIP.PIB.SPIMC.SPIMST0_CLOCK_CONFIG
00000000000C0004 TP.TPCHIP.PIB.SPIMC.SPIMST0_MEMORY_MAPPING
00000000000C0005 TP.TPCHIP.PIB.SPIMC.SPIMST0_TRANSMIT_DATA_REG
00000000000C0006 TP.TPCHIP.PIB.SPIMC.SPIMST0_RECEIVE_DATA_REG
00000000000C0007 TP.TPCHIP.PIB.SPIMC.SPIMST0_SEQUENCER_OP_REG
00000000000C0008 TP.TPCHIP.PIB.SPIMC.SPIMST0_STATUS_REG
00000000000C0020 TP.TPCHIP.PIB.SPIMC.SPIMST1_ERROR_INJECT_
00000000000C0021 TP.TPCHIP.PIB.SPIMC.SPIMST1_COUNTER
00000000000C0022 TP.TPCHIP.PIB.SPIMC.SPIMST1_CONFIG1
00000000000C0023 TP.TPCHIP.PIB.SPIMC.SPIMST1_CLOCK_CONFIG
00000000000C0024 TP.TPCHIP.PIB.SPIMC.SPIMST1_MEMORY_MAPPING
00000000000C0025 TP.TPCHIP.PIB.SPIMC.SPIMST1_TRANSMIT_DATA_REG
00000000000C0026 TP.TPCHIP.PIB.SPIMC.SPIMST1_RECEIVE_DATA_REG
00000000000C0027 TP.TPCHIP.PIB.SPIMC.SPIMST1_SEQUENCER_OP_REG
00000000000C0028 TP.TPCHIP.PIB.SPIMC.SPIMST1_STATUS_REG
00000000000C0040 TP.TPCHIP.PIB.SPIMC.SPIMST2_ERROR_INJECT_
00000000000C0041 TP.TPCHIP.PIB.SPIMC.SPIMST2_COUNTER
00000000000C0042 TP.TPCHIP.PIB.SPIMC.SPIMST2_CONFIG1
00000000000C0043 TP.TPCHIP.PIB.SPIMC.SPIMST2_CLOCK_CONFIG
00000000000C0044 TP.TPCHIP.PIB.SPIMC.SPIMST2_MEMORY_MAPPING
00000000000C0045 TP.TPCHIP.PIB.SPIMC.SPIMST2_TRANSMIT_DATA_REG
00000000000C0046 TP.TPCHIP.PIB.SPIMC.SPIMST2_RECEIVE_DATA_REG
00000000000C0047 TP.TPCHIP.PIB.SPIMC.SPIMST2_SEQUENCER_OP_REG
00000000000C0048 TP.TPCHIP.PIB.SPIMC.SPIMST2_STATUS_REG
00000000000C0060 TP.TPCHIP.PIB.SPIMC.SPIMST3_ERROR_INJECT_
00000000000C0061 TP.TPCHIP.PIB.SPIMC.SPIMST3_COUNTER
00000000000C0062 TP.TPCHIP.PIB.SPIMC.SPIMST3_CONFIG1
00000000000C0063 TP.TPCHIP.PIB.SPIMC.SPIMST3_CLOCK_CONFIG
00000000000C0064 TP.TPCHIP.PIB.SPIMC.SPIMST3_MEMORY_MAPPING
00000000000C0065 TP.TPCHIP.PIB.SPIMC.SPIMST3_TRANSMIT_DATA_REG
00000000000C0066 TP.TPCHIP.PIB.SPIMC.SPIMST3_RECEIVE_DATA_REG
00000000000C0067 TP.TPCHIP.PIB.SPIMC.SPIMST3_SEQUENCER_OP_REG
00000000000C0068 TP.TPCHIP.PIB.SPIMC.SPIMST3_STATUS_REG
00000000000C0080 TP.TPCHIP.PIB.SPIMC.SPIMST4_ERROR_INJECT_
00000000000C0081 TP.TPCHIP.PIB.SPIMC.SPIMST4_COUNTER
00000000000C0082 TP.TPCHIP.PIB.SPIMC.SPIMST4_CONFIG1
00000000000C0083 TP.TPCHIP.PIB.SPIMC.SPIMST4_CLOCK_CONFIG
00000000000C0084 TP.TPCHIP.PIB.SPIMC.SPIMST4_MEMORY_MAPPING
00000000000C0085 TP.TPCHIP.PIB.SPIMC.SPIMST4_TRANSMIT_DATA_REG
00000000000C0086 TP.TPCHIP.PIB.SPIMC.SPIMST4_RECEIVE_DATA_REG
00000000000C0087 TP.TPCHIP.PIB.SPIMC.SPIMST4_SEQUENCER_OP_REG
00000000000C0088 TP.TPCHIP.PIB.SPIMC.SPIMST4_STATUS_REG
00000000000D0000 TP.TPCHIP.PIB.PSU.PSU_PIBHIST_CTRL_STATUS_REG
00000000000D0001 TP.TPCHIP.PIB.PSU.PSU_PIBHIST_FILTER_REG
00000000000D0002 TP.TPCHIP.PIB.PSU.PSU_PIBHIST_LAST_ADDR_TRACE_REG
00000000000D0003 TP.TPCHIP.PIB.PSU.PSU_PIBHIST_LAST_REQDATA_TRACE_REG
00000000000D0004 TP.TPCHIP.PIB.PSU.PSU_PIBHIST_LAST_RSPDATA_TRACE_REG
00000000000D0005 TP.TPCHIP.PIB.PSU.PSU_PIBHIST_2NDLAST_ADDR_TRACE_REG
00000000000D0006 TP.TPCHIP.PIB.PSU.PSU_PIBHIST_2NDLAST_REQDATA_TRACE_REG
00000000000D0007 TP.TPCHIP.PIB.PSU.PSU_PIBHIST_2NDLAST_RSPDATA_TRACE_REG
00000000000D0010 TP.TPCHIP.PIB.PSU.PSU_INSTR_CTRL_STATUS_REG
00000000000D0020 TP.TPCHIP.PIB.PSU.PSU_INSTR0_STOP_TIMER_REG
00000000000D0021 TP.TPCHIP.PIB.PSU.PSU_INSTR0_FILTER_REG
00000000000D0022 TP.TPCHIP.PIB.PSU.PSU_INSTR0_CYCLECNT_REG
00000000000D0023 TP.TPCHIP.PIB.PSU.PSU_INSTR0_ACTCYCLECNT_REG
00000000000D0024 TP.TPCHIP.PIB.PSU.PSU_INSTR0_EVENTCNT_REG
00000000000D0025 TP.TPCHIP.PIB.PSU.PSU_INSTR0_MAXCYCLECNT_REG
00000000000D0026 TP.TPCHIP.PIB.PSU.PSU_INSTR0_MINCYCLECNT_REG
00000000000D0030 TP.TPCHIP.PIB.PSU.PSU_INSTR1_STOP_TIMER_REG
00000000000D0031 TP.TPCHIP.PIB.PSU.PSU_INSTR1_FILTER_REG
00000000000D0032 TP.TPCHIP.PIB.PSU.PSU_INSTR1_CYCLECNT_REG
00000000000D0033 TP.TPCHIP.PIB.PSU.PSU_INSTR1_ACTCYCLECNT_REG
00000000000D0034 TP.TPCHIP.PIB.PSU.PSU_INSTR1_EVENTCNT_REG
00000000000D0035 TP.TPCHIP.PIB.PSU.PSU_INSTR1_MAXCYCLECNT_REG
00000000000D0036 TP.TPCHIP.PIB.PSU.PSU_INSTR1_MINCYCLECNT_REG
00000000000D0040 TP.TPCHIP.PIB.PSU.PSU_INSTR2_STOP_TIMER_REG
00000000000D0041 TP.TPCHIP.PIB.PSU.PSU_INSTR2_FILTER_REG
00000000000D0042 TP.TPCHIP.PIB.PSU.PSU_INSTR2_CYCLECNT_REG
00000000000D0043 TP.TPCHIP.PIB.PSU.PSU_INSTR2_ACTCYCLECNT_REG
00000000000D0044 TP.TPCHIP.PIB.PSU.PSU_INSTR2_EVENTCNT_REG
00000000000D0045 TP.TPCHIP.PIB.PSU.PSU_INSTR2_MAXCYCLECNT_REG
00000000000D0046 TP.TPCHIP.PIB.PSU.PSU_INSTR2_MINCYCLECNT_REG
00000000000D0050 TP.TPCHIP.PIB.PSU.PSU_HOST_SBE_MBOX0_REG
00000000000D0051 TP.TPCHIP.PIB.PSU.PSU_HOST_SBE_MBOX1_REG
00000000000D0052 TP.TPCHIP.PIB.PSU.PSU_HOST_SBE_MBOX2_REG
00000000000D0053 TP.TPCHIP.PIB.PSU.PSU_HOST_SBE_MBOX3_REG
00000000000D0054 TP.TPCHIP.PIB.PSU.PSU_HOST_SBE_MBOX4_REG
00000000000D0055 TP.TPCHIP.PIB.PSU.PSU_HOST_SBE_MBOX5_REG
00000000000D0056 TP.TPCHIP.PIB.PSU.PSU_HOST_SBE_MBOX6_REG
00000000000D0057 TP.TPCHIP.PIB.PSU.PSU_HOST_SBE_MBOX7_REG
00000000000D0060 TP.TPCHIP.PIB.PSU.PSU_SBE_DOORBELL_REG
00000000000D0061 TP.TPCHIP.PIB.PSU.PSU_SBE_DOORBELL_REG
00000000000D0062 TP.TPCHIP.PIB.PSU.PSU_SBE_DOORBELL_REG
00000000000D0063 TP.TPCHIP.PIB.PSU.PSU_HOST_DOORBELL_REG
00000000000D0064 TP.TPCHIP.PIB.PSU.PSU_HOST_DOORBELL_REG
00000000000D0065 TP.TPCHIP.PIB.PSU.PSU_HOST_DOORBELL_REG
00000000000D0070 TP.TPCHIP.PIB.PSU.HANG_PULSE_CONFIG_REG
00000000000D0071 TP.TPCHIP.PIB.PSU.HANG_PULSE_0_REG
00000000000D0072 TP.TPCHIP.PIB.PSU.PRE_COUNTER_REG_0
00000000000D0073 TP.TPCHIP.PIB.PSU.HANG_PULSE_1_REG
00000000000D0074 TP.TPCHIP.PIB.PSU.PRE_COUNTER_REG_1
00000000000D0075 TP.TPCHIP.PIB.PSU.HANG_PULSE_2_REG
00000000000D0076 TP.TPCHIP.PIB.PSU.PRE_COUNTER_REG_2
00000000000D0077 TP.TPCHIP.PIB.PSU.HANG_PULSE_3_REG
00000000000D0078 TP.TPCHIP.PIB.PSU.PRE_COUNTER_REG_3
00000000000E0000 TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.PPE_XIXCR
00000000000E0001 TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.PPE_XIRAMRA
00000000000E0002 TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.PPE_XIRAMGA
00000000000E0003 TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.PPE_XIRAMDBG
00000000000E0004 TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.PPE_XIRAMEDR
00000000000E0005 TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.PPE_XIDBGPRO
00000000000E0006 TP.TPCHIP.PIB.SBE.SBEPM.MIB_XISIB
00000000000E0007 TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.PPE_XIMEM
00000000000E0008 TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.PPE_XISGB
00000000000E0009 TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.MIB.PPE_XIICAC
00000000000E000F TP.TPCHIP.PIB.SBE.SBEPM.SBEPPE.PPE.PPE_XIDBGINF
0000000001000000 TP.TPCHIP.TPC.CPLT_CTRL0
0000000001000010 TP.TPCHIP.TPC.CPLT_CTRL0
0000000001000020 TP.TPCHIP.TPC.CPLT_CTRL0
0000000001000001 TP.TPCHIP.TPC.CPLT_CTRL1
0000000001000011 TP.TPCHIP.TPC.CPLT_CTRL1
0000000001000021 TP.TPCHIP.TPC.CPLT_CTRL1
0000000001000002 TP.TPCHIP.TPC.CPLT_CTRL2
0000000001000012 TP.TPCHIP.TPC.CPLT_CTRL2
0000000001000022 TP.TPCHIP.TPC.CPLT_CTRL2
0000000001000003 TP.TPCHIP.TPC.CPLT_CTRL3
0000000001000013 TP.TPCHIP.TPC.CPLT_CTRL3
0000000001000023 TP.TPCHIP.TPC.CPLT_CTRL3
0000000001000004 TP.TPCHIP.TPC.CPLT_CTRL4
0000000001000014 TP.TPCHIP.TPC.CPLT_CTRL4
0000000001000024 TP.TPCHIP.TPC.CPLT_CTRL4
0000000001000005 TP.TPCHIP.TPC.CPLT_CTRL5
0000000001000015 TP.TPCHIP.TPC.CPLT_CTRL5
0000000001000025 TP.TPCHIP.TPC.CPLT_CTRL5
0000000001000008 TP.TPCHIP.TPC.CPLT_CONF0
0000000001000018 TP.TPCHIP.TPC.CPLT_CONF0
0000000001000028 TP.TPCHIP.TPC.CPLT_CONF0
0000000001000009 TP.TPCHIP.TPC.CPLT_CONF1
0000000001000019 TP.TPCHIP.TPC.CPLT_CONF1
0000000001000029 TP.TPCHIP.TPC.CPLT_CONF1
0000000001000100 TP.TPCHIP.TPC.CPLT_STAT0
0000000001000101 TP.TPCHIP.TPC.CPLT_MASK0
00000000010003FE TP.TPCHIP.TPC.CTRL_PROTECT_MODE_REG
00000000010003FF TP.TPCHIP.TPC.CTRL_ATOMIC_LOCK_REG
0000000001010000 TP.TPCHIP.TPC.EPS.PSC.PSC.PSCOM_MODE_REG
0000000001010001 TP.TPCHIP.TPC.EPS.PSC.PSC.PSCOM_STATUS_ERROR_REG
0000000001010002 TP.TPCHIP.TPC.EPS.PSC.PSC.PSCOM_ERROR_MASK
0000000001010003 TP.TPCHIP.TPC.EPS.PSC.PSC.ADDR_TRAP_REG
0000000001010005 TP.TPCHIP.TPC.EPS.PSC.PSC.WRITE_PROTECT_ENABLE_REG
0000000001010006 TP.TPCHIP.TPC.EPS.PSC.PSC.WRITE_PROTECT_RINGS_REG
0000000001010007 TP.TPCHIP.TPC.EPS.PSC.PSC.ATOMIC_LOCK_MASK_LATCH_REG
0000000001010008 TP.TPCHIP.TPC.EPS.PSC.PSC.RING_FENCE_MASK_LATCH_REG
0000000001010400 TP.TPCHIP.TPC.TRA0.TR0.TRACE_HI_DATA_REG
0000000001010401 TP.TPCHIP.TPC.TRA0.TR0.TRACE_LO_DATA_REG
0000000001010402 TP.TPCHIP.TPC.TRA0.TR0.TRACE_TRCTRL_CONFIG
0000000001010403 TP.TPCHIP.TPC.TRA0.TR0.TRACE_TRDATA_CONFIG_0
0000000001010404 TP.TPCHIP.TPC.TRA0.TR0.TRACE_TRDATA_CONFIG_1
0000000001010405 TP.TPCHIP.TPC.TRA0.TR0.TRACE_TRDATA_CONFIG_2
0000000001010406 TP.TPCHIP.TPC.TRA0.TR0.TRACE_TRDATA_CONFIG_3
0000000001010407 TP.TPCHIP.TPC.TRA0.TR0.TRACE_TRDATA_CONFIG_4
0000000001010408 TP.TPCHIP.TPC.TRA0.TR0.TRACE_TRDATA_CONFIG_5
0000000001010409 TP.TPCHIP.TPC.TRA0.TR0.TRACE_TRDATA_CONFIG_9
0000000001010440 TP.TPCHIP.TPC.TRA0.TR1.TRACE_HI_DATA_REG
0000000001010441 TP.TPCHIP.TPC.TRA0.TR1.TRACE_LO_DATA_REG
0000000001010442 TP.TPCHIP.TPC.TRA0.TR1.TRACE_TRCTRL_CONFIG
0000000001010443 TP.TPCHIP.TPC.TRA0.TR1.TRACE_TRDATA_CONFIG_0
0000000001010444 TP.TPCHIP.TPC.TRA0.TR1.TRACE_TRDATA_CONFIG_1
0000000001010445 TP.TPCHIP.TPC.TRA0.TR1.TRACE_TRDATA_CONFIG_2
0000000001010446 TP.TPCHIP.TPC.TRA0.TR1.TRACE_TRDATA_CONFIG_3
0000000001010447 TP.TPCHIP.TPC.TRA0.TR1.TRACE_TRDATA_CONFIG_4
0000000001010448 TP.TPCHIP.TPC.TRA0.TR1.TRACE_TRDATA_CONFIG_5
0000000001010449 TP.TPCHIP.TPC.TRA0.TR1.TRACE_TRDATA_CONFIG_9
00000000010107C0 TP.TPCHIP.TPC.EPS.DBG.DBG_MODE_REG
00000000010107C1 TP.TPCHIP.TPC.EPS.DBG.DBG_INST1_COND_REG_1
00000000010107C2 TP.TPCHIP.TPC.EPS.DBG.DBG_INST1_COND_REG_2
00000000010107C3 TP.TPCHIP.TPC.EPS.DBG.DBG_INST1_COND_REG_3
00000000010107C4 TP.TPCHIP.TPC.EPS.DBG.DBG_INST2_COND_REG_1
00000000010107C5 TP.TPCHIP.TPC.EPS.DBG.DBG_INST2_COND_REG_2
00000000010107C6 TP.TPCHIP.TPC.EPS.DBG.DBG_INST2_COND_REG_3
00000000010107CD TP.TPCHIP.TPC.EPS.DBG.DBG_TRACE_REG_0
00000000010107CE TP.TPCHIP.TPC.EPS.DBG.DBG_TRACE_REG_1
00000000010107CF TP.TPCHIP.TPC.EPS.DBG.DBG_TRACE_MODE_REG_2
00000000010107D0 TP.TPCHIP.TPC.EPS.DBG.DEBUG_TRACE_CONTROL
00000000010107D1 TP.TPCHIP.TPC.EPS.DBG.XTRA_TRACE_MODE
0000000001010800 TP.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCLFIR
0000000001010801 TP.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCLFIR
0000000001010802 TP.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCLFIR
0000000001010803 TP.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCLFIRMASK
0000000001010804 TP.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCLFIRMASK
0000000001010805 TP.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCLFIRMASK
0000000001010806 TP.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCLFIRACT0
0000000001010807 TP.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCLFIRACT1
000000000101080A TP.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCERRRPT
000000000101080B TP.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCERRRPT2
0000000001010CC0 TP.TPBR.PBA.PBAO.PBAFIR
0000000001010CC1 TP.TPBR.PBA.PBAO.PBAFIR
0000000001010CC2 TP.TPBR.PBA.PBAO.PBAFIR
0000000001010CC3 TP.TPBR.PBA.PBAO.PBAFIRMASK
0000000001010CC4 TP.TPBR.PBA.PBAO.PBAFIRMASK
0000000001010CC5 TP.TPBR.PBA.PBAO.PBAFIRMASK
0000000001010CC6 TP.TPBR.PBA.PBAO.PBAFIRACT0
0000000001010CC7 TP.TPBR.PBA.PBAO.PBAFIRACT1
0000000001010CCA TP.TPBR.PBA.PBAO.PBAOCCACT
0000000001010CCB TP.TPBR.PBA.PBAO.PBAOCFG
0000000001010CCD TP.TPBR.PBA.PBAO.PBAERRRPT1
0000000001010CCE TP.TPBR.PBA.PBAO.PBAERRRPT2
0000000001010CD0 TP.TPBR.PBA.PBAO.PBARBUFVAL0
0000000001010CD1 TP.TPBR.PBA.PBAO.PBARBUFVAL1
0000000001010CD2 TP.TPBR.PBA.PBAO.PBARBUFVAL2
0000000001010CD3 TP.TPBR.PBA.PBAO.PBARBUFVAL3
0000000001010CD4 TP.TPBR.PBA.PBAO.PBARBUFVAL4
0000000001010CD5 TP.TPBR.PBA.PBAO.PBARBUFVAL5
0000000001010CD8 TP.TPBR.PBA.PBAO.PBAWBUFVAL0
0000000001010CD9 TP.TPBR.PBA.PBAO.PBAWBUFVAL1
0000000001010CDA TP.TPBR.PBA.PBAO.PBABAR0
0000000001010CDB TP.TPBR.PBA.PBAO.PBABAR1
0000000001010CDC TP.TPBR.PBA.PBAO.PBABAR2
0000000001010CDD TP.TPBR.PBA.PBAO.PBABAR3
0000000001010CDE TP.TPBR.PBA.PBAO.PBABARMSK0
0000000001010CDF TP.TPBR.PBA.PBAO.PBABARMSK1
0000000001010CE0 TP.TPBR.PBA.PBAO.PBABARMSK2
0000000001010CE1 TP.TPBR.PBA.PBAO.PBABARMSK3
0000000001010CE2 TP.TPBR.PBA.PBAO.PBAPBTXT0
0000000001010CE3 TP.TPBR.PBA.PBAO.PBAPBTXT1
0000000001010CE4 TP.TPBR.PBA.PBAO.PBAPBTXT2
0000000001010CE5 TP.TPBR.PBA.PBAO.PBAPBTXT3
0000000001011020 PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.RX_PSI_CNTL
0000000001011021 PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.RX_PSI_MODE
0000000001011022 PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.RX_PSI_STATUS
0000000001011030 PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.TX_PSI_CNTL
0000000001011031 PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.TX_PSI_MODE
0000000001011032 PSI.PSI.PSI_MAC.PSI_SCOM.PSI_SCOM_REGS.TX_PSI_STATUS
0000000001020000 TP.TPCHIP.TPC.ITR.FMU.FMU_MODE_REG
0000000001020001 TP.TPCHIP.TPC.ITR.FMU.FMU_OSC_CNTR1_REG
0000000001020001 TP.TPCHIP.TPC.ITR.FMU.FMU_PULSE_GEN_REG
0000000001020002 TP.TPCHIP.TPC.ITR.FMU.FMU_OSC_CNTR2_REG
0000000001020003 TP.TPCHIP.TPC.ITR.FMU.FMU_FORCE_OP_REG
0000000001020004 TP.TPCHIP.TPC.ITR.FMU.FMU_KVREF_DATAREG
0000000001020005 TP.TPCHIP.TPC.ITR.FMU.KVREF_TUNE_DATA
0000000001020006 TP.TPCHIP.TPC.ITR.FMU.VMEAS_RESULT_REG
0000000001020007 TP.TPCHIP.TPC.ITR.FMU.KVREF_AND_VMEAS_MODE_STATUS_REG
0000000001020008 TP.TPCHIP.TPC.ITR.FMU.FMU_VMEAS_MAX_RESULT
0000000001020009 TP.TPCHIP.TPC.ITR.FMU.FMU_VMEAS_MIN_RESULT
0000000001030000 TP.TPCHIP.TPC.SYNC_CONFIG
0000000001030001 TP.TPCHIP.TPC.OPCG_ALIGN
0000000001030002 TP.TPCHIP.TPC.OPCG_REG0
0000000001030003 TP.TPCHIP.TPC.OPCG_REG1
0000000001030004 TP.TPCHIP.TPC.OPCG_REG2
0000000001030005 TP.TPCHIP.TPC.SCAN_REGION_TYPE
0000000001030006 TP.TPCHIP.TPC.CLK_REGION
0000000001030008 TP.TPCHIP.TPC.CLOCK_STAT_SL
0000000001030009 TP.TPCHIP.TPC.CLOCK_STAT_NSL
000000000103000A TP.TPCHIP.TPC.CLOCK_STAT_ARY
000000000103000B TP.TPCHIP.TPC.BIST
000000000103000C TP.TPCHIP.TPC.XSTOP1
000000000103000D TP.TPCHIP.TPC.XSTOP2
000000000103000E TP.TPCHIP.TPC.XSTOP3
000000000103000F TP.TPCHIP.TPC.ERROR_STATUS
0000000001030010 TP.TPCHIP.TPC.OPCG_CAPT1
0000000001030011 TP.TPCHIP.TPC.OPCG_CAPT2
0000000001030012 TP.TPCHIP.TPC.OPCG_CAPT3
0000000001030013 TP.TPCHIP.TPC.DBG_CBS_CC
0000000001030014 TP.TPCHIP.TPC.XSTOP4
0000000001030015 TP.TPCHIP.TPC.XSTOP5
0000000001030016 TP.TPCHIP.TPC.REGION_CCFLUSH_STATUS
0000000001030020 TP.TPCHIP.TPC.PCB_OPCG_GO
0000000001030028 TP.TPCHIP.TPC.PHASE_COUNTER_RESET
0000000001030030 TP.TPCHIP.TPC.PCB_OPCG_STOP
00000000010303FE TP.TPCHIP.TPC.CC_PROTECT_MODE_REG
00000000010303FF TP.TPCHIP.TPC.CC_ATOMIC_LOCK_REG
0000000001038000 TP.TPCHIP.TPC.SCAN32
0000000001039000 TP.TPCHIP.TPC.SCAN_LONG_ROTATE
000000000103A000 TP.TPCHIP.TPC.SCAN_UPDATEDR
000000000103B000 TP.TPCHIP.TPC.SCAN_UPDATEDR_LONG
000000000103C000 TP.TPCHIP.TPC.SCAN_CAPTUREDR
000000000103D000 TP.TPCHIP.TPC.SCAN_CAPTUREDR_LONG
000000000103E000 TP.TPCHIP.TPC.SCAN64
000000000103F000 TP.TPCHIP.TPC.SCAN64CONTSCAN
0000000001040000 TP.TPCHIP.TPC.XSTOP
0000000001040001 TP.TPCHIP.TPC.RECOV
0000000001040002 TP.TPCHIP.TPC.SPATTN
0000000001040003 TP.TPCHIP.TPC.LOCAL_XSTOP
0000000001040004 TP.TPCHIP.TPC.HOSTATTN
0000000001040010 TP.TPCHIP.TPC.XSTOP_UNMASKED
0000000001040011 TP.TPCHIP.TPC.RECOV_UNMASKED
0000000001040012 TP.TPCHIP.TPC.SPATTN_UNMASKED
0000000001040013 TP.TPCHIP.TPC.LOCAL_XSTOP_UNMASKED
0000000001040014 TP.TPCHIP.TPC.HOSTATTN_UNMASKED
0000000001040021 TP.TPCHIP.TPC.WOF
0000000001040040 TP.TPCHIP.TPC.XSTOP_MASK
0000000001040050 TP.TPCHIP.TPC.XSTOP_MASK
0000000001040060 TP.TPCHIP.TPC.XSTOP_MASK
0000000001040041 TP.TPCHIP.TPC.RECOV_MASK
0000000001040051 TP.TPCHIP.TPC.RECOV_MASK
0000000001040061 TP.TPCHIP.TPC.RECOV_MASK
0000000001040042 TP.TPCHIP.TPC.SPATTN_MASK
0000000001040052 TP.TPCHIP.TPC.SPATTN_MASK
0000000001040062 TP.TPCHIP.TPC.SPATTN_MASK
0000000001040043 TP.TPCHIP.TPC.LOCAL_XSTOP_MASK
0000000001040053 TP.TPCHIP.TPC.LOCAL_XSTOP_MASK
0000000001040063 TP.TPCHIP.TPC.LOCAL_XSTOP_MASK
0000000001040044 TP.TPCHIP.TPC.HOSTATTN_MASK
0000000001040054 TP.TPCHIP.TPC.HOSTATTN_MASK
0000000001040064 TP.TPCHIP.TPC.HOSTATTN_MASK
0000000001040080 TP.TPCHIP.TPC.EPS.FIR.ANY_LOCAL_ERR_MASK
0000000001040081 TP.TPCHIP.TPC.EPS.FIR.CLKSTOP_ON_XSTOP_MASK1
0000000001040082 TP.TPCHIP.TPC.EPS.FIR.CLKSTOP_ON_XSTOP_MASK2
0000000001040083 TP.TPCHIP.TPC.EPS.FIR.CLKSTOP_ON_XSTOP_MASK3
0000000001040084 TP.TPCHIP.TPC.EPS.FIR.CLKSTOP_ON_XSTOP_MASK4
0000000001040085 TP.TPCHIP.TPC.EPS.FIR.CLKSTOP_ON_XSTOP_MASK5
0000000001040088 TP.TPCHIP.TPC.EPS.FIR.MODE_REG
0000000001040100 TP.TPCHIP.TPC.LOCAL_FIR
0000000001040101 TP.TPCHIP.TPC.LOCAL_FIR
0000000001040102 TP.TPCHIP.TPC.LOCAL_FIR
0000000001040103 TP.TPCHIP.TPC.EPS.FIR.LOCAL_FIR_MASK
0000000001040104 TP.TPCHIP.TPC.EPS.FIR.LOCAL_FIR_MASK
0000000001040105 TP.TPCHIP.TPC.EPS.FIR.LOCAL_FIR_MASK
0000000001040106 TP.TPCHIP.TPC.EPS.FIR.LOCAL_FIR_ACTION0
0000000001040107 TP.TPCHIP.TPC.EPS.FIR.LOCAL_FIR_ACTION1
0000000001040108 TP.TPCHIP.TPC.EPS.FIR.LOCAL_FIR_WOF
0000000001040109 TP.TPCHIP.TPC.EPS.FIR.LOCAL_FIR_ACTION2
0000000001050000 TP.TPCHIP.TPC.EPS.THERM.WSUB.DTS_RESULT0
0000000001050001 TP.TPCHIP.TPC.EPS.THERM.WSUB.DTS_RESULT1
0000000001050002 TP.TPCHIP.TPC.EPS.THERM.WSUB.DTS_RESULT2
0000000001050003 TP.TPCHIP.TPC.EPS.THERM.WSUB.DTS_TRC_RESULT
000000000105000F TP.TPCHIP.TPC.EPS.THERM.WSUB.THERM_MODE_REG
0000000001050010 TP.TPCHIP.TPC.EPS.THERM.WSUB.SKITTER_MODE_REG
0000000001050011 TP.TPCHIP.TPC.EPS.THERM.WSUB.INJECT_REG
0000000001050012 TP.TPCHIP.TPC.EPS.THERM.WSUB.CONTROL_REG
0000000001050013 TP.TPCHIP.TPC.EPS.THERM.WSUB.ERR_STATUS_REG
0000000001050014 TP.TPCHIP.TPC.EPS.THERM.WSUB.SKITTER_FORCE_REG
0000000001050016 TP.TPCHIP.TPC.EPS.THERM.WSUB.SKITTER_CLKSRC_REG
0000000001050019 TP.TPCHIP.TPC.EPS.THERM.WSUB.SKITTER_DATA0
000000000105001A TP.TPCHIP.TPC.EPS.THERM.WSUB.SKITTER_DATA1
000000000105001B TP.TPCHIP.TPC.EPS.THERM.WSUB.SKITTER_DATA2
000000000105001C TP.TPCHIP.TPC.EPS.THERM.WSUB.TIMESTAMP_COUNTER_READ
0000000001060051 TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_FREQ
0000000001060052 TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_CTRL
0000000001060053 TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_CTRL
0000000001060054 TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_CTRL
0000000001060055 TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_STAT
0000000001060056 TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_OCHAR
0000000001060057 TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ICHAR
0000000001060058 TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_ECHAR
0000000001060059 TP.TPCHIP.TPC.DPLL_CNTL.PAU.REGS.DPLL_TESTSEL
0000000001060080 TP.TPCHIP.TPC.DPLL_CNTL.MISC.REGS.MISC_PFET
0000000001060151 TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_FREQ
0000000001060152 TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_CTRL
0000000001060153 TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_CTRL
0000000001060154 TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_CTRL
0000000001060155 TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_STAT
0000000001060156 TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_OCHAR
0000000001060157 TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ICHAR
0000000001060158 TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_ECHAR
0000000001060159 TP.TPCHIP.TPC.DPLL_CNTL.NEST.REGS.DPLL_TESTSEL
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